Pattern 6 levels (#493)

* separating pattern levels from command name: command line done

* separated patten level from command in examples and default pattern files in servers

* command line and server works

* python: patnloop not verified, wip

* works except for patloop (set, and get does not list properly)

* minor

* fixed tests

* added 3 more levels for ctb and moench

* wip

* minor err msg

* minor

* binaries in

* separating pattern levels from command name: command line done

* separated patten level from command in examples and default pattern files in servers

* command line and server works

* python: patnloop not verified, wip

* works except for patloop (set, and get does not list properly)

* minor

* fixed tests

* added 3 more levels for ctb and moench

* wip

* minor err msg

* minor

* binaries in

* python working

* import fix

* changed fw version for ctb and moench. binaries in

Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
This commit is contained in:
Dhanya Thattil
2022-07-14 12:00:07 +02:00
committed by GitHub
parent 5be50785fb
commit 8fcec81a67
31 changed files with 955 additions and 643 deletions

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@ -274,15 +274,28 @@ patword 0x0110 0x0008599f0008503a
patword 0x0111 0x0008599f0008503a
patioctrl 0x8f0effff6dbffdbf
patlimits 0x0000 0x0110
patloop0 0x00be 0x00ef
patnloop0 199
patloop1 0x0400 0x0400
patnloop1 0
patloop2 0x0400 0x0400
patnloop2 0
patwait0 0x002e
patwaittime0 800
patwait1 0x0400
patwaittime1 0
patwait2 0x0400
patwaittime2 0
patloop 0 0x00be 0x00ef
patnloop 0 199
patloop 1 0x0400 0x0400
patnloop 1 0
patloop 2 0x0400 0x0400
patnloop 2 0
patwait 0 0x002e
patwaittime 0 800
patwait 1 0x0400
patwaittime 1 0
patwait 2 0x0400
patwaittime 2 0
patloop 3 0x0000 0x0000
patnloop 3 0
patloop 4 0x0000 0x0000
patnloop 4 0
patloop 5 0x0000 0x0000
patnloop 5 0
patwait 3 0x0000
patwaittime 3 0
patwait 4 0x0000
patwaittime 4 0
patwait 5 0x0000
patwaittime 5 0

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@ -572,5 +572,72 @@
#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
/* Pattern Loop 3 Address RW regiser */
#define PATTERN_LOOP_3_ADDR_REG (0x84 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_3_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_3_ADDR_STRT_OFST)
#define PATTERN_LOOP_3_ADDR_STP_OFST (16)
#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_3_ADDR_STP_OFST)
/* Pattern Loop 3 Iteration RW regiser */
#define PATTERN_LOOP_3_ITERATION_REG (0x85 << MEM_MAP_SHIFT)
/* Pattern Loop 4 Address RW regiser */
#define PATTERN_LOOP_4_ADDR_REG (0x86 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_4_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_4_ADDR_STRT_OFST)
#define PATTERN_LOOP_4_ADDR_STP_OFST (16)
#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_4_ADDR_STP_OFST)
/* Pattern Loop 4 Iteration RW regiser */
#define PATTERN_LOOP_4_ITERATION_REG (0x87 << MEM_MAP_SHIFT)
/* Pattern Loop 5 Address RW regiser */
#define PATTERN_LOOP_5_ADDR_REG (0x88 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_5_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_5_ADDR_STRT_OFST)
#define PATTERN_LOOP_5_ADDR_STP_OFST (16)
#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_5_ADDR_STP_OFST)
/* Pattern Loop 5 Iteration RW regiser */
#define PATTERN_LOOP_5_ITERATION_REG (0x89 << MEM_MAP_SHIFT)
/* Pattern Wait 3 RW regiser */
#define PATTERN_WAIT_3_ADDR_REG (0x8A << MEM_MAP_SHIFT)
#define PATTERN_WAIT_3_ADDR_OFST (0)
#define PATTERN_WAIT_3_ADDR_MSK (0x00001FFF << PATTERN_WAIT_3_ADDR_OFST)
/* Pattern Wait 4 RW regiser */
#define PATTERN_WAIT_4_ADDR_REG (0x8B << MEM_MAP_SHIFT)
#define PATTERN_WAIT_4_ADDR_OFST (0)
#define PATTERN_WAIT_4_ADDR_MSK (0x00001FFF << PATTERN_WAIT_4_ADDR_OFST)
/* Pattern Wait 5 RW regiser */
#define PATTERN_WAIT_5_ADDR_REG (0x8C << MEM_MAP_SHIFT)
#define PATTERN_WAIT_5_ADDR_OFST (0)
#define PATTERN_WAIT_5_ADDR_MSK (0x00001FFF << PATTERN_WAIT_5_ADDR_OFST)
/* Pattern Wait Timer 3 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_3_LSB_REG (0x8D << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_3_MSB_REG (0x8E << MEM_MAP_SHIFT)
/* Pattern Wait Timer 4 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_4_LSB_REG (0x8F << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_4_MSB_REG (0x90 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 5 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_5_LSB_REG (0x91 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_5_MSB_REG (0x92 << MEM_MAP_SHIFT)
/* Round Robin */
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)

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@ -274,15 +274,28 @@ patword 0x0110 0x0008599f0008503a
patword 0x0111 0x0008599f0008503a
patioctrl 0x8f0effff6dbffdbf
patlimits 0x0000 0x0110
patloop0 0x00be 0x00ef
patnloop0 199
patloop1 0x0400 0x0400
patnloop1 0
patloop2 0x0400 0x0400
patnloop2 0
patwait0 0x002e
patwaittime0 800
patwait1 0x0400
patwaittime1 0
patwait2 0x0400
patwaittime2 0
patloop 0 0x00be 0x00ef
patnloop 0 199
patloop 1 0x0400 0x0400
patnloop 1 0
patloop 2 0x0400 0x0400
patnloop 2 0
patwait 0 0x002e
patwaittime 0 800
patwait 1 0x0400
patwaittime 1 0
patwait 2 0x0400
patwaittime 2 0
patloop 3 0x0000 0x0000
patnloop 3 0
patloop 4 0x0000 0x0000
patnloop 4 0
patloop 5 0x0000 0x0000
patnloop 5 0
patwait 3 0x0000
patwaittime 3 0
patwait 4 0x0000
patwaittime 4 0
patwait 5 0x0000
patwaittime 5 0

View File

@ -5,7 +5,7 @@
#include "sls/sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x180314
#define REQRD_FRMWR_VRSN 0x201005
#define REQRD_FRMWR_VRSN 0x220714
#define LINKED_SERVER_NAME "moenchDetectorServer"