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https://github.com/slsdetectorgroup/slsDetectorPackage.git
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Pattern 6 levels (#493)
* separating pattern levels from command name: command line done * separated patten level from command in examples and default pattern files in servers * command line and server works * python: patnloop not verified, wip * works except for patloop (set, and get does not list properly) * minor * fixed tests * added 3 more levels for ctb and moench * wip * minor err msg * minor * binaries in * separating pattern levels from command name: command line done * separated patten level from command in examples and default pattern files in servers * command line and server works * python: patnloop not verified, wip * works except for patloop (set, and get does not list properly) * minor * fixed tests * added 3 more levels for ctb and moench * wip * minor err msg * minor * binaries in * python working * import fix * changed fw version for ctb and moench. binaries in Co-authored-by: Erik Frojdh <erik.frojdh@gmail.com>
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@ -568,6 +568,72 @@
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#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
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#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
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/* Pattern Loop 3 Address RW regiser */
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#define PATTERN_LOOP_3_ADDR_REG (0x84 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_3_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_3_ADDR_STRT_MSK \
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(0x00001FFF << PATTERN_LOOP_3_ADDR_STRT_OFST)
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#define PATTERN_LOOP_3_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_3_ADDR_STP_OFST)
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/* Pattern Loop 3 Iteration RW regiser */
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#define PATTERN_LOOP_3_ITERATION_REG (0x85 << MEM_MAP_SHIFT)
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/* Pattern Loop 4 Address RW regiser */
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#define PATTERN_LOOP_4_ADDR_REG (0x86 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_4_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_4_ADDR_STRT_MSK \
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(0x00001FFF << PATTERN_LOOP_4_ADDR_STRT_OFST)
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#define PATTERN_LOOP_4_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_4_ADDR_STP_OFST)
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/* Pattern Loop 4 Iteration RW regiser */
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#define PATTERN_LOOP_4_ITERATION_REG (0x87 << MEM_MAP_SHIFT)
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/* Pattern Loop 5 Address RW regiser */
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#define PATTERN_LOOP_5_ADDR_REG (0x88 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_5_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_5_ADDR_STRT_MSK \
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(0x00001FFF << PATTERN_LOOP_5_ADDR_STRT_OFST)
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#define PATTERN_LOOP_5_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_5_ADDR_STP_OFST)
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/* Pattern Loop 5 Iteration RW regiser */
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#define PATTERN_LOOP_5_ITERATION_REG (0x89 << MEM_MAP_SHIFT)
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/* Pattern Wait 3 RW regiser */
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#define PATTERN_WAIT_3_ADDR_REG (0x8A << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_3_ADDR_OFST (0)
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#define PATTERN_WAIT_3_ADDR_MSK (0x00001FFF << PATTERN_WAIT_3_ADDR_OFST)
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/* Pattern Wait 4 RW regiser */
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#define PATTERN_WAIT_4_ADDR_REG (0x8B << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_4_ADDR_OFST (0)
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#define PATTERN_WAIT_4_ADDR_MSK (0x00001FFF << PATTERN_WAIT_4_ADDR_OFST)
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/* Pattern Wait 5 RW regiser */
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#define PATTERN_WAIT_5_ADDR_REG (0x8C << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_5_ADDR_OFST (0)
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#define PATTERN_WAIT_5_ADDR_MSK (0x00001FFF << PATTERN_WAIT_5_ADDR_OFST)
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/* Pattern Wait Timer 3 64 bit RW register. t = PWT1 x T run clock */
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#define PATTERN_WAIT_TIMER_3_LSB_REG (0x8D << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_TIMER_3_MSB_REG (0x8E << MEM_MAP_SHIFT)
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/* Pattern Wait Timer 4 64 bit RW register. t = PWT1 x T run clock */
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#define PATTERN_WAIT_TIMER_4_LSB_REG (0x8F << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_TIMER_4_MSB_REG (0x90 << MEM_MAP_SHIFT)
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/* Pattern Wait Timer 5 64 bit RW register. t = PWT1 x T run clock */
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#define PATTERN_WAIT_TIMER_5_LSB_REG (0x91 << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_TIMER_5_MSB_REG (0x92 << MEM_MAP_SHIFT)
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/** I2C Control register */
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#define I2C_TRANSFER_COMMAND_FIFO_REG (0x100 << MEM_MAP_SHIFT)
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#define I2C_RX_DATA_FIFO_REG (0x101 << MEM_MAP_SHIFT)
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@ -5,7 +5,7 @@
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#include "sls/sls_detector_defs.h"
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#define MIN_REQRD_VRSN_T_RD_API 0x181130
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#define REQRD_FRMWR_VRSN 0x201005
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#define REQRD_FRMWR_VRSN 0x220714
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#define LINKED_SERVER_NAME "ctbDetectorServer"
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