8.0.2.rc: m3 clkdiv0 20 (#923)

* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20
This commit is contained in:
2024-07-25 17:17:20 +02:00
committed by GitHub
parent 61e9437842
commit 8d185988c1
6 changed files with 10 additions and 2 deletions

View File

@ -7,7 +7,7 @@
#define APIGOTTHARD "8.0.0 0x231109"
#define APIGOTTHARD2 "8.0.0 0x231109"
#define APIJUNGFRAU "8.0.0 0x231109"
#define APIMYTHEN3 "8.0.0 0x231109"
#define APIEIGER "8.0.0 0x231109"
#define APILIB "8.0.1 0x240112"
#define APIMOENCH "8.0.2 0x240703"
#define APIMYTHEN3 "8.0.2 0x240715"