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8.0.2.rc: m3 clkdiv0 20 (#923)

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* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20
This commit is contained in:
maliakal_d
2024-07-25 17:17:20 +02:00
committed by GitHub
parent 61e9437842
commit 8d185988c1
6 changed files with 10 additions and 2 deletions
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BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServerv8.0.0 → slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServerv8.0.2
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6
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -479,6 +479,11 @@ void setupDetector() {
READOUT_PLL_VCO_FREQ_HZ, SYSTEM_PLL_VCO_FREQ_HZ);
ALTERA_PLL_C10_ResetPLL(READOUT_PLL);
ALTERA_PLL_C10_ResetPLL(SYSTEM_PLL);
// change startup clock divider in software
// because firmware only sets max clock divider
setClockDividerWithTimeUpdateOption(READOUT_C0, DEFAULT_READOUT_C0_STARTUP,
0);
// hv
DAC6571_SetDefines(HV_HARD_MAX_VOLTAGE, HV_DRIVER_FILE_NAME);
// dac
@ -2331,6 +2336,7 @@ int setClockDividerWithTimeUpdateOption(enum CLKINDEX ind, int val,
return FAIL;
}
if (val < 2 || val > getMaxClockDivider()) {
LOG(logERROR, ("Invalid clock divider %d\n", val));
return FAIL;
}
char *clock_names[] = {CLK_NAMES};

2
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -64,6 +64,8 @@
#define DEFAULT_SYSTEM_C2 (5) //(200000000) // smp_clk, 200 MHz const
#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz
#define DEFAULT_READOUT_C0_STARTUP (20) //(50000000) // rdo_clk, 50 MHz
#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
#define DEFAULT_ADIF_PIPELINE_VAL (8)