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8.0.2.rc: m3 clkdiv0 20 (#923)

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* m3: clk 0 changed from 10 to 20 (100MHz to 50MHz)

* g2: startup clk div back to 10 as in firmware but setting in software startup to 20
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maliakal_d
2024-07-25 17:17:20 +02:00
committed by GitHub
parent 61e9437842
commit 8d185988c1
6 changed files with 10 additions and 2 deletions
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serverBin/mythen3DetectorServerv8.0.0
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../slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServerv8.0.0

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serverBin/mythen3DetectorServerv8.0.2 Symbolic link
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../slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServerv8.0.2