detectors/slsDetectorPackage
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merge from developer

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maliakal_d
2020-01-22 17:30:13 +01:00
parent 981b13494c ffc09ed19c
commit 8cbf3c62a9
36 changed files with 1260 additions and 404 deletions
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13
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
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@ -4,10 +4,13 @@
#define REG_OFFSET (4)
/* Base addresses 0x1804 0000 ---------------------------------------------*/
/* Reconfiguration core for readout pll */
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
/* Reconfiguration core for system pll */
#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
/* Clock Generation */
#define BASE_CLK_GENERATION (0x1000) // 0x1804_1000 - 0x1804_XXXX //TODO
@ -160,15 +163,15 @@
#define PAT_STATUS_REG (0x00 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PAT_STATUS_RUN_BUSY_OFST (0)
#define PAT_STATUS_RUN_BUSY_MSK (0x00000001 << PAT_STATUS_RUN_BUSY_OFST)
#define PAT_STATUS_WAIT_FOR_TRGGR_OFST (0)
#define PAT_STATUS_WAIT_FOR_TRGGR_OFST (3)
#define PAT_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << PAT_STATUS_WAIT_FOR_TRGGR_OFST)
#define PAT_STATUS_DLY_BFRE_TRGGR_OFST (0)
#define PAT_STATUS_DLY_BFRE_TRGGR_OFST (4)
#define PAT_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_BFRE_TRGGR_OFST)
#define PAT_STATUS_FIFO_FULL_OFST (0)
#define PAT_STATUS_FIFO_FULL_OFST (5)
#define PAT_STATUS_FIFO_FULL_MSK (0x00000001 << PAT_STATUS_FIFO_FULL_OFST)
#define PAT_STATUS_DLY_AFTR_TRGGR_OFST (0)
#define PAT_STATUS_DLY_AFTR_TRGGR_OFST (15)
#define PAT_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_AFTR_TRGGR_OFST)
#define PAT_STATUS_CSM_BUSY_OFST (0)
#define PAT_STATUS_CSM_BUSY_OFST (17)
#define PAT_STATUS_CSM_BUSY_MSK (0x00000001 << PAT_STATUS_CSM_BUSY_OFST)
/* Delay left 64bit Register */

BIN
slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServer_developer
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50
slsDetectorServers/mythen3DetectorServer/slsDetectorFunctionList.c
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@ -33,12 +33,12 @@ int virtual_status = 0;
int virtual_stop = 0;
#endif
int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0, 0, 0};
uint32_t clkFrequency[NUM_CLOCKS] = {0, 0, 0, 0, 0};
int32_t clkPhase[NUM_CLOCKS] = {};
uint32_t clkFrequency[NUM_CLOCKS] = {};
int highvoltage = 0;
int dacValues[NDAC] = {0};
int detPos[2] = {0, 0};
int detPos[2] = {};
uint32_t countermask = 0; // will be removed later when in firmware converted to mask
int isInitCheckDone() {
@ -85,13 +85,10 @@ void basictests() {
uint64_t macadd = getDetectorMAC();
int64_t fwversion = getFirmwareVersion();
int64_t swversion = getServerVersion();
int64_t sw_fw_apiversion = 0;
int64_t sw_fw_apiversion = getFirmwareAPIVersion();;
int64_t client_sw_apiversion = getClientServerAPIVersion();
uint32_t requiredFirmwareVersion = REQRD_FRMWRE_VRSN;
if (fwversion >= MIN_REQRD_VRSN_T_RD_API)
sw_fw_apiversion = getFirmwareAPIVersion();
FILE_LOG(logINFOBLUE, ("*************************************************\n"
"Hardware Version:\t\t 0x%x\n"
@ -162,7 +159,7 @@ int checkType() {
#ifdef VIRTUAL
return OK;
#endif
volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
if (type != MYTHEN3){
FILE_LOG(logERROR, ("This is not a Mythen3 Server (read %d, expected %d)\n", type, MYTHEN3));
return FAIL;
@ -610,7 +607,6 @@ int setDelayAfterTrigger(int64_t val) {
int64_t getDelayAfterTrigger() {
return get64BitReg(SET_TRIGGER_DELAY_LSB_REG, SET_TRIGGER_DELAY_MSB_REG) / (1E-9 * FIXED_PLL_FREQUENCY);
}
int64_t getNumFramesLeft() {
@ -708,7 +704,7 @@ int setHighVoltage(int val){
/* parameters - timing */
void setTiming( enum timingMode arg){
if(arg != GET_TIMING_MODE){
switch((int)arg){
switch (arg) {
case AUTO_TIMING:
FILE_LOG(logINFO, ("Set Timing: Auto\n"));
bus_w(EXT_SIGNAL_REG, bus_r(EXT_SIGNAL_REG) & ~EXT_SIGNAL_MSK);
@ -719,7 +715,6 @@ void setTiming( enum timingMode arg){
break;
default:
FILE_LOG(logERROR, ("Unknown timing mode %d\n", arg));
return;
}
}
}
@ -727,7 +722,7 @@ void setTiming( enum timingMode arg){
enum timingMode getTiming() {
if (bus_r(EXT_SIGNAL_REG) == EXT_SIGNAL_MSK)
return TRIGGER_EXPOSURE;
return AUTO_TIMING;
return AUTO_TIMING;
}
@ -1143,7 +1138,7 @@ int checkDetectorType() {
}
if (abs(type - TYPE_MYTHEN3_MODULE_VAL) > TYPE_TOLERANCE) {
FILE_LOG(logERROR, ("Wrong Module attached! Expected %d for Mythen, got %d\n", TYPE_MYTHEN3_MODULE_VAL, type));
FILE_LOG(logERROR, ("Wrong Module attached! Expected %d for Mythen3, got %d\n", TYPE_MYTHEN3_MODULE_VAL, type));
return FAIL;
}
return OK;
@ -1204,8 +1199,8 @@ int setPhase(enum CLKINDEX ind, int val, int degrees) {
relativePhase *= -1;
direction = 0;
}
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
ALTERA_PLL_C10_SetPhaseShift(pllIndex, clkIndex, relativePhase, direction);
clkPhase[ind] = valShift;
@ -1277,7 +1272,7 @@ int getVCOFrequency(enum CLKINDEX ind) {
FILE_LOG(logERROR, ("Unknown clock index %d to get vco frequency\n", ind));
return -1;
}
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
return ALTERA_PLL_C10_GetVCOFrequency(pllIndex);
}
@ -1295,7 +1290,7 @@ int setClockDivider(enum CLKINDEX ind, int val) {
}
char* clock_names[] = {CLK_NAMES};
int vcofreq = getVCOFrequency(ind);
int currentdiv = vcofreq / clkFrequency[ind];
int currentdiv = vcofreq / (int)clkFrequency[ind];
int newfreq = vcofreq / val;
FILE_LOG(logINFO, ("\tSetting %s clock (%d) divider from %d (%d Hz) to %d (%d Hz). \n\t(Vcofreq: %d Hz)\n", clock_names[ind], ind, currentdiv, clkFrequency[ind], val, newfreq, vcofreq));
@ -1310,8 +1305,8 @@ int setClockDivider(enum CLKINDEX ind, int val) {
}
// Calculate and set output frequency
int pllIndex = ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL;
int clkIndex = ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind;
int pllIndex = (int)(ind >= SYSTEM_C0 ? SYSTEM_PLL : READOUT_PLL);
int clkIndex = (int)(ind >= SYSTEM_C0 ? ind - SYSTEM_C0 : ind);
ALTERA_PLL_C10_SetOuputFrequency (pllIndex, clkIndex, newfreq);
clkFrequency[ind] = newfreq;
FILE_LOG(logINFO, ("\t%s clock (%d) divider set to %d (%d Hz)\n", clock_names[ind], ind, val, clkFrequency[ind]));
@ -1345,7 +1340,7 @@ int getClockDivider(enum CLKINDEX ind) {
FILE_LOG(logERROR, ("Unknown clock index %d to get clock divider\n", ind));
return -1;
}
return (getVCOFrequency(ind) / clkFrequency[ind]);
return (getVCOFrequency(ind) / (int)clkFrequency[ind]);
}
/* aquisition */
@ -1482,7 +1477,7 @@ int stopStateMachine(){
#endif
//stop state machine
bus_w(CONTROL_REG, bus_r(CONTROL_REG) | CONTROL_STP_ACQSTN_MSK);
FILE_LOG(logINFO, ("Status Register: %08x\n",bus_r(STATUS_REG)));
FILE_LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
return OK;
}
@ -1539,7 +1534,7 @@ enum runStatus getRunStatus(){
return s;
}
void readFrame(int *ret, char *mess){
void readFrame(int *ret, char *mess) {
// wait for status to be done
while(runBusy()){
usleep(500);
@ -1559,7 +1554,6 @@ void readFrame(int *ret, char *mess){
} else {
FILE_LOG(logINFOGREEN, ("Acquisition successfully finished\n"));
}
}
u_int32_t runBusy() {
@ -1573,11 +1567,11 @@ u_int32_t runBusy() {
/* common */
int calculateDataBytes(){
int calculateDataBytes() {
return 0;
}
int getTotalNumberOfChannels(){return ((int)getNumberOfChannelsPerChip() * (int)getNumberOfChips());}
int getNumberOfChips(){return NCHIP;}
int getNumberOfDACs(){return NDAC;}
int getNumberOfChannelsPerChip(){return NCHAN;}
int getTotalNumberOfChannels() {return (getNumberOfChannelsPerChip() * getNumberOfChips());}
int getNumberOfChips() {return NCHIP;}
int getNumberOfDACs() {return NDAC;}
int getNumberOfChannelsPerChip() {return NCHAN;}

4
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -2,7 +2,6 @@
#include "sls_detector_defs.h"
#define REQRD_FRMWRE_VRSN 0x190000
#define MIN_REQRD_VRSN_T_RD_API 0x190000
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
@ -46,7 +45,6 @@
#define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
#define SYSTEM_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
#define WAIT_TIME_US_STP_ACQ (100)
/** Other Definitions */
#define BIT16_MASK (0xFFFF)
@ -99,4 +97,4 @@ typedef struct udp_header_struct {
uint16_t udp_destport;
} udp_header;
#define UDP_IP_HEADER_LENGTH_BYTES (28)
#define PACKETS_PER_FRAME (2)
#define PACKETS_PER_FRAME (2)