mythen3: fix of external signals to not allow master output inversion, but can edge detect not configurable, and default dout pulse length

This commit is contained in:
maliakal_d 2020-05-28 13:09:09 +02:00
parent 754536898a
commit 8aa7144252
6 changed files with 51 additions and 20 deletions

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@ -186,12 +186,16 @@
/** DOUTIF1 Master Ouput Register */ /** DOUTIF1 Master Ouput Register */
#define DOUTIF1_REG (0x01 * REG_OFFSET + BASE_PIPELINE) #define DOUTIF1_REG (0x01 * REG_OFFSET + BASE_PIPELINE)
#define DOUTIF1_BYPASS_OFST (0) #define DOUTIF1_TRIGGER_BYPASS_OFST (0)
#define DOUTIF1_BYPASS_MSK (0x0000000F << DOUTIF1_BYPASS_OFST) #define DOUTIF1_TRIGGER_BYPASS_MSK (0x00000001 << DOUTIF1_TRIGGER_BYPASS_OFST)
#define DOUTIF1_BYPASS_GATE_OFST (1)
#define DOUTIF1_BYPASS_GATE_MSK (0x00000007 << DOUTIF1_BYPASS_GATE_OFST)
#define DOUTIF1_INVERSION_OFST (4) #define DOUTIF1_INVERSION_OFST (4)
#define DOUTIF1_INVERSION_MSK (0x0000000F << DOUTIF1_INVERSION_OFST) #define DOUTIF1_INVERSION_MSK (0x0000000F << DOUTIF1_INVERSION_OFST)
#define DOUTIF1_RISING_OFST (8) #define DOUTIF1_RISING_TRIGGER_OFST (8)
#define DOUTIF1_RISING_MSK (0x0000000F << DOUTIF1_RISING_OFST) #define DOUTIF1_RISING_TRIGGER_MSK (0x00000001 << DOUTIF1_RISING_TRIGGER_OFST)
#define DOUTIF1_RISING_GATE_OFST (9)
#define DOUTIF1_RISING_GATE_MSK (0x00000007 << DOUTIF1_RISING_GATE_OFST)
#define DOUTIF1_FALLING_OFST (12) #define DOUTIF1_FALLING_OFST (12)
#define DOUTIF1_FALLING_MSK (0x0000000F << DOUTIF1_FALLING_OFST) #define DOUTIF1_FALLING_MSK (0x0000000F << DOUTIF1_FALLING_OFST)
@ -211,13 +215,13 @@
#define DOUTIF_RISING_LNGTH_REG (0x03 * REG_OFFSET + BASE_PIPELINE) #define DOUTIF_RISING_LNGTH_REG (0x03 * REG_OFFSET + BASE_PIPELINE)
#define DOUTIF_RISING_LNGTH_PORT_1_OFST (0) #define DOUTIF_RISING_LNGTH_PORT_1_OFST (0)
#define DOUTIF_RISING_LNGTH_PORT_1_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_1_OFST) #define DOUTIF_RISING_LNGTH_PORT_1_MSK (0x000000FF << DOUTIF_RISING_LNGTH_PORT_1_OFST)
#define DOUTIF_RISING_LNGTH_PORT_2_OFST (0) #define DOUTIF_RISING_LNGTH_PORT_2_OFST (8)
#define DOUTIF_RISING_LNGTH_PORT_2_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_2_OFST) #define DOUTIF_RISING_LNGTH_PORT_2_MSK (0x000000FF << DOUTIF_RISING_LNGTH_PORT_2_OFST)
#define DOUTIF_RISING_LNGTH_PORT_3_OFST (0) #define DOUTIF_RISING_LNGTH_PORT_3_OFST (16)
#define DOUTIF_RISING_LNGTH_PORT_3_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_3_OFST) #define DOUTIF_RISING_LNGTH_PORT_3_MSK (0x000000FF << DOUTIF_RISING_LNGTH_PORT_3_OFST)
#define DOUTIF_RISING_LNGTH_PORT_4_OFST (0) #define DOUTIF_RISING_LNGTH_PORT_4_OFST (24)
#define DOUTIF_RISING_LNGTH_PORT_4_MSK (0x0000000F << DOUTIF_RISING_LNGTH_PORT_4_OFST) #define DOUTIF_RISING_LNGTH_PORT_4_MSK (0x000000FF << DOUTIF_RISING_LNGTH_PORT_4_OFST)
/* ASIC Exposure Control registers /* ASIC Exposure Control registers

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@ -1245,14 +1245,28 @@ enum timingMode getTiming() {
void setInitialExtSignals() { void setInitialExtSignals() {
LOG(logINFOBLUE, ("Setting Initial External Signals\n")); LOG(logINFOBLUE, ("Setting Initial External Signals\n"));
// default, everything is 0 // default, everything is 0
bus_w(DINF1_REG, 0);
bus_w(DOUTIF1_REG, 0);
bus_w(DINF2_REG, 0);
bus_w(DOUTIF_RISING_LNGTH_REG, 0);
// bypass everything // bypass everything
// (except master input can edge detect) // (except master triggers can edge detect)
bus_w(DINF1_REG, DINF1_BYPASS_GATE_MSK); bus_w(DINF1_REG, DINF1_BYPASS_GATE_MSK);
bus_w(DOUTIF1_REG, DOUTIF1_BYPASS_MSK); bus_w(DOUTIF1_REG, DOUTIF1_BYPASS_GATE_MSK);
bus_w(DINF2_REG, DINF2_BYPASS_MSK); bus_w(DINF2_REG, DINF2_BYPASS_MSK);
// master input can edge detect, so rising is 1 // master input/output can edge detect, so rising is 1
bus_w(DINF1_REG, bus_r(DINF1_REG) | DINF1_RISING_TRIGGER_MSK); bus_w(DINF1_REG, bus_r(DINF1_REG) | DINF1_RISING_TRIGGER_MSK);
bus_w(DOUTIF1_REG, bus_r(DOUTIF1_REG) | DOUTIF1_RISING_TRIGGER_MSK);
// set default value for master output rising pulse length for port1
bus_w(DOUTIF_RISING_LNGTH_REG,
bus_r(DOUTIF_RISING_LNGTH_REG) & ~DOUTIF_RISING_LNGTH_PORT_1_MSK);
bus_w(DOUTIF_RISING_LNGTH_REG, bus_r(DOUTIF_RISING_LNGTH_REG) |
((DEFAULT_MSTR_OTPT_P1_NUM_PULSES
<< DOUTIF_RISING_LNGTH_PORT_1_OFST) &
DOUTIF_RISING_LNGTH_PORT_1_MSK));
} }
void setExtSignal(int signalIndex, enum externalSignalFlag mode) { void setExtSignal(int signalIndex, enum externalSignalFlag mode) {

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@ -41,6 +41,7 @@
#define DEFAULT_SYSTEM_C1 (10) //(125000000) // chip_clk, 125 MHz #define DEFAULT_SYSTEM_C1 (10) //(125000000) // chip_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (10) //(125000000) // sync_clk, 125 MHz #define DEFAULT_SYSTEM_C2 (10) //(125000000) // sync_clk, 125 MHz
#define DEFAULT_ASIC_LATCHING_NUM_PULSES (10) #define DEFAULT_ASIC_LATCHING_NUM_PULSES (10)
#define DEFAULT_MSTR_OTPT_P1_NUM_PULSES (20)
/* Firmware Definitions */ /* Firmware Definitions */
#define IP_HEADER_SIZE (20) #define IP_HEADER_SIZE (20)

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@ -517,6 +517,15 @@ int set_external_signal_flag(int file_des) {
functionNotImplemented(); functionNotImplemented();
#else #else
if (Server_VerifyLock() == OK) { if (Server_VerifyLock() == OK) {
#ifdef MYTHEN3D
// to be implemented in hardware as busy configurable
if (signalIndex == 4) {
ret = FAIL;
sprintf(mess, "Signal index %d not configurable yet\n",
signalIndex);
LOG(logERROR, (mess));
} else
#endif
if (signalIndex < 0 || signalIndex >= MAX_EXT_SIGNALS) { if (signalIndex < 0 || signalIndex >= MAX_EXT_SIGNALS) {
ret = FAIL; ret = FAIL;
sprintf(mess, "Signal index %d can only be between 0 and %d\n", sprintf(mess, "Signal index %d can only be between 0 and %d\n",

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@ -923,9 +923,11 @@ class Detector {
/** [Gotthard] signal index is 0 /** [Gotthard] signal index is 0
* Options: TRIGGER_IN_RISING_EDGE, TRIGGER_IN_FALLING_EDGE * Options: TRIGGER_IN_RISING_EDGE, TRIGGER_IN_FALLING_EDGE
* [Mythen3] signal index 0-3 for master input, 4-7 master output signals * [Mythen3] signal index 0 is master input trigger signal, 1-3 for master
* Options: TRIGGER_IN_RISING_EDGE, TRIGGER_IN_FALLING_EDGE (for master * input gate signals, 4 is busy out signal, 5-7 is master output gate
* input trigger only), INVERSION_ON, INVERSION_OFF */ * signals.
* Options: TRIGGER_IN_RISING_EDGE, TRIGGER_IN_FALLING_EDGE (for
* master input trigger only), INVERSION_ON, INVERSION_OFF */
void setExternalSignalFlags(int signalIndex, defs::externalSignalFlag value, void setExternalSignalFlags(int signalIndex, defs::externalSignalFlag value,
Positions pos = {}); Positions pos = {});

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@ -766,8 +766,9 @@ std::string CmdProxy::ExternalSignal(int action) {
"[trigger_in_rising_edge|trigger_in_falling_edge]" "[trigger_in_rising_edge|trigger_in_falling_edge]"
"\n\t[Mythen3] [0-7] " "\n\t[Mythen3] [0-7] "
"[trigger_in_rising_edge|trigger_in_falling_edge|inversion_on|" "[trigger_in_rising_edge|trigger_in_falling_edge|inversion_on|"
"inversion_off]\n\t where 0-3 is master input signals and 4-7 is " "inversion_off]\n\t where 0 is master input trigger signal, 1-3 "
"master output signals" "is master input gate signals, 4 is busy out signal and 5-7 is "
"master output gate signals"
<< '\n'; << '\n';
} else if (action == defs::GET_ACTION) { } else if (action == defs::GET_ACTION) {
if (args.size() != 1) { if (args.size() != 1) {