diff --git a/slsDetectorSoftware/slsDetectorAnalysis/energyConversion.cpp b/slsDetectorSoftware/slsDetectorAnalysis/energyConversion.cpp
index f6f7cd061..9bfd59f23 100644
--- a/slsDetectorSoftware/slsDetectorAnalysis/energyConversion.cpp
+++ b/slsDetectorSoftware/slsDetectorAnalysis/energyConversion.cpp
@@ -74,173 +74,233 @@ int energyConversion::writeCalibrationFile(string fname, double gain, double off
 
 
 slsDetectorDefs::sls_detector_module* energyConversion::readSettingsFile(string fname,  detectorType myDetectorType, sls_detector_module *myMod){
-  
-  int nflag=0;
 
-      
-  if (myMod==NULL) {
-    myMod=createModule(myDetectorType);
-    nflag=1;
-  }
-
-  string myfname;
-  string str;
-  ifstream infile;
-  ostringstream oss;
-  int iline=0;
-  string sargname;
-  int ival;
-  int ichan=0, ichip=0, idac=0;
-  int nch=((myMod->nchan)/(myMod->nchip));
- 
-
-#ifdef VERBOSE
-  std::cout<<   "reading settings file for module number "<< myMod->module << std::endl;
-#endif
-  myfname=fname;
-#ifdef VERBOSE
-  std::cout<< "file name is "<< myfname <<   std::endl;
-#endif
-  infile.open(myfname.c_str(), ios_base::in);
-  if (infile.is_open()) {
+	int nflag=0;
 
 
-    switch (myDetectorType) {
-
-    case MYTHEN:
-	
-      for (int iarg=0; iarg<myMod->ndac; iarg++) {
-	getline(infile,str);
-	iline++;
-	istringstream ssstr(str);
-	ssstr >> sargname >> ival;
-#ifdef VERBOSE
-	std::cout<< sargname << " dac nr. " << idac << " is " << ival << std::endl;
-#endif
-	myMod->dacs[idac]=ival;
-	idac++;
-      }
-      for (ichip=0; ichip<myMod->nchip; ichip++) { 
-	getline(infile,str); 
-	iline++;
-#ifdef VERBOSE
-	//	  std::cout<< str << std::endl;
-#endif
-	istringstream ssstr(str);
-	ssstr >> sargname >> ival;
-#ifdef VERBOSE
-	//	  std::cout<< "chip " << ichip << " " << sargname << " is " << ival << std::endl;
-#endif
-	  
-	myMod->chipregs[ichip]=ival;
-	for (ichan=0; ichan<nch; ichan++) {
-	  getline(infile,str); 
-#ifdef VERBOSE
-	  // std::cout<< str << std::endl;
-#endif
-	  istringstream ssstr(str);
-	    
-#ifdef VERBOSE
-	  //   std::cout<< "channel " << ichan+ichip*thisDetector->nChans <<" iline " << iline<< std::endl;
-#endif
-	  iline++;
-	  myMod->chanregs[ichip*nch+ichan]=0;
-	  for (int iarg=0; iarg<6 ; iarg++) {
-	    ssstr >>  ival; 
-	    //if (ssstr.good()) {
-	    switch (iarg) {
-	    case 0:
-#ifdef VERBOSE
-	      //		 std::cout<< "trimbits " << ival ;
-#endif
-	      myMod->chanregs[ichip*nch+ichan]|=ival&TRIMBITMASK;
-	      break;
-	    case 1:
-#ifdef VERBOSE
-	      //std::cout<< " compen " << ival ;
-#endif
-	      myMod->chanregs[ichip*nch+ichan]|=ival<<9;
-	      break;
-	    case 2:
-#ifdef VERBOSE
-	      //std::cout<< " anen " << ival ;
-#endif
-	      myMod->chanregs[ichip*nch+ichan]|=ival<<8;
-	      break;
-	    case 3:
-#ifdef VERBOSE
-	      //std::cout<< " calen " << ival  ;
-#endif
-	      myMod->chanregs[ichip*nch+ichan]|=ival<<7;
-	      break;
-	    case 4:
-#ifdef VERBOSE
-	      //std::cout<< " outcomp " << ival  ;
-#endif
-	      myMod->chanregs[ichip*nch+ichan]|=ival<<10;
-	      break;
-	    case 5:
-#ifdef VERBOSE
-	      //std::cout<< " counts " << ival  << std::endl;
-#endif
-	      myMod->chanregs[ichip*nch+ichan]|=ival<<11;
-	      break;
-	    default:
-	      std::cout<< " too many columns" << std::endl; 
-	      break;
-	    }
-	  }
+	if (myMod==NULL) {
+		myMod=createModule(myDetectorType);
+		nflag=1;
 	}
-	//	}
-      }
+
+	int id=0,i;
+	string names[100];
+	string myfname;
+	string str;
+	ifstream infile;
+	ostringstream oss;
+	int iline=0;
+	string sargname;
+	int ival;
+	int ichan=0, ichip=0, idac=0;
+	int nch=((myMod->nchan)/(myMod->nchip));
+
+
+	//to verify dac
+	switch (myDetectorType) {
+	case MYTHEN:
+		break;
+	case MOENCH:
+	case GOTTHARD:
+		names[id++]="Vref";
+		names[id++]="VcascN";
+		names[id++]="VcascP";
+		names[id++]="Vout";
+		names[id++]="Vcasc";
+		names[id++]="Vin";
+		names[id++]="Vref_comp";
+		names[id++]="Vib_test";
+		break;
+	case EIGER:
+		names[id++]="SvP";
+		names[id++]="SvN";
+		names[id++]="Vtr";
+		names[id++]="Vrf";
+		names[id++]="Vrs";
+		names[id++]="Vin";
+		names[id++]="Vtgstv";
+		names[id++]="Vcmp_ll";
+		names[id++]="Vcmp_lr";
+		names[id++]="cal";
+		names[id++]="Vcmp_rl";
+		names[id++]="Vcmp_rr";
+		names[id++]="rxb_rb";
+		names[id++]="rxb_lb";
+		names[id++]="Vcmp_lr";
+		names[id++]="Vcp";
+		names[id++]="Vcmp_rl";
+		names[id++]="Vcn";
+		names[id++]="Vis";
+		names[id++]="iodelay";
+		break;
+	default:
+		cout << "Unknown detector type - unknown format for settings file" << endl;
+		return NULL;
+	}
+
 #ifdef VERBOSE
-      std::cout<< "read " << ichan*ichip << " channels" <<std::endl; 
+	std::cout<<   "reading settings file for module number "<< myMod->module << std::endl;
+#endif
+	myfname=fname;
+#ifdef VERBOSE
+	std::cout<< "file name is "<< myfname <<   std::endl;
+#endif
+	infile.open(myfname.c_str(), ios_base::in);
+	if (infile.is_open()) {
+
+
+		switch (myDetectorType) {
+
+		case MYTHEN:
+
+			for (int iarg=0; iarg<myMod->ndac; iarg++) {
+				getline(infile,str);
+				iline++;
+				istringstream ssstr(str);
+				ssstr >> sargname >> ival;
+#ifdef VERBOSE
+				std::cout<< sargname << " dac nr. " << idac << " is " << ival << std::endl;
+#endif
+				myMod->dacs[idac]=ival;
+				idac++;
+			}
+			for (ichip=0; ichip<myMod->nchip; ichip++) {
+				getline(infile,str);
+				iline++;
+#ifdef VERBOSE
+				//	  std::cout<< str << std::endl;
+#endif
+				istringstream ssstr(str);
+				ssstr >> sargname >> ival;
+#ifdef VERBOSE
+				//	  std::cout<< "chip " << ichip << " " << sargname << " is " << ival << std::endl;
+#endif
+
+				myMod->chipregs[ichip]=ival;
+				for (ichan=0; ichan<nch; ichan++) {
+					getline(infile,str);
+#ifdef VERBOSE
+					// std::cout<< str << std::endl;
+#endif
+					istringstream ssstr(str);
+
+#ifdef VERBOSE
+					//   std::cout<< "channel " << ichan+ichip*thisDetector->nChans <<" iline " << iline<< std::endl;
+#endif
+					iline++;
+					myMod->chanregs[ichip*nch+ichan]=0;
+					for (int iarg=0; iarg<6 ; iarg++) {
+						ssstr >>  ival;
+						//if (ssstr.good()) {
+						switch (iarg) {
+						case 0:
+#ifdef VERBOSE
+							//		 std::cout<< "trimbits " << ival ;
+#endif
+							myMod->chanregs[ichip*nch+ichan]|=ival&TRIMBITMASK;
+							break;
+						case 1:
+#ifdef VERBOSE
+							//std::cout<< " compen " << ival ;
+#endif
+							myMod->chanregs[ichip*nch+ichan]|=ival<<9;
+							break;
+						case 2:
+#ifdef VERBOSE
+							//std::cout<< " anen " << ival ;
+#endif
+							myMod->chanregs[ichip*nch+ichan]|=ival<<8;
+							break;
+						case 3:
+#ifdef VERBOSE
+							//std::cout<< " calen " << ival  ;
+#endif
+							myMod->chanregs[ichip*nch+ichan]|=ival<<7;
+							break;
+						case 4:
+#ifdef VERBOSE
+							//std::cout<< " outcomp " << ival  ;
+#endif
+							myMod->chanregs[ichip*nch+ichan]|=ival<<10;
+							break;
+						case 5:
+#ifdef VERBOSE
+							//std::cout<< " counts " << ival  << std::endl;
+#endif
+							myMod->chanregs[ichip*nch+ichan]|=ival<<11;
+							break;
+						default:
+							std::cout<< " too many columns" << std::endl;
+							break;
+						}
+					}
+				}
+				//	}
+			}
+#ifdef VERBOSE
+			std::cout<< "read " << ichan*ichip << " channels" <<std::endl;
 #endif
 
 
-      break;
+			break;
 
-    case MOENCH:
-    case GOTTHARD:
-      //---------------dacs---------------
-      for (int iarg=0; iarg<myMod->ndac; iarg++) {
-	getline(infile,str);
-	iline++;
+		case EIGER:
+		case MOENCH:
+		case GOTTHARD:
+			//---------------dacs---------------
+			while(infile.good()) {
+				getline(infile,str);
+				iline++;
 #ifdef VERBOSE
-	std::cout<< str << std::endl;
+				std::cout<< str << std::endl;
 #endif
-	istringstream ssstr(str);
-	ssstr >> sargname >> ival;
+				istringstream ssstr(str);
+				ssstr >> sargname >> ival;
+				for (i=0;i<id;i++){
+					if (!strcasecmp(sargname.c_str(),names[i].c_str())){
+						myMod->dacs[i]=ival;
+						idac++;
 #ifdef VERBOSE
-	std::cout<< sargname << " dac nr. " << idac << " is " << ival << std::endl;
+						std::cout<< sargname << " dac nr. " << idac << " is " << ival << std::endl;
 #endif
-	myMod->dacs[idac]=ival;
-	idac++;
-      }
-      break;
-	
+						break;
+					}
+				}
+				if (i < id) {
+#ifdef VERBOSE
+					std::cout<< sargname << " dac nr. " << idac << " is " << ival << std::endl;
+#endif
+				}else{
+					std::cout<< "Unknown dac " << sargname << std::endl;
+					infile.close();
+					deleteModule(myMod);
+					return NULL;
+				}
+			}
+			break;
 
-    default:
-      std::cout<< "Unknown detector type - don't know how to read file" <<  myfname << std::endl;
-      infile.close();
-      deleteModule(myMod);
-      return NULL;
 
-    }
+		default:
+			std::cout<< "Unknown detector type - don't know how to read file" <<  myfname << std::endl;
+			infile.close();
+			deleteModule(myMod);
+			return NULL;
 
-    infile.close();
-    strcpy(settingsFile,fname.c_str());
-    return myMod;
+		}
 
-  } else {
-    std::cout<< "could not open settings file " <<  myfname << std::endl;
-      
-    if (nflag)
-      deleteModule(myMod);
+		infile.close();
+		strcpy(settingsFile,fname.c_str());
+		return myMod;
+
+	} else {
+		std::cout<< "could not open settings file " <<  myfname << std::endl;
+
+		if (nflag)
+			deleteModule(myMod);
+
+		return NULL;
+	}
 
-    return NULL;
-  }
- 
 };
 
 
@@ -273,6 +333,28 @@ int energyConversion::writeSettingsFile(string fname, detectorType myDetectorTyp
     names[id++]="Vref_comp";
     names[id++]="Vib_test";
     break;
+  case EIGER:
+	names[id++]="SvP";
+	names[id++]="SvN";
+	names[id++]="Vtr";
+	names[id++]="Vrf";
+	names[id++]="Vrs";
+	names[id++]="Vin";
+	names[id++]="Vtgstv";
+	names[id++]="Vcmp_ll";
+	names[id++]="Vcmp_lr";
+	names[id++]="cal";
+	names[id++]="Vcmp_rl";
+	names[id++]="Vcmp_rr";
+	names[id++]="rxb_rb";
+	names[id++]="rxb_lb";
+	names[id++]="Vcmp_lr";
+	names[id++]="Vcp";
+	names[id++]="Vcmp_rl";
+	names[id++]="Vcn";
+	names[id++]="Vis";
+	names[id++]="iodelay";
+	break;
   default:
     cout << "Unknown detector type - unknown format for settings file" << endl;
     return FAIL;
@@ -289,7 +371,7 @@ int energyConversion::writeSettingsFile(string fname, detectorType myDetectorTyp
       outfile << names[idac] << " " << iv << std::endl;
     }
       
-    if((myDetectorType!=GOTTHARD)&&(myDetectorType!=MOENCH)){
+    if((myDetectorType!=GOTTHARD)&&(myDetectorType!=MOENCH)&&(myDetectorType!=EIGER)){
       for (ichip=0; ichip<mod.nchip; ichip++) {
 	iv1=mod.chipregs[ichip]&1;
 	outfile << names[idac] << " " << iv1 << std::endl;