merging refactor (replacing)

slsDetectorServers/gotthardDetectorServer/.target-makefrag

@@ -0,0 +1 @@
+AXIS_BUILDTYPE ?= cris-axis-linux-gnu

slsDetectorServers/gotthardDetectorServer/AD9252.h

@@ -0,0 +1 @@
+../slsDetectorServer/AD9252.h

slsDetectorServers/gotthardDetectorServer/AD9257.h

@@ -0,0 +1 @@
+../slsDetectorServer/AD9257.h

slsDetectorServers/gotthardDetectorServer/LTC2620.h

@@ -0,0 +1 @@
+../slsDetectorServer/LTC2620.h

slsDetectorServers/gotthardDetectorServer/Makefile

@@ -0,0 +1,37 @@
+CROSS  		= 	bfin-uclinux-
+CC    		= 	$(CROSS)gcc
+CFLAGS 		+=	-Wall  -DGOTTHARDD  -DSTOP_SERVER  # -DVERBOSE 
+LDLIBS		+= 	-lm  -lstdc++ 
+
+PROGS		= 	gotthardDetectorServer 
+DESTDIR		?= 	bin
+INSTMODE	= 	0777
+
+SRCS 		= 	communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c  slsDetectorFunctionList.c 
+OBJS 		= 	$(SRCS:%.c=%.o)
+
+
+all: clean versioning $(PROGS) 
+
+boot: $(OBJS)
+
+version_name=APIGOTTHARD
+version_path=slsDetectorServers/gotthardDetectorServer
+versioning: 
+	cd ../../ && echo $(PWD) && echo `tput setaf 6; ./updateAPIVersion.sh $(version_name) $(version_path);  tput sgr0;`
+
+	
+$(PROGS): $(OBJS) 
+#	echo $(OBJS)
+	mkdir -p $(DESTDIR) 
+	$(CC) -o $@ $^ $(CFLAGS)   $(LDLIBS)
+	mv $(PROGS) $(DESTDIR)
+	rm *.gdb
+
+clean:
+	rm -rf $(DESTDIR)/$(PROGS) *.o *.gdb
+
+
+
+
+

slsDetectorServers/gotthardDetectorServer/Makefile.virtual

@@ -0,0 +1,27 @@
+CC          =   gcc
+CFLAGS      +=  -Wall -DGOTTHARDD -DVIRTUAL -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
+LDLIBS      +=  -lm  -lstdc++  -pthread
+
+PROGS       =   gotthardDetectorServer_virtual 
+DESTDIR     ?=  bin
+INSTMODE    =   0777
+
+SRC_CLNT    =   communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c  slsDetectorFunctionList.c 
+OBJS        =   $(SRC_CLNT:.c=.o) 
+ 
+all: clean versioning $(PROGS)
+
+boot: $(OBJS) 
+
+versioning: 
+    @echo `tput setaf 6;    ./updateGitVersion.sh; tput sgr0;`
+    
+$(PROGS): $(OBJS)
+#   echo $(OBJS) 
+    mkdir -p $(DESTDIR) 
+    $(CC) -o $@ $^ $(CFLAGS) $(LDLIBS) 
+    mv $(PROGS) $(DESTDIR)
+
+clean:
+    rm -rf $(DESTDIR)/$(PROGS)  *.o
+   

slsDetectorServers/gotthardDetectorServer/RegisterDefs.h

@@ -0,0 +1,369 @@
+#pragma once
+
+/* Definitions for FPGA*/
+#define MEM_MAP_SHIFT                   (11)
+
+/** Gain register */
+#define GAIN_REG                        (0x10 << MEM_MAP_SHIFT)
+
+#define GAIN_CONFGAIN_OFST              (0)
+#define GAIN_CONFGAIN_MSK               (0x000000FF << GAIN_CONFGAIN_OFST)
+#define GAIN_CONFGAIN_HGH_GAIN_VAL      ((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_DYNMC_GAIN_VAL    ((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_LW_GAIN_VAL       ((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_MDM_GAIN_VAL      ((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL  ((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+
+/** Flow Control register */
+//#define FLOW_CONTROL_REG                (0x11 << MEM_MAP_SHIFT)
+
+/** Flow Status register */
+//#define FLOW_STATUS_REG                 (0x12 << MEM_MAP_SHIFT)
+
+/** Frame register */
+//#define FRAME_REG                       (0x13 << MEM_MAP_SHIFT)
+
+/** Multi Purpose register */
+#define MULTI_PURPOSE_REG               (0x14 << MEM_MAP_SHIFT)
+
+#define PHS_STP_OFST                    (0)
+#define PHS_STP_MSK                     (0x00000001 << PHS_STP_OFST)
+#define RST_CNTR_OFST                   (2)
+#define RST_CNTR_MSK                    (0x00000001 << RST_CNTR_OFST)
+#define SW1_OFST                        (5)
+#define SW1_MSK                         (0x00000001 << SW1_OFST)
+#define WRT_BCK_OFST                    (6)
+#define WRT_BCK_MSK                     (0x00000001 << WRT_BCK_OFST)
+#define RST_OFST                        (7)
+#define RST_MSK                         (0x00000001 << RST_OFST)
+#define PLL_CLK_SL_OFST                 (8)
+#define PLL_CLK_SL_MSK                  (0x00000007 << PLL_CLK_SL_OFST)
+#define PLL_CLK_SL_MSTR_VAL             ((0x1 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
+#define PLL_CLK_SL_MSTR_ADC_VAL         ((0x2 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
+#define PLL_CLK_SL_SLV_VAL              ((0x3 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
+#define PLL_CLK_SL_SLV_ADC_VAL          ((0x4 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
+#define ENT_RSTN_OFST                   (11)
+#define ENT_RSTN_MSK                    (0x00000001 << ENT_RSTN_OFST)
+#define INT_RSTN_OFST                   (12)
+#define INT_RSTN_MSK                    (0x00000001 << INT_RSTN_OFST)
+#define DGTL_TST_OFST                   (14)
+#define DGTL_TST_MSK                    (0x00000001 << DGTL_TST_OFST)
+#define CHNG_AT_PWR_ON_OFST             (15)                                    // Not used in SW
+#define CHNG_AT_PWR_ON_MSK              (0x00000001 << CHNG_AT_PWR_ON_OFST) // Not used in SW
+#define RST_TO_SW1_DLY_OFST             (16)
+#define RST_TO_SW1_DLY_MSK              (0x0000000F << RST_TO_SW1_DLY_OFST)
+#define STRT_ACQ_DLY_OFST               (20)
+#define STRT_ACQ_DLY_MSK                (0x0000000F << STRT_ACQ_DLY_OFST)
+
+/** DAQ register */
+#define DAQ_REG                         (0x15 << MEM_MAP_SHIFT)
+
+#define DAQ_TKN_TMNG_OFST               (0)
+#define DAQ_TKN_TMNG_MSK                (0x0000FFFF << DAQ_TKN_TMNG_OFST)
+#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL     ((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
+#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL     ((0x1f10 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
+#define DAQ_PCKT_LNGTH_OFST             (16)
+#define DAQ_PCKT_LNGTH_MSK              (0x0000FFFF << DAQ_PCKT_LNGTH_OFST)
+#define DAQ_PCKT_LNGTH_NO_ROI_VAL       ((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
+#define DAQ_PCKT_LNGTH_ROI_VAL          ((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
+
+/** Time From Start register */
+//#define TIME_FROM_START_REG             (0x16 << MEM_MAP_SHIFT)
+
+/** DAC Control register */
+#define SPI_REG                         (0x17 << MEM_MAP_SHIFT)
+
+#define SPI_DAC_SRL_CS_OTPT_OFST        (0)
+#define SPI_DAC_SRL_CS_OTPT_MSK         (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
+#define SPI_DAC_SRL_CLK_OTPT_OFST       (1)
+#define SPI_DAC_SRL_CLK_OTPT_MSK        (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
+#define SPI_DAC_SRL_DGTL_OTPT_OFST      (2)
+#define SPI_DAC_SRL_DGTL_OTPT_MSK       (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
+
+/** ADC SPI register */
+#define ADC_SPI_REG                     (0x18 << MEM_MAP_SHIFT)
+
+#define ADC_SPI_SRL_CLK_OTPT_OFST       (0)
+#define ADC_SPI_SRL_CLK_OTPT_MSK        (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
+#define ADC_SPI_SRL_DT_OTPT_OFST        (1)
+#define ADC_SPI_SRL_DT_OTPT_MSK         (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
+#define ADC_SPI_SRL_CS_OTPT_OFST        (2)
+#define ADC_SPI_SRL_CS_OTPT_MSK         (0x0000001F << ADC_SPI_SRL_CS_OTPT_OFST)
+
+/** ADC Sync register */
+#define ADC_SYNC_REG                    (0x19 << MEM_MAP_SHIFT)
+
+#define ADC_SYNC_ENET_STRT_DLY_OFST     (0)
+#define ADC_SYNC_ENET_STRT_DLY_MSK      (0x0000000F << ADC_SYNC_ENET_STRT_DLY_OFST)
+#define ADC_SYNC_ENET_STRT_DLY_VAL      ((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
+#define ADC_SYNC_TKN1_HGH_DLY_OFST      (4)
+#define ADC_SYNC_TKN1_HGH_DLY_MSK       (0x0000000F << ADC_SYNC_TKN1_HGH_DLY_OFST)
+#define ADC_SYNC_TKN1_HGH_DLY_VAL       ((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
+#define ADC_SYNC_TKN2_HGH_DLY_OFST      (8)
+#define ADC_SYNC_TKN2_HGH_DLY_MSK       (0x0000000F << ADC_SYNC_TKN2_HGH_DLY_OFST)
+#define ADC_SYNC_TKN2_HGH_DLY_VAL       ((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
+#define ADC_SYNC_TKN1_LOW_DLY_OFST      (12)
+#define ADC_SYNC_TKN1_LOW_DLY_MSK       (0x0000000F << ADC_SYNC_TKN1_LOW_DLY_OFST)
+#define ADC_SYNC_TKN1_LOW_DLY_VAL       ((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
+#define ADC_SYNC_TKN2_LOW_DLY_OFST      (16)
+#define ADC_SYNC_TKN2_LOW_DLY_MSK       (0x0000000F << ADC_SYNC_TKN2_LOW_DLY_OFST)
+#define ADC_SYNC_TKN2_LOW_DLY_VAL       ((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
+//0x32214
+#define ADC_SYNC_TKN_VAL                (ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL |  ADC_SYNC_TKN2_LOW_DLY_VAL)
+#define ADC_SYNC_CLEAN_FIFOS_OFST       (20)
+#define ADC_SYNC_CLEAN_FIFOS_MSK        (0x00000001 << ADC_SYNC_CLEAN_FIFOS_OFST)
+#define ADC_SYNC_ENET_DELAY_OFST        (24)
+#define ADC_SYNC_ENET_DELAY_MSK         (0x000000FF << ADC_SYNC_ENET_DELAY_OFST)
+#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL  ((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
+#define ADC_SYNC_ENET_DELAY_ROI_VAL     ((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
+
+/** Time From Start register */
+//#define MU_TIME_REG                     (0x1a << MEM_MAP_SHIFT)
+
+/** Temperatre SPI In register */
+#define TEMP_SPI_IN_REG                 (0x1b << MEM_MAP_SHIFT)
+
+#define TEMP_SPI_IN_T1_CLK_OFST         (0)
+#define TEMP_SPI_IN_T1_CLK_MSK          (0x00000001 << TEMP_SPI_IN_T1_CLK_OFST)
+#define TEMP_SPI_IN_T1_CS_OFST          (1)
+#define TEMP_SPI_IN_T1_CS_MSK           (0x00000001 << TEMP_SPI_IN_T1_CS_OFST)
+#define TEMP_SPI_IN_T2_CLK_OFST         (2)
+#define TEMP_SPI_IN_T2_CLK_MSK          (0x00000001 << TEMP_SPI_IN_T2_CLK_OFST)
+#define TEMP_SPI_IN_T2_CS_OFST          (3)
+#define TEMP_SPI_IN_T2_CS_MSK           (0x00000001 << TEMP_SPI_IN_T2_CS_OFST)
+#define TEMP_SPI_IN_IDLE_MSK            (TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CS_MSK | TEMP_SPI_IN_T1_CLK_MSK | TEMP_SPI_IN_T2_CLK_MSK)
+
+/** Temperatre SPI Out register */
+#define TEMP_SPI_OUT_REG                (0x1c << MEM_MAP_SHIFT)
+
+#define TEMP_SPI_OUT_T1_DT_OFST         (0)
+#define TEMP_SPI_OUT_T1_DT_MSK          (0x00000001 << TEMP_SPI_OUT_T1_DT_OFST)
+#define TEMP_SPI_OUT_T2_DT_OFST         (1)
+#define TEMP_SPI_OUT_T2_DT_MSK          (0x00000001 << TEMP_SPI_OUT_T2_DT_OFST)
+
+/** TSE Configure register */
+#define TSE_CONF_REG                    (0x1d << MEM_MAP_SHIFT)
+
+/** SPI Configure register */
+#define ENET_CONF_REG                   (0x1e << MEM_MAP_SHIFT)
+
+/** Write TSE Shadow register */
+//#define WRITE_TSE_SHADOW_REG            (0x1f << MEM_MAP_SHIFT)
+
+/** High Voltage register */
+#define HV_REG                          (0x20 << MEM_MAP_SHIFT)
+
+#define HV_ENBL_OFST                    (0)
+#define HV_ENBL_MSK                     (0x00000001 << HV_ENBL_OFST)
+#define HV_SEL_OFST                     (1)
+#define HV_SEL_MSK                      (0x00000007 << HV_SEL_OFST)
+#define HV_SEL_90_VAL                   ((0x0 << HV_SEL_OFST) & HV_SEL_MSK)
+#define HV_SEL_110_VAL                  ((0x1 << HV_SEL_OFST) & HV_SEL_MSK)
+#define HV_SEL_120_VAL                  ((0x2 << HV_SEL_OFST) & HV_SEL_MSK)
+#define HV_SEL_150_VAL                  ((0x3 << HV_SEL_OFST) & HV_SEL_MSK)
+#define HV_SEL_180_VAL                  ((0x4 << HV_SEL_OFST) & HV_SEL_MSK)
+#define HV_SEL_200_VAL                  ((0x5 << HV_SEL_OFST) & HV_SEL_MSK)
+
+/** Dummy register */
+#define DUMMY_REG                       (0x21 << MEM_MAP_SHIFT)
+
+/** Firmware Version register */
+#define FPGA_VERSION_REG                (0x22 << MEM_MAP_SHIFT)
+
+#define FPGA_VERSION_OFST               (0)
+#define FPGA_VERSION_MSK                (0x00FFFFFF << FPGA_VERSION_OFST)       // to get in format yymmdd
+
+/* Fix Pattern register */
+#define FIX_PATT_REG                    (0x23 << MEM_MAP_SHIFT)
+
+#define FIX_PATT_VAL                    (0xACDC1980)
+
+/** 16 bit Control register */
+#define CONTROL_REG                     (0x24 << MEM_MAP_SHIFT)
+
+#define CONTROL_STRT_ACQ_OFST           (0)
+#define CONTROL_STRT_ACQ_MSK            (0x00000001 << CONTROL_STRT_ACQ_OFST)
+#define CONTROL_STP_ACQ_OFST            (1)
+#define CONTROL_STP_ACQ_MSK             (0x00000001 << CONTROL_STP_ACQ_OFST)
+#define CONTROL_STRT_FF_TST_OFST        (2)                                          // Not used in FW & SW
+#define CONTROL_STRT_FF_TST_MSK         (0x00000001 << CONTROL_STRT_FF_TST_OFST)
+#define CONTROL_STP_FF_TST_OFST         (3)                                          // Not used in FW & SW
+#define CONTROL_STP_FF_TST_MSK          (0x00000001 << CONTROL_STP_FF_TST_OFST)
+#define CONTROL_STRT_RDT_OFST           (4)
+#define CONTROL_STRT_RDT_MSK            (0x00000001 << CONTROL_STRT_RDT_OFST)
+#define CONTROL_STP_RDT_OFST            (5)
+#define CONTROL_STP_RDT_MSK             (0x00000001 << CONTROL_STP_RDT_OFST)
+#define CONTROL_STRT_EXPSR_OFST         (6)
+#define CONTROL_STRT_EXPSR_MSK          (0x00000001 << CONTROL_STRT_EXPSR_OFST)
+#define CONTROL_STP_EXPSR_OFST          (7)
+#define CONTROL_STP_EXPSR_MSK           (0x00000001 << CONTROL_STP_EXPSR_OFST)
+#define CONTROL_STRT_TRN_OFST           (8)
+#define CONTROL_STRT_TRN_MSK            (0x00000001 << CONTROL_STRT_TRN_OFST)
+#define CONTROL_STP_TRN_OFST            (9)
+#define CONTROL_STP_TRN_MSK             (0x00000001 << CONTROL_STP_TRN_OFST)
+#define CONTROL_SYNC_RST_OFST           (10)
+#define CONTROL_SYNC_RST_MSK            (0x00000001 << CONTROL_SYNC_RST_OFST)
+
+/** Status register */
+#define STATUS_REG                      (0x25 << MEM_MAP_SHIFT)
+
+#define STATUS_RN_BSY_OFST              (0)
+#define STATUS_RN_BSY_MSK               (0x00000001 << STATUS_RN_BSY_OFST)
+#define STATUS_RDT_BSY_OFST             (1)
+#define STATUS_RDT_BSY_MSK              (0x00000001 << STATUS_RDT_BSY_OFST)
+#define STATUS_WTNG_FR_TRGGR_OFST       (3)
+#define STATUS_WTNG_FR_TRGGR_MSK        (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
+#define STATUS_DLY_BFR_OFST             (4)
+#define STATUS_DLY_BFR_MSK              (0x00000001 << STATUS_DLY_BFR_OFST)
+#define STATUS_DLY_AFTR_OFST            (5)
+#define STATUS_DLY_AFTR_MSK             (0x00000001 << STATUS_DLY_AFTR_OFST)
+#define STATUS_EXPSNG_OFST              (6)
+#define STATUS_EXPSNG_MSK               (0x00000001 << STATUS_EXPSNG_OFST)
+#define STATUS_CNT_ENBL_OFST            (7)
+#define STATUS_CNT_ENBL_MSK             (0x00000001 << STATUS_CNT_ENBL_OFST)
+#define STATUS_RD_STT_OFST              (8)
+#define STATUS_RD_STT_MSK               (0x00000007 << STATUS_RD_STT_OFST)
+#define STATUS_RN_STT_OFST              (12)
+#define STATUS_RN_STT_MSK               (0x00000007 << STATUS_RN_STT_OFST)
+#define STATUS_SM_FF_FLL_OFST           (15)
+#define STATUS_SM_FF_FLL_MSK            (0x00000001 << STATUS_SM_FF_FLL_OFST)
+#define STATUS_ALL_FF_EMPTY_OFST        (11)
+#define STATUS_ALL_FF_EMPTY_MSK         (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
+#define STATUS_RN_MSHN_BSY_OFST         (17)
+#define STATUS_RN_MSHN_BSY_MSK          (0x00000001 << STATUS_RN_MSHN_BSY_OFST)
+#define STATUS_RD_MSHN_BSY_OFST         (18)
+#define STATUS_RD_MSHN_BSY_MSK          (0x00000001 << STATUS_RD_MSHN_BSY_OFST)
+#define STATUS_RN_FNSHD_OFST            (20)
+#define STATUS_RN_FNSHD_MSK             (0x00000001 << STATUS_RN_FNSHD_OFST)
+#define STATUS_IDLE_MSK                 (0x0000FFFF << 0)
+
+/** Config register */
+#define CONFIG_REG                      (0x26 << MEM_MAP_SHIFT)
+
+#define CONFIG_SLAVE_OFST               (0)                                     // Not used in FW & SW
+#define CONFIG_SLAVE_MSK                (0x00000001 << CONFIG_SLAVE_OFST)
+#define CONFIG_MASTER_OFST              (1)                                     // Not used in FW & SW
+#define CONFIG_MASTER_MSK               (0x00000001 << CONFIG_MASTER_OFST)
+#define CONFIG_TM_GT_ENBL_OFST          (2)                                     // Not used in FW & SW
+#define CONFIG_TM_GT_ENBL_MSK           (0x00000001 << CONFIG_TM_GT_ENBL_OFST)
+#define CONFIG_CPU_RDT_OFST             (12)
+#define CONFIG_CPU_RDT_MSK              (0x00000001 << CONFIG_CPU_RDT_OFST)
+#define CONFIG_CNTNS_RDT_OFST           (23)                                    // Not used in FW & SW
+#define CONFIG_CNTNS_RDT_MSK            (0x00000001 << CONFIG_CNTNS_RDT_OFST)
+#define CONFIG_ACCMLT_CNTS_OFST         (24)                                    // Not used in FW & SW
+#define CONFIG_ACCMLT_CNTS_MSK          (0x00000001 << CONFIG_ACCMLT_CNTS_OFST)
+
+/** External Signal register */
+#define EXT_SIGNAL_REG                  (0x27 << MEM_MAP_SHIFT)
+
+#define EXT_SIGNAL_OFST                 (0)
+#define EXT_SIGNAL_MSK                  (0x00000007 << EXT_SIGNAL_OFST)
+#define EXT_SIGNAL_OFF_VAL              ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
+#define EXT_SIGNAL_TRGGR_IN_RSNG_VAL    ((0x3 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
+#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL   ((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
+
+/** Look at me register */
+//#define LOOK_AT_ME_REG                  (0x28 << MEM_MAP_SHIFT)
+
+/** FPGA SVN register */
+//#define FPGA_SVN_REG                    (0x29 << MEM_MAP_SHIFT)
+
+/** Chip of Interest register */
+#define CHIP_OF_INTRST_REG              (0x2a << MEM_MAP_SHIFT)
+
+#define CHIP_OF_INTRST_ADC_SEL_OFST     (0)
+#define CHIP_OF_INTRST_ADC_SEL_MSK      (0x0000001F << CHIP_OF_INTRST_ADC_SEL_OFST)
+#define CHIP_OF_INTRST_NUM_CHNNLS_OFST  (16)
+#define CHIP_OF_INTRST_NUM_CHNNLS_MSK   (0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
+
+/** Out MUX register */
+//#define OUT_MUX_REG                     (0x2b << MEM_MAP_SHIFT)
+
+/** Board Version register */
+#define BOARD_REVISION_REG              (0x2c << MEM_MAP_SHIFT)
+
+#define BOARD_REVISION_OFST             (0)
+#define BOARD_REVISION_MSK              (0x0000FFFF << BOARD_REVISION_OFST)
+#define DETECTOR_TYPE_OFST              (16)
+#define DETECTOR_TYPE_MSK               (0x0000000F << DETECTOR_TYPE_OFST)
+//#define DETECTOR_TYPE_GOTTHARD_VAL          (??)
+#define DETECTOR_TYPE_MOENCH_VAL        (2)
+
+/** Memory Test register */
+//#define MEMORY_TEST_REG                 (0x2d << MEM_MAP_SHIFT)
+
+/** Hit Threshold register */
+//#define HIT_THRESHOLD_REG               (0x2e << MEM_MAP_SHIFT)
+
+/** Hit Count register */
+//#define HIT_COUNT_REG                   (0x2f << MEM_MAP_SHIFT)
+
+/* 16 bit Fifo Data register */
+#define FIFO_DATA_REG                   (0x50 << MEM_MAP_SHIFT)                 // Not used in FW and SW (16bit)
+
+/** Dacs Set 1 register */
+//#define DACS_SET_1_REG                  (0x65 << MEM_MAP_SHIFT)
+
+/** Dacs Set 2 register */
+//#define DACS_SET_2_REG                  (0x66 << MEM_MAP_SHIFT)
+
+/** Dacs Set 3 register */
+//#define DACS_SET_3_REG                  (0x67 << MEM_MAP_SHIFT)
+
+/* Set Delay 64 bit register */
+#define SET_DELAY_LSB_REG               (0x68 << MEM_MAP_SHIFT)
+#define SET_DELAY_MSB_REG               (0x69 << MEM_MAP_SHIFT)
+
+/* Get Delay 64 bit register */
+#define GET_DELAY_LSB_REG               (0x6a << MEM_MAP_SHIFT)
+#define GET_DELAY_MSB_REG               (0x6b << MEM_MAP_SHIFT)
+
+/* Set Cycles 64 bit register */
+#define SET_TRAINS_LSB_REG              (0x6c << MEM_MAP_SHIFT)
+#define SET_TRAINS_MSB_REG              (0x6d << MEM_MAP_SHIFT)
+
+/* Get Cycles 64 bit register */
+#define GET_TRAINS_LSB_REG              (0x6e << MEM_MAP_SHIFT)
+#define GET_TRAINS_MSB_REG              (0x6f << MEM_MAP_SHIFT)
+
+/* Set Frames 64 bit register */
+#define SET_FRAMES_LSB_REG              (0x70 << MEM_MAP_SHIFT)
+#define SET_FRAMES_MSB_REG              (0x71 << MEM_MAP_SHIFT)
+
+/* Get Frames 64 bit register */
+#define GET_FRAMES_LSB_REG              (0x72 << MEM_MAP_SHIFT)
+#define GET_FRAMES_MSB_REG              (0x73 << MEM_MAP_SHIFT)
+
+/* Set Period 64 bit register */
+#define SET_PERIOD_LSB_REG              (0x74 << MEM_MAP_SHIFT)
+#define SET_PERIOD_MSB_REG              (0x75 << MEM_MAP_SHIFT)
+
+/* Get Period 64 bit register */
+#define GET_PERIOD_LSB_REG              (0x76 << MEM_MAP_SHIFT)
+#define GET_PERIOD_MSB_REG              (0x77 << MEM_MAP_SHIFT)
+
+/* Set Exptime 64 bit register */
+#define SET_EXPTIME_LSB_REG             (0x78 << MEM_MAP_SHIFT)
+#define SET_EXPTIME_MSB_REG             (0x79 << MEM_MAP_SHIFT)
+
+/* Get Exptime 64 bit register */
+#define GET_EXPTIME_LSB_REG             (0x7a << MEM_MAP_SHIFT)
+#define GET_EXPTIME_MSB_REG             (0x7b << MEM_MAP_SHIFT)
+
+/* Set Gates 64 bit register */
+//#define SET_GATES_LSB_REG               (0x7c << MEM_MAP_SHIFT)
+//#define SET_GATES_MSB_REG               (0x7d << MEM_MAP_SHIFT)
+
+/* Set Gates 64 bit register */
+//#define GET_GATES_LSB_REG               (0x7e << MEM_MAP_SHIFT)
+//#define GET_GATES_MSB_REG               (0x7f << MEM_MAP_SHIFT)
+
+/* Dark Image starting address */
+#define DARK_IMAGE_REG                  (0x81 << MEM_MAP_SHIFT)
+
+/* Gain Image starting address */
+#define GAIN_IMAGE_REG                  (0x82 << MEM_MAP_SHIFT)
+
+/* Counter Block Memory starting address */
+#define COUNTER_MEMORY_REG              (0x85 << MEM_MAP_SHIFT)
+

slsDetectorServers/gotthardDetectorServer/ansi.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/ansi.h

slsDetectorServers/gotthardDetectorServer/blackfin.h

@@ -0,0 +1 @@
+../slsDetectorServer/blackfin.h

slsDetectorServers/gotthardDetectorServer/common.h

@@ -0,0 +1 @@
+../slsDetectorServer/common.h

slsDetectorServers/gotthardDetectorServer/commonServerFunctions.h

@@ -0,0 +1 @@
+../slsDetectorServer/commonServerFunctions.h

slsDetectorServers/gotthardDetectorServer/communication_funcs.c

@@ -0,0 +1 @@
+../slsDetectorServer/communication_funcs.c

slsDetectorServers/gotthardDetectorServer/communication_funcs.h

@@ -0,0 +1 @@
+../slsDetectorServer/communication_funcs.h

slsDetectorServers/gotthardDetectorServer/config.txt

@@ -0,0 +1,23 @@
+#masterflags (no_master, is_master, is_slave)
+masterflags no_master
+
+#master default delay 
+masterdefaultdelay 70
+
+#patternphase 
+patternphase 0
+
+#adcphase 
+adcphase 0
+
+#slave pattern phase
+slavepatternphase 0
+
+#slave adc phase 
+slaveadcphase 0
+
+#rst to sw1 delay
+rsttosw1delay 2
+
+#start acquisition delay
+startacqdelay 1

slsDetectorServers/gotthardDetectorServer/logger.h

@@ -0,0 +1 @@
+../slsDetectorServer/logger.h

slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.h

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorFunctionList.h

slsDetectorServers/gotthardDetectorServer/slsDetectorServer.c

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer.c

slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h

@@ -0,0 +1,123 @@
+#pragma once
+#include "sls_detector_defs.h"
+#include <stdlib.h>
+
+/* Enums */
+enum ADCINDEX				        {TEMP_FPGA, TEMP_ADC};
+enum DACINDEX				        {VREF_DS, VCASCN_PB, VCASCP_PB, VOUT_CM, VCASC_OUT, VIN_CM, VREF_COMP, IB_TESTC};
+#define DEFAULT_DAC_VALS   	        { 	                        \
+                                    660,    /* VREF_DS */       \
+                                    650,    /* VCASCN_PB */     \
+                                    1480,   /* VCASCP_PB */     \
+                                    1520,   /* VOUT_CM */       \
+                                    1320,   /* VCASC_OUT */     \
+                                    1350,   /* VIN_CM */        \
+                                    350,    /* VREF_COMP */     \
+                                    2001    /* IB_TESTC */      \
+                                    };
+
+/* for 25 um */
+#define CONFIG_FILE                 "config.txt"
+
+/* Hardware Definitions */
+#define NCHAN 						(128)
+#define NCHIP 						(10)
+#define NDAC 						(8)
+#define NCHIPS_PER_ADC              (2)
+#define DYNAMIC_RANGE				(16)
+#define NUM_BITS_PER_PIXEL			(DYNAMIC_RANGE / 8)
+#define DATA_BYTES					(NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
+#define CLK_FREQ					(32.007729)	/* MHz */
+
+/** Firmware Definitions */
+#define IP_PACKET_SIZE_NO_ROI       (NCHIP * (NCHAN / 2) * 2 + 14 + 20)     // 2 packets, so divide by 2
+#define IP_PACKET_SIZE_ROI          (NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20)
+
+#define UDP_PACKETSIZE_NO_ROI       (NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2)  // 2 packets, so divide by 2
+#define UDP_PACKETSIZE_ROI          (NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2)
+
+/** Default Parameters */
+#define DEFAULT_NUM_FRAMES			(1)
+#define DEFAULT_NUM_CYCLES			(1)
+#define DEFAULT_EXPTIME				(1 * 1000 * 1000)	        // 1 ms
+#define DEFAULT_PERIOD				(1 * 1000 * 1000 * 1000)	// 1 s
+#define DEFAULT_DELAY				(0)
+#define DEFAULT_SETTINGS            (DYNAMICGAIN)
+#define DEFAULT_TIMING_MODE         (AUTO_TIMING)
+#define DEFAULT_TRIGGER_MODE        (TRIGGER_IN_RISING_EDGE)
+#define DEFAULT_HIGH_VOLTAGE		(0)
+#define DEFAULT_PHASE_SHIFT         (120)
+#define DEFAULT_TX_UDP_PORT         (0xE185)
+
+#define DAC_MIN_MV                  (0)
+#define DAC_MAX_MV                  (2500)
+
+/** ENEt conf structs */
+typedef struct mac_header_struct{
+    u_int8_t    mac_dest_mac2;
+    u_int8_t    mac_dest_mac1;
+    u_int8_t    mac_dummy1;
+    u_int8_t    mac_dummy2;
+    u_int8_t    mac_dest_mac6;
+    u_int8_t    mac_dest_mac5;
+    u_int8_t    mac_dest_mac4;
+    u_int8_t    mac_dest_mac3;
+    u_int8_t    mac_src_mac4;
+    u_int8_t    mac_src_mac3;
+    u_int8_t    mac_src_mac2;
+    u_int8_t    mac_src_mac1;
+    u_int16_t   mac_ether_type;
+    u_int8_t    mac_src_mac6;
+    u_int8_t    mac_src_mac5;
+} mac_header;
+
+typedef struct ip_header_struct {
+    u_int16_t     ip_len;
+    u_int8_t      ip_tos;
+    u_int8_t      ip_ihl:4 ,ip_ver:4;
+    u_int16_t     ip_offset:13,ip_flag:3;
+    u_int16_t     ip_ident;
+    u_int16_t     ip_chksum;
+    u_int8_t      ip_protocol;
+    u_int8_t      ip_ttl;
+    u_int32_t     ip_sourceip;
+    u_int32_t     ip_destip;
+} ip_header;
+
+typedef struct udp_header_struct{
+    u_int16_t   udp_destport;
+    u_int16_t   udp_srcport;
+    u_int16_t   udp_chksum;
+    u_int16_t   udp_len;
+} udp_header;
+
+typedef struct mac_conf_struct{
+    mac_header  mac;
+    ip_header   ip;
+    udp_header  udp;
+    u_int32_t   npack;
+    u_int32_t   lpack;
+    u_int32_t   npad;
+    u_int32_t   cdone;
+} mac_conf;
+
+typedef struct tse_conf_struct{
+    u_int32_t   rev;                    //0x0
+    u_int32_t   scratch;
+    u_int32_t   command_config;
+    u_int32_t   mac_0;                  //0x3
+    u_int32_t   mac_1;
+    u_int32_t   frm_length;
+    u_int32_t   pause_quant;
+    u_int32_t   rx_section_empty;       //0x7
+    u_int32_t   rx_section_full;
+    u_int32_t   tx_section_empty;
+    u_int32_t   tx_section_full;
+    u_int32_t   rx_almost_empty;        //0xB
+    u_int32_t   rx_almost_full;
+    u_int32_t   tx_almost_empty;
+    u_int32_t   tx_almost_full;
+    u_int32_t   mdio_addr0;             //0xF
+    u_int32_t   mdio_addr1;
+}tse_conf;
+

slsDetectorServers/gotthardDetectorServer/slsDetectorServer_funcs.c

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer_funcs.c

slsDetectorServers/gotthardDetectorServer/slsDetectorServer_funcs.h

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer_funcs.h

slsDetectorServers/gotthardDetectorServer/sls_detector_defs.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/sls_detector_defs.h

slsDetectorServers/gotthardDetectorServer/sls_detector_funcs.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/sls_detector_funcs.h

slsDetectorServers/gotthardDetectorServer/versionAPI.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/versionAPI.h