merging refactor (replacing)

slsDetectorServers/ctbDetectorServer/AD7689.h

@@ -0,0 +1 @@
+../slsDetectorServer/AD7689.h

slsDetectorServers/ctbDetectorServer/AD9257.h

@@ -0,0 +1 @@
+../slsDetectorServer/AD9257.h

slsDetectorServers/ctbDetectorServer/ALTERA_PLL.h

@@ -0,0 +1 @@
+../slsDetectorServer/ALTERA_PLL.h

slsDetectorServers/ctbDetectorServer/I2C.h

@@ -0,0 +1 @@
+../slsDetectorServer/I2C.h

slsDetectorServers/ctbDetectorServer/INA226.h

@@ -0,0 +1 @@
+../slsDetectorServer/INA226.h

slsDetectorServers/ctbDetectorServer/LTC2620.h

@@ -0,0 +1 @@
+../slsDetectorServer/LTC2620.h

slsDetectorServers/ctbDetectorServer/MAX1932.h

@@ -0,0 +1 @@
+../slsDetectorServer/MAX1932.h

slsDetectorServers/ctbDetectorServer/Makefile

@@ -0,0 +1,34 @@
+CROSS  		= bfin-uclinux-
+CC    		= $(CROSS)gcc
+CFLAGS		+=  -Wall -DCHIPTESTBOARDD  -DSTOP_SERVER -DDEBUG1 #-DJCTB -DVERBOSEI #-DVERBOSE
+LDLIBS		+= 	-lm  -lstdc++ 
+
+PROGS		= 	ctbDetectorServer 
+DESTDIR		?= 	bin
+INSTMODE	= 	0777
+
+SRC_CLNT	=	communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c  slsDetectorFunctionList.c 
+OBJS 		= 	$(SRC_CLNT:.c=.o) 
+ 
+all: clean versioning $(PROGS)
+
+boot: $(OBJS) 
+
+version_name=APICTB
+version_path=slsDetectorServers/ctbDetectorServer
+versioning: 
+	cd ../../ && echo $(PWD) && echo `tput setaf 6; ./updateAPIVersion.sh $(version_name) $(version_path);  tput sgr0;`
+
+
+$(PROGS): $(OBJS)
+#	echo $(OBJS) 
+	mkdir -p $(DESTDIR) 
+	$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS) 
+	mv $(PROGS) $(DESTDIR)
+	rm *.gdb
+
+clean:
+	rm -rf $(DESTDIR)/$(PROGS)  *.o *.gdb
+	
+
+	

slsDetectorServers/ctbDetectorServer/Makefile.virtual

@@ -0,0 +1,27 @@
+CC    		= gcc
+CFLAGS		+=  -Wall -DCHIPTESTBOARDD -DVIRTUAL -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
+LDLIBS		+= 	-lm  -lstdc++  -pthread
+
+PROGS		= 	ctbDetectorServer_virtual 
+DESTDIR		?= 	bin
+INSTMODE	= 	0777
+
+SRC_CLNT	=	communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c  slsDetectorFunctionList.c 
+OBJS 		= 	$(SRC_CLNT:.c=.o) 
+ 
+all: clean versioning $(PROGS)
+
+boot: $(OBJS) 
+
+versioning: 
+	@echo `tput setaf 6;	./updateGitVersion.sh; tput sgr0;`
+	
+$(PROGS): $(OBJS)
+#	echo $(OBJS) 
+	mkdir -p $(DESTDIR) 
+	$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS) 
+	mv $(PROGS) $(DESTDIR)
+
+clean:
+	rm -rf $(DESTDIR)/$(PROGS)  *.o
+	

slsDetectorServers/ctbDetectorServer/RegisterDefs.h

@@ -0,0 +1,551 @@
+#pragma once
+
+/* Definitions for FPGA */
+#define MEM_MAP_SHIFT 1
+
+/* FPGA Version RO register */
+#define FPGA_VERSION_REG      			    (0x00 << MEM_MAP_SHIFT)
+
+#define FPGA_VERSION_BRD_RVSN_OFST			(0)
+#define FPGA_VERSION_BRD_RVSN_MSK			(0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
+#define FPGA_VERSION_DTCTR_TYP_OFST		    (24)
+#define FPGA_VERSION_DTCTR_TYP_MSK   	    (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
+#define FPGA_VERSION_DTCTR_TYP_CTB_VAL      ((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
+
+/* Fix pattern RO register */
+#define FIX_PATT_REG          			    (0x01 << MEM_MAP_SHIFT)
+
+#define FIX_PATT_VAL                        (0xACDC2016)
+
+/* Status RO register */
+#define STATUS_REG            			    (0x02 << MEM_MAP_SHIFT)
+
+#define STATUS_RN_BSY_OFST				    (0)
+#define STATUS_RN_BSY_MSK      			    (0x00000001 << STATUS_RN_BSY_OFST)
+#define STATUS_RDT_BSY_OFST                 (1)
+#define STATUS_RDT_BSY_MSK                  (0x00000001 << STATUS_RDT_BSY_OFST)
+#define STATUS_ANY_FF_FLL_OFST              (2)
+#define STATUS_ANY_FF_FLL_MSK               (0x00000001 << STATUS_ANY_FF_FLL_OFST)
+#define STATUS_WTNG_FR_TRGGR_OFST  		    (3)
+#define STATUS_WTNG_FR_TRGGR_MSK  		    (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
+#define STATUS_DLY_BFR_OFST  			    (4)
+#define STATUS_DLY_BFR_MSK  			    (0x00000001 << STATUS_DLY_BFR_OFST)
+#define STATUS_DLY_AFTR_OFST  			    (5)
+#define STATUS_DLY_AFTR_MSK  			    (0x00000001 << STATUS_DLY_AFTR_OFST)
+#define STATUS_EXPSNG_OFST                  (6)
+#define STATUS_EXPSNG_MSK                   (0x00000001 << STATUS_EXPSNG_OFST)
+#define STATUS_CNT_ENBL_OFST                (7)
+#define STATUS_CNT_ENBL_MSK                 (0x00000001 << STATUS_CNT_ENBL_OFST)
+#define STATUS_SM_FF_FLL_OFST               (11)
+#define STATUS_SM_FF_FLL_MSK                (0x00000001 << STATUS_SM_FF_FLL_OFST)
+#define STATUS_STPPD_OFST                   (15)
+#define STATUS_STPPD_MSK                    (0x00000001 << STATUS_STPPD_OFST)
+#define STATUS_ALL_FF_EMPTY_OFST            (16)
+#define STATUS_ALL_FF_EMPTY_MSK             (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
+#define STATUS_CYCL_RN_BSY_OFST  		    (17)
+#define STATUS_CYCL_RN_BSY_MSK  		    (0x00000001 << STATUS_CYCL_RN_BSY_OFST)
+#define STATUS_FRM_RN_BSY_OFST              (18)
+#define STATUS_FRM_RN_BSY_MSK               (0x00000001 << STATUS_FRM_RN_BSY_OFST)
+#define STATUS_ADC_DESERON_OFST             (19)
+#define STATUS_ADC_DESERON_MSK              (0x00000001 << STATUS_ADC_DESERON_OFST)
+#define STATUS_PLL_RCNFG_BSY_OFST           (20)
+#define STATUS_PLL_RCNFG_BSY_MSK            (0x00000001 << STATUS_PLL_RCNFG_BSY_OFST)
+#define STATUS_DT_STRMNG_BSY_OFST           (21)
+#define STATUS_DT_STRMNG_BSY_MSK            (0x00000001 << STATUS_DT_STRMNG_BSY_OFST)
+#define STATUS_FRM_PCKR_BSY_OFST            (22)
+#define STATUS_FRM_PCKR_BSY_MSK             (0x00000001 << STATUS_FRM_PCKR_BSY_OFST)
+#define STATUS_PLL_PHS_DN_OFST              (23)
+#define STATUS_PLL_PHS_DN_MSK               (0x00000001 << STATUS_PLL_PHS_DN_OFST)
+#define STATUS_PT_CNTRL_STTS_OFF_OFST       (24)
+#define STATUS_PT_CNTRL_STTS_OFF_MSK        (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
+#define STATUS_IDLE_MSK                     (0x677FF)
+
+/* Look at me RO register TODO */
+#define LOOK_AT_ME_REG                      (0x03 << MEM_MAP_SHIFT)
+
+/* System Status RO register */
+#define SYSTEM_STATUS_REG       		    (0x04 << MEM_MAP_SHIFT)
+
+#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST	(0)
+#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK 	(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
+#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST	(1)
+#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK 	(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
+#define SYSTEM_STATUS_DDR3_INT_DN_OFST		(2)
+#define SYSTEM_STATUS_DDR3_INT_DN_MSK 		(0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
+#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST	(3)
+#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK 	(0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
+#define SYSTEM_STATUS_PLL_A_LCK_OFST		(4)
+#define SYSTEM_STATUS_PLL_A_LCK_MSK 		(0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
+
+/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as PLL_PARAM_REG 0x50 */
+//#define PLL_PARAM_REG                       (0x05 << MEM_MAP_SHIFT)
+
+/* FIFO Data RO register TODO */
+#define FIFO_DATA_REG                       (0x06 << MEM_MAP_SHIFT)
+
+#define FIFO_DATA_HRDWR_SRL_NMBR_OFST       (0)
+#define FIFO_DATA_HRDWR_SRL_NMBR_MSK        (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
+//#define FIFO_DATA_WRD_OFST                  (16)
+//#define FIFO_DATA_WRD_MSK                   (0x0000FFFF << FIFO_DATA_WRD_OFST)
+
+/* FIFO Status RO register TODO */
+#define FIFO_STATUS_REG                     (0x07 << MEM_MAP_SHIFT)
+
+/* FIFO Empty RO register TODO */
+#define FIFO_EMPTY_REG                      (0x08 << MEM_MAP_SHIFT)
+#define FIFO_EMPTY_ALL_EMPTY_MSK			(0xFFFFFFFF)
+
+/* FIFO Full RO register TODO */
+#define FIFO_FULL_REG                       (0x09 << MEM_MAP_SHIFT)
+
+/* MCB Serial Number RO register */
+#define MOD_SERIAL_NUMBER_REG				(0x0A << MEM_MAP_SHIFT)
+
+#define MOD_SERIAL_NUMBER_OFST              (0)
+#define MOD_SERIAL_NUMBER_MSK               (0x000000FF << MOD_SERIAL_NUMBER_OFST)
+#define MOD_SERIAL_NUMBER_VRSN_OFST         (16)
+#define MOD_SERIAL_NUMBER_VRSN_MSK          (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
+
+/* API Version RO register */
+#define API_VERSION_REG                     (0x0F << MEM_MAP_SHIFT)
+
+#define API_VERSION_OFST                    (0)
+#define API_VERSION_MSK                     (0x00FFFFFF << API_VERSION_OFST)
+#define API_VERSION_DTCTR_TYP_OFST          (24)
+#define API_VERSION_DTCTR_TYP_MSK           (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
+
+/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using CONTROL_CRST. TODO */
+#define TIME_FROM_START_LSB_REG   		    (0x10 << MEM_MAP_SHIFT)
+#define TIME_FROM_START_MSB_REG   		    (0x11 << MEM_MAP_SHIFT)
+
+/* Delay Left 64 bit RO register. t = DLY x 50 ns. TODO */
+#define DELAY_LEFT_LSB_REG     			    (0x12 << MEM_MAP_SHIFT)
+#define DELAY_LEFT_MSB_REG     			    (0x13 << MEM_MAP_SHIFT)
+
+/* Cycles Left 64 bit RO register TODO */
+#define CYCLES_LEFT_LSB_REG    			    (0x14 << MEM_MAP_SHIFT)
+#define CYCLES_LEFT_MSB_REG    			    (0x15 << MEM_MAP_SHIFT)
+
+/* Frames Left 64 bit RO register TODO */
+#define FRAMES_LEFT_LSB_REG   			    (0x16 << MEM_MAP_SHIFT)
+#define FRAMES_LEFT_MSB_REG    			    (0x17 << MEM_MAP_SHIFT)
+
+/* Period Left 64 bit RO register. t = T x 50 ns. TODO */
+#define PERIOD_LEFT_LSB_REG    			    (0x18 << MEM_MAP_SHIFT)
+#define PERIOD_LEFT_MSB_REG    			    (0x19 << MEM_MAP_SHIFT)
+
+/* Exposure Time Left 64 bit RO register */
+//#define EXPTIME_LEFT_LSB_REG                (0x1A << MEM_MAP_SHIFT)            // Not used in FW
+//#define EXPTIME_LEFT_MSB_REG                (0x1B << MEM_MAP_SHIFT)            // Not used in FW
+
+/* Gates Left 64 bit RO register */
+//#define GATES_LEFT_LSB_REG                  (0x1C << MEM_MAP_SHIFT)            // Not used in FW
+//#define GATES_LEFT_MSB_REG                  (0x1D << MEM_MAP_SHIFT)            // Not used in FW
+
+/* Data In 64 bit RO register TODO */
+#define DATA_IN_LSB_REG                     (0x1E << MEM_MAP_SHIFT)
+#define DATA_IN_MSB_REG                     (0x1F << MEM_MAP_SHIFT)
+
+/* Pattern Out 64 bit RO register */
+#define PATTERN_OUT_LSB_REG                 (0x20 << MEM_MAP_SHIFT)
+#define PATTERN_OUT_MSB_REG                 (0x21 << MEM_MAP_SHIFT)
+
+/* Frames From Start 64 bit RO register TODO */
+//#define FRAMES_FROM_START_LSB_REG           (0x22 << MEM_MAP_SHIFT)            // Not used in FW
+//#define FRAMES_FROM_START_MSB_REG           (0x23 << MEM_MAP_SHIFT)            // Not used in FW
+
+/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
+#define FRAMES_FROM_START_PG_LSB_REG        (0x24 << MEM_MAP_SHIFT)
+#define FRAMES_FROM_START_PG_MSB_REG        (0x25 << MEM_MAP_SHIFT)
+
+/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame start until reset) TODO */
+#define START_FRAME_TIME_LSB_REG		    (0x26 << MEM_MAP_SHIFT)
+#define START_FRAME_TIME_MSB_REG 		    (0x27 << MEM_MAP_SHIFT)
+
+/* Power Status RO register */
+#define POWER_STATUS_REG                    (0x29 << MEM_MAP_SHIFT)
+
+#define POWER_STATUS_ALRT_OFST              (27)
+#define POWER_STATUS_ALRT_MSK               (0x0000001F << POWER_STATUS_ALRT_OFST)
+
+/* DAC Value Out RO register */
+//#define DAC_VAL_OUT_REG                     (0x2A << MEM_MAP_SHIFT)
+
+/* Slow ADC SPI Value RO register */
+#define ADC_SPI_SLOW_VAL_REG                (0x2B << MEM_MAP_SHIFT)
+
+/* FIFO Digital In Status RO register */
+#define FIFO_DIN_STATUS_REG                 (0x3B << MEM_MAP_SHIFT)
+#define FIFO_DIN_STATUS_FIFO_FULL_OFST		(30)
+#define FIFO_DIN_STATUS_FIFO_FULL_MSK		(0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
+#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST		(31)
+#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK		(0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
+
+/* FIFO Digital In 64 bit RO register */
+#define FIFO_DIN_LSB_REG                    (0x3C << MEM_MAP_SHIFT)
+#define FIFO_DIN_MSB_REG                    (0x3D << MEM_MAP_SHIFT)
+
+/* SPI (Serial Peripheral Interface) DAC, HV RW register */
+#define SPI_REG							    (0x40 << MEM_MAP_SHIFT)
+
+#define SPI_DAC_SRL_DGTL_OTPT_OFST		    (0)
+#define SPI_DAC_SRL_DGTL_OTPT_MSK		    (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
+#define SPI_DAC_SRL_CLK_OTPT_OFST			(1)
+#define SPI_DAC_SRL_CLK_OTPT_MSK			(0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
+#define SPI_DAC_SRL_CS_OTPT_OFST			(2)
+#define SPI_DAC_SRL_CS_OTPT_MSK			    (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
+#define SPI_HV_SRL_DGTL_OTPT_OFST		    (8)
+#define SPI_HV_SRL_DGTL_OTPT_MSK		    (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
+#define SPI_HV_SRL_CLK_OTPT_OFST			(9)
+#define SPI_HV_SRL_CLK_OTPT_MSK			    (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
+#define SPI_HV_SRL_CS_OTPT_OFST			    (10)
+#define SPI_HV_SRL_CS_OTPT_MSK			    (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
+
+/* ADC SPI (Serial Peripheral Interface) RW register */
+#define ADC_SPI_REG   					    (0x41 << MEM_MAP_SHIFT)
+
+#define ADC_SPI_SRL_CLK_OTPT_OFST			(0)
+#define ADC_SPI_SRL_CLK_OTPT_MSK			(0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
+#define ADC_SPI_SRL_DT_OTPT_OFST		    (1)
+#define ADC_SPI_SRL_DT_OTPT_MSK			    (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
+#define ADC_SPI_SRL_CS_OTPT_OFST			(2)
+#define ADC_SPI_SRL_CS_OTPT_MSK			    (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
+#define ADC_SPI_SLOW_SRL_DT_OFST            (8)
+#define ADC_SPI_SLOW_SRL_DT_MSK             (0x00000001 << ADC_SPI_SLOW_SRL_DT_OFST)
+#define ADC_SPI_SLOW_SRL_CLK_OFST           (9)
+#define ADC_SPI_SLOW_SRL_CLK_MSK            (0x00000001 << ADC_SPI_SLOW_SRL_CLK_OFST)
+#define ADC_SPI_SLOW_SRL_CNV_OFST           (10)
+#define ADC_SPI_SLOW_SRL_CNV_MSK            (0x00000001 << ADC_SPI_SLOW_SRL_CNV_OFST)
+
+/* ADC Offset RW register */
+#define ADC_OFFSET_REG 					    (0x42 << MEM_MAP_SHIFT)
+
+#define ADC_OFFSET_ADC_PPLN_OFST            (0)
+#define ADC_OFFSET_ADC_PPLN_MSK             (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
+#define ADC_OFFSET_DBT_PPLN_OFST            (16)
+#define ADC_OFFSET_DBT_PPLN_MSK             (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
+
+/* ADC Port Invert RW register */
+#define ADC_PORT_INVERT_REG   			    (0x43 << MEM_MAP_SHIFT)
+
+#define ADC_PORT_INVERT_0_INPT_OFST         (0)
+#define ADC_PORT_INVERT_0_INPT_MSK          (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
+#define ADC_PORT_INVERT_1_INPT_OFST         (8)
+#define ADC_PORT_INVERT_1_INPT_MSK          (0x000000FF << ADC_PORT_INVERT_1_INPT_OFST)
+#define ADC_PORT_INVERT_2_INPT_OFST         (16)
+#define ADC_PORT_INVERT_2_INPT_MSK          (0x000000FF << ADC_PORT_INVERT_2_INPT_OFST)
+#define ADC_PORT_INVERT_3_INPT_OFST         (24)
+#define ADC_PORT_INVERT_3_INPT_MSK          (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
+
+/* Dummy RW register */
+#define DUMMY_REG                           (0x44 << MEM_MAP_SHIFT)
+
+#define DUMMY_FIFO_CHNNL_SLCT_OFST          (0)
+#define DUMMY_FIFO_CHNNL_SLCT_MSK           (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
+#define DUMMY_ANLG_FIFO_RD_STRBE_OFST       (8)
+#define DUMMY_ANLG_FIFO_RD_STRBE_MSK        (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
+#define DUMMY_DGTL_FIFO_RD_STRBE_OFST       (9)
+#define DUMMY_DGTL_FIFO_RD_STRBE_MSK        (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
+
+/* Receiver IP Address RW register */
+#define RX_IP_REG    			            (0x45 << MEM_MAP_SHIFT)
+
+/* UDP Port RW register */
+#define UDP_PORT_REG    				    (0x46 << MEM_MAP_SHIFT)
+
+#define UDP_PORT_RX_OFST				    (0)
+#define UDP_PORT_RX_MSK					    (0x0000FFFF << UDP_PORT_RX_OFST)
+#define UDP_PORT_TX_OFST				    (16)
+#define UDP_PORT_TX_MSK					    (0x0000FFFF << UDP_PORT_TX_OFST)
+
+/* Receiver Mac Address 64 bit RW register */
+#define RX_MAC_LSB_REG					    (0x47 << MEM_MAP_SHIFT)
+#define RX_MAC_MSB_REG					    (0x48 << MEM_MAP_SHIFT)
+
+#define RX_MAC_LSB_OFST					    (0)
+#define RX_MAC_LSB_MSK					    (0xFFFFFFFF << RX_MAC_LSB_OFST)
+#define RX_MAC_MSB_OFST					    (0)
+#define RX_MAC_MSB_MSK					    (0x0000FFFF << RX_MAC_MSB_OFST)
+
+/* Detector/ Transmitter Mac Address 64 bit RW register */
+#define TX_MAC_LSB_REG					    (0x49 << MEM_MAP_SHIFT)
+#define TX_MAC_MSB_REG					    (0x4A << MEM_MAP_SHIFT)
+
+#define TX_MAC_LSB_OFST					    (0)
+#define TX_MAC_LSB_MSK					    (0xFFFFFFFF << TX_MAC_LSB_OFST)
+#define TX_MAC_MSB_OFST					    (0)
+#define TX_MAC_MSB_MSK					    (0x0000FFFF << TX_MAC_MSB_OFST)
+
+/* Detector/ Transmitter IP Address RW register */
+#define TX_IP_REG						    (0x4B << MEM_MAP_SHIFT)
+
+/* Detector/ Transmitter IP Checksum RW register */
+#define TX_IP_CHECKSUM_REG				    (0x4C << MEM_MAP_SHIFT)
+
+#define TX_IP_CHECKSUM_OFST				    (0)
+#define TX_IP_CHECKSUM_MSK				    (0x0000FFFF << TX_IP_CHECKSUM_OFST)
+
+/* Configuration RW register */
+#define CONFIG_REG            			    (0x4D << MEM_MAP_SHIFT)
+
+#define CONFIG_LED_DSBL_OFST                (0)
+#define CONFIG_LED_DSBL_MSK                 (0x00000001 << CONFIG_LED_DSBL_OFST)
+#define CONFIG_DSBL_ANLG_OTPT_OFST          (8)
+#define CONFIG_DSBL_ANLG_OTPT_MSK           (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
+#define CONFIG_ENBLE_DGTL_OTPT_OFST         (9)
+#define CONFIG_ENBLE_DGTL_OTPT_MSK          (0x00000001 << CONFIG_ENBLE_DGTL_OTPT_OFST)
+#define CONFIG_GB10_SND_UDP_OFST            (12)
+#define CONFIG_GB10_SND_UDP_MSK             (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
+
+/* External Signal RW register */
+#define EXT_SIGNAL_REG        			    (0x4E << MEM_MAP_SHIFT)
+
+#define EXT_SIGNAL_OFST					    (0)
+#define EXT_SIGNAL_MSK					    (0x00000001 << EXT_SIGNAL_OFST)
+#define EXT_SIGNAL_AUTO_VAL                 ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
+#define EXT_SIGNAL_TRGGR_VAL                ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
+
+/* Control RW register */
+#define CONTROL_REG           			    (0x4F << MEM_MAP_SHIFT)
+
+#define CONTROL_STRT_ACQSTN_OFST       	    (0)
+#define CONTROL_STRT_ACQSTN_MSK			    (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
+#define CONTROL_STP_ACQSTN_OFST			    (1)
+#define CONTROL_STP_ACQSTN_MSK			    (0x00000001 << CONTROL_STP_ACQSTN_OFST)
+//#define CONTROL_STRT_FF_TST_OFST            (2)
+//#define CONTROL_STRT_FF_TST_MSK             (0x00000001 << CONTROL_STRT_FF_TST_OFST)
+//#define CONTROL_STP_FF_TST_OFST             (3)
+//#define CONTROL_STP_FF_TST_MSK              (0x00000001 << CONTROL_STP_FF_TST_OFST)
+//#define CONTROL_STRT_RDT_OFST               (4)
+//#define CONTROL_STRT_RDT_MSK                (0x00000001 << CONTROL_STRT_RDT_OFST)
+//#define CONTROL_STP_RDT_OFST                (5)
+//#define CONTROL_STP_RDT_MSK                 (0x00000001 << CONTROL_STP_RDT_OFST)
+#define CONTROL_STRT_EXPSR_OFST             (6)
+#define CONTROL_STRT_EXPSR_MSK              (0x00000001 << CONTROL_STRT_EXPSR_OFST)
+//#define CONTROL_STP_EXPSR_OFST              (7)
+//#define CONTROL_STP_EXPSR_MSK               (0x00000001 << CONTROL_STP_RDT_OFST)
+//#define CONTROL_STRT_TRN_OFST               (8)
+//#define CONTROL_STRT_TRN_MSK                (0x00000001 << CONTROL_STRT_RDT_OFST)
+//#define CONTROL_STP_TRN_OFST                (9)
+//#define CONTROL_STP_TRN_MSK                 (0x00000001 << CONTROL_STP_RDT_OFST)
+#define CONTROL_CRE_RST_OFST			    (10)
+#define CONTROL_CRE_RST_MSK			        (0x00000001 << CONTROL_CRE_RST_OFST)
+#define CONTROL_PRPHRL_RST_OFST		        (11)										// Only GBE10?
+#define CONTROL_PRPHRL_RST_MSK		        (0x00000001 << CONTROL_PRPHRL_RST_OFST)
+#define CONTROL_MMRY_RST_OFST		        (12)
+#define CONTROL_MMRY_RST_MSK		        (0x00000001 << CONTROL_MMRY_RST_OFST)
+//#define CONTROL_PLL_RCNFG_WR_OFST           (13)
+//#define CONTROL_PLL_RCNFG_WR_MSK            (0x00000001 << CONTROL_PLL_RCNFG_WR_OFST)
+#define CONTROL_SND_10GB_PCKT_OFST          (14)
+#define CONTROL_SND_10GB_PCKT_MSK           (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
+#define CONTROL_CLR_ACQSTN_FIFO_OFST		(15)
+#define CONTROL_CLR_ACQSTN_FIFO_MSK		    (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
+
+/* Reconfiguratble PLL Paramater RW register */
+#define PLL_PARAM_REG					    (0x50 << MEM_MAP_SHIFT)
+
+/* Reconfiguratble PLL Control RW regiser */
+#define PLL_CNTRL_REG					    (0x51 << MEM_MAP_SHIFT)
+
+#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST		(0)
+#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK		(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
+#define PLL_CNTRL_WR_PRMTR_OFST		        (2)
+#define PLL_CNTRL_WR_PRMTR_MSK		        (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
+#define PLL_CNTRL_PLL_RST_OFST				(3)
+#define PLL_CNTRL_PLL_RST_MSK				(0x00000001 << PLL_CNTRL_PLL_RST_OFST)
+#define PLL_CNTRL_ADDR_OFST				    (16)
+#define PLL_CNTRL_ADDR_MSK				    (0x0000003F << PLL_CNTRL_ADDR_OFST)
+
+/* Pattern Control RW register */
+#define PATTERN_CNTRL_REG                   (0x52 << MEM_MAP_SHIFT)
+
+#define PATTERN_CNTRL_WR_OFST               (0)
+#define PATTERN_CNTRL_WR_MSK                (0x00000001 << PATTERN_CNTRL_WR_OFST)
+#define PATTERN_CNTRL_RD_OFST               (1)
+#define PATTERN_CNTRL_RD_MSK                (0x00000001 << PATTERN_CNTRL_RD_OFST)
+#define PATTERN_CNTRL_ADDR_OFST             (16)
+#define PATTERN_CNTRL_ADDR_MSK              (0x0000FFFF << PATTERN_CNTRL_ADDR_OFST)
+
+/* Pattern Limit RW regiser */
+#define PATTERN_LIMIT_REG                   (0x53 << MEM_MAP_SHIFT)
+
+#define PATTERN_LIMIT_STRT_OFST       		(0)
+#define PATTERN_LIMIT_STRT_MSK        		(0x0000FFFF << PATTERN_LIMIT_STRT_OFST)
+#define PATTERN_LIMIT_STP_OFST        		(16)
+#define PATTERN_LIMIT_STP_MSK         		(0x0000FFFF << PATTERN_LIMIT_STP_OFST)
+
+/* Pattern Loop 0 Address RW regiser */
+#define PATTERN_LOOP_0_ADDR_REG             (0x54 << MEM_MAP_SHIFT)
+
+#define PATTERN_LOOP_0_ADDR_STRT_OFST       (0)
+#define PATTERN_LOOP_0_ADDR_STRT_MSK        (0x0000FFFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
+#define PATTERN_LOOP_0_ADDR_STP_OFST        (16)
+#define PATTERN_LOOP_0_ADDR_STP_MSK         (0x0000FFFF << PATTERN_LOOP_0_ADDR_STP_OFST)
+
+/* Pattern Loop 0 Iteration RW regiser */
+#define PATTERN_LOOP_0_ITERATION_REG        (0x55 << MEM_MAP_SHIFT)
+
+/* Pattern Loop 1 Address RW regiser */
+#define PATTERN_LOOP_1_ADDR_REG             (0x56 << MEM_MAP_SHIFT)
+
+#define PATTERN_LOOP_1_ADDR_STRT_OFST       (0)
+#define PATTERN_LOOP_1_ADDR_STRT_MSK        (0x0000FFFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
+#define PATTERN_LOOP_1_ADDR_STP_OFST        (16)
+#define PATTERN_LOOP_1_ADDR_STP_MSK         (0x0000FFFF << PATTERN_LOOP_1_ADDR_STP_OFST)
+
+/* Pattern Loop 1 Iteration RW regiser */
+#define PATTERN_LOOP_1_ITERATION_REG        (0x57 << MEM_MAP_SHIFT)
+
+/* Pattern Loop 2 Address RW regiser */
+#define PATTERN_LOOP_2_ADDR_REG             (0x58 << MEM_MAP_SHIFT)
+
+#define PATTERN_LOOP_2_ADDR_STRT_OFST       (0)
+#define PATTERN_LOOP_2_ADDR_STRT_MSK        (0x0000FFFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
+#define PATTERN_LOOP_2_ADDR_STP_OFST        (16)
+#define PATTERN_LOOP_2_ADDR_STP_MSK         (0x0000FFFF << PATTERN_LOOP_2_ADDR_STP_OFST)
+
+/* Pattern Loop 2 Iteration RW regiser */
+#define PATTERN_LOOP_2_ITERATION_REG        (0x59 << MEM_MAP_SHIFT)
+
+/* Pattern Wait 0 RW regiser */
+#define PATTERN_WAIT_0_ADDR_REG             (0x5A << MEM_MAP_SHIFT)
+
+#define PATTERN_WAIT_0_ADDR_OFST            (0)
+#define PATTERN_WAIT_0_ADDR_MSK             (0x0000FFFF << PATTERN_WAIT_0_ADDR_OFST)
+//FIXME: is mask 3FF
+
+/* Pattern Wait 1 RW regiser */
+#define PATTERN_WAIT_1_ADDR_REG             (0x5B << MEM_MAP_SHIFT)
+
+#define PATTERN_WAIT_1_ADDR_OFST            (0)
+#define PATTERN_WAIT_1_ADDR_MSK             (0x0000FFFF << PATTERN_WAIT_1_ADDR_OFST)
+
+/* Pattern Wait 2 RW regiser */
+#define PATTERN_WAIT_2_ADDR_REG             (0x5C << MEM_MAP_SHIFT)
+
+#define PATTERN_WAIT_2_ADDR_OFST            (0)
+#define PATTERN_WAIT_2_ADDR_MSK             (0x0000FFFF << PATTERN_WAIT_2_ADDR_OFST)
+
+/* Samples RW register */
+#define SAMPLES_REG 						(0x5D << MEM_MAP_SHIFT)
+
+/** Power RW register */
+#define POWER_REG					        (0x5E << MEM_MAP_SHIFT)
+
+#define POWER_ENBL_VLTG_RGLTR_OFST          (16)
+#define POWER_ENBL_VLTG_RGLTR_MSK           (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
+#define POWER_HV_SLCT_OFST                  (31)
+#define POWER_HV_SLCT_MSK                   (0x00000001 << POWER_HV_SLCT_OFST)
+
+/* Number of Words RW register TODO */
+#define NUMBER_OF_WORDS_REG                 (0x5F << MEM_MAP_SHIFT)
+
+
+/* Delay 64 bit RW register. t = DLY x 50 ns. */
+#define DELAY_LSB_REG     			        (0x60 << MEM_MAP_SHIFT)
+#define DELAY_MSB_REG     			        (0x61 << MEM_MAP_SHIFT)
+
+/* Cycles 64 bit RW register */
+#define CYCLES_LSB_REG    			        (0x62 << MEM_MAP_SHIFT)
+#define CYCLES_MSB_REG    			        (0x63 << MEM_MAP_SHIFT)
+
+/* Frames 64 bit RW register */
+#define FRAMES_LSB_REG   			        (0x64 << MEM_MAP_SHIFT)
+#define FRAMES_MSB_REG    			        (0x65 << MEM_MAP_SHIFT)
+
+/* Period 64 bit RW register */
+#define PERIOD_LSB_REG    			        (0x66 << MEM_MAP_SHIFT)
+#define PERIOD_MSB_REG    			        (0x67 << MEM_MAP_SHIFT)
+
+/* Period 64 bit RW register */
+//#define EXPTIME_LSB_REG    			    (0x68 << MEM_MAP_SHIFT)                 // Not used in FW
+//#define EXPTIME_MSB_REG    			    (0x69 << MEM_MAP_SHIFT)                 // Not used in FW
+
+/* Gates 64 bit RW register */
+//#define GATES_LSB_REG                      (0x6A << MEM_MAP_SHIFT)                 // Not used in FW
+//#define GATES_MSB_REG                      (0x6B << MEM_MAP_SHIFT)                 // Not used in FW
+
+/* Pattern IO Control 64 bit RW regiser
+ * Each bit configured as output(1)/ input(0) */
+#define PATTERN_IO_CNTRL_LSB_REG            (0x6C << MEM_MAP_SHIFT)
+#define PATTERN_IO_CNTRL_MSB_REG            (0x6D << MEM_MAP_SHIFT)
+
+/* Pattern IO Clock Control 64 bit RW regiser
+ * When bit n enabled (1), clocked output for DIO[n] (T run clock)
+ * When bit n disabled (0), Dio[n] driven by its pattern output */
+#define PATTERN_IO_CLK_CNTRL_LSB_REG        (0x6E << MEM_MAP_SHIFT)
+#define PATTERN_IO_CLK_CNTRL_MSB_REG        (0x6F << MEM_MAP_SHIFT)
+
+/* Pattern In 64 bit RW register */
+#define PATTERN_IN_LSB_REG                  (0x70 << MEM_MAP_SHIFT)
+#define PATTERN_IN_MSB_REG                  (0x71 << MEM_MAP_SHIFT)
+
+/* Pattern Wait Timer 0 64 bit RW register. t = PWT1 x T run clock */
+#define PATTERN_WAIT_TIMER_0_LSB_REG        (0x72 << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_0_MSB_REG        (0x73 << MEM_MAP_SHIFT)
+
+/* Pattern Wait Timer 1 64 bit RW register. t = PWT2 x T run clock */
+#define PATTERN_WAIT_TIMER_1_LSB_REG        (0x74 << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_1_MSB_REG        (0x75 << MEM_MAP_SHIFT)
+
+/* Pattern Wait Timer 2 64 bit RW register. t = PWT3 x T run clock */
+#define PATTERN_WAIT_TIMER_2_LSB_REG        (0x76 << MEM_MAP_SHIFT)
+#define PATTERN_WAIT_TIMER_2_MSB_REG        (0x77 << MEM_MAP_SHIFT)
+
+/* ADC Disable RW register TODO */
+#define ADC_DISABLE_REG                     (0x78 << MEM_MAP_SHIFT)
+
+/* DAC Value RW register TODO  */
+//#define DAC_VALUE_REG                       (0x79 << MEM_MAP_SHIFT)
+
+/* DAC Number RW register TODO */
+//#define DAC_NUMBER_REG                      (0x7A << MEM_MAP_SHIFT)
+
+/* Digital Bit External Trigger RW register */
+#define DBIT_EXT_TRG_REG                    (0x7B << MEM_MAP_SHIFT)
+
+#define DBIT_EXT_TRG_SRC_OFST               (0)
+#define DBIT_EXT_TRG_SRC_MSK                (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
+#define DBIT_EXT_TRG_OPRTN_MD_OFST          (16)
+#define DBIT_EXT_TRG_OPRTN_MD_MSK           (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
+
+/* Pin Delay 0 RW register */
+#define OUTPUT_DELAY_0_REG                  (0x7C << MEM_MAP_SHIFT)
+#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS		(25)
+#define OUTPUT_DELAY_0_OTPT_STTNG_OFST      (0)     //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
+#define OUTPUT_DELAY_0_OTPT_STTNG_MSK       (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
+// 1: load dynamic output settings, 0: trigger start of dynamic output delay configuration pn falling edge of ODT (output delay trigger) bit
+#define OUTPUT_DELAY_0_OTPT_TRGGR_OFST      (31)
+#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK       (0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
+#define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL    (1)
+#define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL  (0)
+
+/* Pin Delay 1 RW register
+ * Each bit configured as enable for dynamic output delay configuration */
+#define PIN_DELAY_1_REG                     (0x7D << MEM_MAP_SHIFT)
+
+/** Pattern Mask 64 bit RW regiser */
+#define PATTERN_MASK_LSB_REG                (0x80 << MEM_MAP_SHIFT)
+#define PATTERN_MASK_MSB_REG                (0x81 << MEM_MAP_SHIFT)
+
+/** Pattern Set 64 bit RW regiser */
+#define PATTERN_SET_LSB_REG                 (0x82 << MEM_MAP_SHIFT)
+#define PATTERN_SET_MSB_REG                 (0x83 << MEM_MAP_SHIFT)
+
+/** I2C Control register */
+#define I2C_TRANSFER_COMMAND_FIFO_REG       (0x100 << MEM_MAP_SHIFT)
+#define I2C_RX_DATA_FIFO_REG                (0x101 << MEM_MAP_SHIFT)
+#define I2C_CONTROL_REG                     (0x102 << MEM_MAP_SHIFT)
+#define I2C_STATUS_REG                      (0x105 << MEM_MAP_SHIFT)
+#define I2C_RX_DATA_FIFO_LEVEL_REG          (0x107 << MEM_MAP_SHIFT)
+#define I2C_SCL_LOW_COUNT_REG               (0x108 << MEM_MAP_SHIFT)
+#define I2C_SCL_HIGH_COUNT_REG              (0x109 << MEM_MAP_SHIFT)
+#define I2C_SDA_HOLD_REG                    (0x10A << MEM_MAP_SHIFT)
+//fixme: upto 0x10f
+
+
+
+
+
+
+

slsDetectorServers/ctbDetectorServer/UDPPacketHeaderGenerator.h

@@ -0,0 +1 @@
+../slsDetectorServer/UDPPacketHeaderGenerator.h

slsDetectorServers/ctbDetectorServer/ansi.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/ansi.h

slsDetectorServers/ctbDetectorServer/blackfin.h

@@ -0,0 +1 @@
+../slsDetectorServer/blackfin.h

slsDetectorServers/ctbDetectorServer/common.h

@@ -0,0 +1 @@
+../slsDetectorServer/common.h

slsDetectorServers/ctbDetectorServer/commonServerFunctions.h

@@ -0,0 +1 @@
+../slsDetectorServer/commonServerFunctions.h

slsDetectorServers/ctbDetectorServer/communication_funcs.c

@@ -0,0 +1 @@
+../slsDetectorServer/communication_funcs.c

slsDetectorServers/ctbDetectorServer/communication_funcs.h

@@ -0,0 +1 @@
+../slsDetectorServer/communication_funcs.h

slsDetectorServers/ctbDetectorServer/communication_funcs_UDP.h

@@ -0,0 +1 @@
+../slsDetectorServer/communication_funcs_UDP.h

slsDetectorServers/ctbDetectorServer/logger.h

@@ -0,0 +1 @@
+../slsDetectorServer/logger.h

slsDetectorServers/ctbDetectorServer/programfpga.h

@@ -0,0 +1 @@
+../slsDetectorServer/programfpga.h

slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.h

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorFunctionList.h

slsDetectorServers/ctbDetectorServer/slsDetectorServer.c

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer.c

slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h

@@ -0,0 +1,99 @@
+#pragma once
+#include "sls_detector_defs.h"
+#include "RegisterDefs.h"
+
+
+#define MIN_REQRD_VRSN_T_RD_API     0x181130
+#define REQRD_FRMWR_VRSN            0x190402
+
+#define CTRL_SRVR_INIT_TIME_US      (1 * 1000 * 1000)
+
+/* Struct Definitions */
+typedef struct ip_header_struct {
+	uint16_t     ip_len;
+	uint8_t      ip_tos;
+	uint8_t      ip_ihl:4 ,ip_ver:4;
+	uint16_t     ip_offset:13,ip_flag:3;
+	uint16_t     ip_ident;
+	uint16_t     ip_chksum;
+	uint8_t      ip_protocol;
+	uint8_t      ip_ttl;
+	uint32_t     ip_sourceip;
+	uint32_t     ip_destip;
+} ip_header;
+
+/* Enums */
+enum CLKINDEX               {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
+enum ADCINDEX				{V_PWR_IO, V_PWR_A, V_PWR_B, V_PWR_C, V_PWR_D, I_PWR_IO, I_PWR_A, I_PWR_B, I_PWR_C, I_PWR_D};
+enum DACINDEX               {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
+                             D10, D11, D12, D13, D14, D15, D16, D17,
+                             D_PWR_D, D_PWR_CHIP, D_PWR_C, D_PWR_B, D_PWR_A, D_PWR_IO};
+
+/* Hardware Definitions */
+#define NCHAN 						(36)
+#define NCHAN_ANALOG                (32)
+#define NCHAN_DIGITAL               (4)
+#define NCHIP 						(1)
+#define NDAC 						(24)
+#define NPWR                        (6)
+#define NDAC_ONLY                   (NDAC - NPWR)
+#define DYNAMIC_RANGE               (16)
+#define NUM_BYTES_PER_PIXEL         (DYNAMIC_RANGE / 8)
+#define CLK_FREQ					(156.25)	/* MHz */
+#define I2C_POWER_VIO_DEVICE_ID     (0x40)
+#define I2C_POWER_VA_DEVICE_ID      (0x41)
+#define I2C_POWER_VB_DEVICE_ID      (0x42)
+#define I2C_POWER_VC_DEVICE_ID      (0x43)
+#define I2C_POWER_VD_DEVICE_ID      (0x44)
+#define I2C_SHUNT_RESISTER_OHMS     (0.005)
+
+/** Default Parameters */
+#define DEFAULT_DATA_BYTES          (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
+#define DEFAULT_NUM_SAMPLES         (1)
+#define DEFAULT_NUM_FRAMES			(1)
+#define DEFAULT_EXPTIME				(0)
+#define DEFAULT_NUM_CYCLES			(1)
+#define DEFAULT_PERIOD				(1 * 1000 * 1000)	//ns
+#define DEFAULT_DELAY				(0)
+#define DEFAULT_HIGH_VOLTAGE		(0)
+#define DEFAULT_VLIMIT              (-100)
+#define DEFAULT_TIMING_MODE			(AUTO_TIMING)
+#define DEFAULT_TX_UDP_PORT			(0x7e9a)
+#define DEFAULT_RUN_CLK             (40)
+#define DEFAULT_ADC_CLK             (20)
+#define DEFAULT_SYNC_CLK            (20)
+#define DEFAULT_DBIT_CLK            (200)
+
+#define HIGHVOLTAGE_MIN             (60)
+#define HIGHVOLTAGE_MAX             (200) // min dac val
+#define DAC_MIN_MV                  (0)
+#define DAC_MAX_MV                  (2500)
+#define VCHIP_MIN_MV                (1673)
+#define VCHIP_MAX_MV                (2668) // min dac val
+#define POWER_RGLTR_MIN             (636)
+#define POWER_RGLTR_MAX             (2638) // min dac val (not vchip-max) because of dac conversions
+#define VCHIP_POWER_INCRMNT         (200)
+#define VIO_MIN_MV                  (1200) // for fpga to function
+
+/* Defines in the Firmware */
+#define MAX_PATTERN_LENGTH  		(0xFFFF)
+#define DIGITAL_IO_DELAY_MAXIMUM_PS	((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
+#define MAX_PHASE_SHIFTS_STEPS		(8)
+
+#define WAIT_TME_US_FR_ACQDONE_REG 	(100) // wait time in us after acquisition done to ensure there is no data in fifo
+#define WAIT_TIME_US_PLL            (10 * 1000)
+#define WAIT_TIME_US_STP_ACQ        (100)
+#define WAIT_TIME_CONFIGURE_MAC     (500 * 1000)
+#define WAIT_TIME_PATTERN_READ     	(10)
+#define WAIT_TIME_FIFO_RD_STROBE  	(10)
+
+/* MSB & LSB DEFINES */
+#define MSB_OF_64_BIT_REG_OFST		(32)
+#define LSB_OF_64_BIT_REG_OFST		(0)
+#define BIT_32_MSK					(0xFFFFFFFF)
+
+#define IP_PACKETSIZE               (0x2032)
+#define ADC_PORT_INVERT_VAL         (0x453b2593)
+#define MAXIMUM_ADC_CLK             (65)
+#define PLL_VCO_FREQ_MHZ            (800)
+

slsDetectorServers/ctbDetectorServer/slsDetectorServer_funcs.c

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer_funcs.c

slsDetectorServers/ctbDetectorServer/slsDetectorServer_funcs.h

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer_funcs.h

slsDetectorServers/ctbDetectorServer/sls_detector_defs.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/sls_detector_defs.h

slsDetectorServers/ctbDetectorServer/sls_detector_funcs.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/sls_detector_funcs.h

slsDetectorServers/ctbDetectorServer/versionAPI.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/versionAPI.h

slsDetectorServers/eigerDetectorServer/9mhvserial_bf.c

@@ -0,0 +1,202 @@
+#include "ansi.h"
+
+#include <termios.h>  	/* POSIX terminal control definitions */
+#include <stdio.h>
+#include <stdlib.h>			// atoi
+#include <fcntl.h>			// File control definitions
+#include <sys/ioctl.h>		// ioctl
+#include <unistd.h>			// read, close
+#include <string.h>  		// memset
+#include <linux/i2c-dev.h>	// I2C_SLAVE, __u8 reg
+#include <errno.h>
+
+#define PORTNAME 				"/dev/ttyBF1"
+#define GOODBYE 				200
+#define BUFFERSIZE 				16
+#define I2C_DEVICE_FILE			"/dev/i2c-0"
+#define I2C_DEVICE_ADDRESS		0x4C
+//#define I2C_DEVICE_ADDRESS	0x48
+#define I2C_REGISTER_ADDRESS	0x40
+
+
+
+int i2c_open(const char* file,unsigned int addr){
+
+	//device file
+	int fd = open( file, O_RDWR );
+	if (fd < 0)	{
+		FILE_LOG(logERROR, ("Warning: Unable to open file %s\n",file));
+		return -1;
+	}
+
+	//device address
+	if( ioctl( fd, I2C_SLAVE, addr&0x7F ) < 0 )	{
+		FILE_LOG(logERROR, ("Warning: Unable to set slave address:0x%x \n",addr));
+		return -2;
+	}
+	return fd;
+}
+
+
+int i2c_read(){
+
+	int fd = i2c_open(I2C_DEVICE_FILE, I2C_DEVICE_ADDRESS);
+	__u8 reg = I2C_REGISTER_ADDRESS & 0xff;
+
+	unsigned char buf = reg;
+	if (write(fd, &buf, 1)!= 1){
+		FILE_LOG(logERROR, ("Warning: Unable to write read request to register %d\n", reg));
+		return -1;
+	}
+	//read and update value (but old value read out)
+	if(read(fd, &buf, 1) != 1){
+		FILE_LOG(logERROR, ("Warning: Unable to read register %d\n", reg));
+		return -2;
+	}
+	//read again to read the updated value
+	if(read(fd, &buf, 1) != 1){
+		FILE_LOG(logERROR, ("Warning: Unable to read register %d\n", reg));
+		return -2;
+	}
+	close(fd);
+	return buf;
+}
+
+
+int i2c_write(unsigned int value){
+
+	__u8 val = value & 0xff;
+
+	int fd = i2c_open(I2C_DEVICE_FILE, I2C_DEVICE_ADDRESS);
+	if(fd < 0)
+		return fd;
+
+	__u8 reg = I2C_REGISTER_ADDRESS & 0xff;
+	char buf[3];
+	buf[0] = reg;
+	buf[1] = val;
+	if (write(fd, buf, 2) != 2) {
+		FILE_LOG(logERROR, ("Warning: Unable to write %d to register %d\n",val, reg));
+		return -1;
+	}
+
+	close(fd);
+	return 0;
+}
+
+
+
+
+
+int main(int argc, char* argv[]) {
+
+	int fd = open(PORTNAME, O_RDWR | O_NOCTTY | O_SYNC);
+	if(fd < 0){
+		FILE_LOG(logERROR, ("Warning: Unable to open port %s\n", PORTNAME));
+		return -1;
+	}
+	FILE_LOG(logINFO, ("opened port at %s\n",PORTNAME));
+
+	struct termios serial_conf;
+	// reset structure
+	memset(&serial_conf,0,sizeof(serial_conf));
+	// control options
+	serial_conf.c_cflag = B2400 | CS8 | CREAD | CLOCAL;
+	// input options
+	serial_conf.c_iflag = IGNPAR;
+	// output options
+	serial_conf.c_oflag = 0;
+	// line options
+	serial_conf.c_lflag = ICANON;
+	// flush input
+	if(tcflush(fd, TCIOFLUSH) < 0){
+		FILE_LOG(logERROR, ("Warning: error form tcflush %d\n", errno));
+		return 0;
+	}
+	// set new options for the port, TCSANOW:changes occur immediately without waiting for data to complete
+	if(tcsetattr(fd, TCSANOW, &serial_conf) < 0){
+		FILE_LOG(logERROR, ("Warning: error form tcsetattr %d\n", errno));
+		return 0;
+	}
+
+	if(tcsetattr(fd, TCSAFLUSH, &serial_conf) < 0){
+		FILE_LOG(logERROR, ("Warning: error form tcsetattr %d\n", errno));
+		return 0;
+	}
+
+	int ret = 0;
+	int n = 0;
+	int ival= 0;
+	char buffer[BUFFERSIZE];
+	memset(buffer,0,BUFFERSIZE);
+	buffer[BUFFERSIZE-1] = '\n';
+	FILE_LOG(logINFO, ("Ready...\n"));
+
+
+	while(ret != GOODBYE){
+		memset(buffer,0,BUFFERSIZE);
+		n = read(fd,buffer,BUFFERSIZE);
+		FILE_LOG(logDEBUG1, ("Received %d Bytes\n", n));
+		FILE_LOG(logINFO, ("Got message: '%s'\n",buffer));
+
+		switch(buffer[0]){
+		case '\0':
+			FILE_LOG(logINFO, ("Got Start (Detector restart)\n"));
+			break;
+		case 's':
+			FILE_LOG(logINFO, ("Got Start \n"));
+			break;
+		case 'p':
+			if (!sscanf(&buffer[1],"%d",&ival)){
+				FILE_LOG(logERROR, ("Warning: cannot scan voltage value\n"));
+				break;
+			}
+			// ok/ fail
+			memset(buffer,0,BUFFERSIZE);
+			buffer[BUFFERSIZE-1] = '\n';
+			if(i2c_write(ival)<0)
+				strcpy(buffer,"fail ");
+			else
+				strcpy(buffer,"success ");
+			FILE_LOG(logINFO, ("Sending: '%s'\n",buffer));
+			n = write(fd, buffer, BUFFERSIZE);
+			FILE_LOG(logDEBUG1, ("Sent %d Bytes\n", n));
+			break;
+
+		case 'g':
+			ival = i2c_read();
+			//ok/ fail
+			memset(buffer,0,BUFFERSIZE);
+			buffer[BUFFERSIZE-1] = '\n';
+			if(ival < 0)
+				strcpy(buffer,"fail ");
+			else
+				strcpy(buffer,"success ");
+			n = write(fd, buffer, BUFFERSIZE);
+			FILE_LOG(logINFO, ("Sending: '%s'\n",buffer));
+			FILE_LOG(logDEBUG1, ("Sent %d Bytes\n", n));
+			//value
+			memset(buffer,0,BUFFERSIZE);
+			buffer[BUFFERSIZE-1] = '\n';
+			if(ival >= 0){
+				FILE_LOG(logINFO, ("Sending: '%d'\n",ival));
+				sprintf(buffer,"%d ",ival);
+				n = write(fd, buffer, BUFFERSIZE);
+				FILE_LOG(logINFO, ("Sent %d Bytes\n", n));
+			}else FILE_LOG(logERROR, ("%s\n",buffer));
+			break;
+
+		case 'e':
+			printf("Exiting Program\n");
+			ret = GOODBYE;
+			break;
+		default:
+			FILE_LOG(logERROR, ("Unknown Command. buffer:'%s'\n",buffer));
+			break;
+		}
+	}
+
+	close(fd);
+	printf("Goodbye Serial Communication for HV(9M)\n");
+	return 0;
+}

slsDetectorServers/eigerDetectorServer/Beb.h

@@ -0,0 +1,84 @@
+#pragma once
+
+
+#include "LocalLinkInterface.h"
+#include "slsDetectorServer_defs.h"
+
+
+struct BebInfo{
+	unsigned int beb_number;
+	unsigned int serial_address;
+	char  src_mac_1GbE[50];
+	char src_mac_10GbE[50];
+	char  src_ip_1GbE[50];
+	char src_ip_10GbE[50];
+	unsigned int src_port_1GbE;
+	unsigned int src_port_10GbE;
+};
+
+
+void BebInfo_BebInfo(struct BebInfo* bebInfo, unsigned int beb_num);
+void BebInfo_BebDstInfo(struct BebInfo* bebInfo, unsigned int beb_num);
+int BebInfo_SetSerialAddress(struct BebInfo* bebInfo, unsigned int add);
+int BebInfo_SetHeaderInfo(struct BebInfo* bebInfo, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);//src_port fixed 42000+beb_number or 52000 + beb_number);
+unsigned int BebInfo_GetBebNumber(struct BebInfo* bebInfo);
+unsigned int BebInfo_GetSerialAddress(struct BebInfo* bebInfo);
+char*  BebInfo_GetSrcMAC(struct BebInfo* bebInfo, int ten_gig);
+char*  BebInfo_GetSrcIP(struct BebInfo* bebInfo, int ten_gig);
+unsigned int BebInfo_GetSrcPort(struct BebInfo* bebInfo, int ten_gig);
+void BebInfo_Print(struct BebInfo* bebInfo);
+void Beb_ClearBebInfos();
+int Beb_InitBebInfos();
+int Beb_CheckSourceStuffBebInfo();
+unsigned int Beb_GetBebInfoIndex(unsigned int beb_numb);
+
+
+void Beb_GetModuleConfiguration(int* master, int* top, int* normal);
+void Beb_EndofDataSend(int tengiga);
+
+int Beb_SetMasterViaSoftware();
+int Beb_SetSlaveViaSoftware();
+int Beb_Activate(int enable);
+int Beb_Set32bitOverflow(int val);
+int Beb_SetNetworkParameter(enum NETWORKINDEX mode, int val);
+int Beb_ResetToHardwareSettings();
+u_int32_t Beb_GetFirmwareRevision();
+u_int32_t Beb_GetFirmwareSoftwareAPIVersion();
+void Beb_ResetFrameNumber();
+int Beb_WriteTo(unsigned int index);
+int Beb_SetMAC(char* mac, uint8_t* dst_ptr);
+int Beb_SetIP(char* ip, uint8_t* dst_ptr);
+int Beb_SetPortNumber(unsigned int port_number, uint8_t* dst_ptr);
+void Beb_AdjustIPChecksum(struct udp_header_type *ip);
+
+int Beb_SetHeaderData(unsigned int beb_number, int ten_gig, char* dst_mac, char* dst_ip, unsigned int dst_port);
+int Beb_SetHeaderData1(char* src_mac, char* src_ip, unsigned int src_port, char* dst_mac, char* dst_ip, unsigned int dst_port);
+
+void Beb_SwapDataFun(int little_endian, unsigned int n, unsigned int *d);
+int Beb_SetByteOrder();
+void Beb_Beb();
+int Beb_SetBebSrcHeaderInfos(unsigned int beb_number, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);
+int Beb_SetUpUDPHeader(unsigned int beb_number, int ten_gig, unsigned int header_number, char* dst_mac, char* dst_ip, unsigned int dst_port);
+
+/*int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int  left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty=1);*/
+int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int  left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty);
+
+int Beb_StopAcquisition();
+int Beb_SetUpTransferParameters(short the_bit_mode);
+/*int Beb_RequestNImages(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait=0); //all images go to the same destination!*/
+int Beb_RequestNImages(unsigned int beb_number, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait);
+
+int Beb_Test(unsigned int beb_number);
+
+int Beb_GetBebFPGATemp();
+
+void Beb_SetDetectorNumber(uint32_t detid);
+int Beb_SetDetectorPosition(int pos[]);
+
+uint16_t Beb_swap_uint16( uint16_t val);
+int Beb_open(u_int32_t** csp0base, u_int32_t offset);
+u_int32_t Beb_Read32 (u_int32_t* baseaddr, u_int32_t offset);
+u_int32_t Beb_Write32 (u_int32_t* baseaddr, u_int32_t offset, u_int32_t data);
+void Beb_close(int fd,u_int32_t* csp0base);
+
+

slsDetectorServers/eigerDetectorServer/FebControl.h

@@ -0,0 +1,157 @@
+#pragma once
+#include "FebInterface.h"
+#include <netinet/in.h>
+
+
+struct Module{
+	unsigned int module_number;
+	int top_address_valid;
+	unsigned int top_left_address;
+	unsigned int top_right_address;
+	int bottom_address_valid;
+	unsigned int bottom_left_address;
+	unsigned int bottom_right_address;
+
+	unsigned int idelay_top[4];    //ll,lr,rl,ll
+	unsigned int idelay_bottom[4]; //ll,lr,rl,ll
+	float high_voltage;
+	int* top_dac;
+	int* bottom_dac;
+};
+
+
+void Module_Module(struct Module* mod,unsigned int number, unsigned int address_top);
+void Module_ModuleBottom(struct Module* mod,unsigned int number, unsigned int address_bottom);
+void Module_Module1(struct Module* mod,unsigned int number, unsigned int address_top, unsigned int address_bottom);
+unsigned int Module_GetModuleNumber(struct Module* mod);
+int Module_TopAddressIsValid(struct Module* mod);
+unsigned int Module_GetTopBaseAddress(struct Module* mod);
+unsigned int Module_GetTopLeftAddress(struct Module* mod) ;
+unsigned int Module_GetTopRightAddress(struct Module* mod);
+unsigned int Module_GetBottomBaseAddress(struct Module* mod);
+int Module_BottomAddressIsValid(struct Module* mod);
+unsigned int Module_GetBottomLeftAddress(struct Module* mod);
+unsigned int Module_GetBottomRightAddress(struct Module* mod);
+unsigned int Module_SetTopIDelay(struct Module* mod,unsigned int chip,unsigned int value);
+unsigned int Module_GetTopIDelay(struct Module* mod,unsigned int chip) ;
+unsigned int Module_SetBottomIDelay(struct Module* mod,unsigned int chip,unsigned int value);
+unsigned int Module_GetBottomIDelay(struct Module* mod,unsigned int chip);
+
+float Module_SetHighVoltage(struct Module* mod,float value);
+float Module_GetHighVoltage(struct Module* mod);
+
+int Module_SetTopDACValue(struct Module* mod,unsigned int i, int value);
+int Module_GetTopDACValue(struct Module* mod,unsigned int i);
+int Module_SetBottomDACValue(struct Module* mod,unsigned int i, int value);
+int Module_GetBottomDACValue(struct Module* mod,unsigned int i);
+
+
+void Feb_Control_activate(int activate);
+
+int Feb_Control_IsBottomModule();
+int Feb_Control_GetModuleNumber();
+
+void Feb_Control_PrintModuleList();
+int Feb_Control_GetModuleIndex(unsigned int module_number, unsigned int* module_index);
+int Feb_Control_CheckModuleAddresses(struct Module* m);
+int Feb_Control_AddModule(unsigned int module_number, unsigned int top_address);
+int Feb_Control_AddModule1(unsigned int module_number, int top_enable, unsigned int top_address, unsigned int bottom_address, int half_module);
+int  Feb_Control_GetDACNumber(char* s, unsigned int* n);
+int  Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch, unsigned int* value);
+int  Feb_Control_VoltageToDAC(float value, unsigned int* digital, unsigned int nsteps, float vmin, float vmax);
+float Feb_Control_DACToVoltage(unsigned int digital,unsigned int nsteps,float vmin,float vmax);
+int Feb_Control_SendIDelays(unsigned int dst_num, int chip_lr, unsigned int channels, unsigned int ndelay_units);
+int Feb_Control_SetStaticBits();
+int Feb_Control_SetStaticBits1(unsigned int the_static_bits);
+int Feb_Control_SendBitModeToBebServer();
+unsigned int Feb_Control_ConvertTimeToRegister(float time_in_sec);
+unsigned int Feb_Control_AddressToAll();
+int Feb_Control_SetCommandRegister(unsigned int cmd);
+int Feb_Control_GetDAQStatusRegister(unsigned int dst_address, unsigned int* ret_status);
+int Feb_Control_StartDAQOnlyNWaitForFinish(int sleep_time_us);
+int Feb_Control_ResetChipCompletely();
+int Feb_Control_ResetChipPartially();
+void Feb_Control_FebControl();
+int Feb_Control_Init(int master, int top, int normal, int module_num);
+int Feb_Control_OpenSerialCommunication();
+void Feb_Control_CloseSerialCommunication();
+int Feb_Control_CheckSetup();
+unsigned int Feb_Control_GetNModules();
+unsigned int Feb_Control_GetNHalfModules();
+
+int Feb_Control_SetHighVoltage(int value);
+int Feb_Control_GetHighVoltage(int* value);
+
+int Feb_Control_SendHighVoltage(int dacvalue);
+int Feb_Control_ReceiveHighVoltage(unsigned int* value);
+
+int Feb_Control_SetIDelays(unsigned int module_num, unsigned int  ndelay_units);
+int Feb_Control_SetIDelays1(unsigned int module_num, unsigned int chip_pos, unsigned int ndelay_units);
+
+int Feb_Control_DecodeDACString(char* dac_str, unsigned int* module_index, int* top, int* bottom, unsigned int* dac_ch);
+int Feb_Control_SetDAC(char* s, int value, int is_a_voltage_mv);
+int Feb_Control_GetDAC(char* s, int* ret_value, int voltage_mv);
+int Feb_Control_GetDACName(unsigned int dac_num,char* s);
+
+int Feb_Control_SetTrimbits(unsigned int module_num, unsigned int* trimbits);
+unsigned int* Feb_Control_GetTrimbits();
+int Feb_Control_SaveAllTrimbitsTo(int value);
+int Feb_Control_Reset();
+int Feb_Control_PrepareForAcquisition();
+
+int Feb_Control_StartAcquisition();
+int Feb_Control_StopAcquisition();
+int Feb_Control_AcquisitionInProgress();
+int Feb_Control_AcquisitionStartedBit();
+int Feb_Control_WaitForFinishedFlag(int sleep_time_us);
+int Feb_Control_WaitForStartedFlag(int sleep_time_us, int prev_flag);
+void Feb_Control_PrintAcquisitionSetup();
+int Feb_Control_SetNExposures(unsigned int n_images);
+unsigned int Feb_Control_GetNExposures();
+int Feb_Control_SetExposureTime(double the_exposure_time_in_sec);
+double Feb_Control_GetExposureTime();
+int64_t Feb_Control_GetExposureTime_in_nsec();
+int Feb_Control_SetSubFrameExposureTime(int64_t the_subframe_exposure_time_in_10nsec);
+int64_t Feb_Control_GetSubFrameExposureTime();
+int Feb_Control_SetSubFramePeriod(int64_t the_subframe_period_in_10nsec);
+int64_t Feb_Control_GetSubFramePeriod();
+int Feb_Control_SetExposurePeriod(double the_exposure_period_in_sec);
+double Feb_Control_GetExposurePeriod();
+int Feb_Control_SetDynamicRange(unsigned int four_eight_sixteen_or_thirtytwo);
+unsigned int Feb_Control_GetDynamicRange();
+int Feb_Control_SetReadoutSpeed(unsigned int readout_speed); //0 was default, 0->full,1->half,2->quarter or 3->super_slow
+int Feb_Control_SetReadoutMode(unsigned int readout_mode); ///0 was default,0->parallel,1->non-parallel,2-> safe_mode
+int Feb_Control_SetTriggerMode(unsigned int trigger_mode, int polarity);//0 and 1 was default,
+int Feb_Control_SetExternalEnableMode(int use_external_enable, int polarity);//0 and 1 was default,
+
+int Feb_Control_SetInTestModeVariable(int on);
+int Feb_Control_GetTestModeVariable();
+
+void Feb_Control_Set_Counter_Bit(int value);
+int Feb_Control_Get_Counter_Bit();
+int Feb_Control_Pulse_Pixel(int npulses,int x, int y);
+int Feb_Control_PulsePixelNMove(int npulses, int inc_x_pos, int inc_y_pos);
+int Feb_Control_Shift32InSerialIn(unsigned int value_to_shift_in);
+int Feb_Control_SendTokenIn();
+int Feb_Control_ClockRowClock(unsigned int ntimes);
+int Feb_Control_PulseChip(int npulses);
+
+int64_t Feb_Control_Get_RateTable_Tau_in_nsec();
+int64_t Feb_Control_Get_RateTable_Period_in_nsec();
+int Feb_Control_SetRateCorrectionTau(int64_t tau_in_Nsec);
+int Feb_Control_SetRateCorrectionTable(unsigned int *table);
+int Feb_Control_GetRateCorrectionVariable();
+void Feb_Control_SetRateCorrectionVariable(int activate_rate_correction);
+int Feb_Control_PrintCorrectedValues();
+
+int Feb_Control_GetLeftFPGATemp();
+int Feb_Control_GetRightFPGATemp();
+
+int64_t Feb_Control_GetMeasuredPeriod();
+int64_t Feb_Control_GetSubMeasuredPeriod();
+
+int Feb_Control_SoftwareTrigger();
+
+uint32_t Feb_Control_WriteRegister(uint32_t offset, uint32_t data);
+uint32_t Feb_Control_ReadRegister(uint32_t offset);
+

slsDetectorServers/eigerDetectorServer/FebInterface.c

@@ -0,0 +1,195 @@
+#include "FebInterface.h"
+#include "LocalLinkInterface.h"
+#include "xparameters.h"
+#include "logger.h"
+
+#include <unistd.h>
+
+
+
+struct LocalLinkInterface ll_local,* ll;
+
+unsigned int  Feb_Interface_nfebs;
+unsigned int* Feb_Interface_feb_numb;
+
+int           Feb_Interface_send_ndata;
+unsigned int  Feb_Interface_send_buffer_size;
+unsigned int* Feb_Interface_send_data_raw;
+unsigned int* Feb_Interface_send_data;
+
+int           Feb_Interface_recv_ndata;
+unsigned int  Feb_Interface_recv_buffer_size;
+unsigned int* Feb_Interface_recv_data_raw;
+unsigned int* Feb_Interface_recv_data;
+
+
+void Feb_Interface_FebInterface() {
+	ll = &ll_local;
+	Feb_Interface_nfebs    = 0;
+	Feb_Interface_feb_numb = 0;
+
+	Feb_Interface_send_ndata = 0;
+	Feb_Interface_send_buffer_size = 1026;
+	Feb_Interface_send_data_raw = malloc((Feb_Interface_send_buffer_size+1) * sizeof(unsigned int));
+	Feb_Interface_send_data     = &Feb_Interface_send_data_raw[1];
+
+	Feb_Interface_recv_ndata = 0;
+	Feb_Interface_recv_buffer_size = 1026;
+	Feb_Interface_recv_data_raw = malloc((Feb_Interface_recv_buffer_size+1) * sizeof(unsigned int));
+	Feb_Interface_recv_data     = &Feb_Interface_recv_data_raw[1];
+
+	Local_LocalLinkInterface1(ll,XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR);
+
+}
+
+
+
+void Feb_Interface_SendCompleteList(unsigned int n,unsigned int* list) {
+	unsigned int i;
+	if (Feb_Interface_feb_numb) free(Feb_Interface_feb_numb);
+	Feb_Interface_nfebs = n;
+	Feb_Interface_feb_numb = malloc(n * sizeof(unsigned int));
+	for(i=0;i<n;i++) Feb_Interface_feb_numb[i] = list[i];
+}
+
+int Feb_Interface_WriteTo(unsigned int ch) {
+	if (ch>0xfff) return 0;
+
+	FILE_LOG(logDEBUG1, ("FIW ch %d\n", ch));
+
+Feb_Interface_send_data_raw[0] = 0x8fff0000;
+if (Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
+
+Feb_Interface_send_data_raw[0] = 0x90000000 | (ch<<16);
+if (Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
+
+Feb_Interface_send_data_raw[0] = 0xc0000000;
+return ((Feb_Interface_send_ndata+1)*4==Local_Write(ll,(Feb_Interface_send_ndata+1)*4,Feb_Interface_send_data_raw));
+}
+
+int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys) {
+	unsigned int t;
+	if (ch>=0xfff) return 0;
+
+	Feb_Interface_recv_data_raw[0] = 0xa0000000 | (ch<<16);
+	Local_Write(ll,4,Feb_Interface_recv_data_raw);
+	usleep(20);
+
+	Feb_Interface_recv_ndata=-1;
+	for(t=0;t<ntrys;t++) {
+		if ((Feb_Interface_recv_ndata=Local_Read(ll,Feb_Interface_recv_buffer_size*4,Feb_Interface_recv_data_raw)/4)>0) {
+			Feb_Interface_recv_ndata--;
+			break;
+		}
+		usleep(1000);
+	}
+
+	return (Feb_Interface_recv_ndata>=0);
+}
+
+
+
+int Feb_Interface_SetByteOrder() {
+	Feb_Interface_send_data_raw[0] = 0x8fff0000;
+	if (Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
+	Feb_Interface_send_ndata   = 2;
+	Feb_Interface_send_data[0] = 0;
+	Feb_Interface_send_data[1] = 0;
+	unsigned int i;
+	unsigned int dst = 0xff;
+	for(i=0;i<Feb_Interface_nfebs;i++) dst = (dst | Feb_Interface_feb_numb[i]);
+	int passed = Feb_Interface_WriteTo(dst);
+
+	return passed;
+}
+
+
+int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read) {
+	return Feb_Interface_ReadRegisters(sub_num,1,&reg_num,value_read);
+}
+
+
+int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read) {
+	//here   cout<<"Reading Register ...."<<endl;
+	unsigned int i;
+	nreads &= 0x3ff;
+	if (!nreads||nreads>Feb_Interface_send_buffer_size-2) return 0;
+
+	Feb_Interface_send_ndata   = nreads+2;
+	Feb_Interface_send_data[0] = 0x20000000 | nreads << 14;
+
+	for(i=0;i<nreads;i++) Feb_Interface_send_data[i+1]=reg_nums[i];
+	Feb_Interface_send_data[nreads+1] = 0;
+
+	if (!Feb_Interface_WriteTo(sub_num)||!Feb_Interface_ReadFrom(sub_num,20)||Feb_Interface_recv_ndata!=(int)(nreads+2)) return 0;
+
+	for(i=0;i<nreads;i++) values_read[i] = Feb_Interface_recv_data[i+1];
+
+	return 1;
+}
+
+int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address) {
+	return Feb_Interface_WriteRegisters(sub_num,1,&reg_num,&value,&wait_on,&wait_on_address);
+}
+
+int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses) {
+	unsigned int i;
+	nwrites &= 0x3ff; //10 bits
+	if (!nwrites||2*nwrites>Feb_Interface_send_buffer_size-2) return 0;
+
+	//cout<<"Write register : "<<this<<"  "<<s_num<<" "<<nwrites<<" "<<reg_nums<<" "<<values<<" "<<wait_ons<<" "<<wait_on_addresses<<endl;
+	Feb_Interface_send_ndata               = 2*nwrites+2;
+	Feb_Interface_send_data[0]           = 0x80000000 | nwrites << 14;
+	Feb_Interface_send_data[2*nwrites+1] = 0;
+
+	for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+1] = 0x3fff&reg_nums[i];
+	for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+2] = values[i];
+	// wait on busy data(28), address of busy flag data(27 downto 14)
+	if (wait_ons&&wait_on_addresses) for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+1] |= (wait_ons[i]<<28 | (0x3fff&wait_on_addresses[i])<<14);
+
+	if (!Feb_Interface_WriteTo(sub_num)) return 0;
+
+	return 1;
+}
+
+int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values) {
+	unsigned int max_single_packet_size = 352;
+	int passed=1;
+	unsigned int n_to_send  = max_single_packet_size;
+	unsigned int ndata_sent = 0;
+	unsigned int ndata_countdown = nwrites;
+	while(ndata_countdown>0) {
+		n_to_send = ndata_countdown<max_single_packet_size ? ndata_countdown:max_single_packet_size;
+		if (!Feb_Interface_WriteMemory(sub_num,mem_num,start_address,n_to_send,&(values[ndata_sent]))) {passed=0; break;}
+		ndata_countdown-=n_to_send;
+		ndata_sent     +=n_to_send;
+		start_address  +=n_to_send;
+		usleep(500);//500 works
+	}
+	return passed;
+}
+
+int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values) {
+	// -1 means write to all
+	unsigned int i;
+	mem_num       &= 0x3f;
+	start_address &= 0x3fff;
+	nwrites       &= 0x3ff;
+	if (!nwrites||nwrites>Feb_Interface_send_buffer_size-2) {
+		FILE_LOG(logERROR, ("invalid nwrites:%d\n",nwrites));
+		return 0;
+	}//*d-1026
+
+	Feb_Interface_send_ndata           =  nwrites+2;//*d-1026
+	Feb_Interface_send_data[0]         = 0xc0000000 | mem_num << 24 | nwrites << 14 | start_address; //cmd -> write to memory, nwrites, mem number, start address
+	Feb_Interface_send_data[nwrites+1] = 0;
+	for(i=0;i<nwrites;i++) Feb_Interface_send_data[i+1] = values[i];
+
+
+	if (!Feb_Interface_WriteTo(sub_num)) return 0;
+
+	return 1;
+}
+
+
+

slsDetectorServers/eigerDetectorServer/FebInterface.h

@@ -0,0 +1,14 @@
+#pragma once
+
+int Feb_Interface_WriteTo(unsigned int ch);
+int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys);
+void Feb_Interface_FebInterface();
+void Feb_Interface_SendCompleteList(unsigned int n,unsigned int* list);
+int Feb_Interface_SetByteOrder();
+int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read);
+int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read);
+int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address);
+int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses);
+int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
+int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
+

slsDetectorServers/eigerDetectorServer/FebRegisterDefs.h

@@ -0,0 +1,221 @@
+
+//daq register definitions
+#define DAQ_REG_CTRL                  	1
+#define DAQ_REG_CHIP_CMDS             	2
+#define DAQ_REG_STATIC_BITS           	3
+#define DAQ_REG_CLK_ROW_CLK_NTIMES    	3
+#define DAQ_REG_SHIFT_IN_32           	3
+#define DAQ_REG_READOUT_NROWS         	3
+#define DAQ_REG_SEND_N_TESTPULSES     	3
+
+#define DAQ_REG_NEXPOSURES            	3
+#define DAQ_REG_EXPOSURE_TIMER        	4 // == (31 downto 3) * 10^(2 downto 0)
+#define DAQ_REG_EXPOSURE_REPEAT_TIMER 	5 // == (31 downto 3) * 10^(2 downto 0)
+#define DAQ_REG_SUBFRAME_EXPOSURES   	6
+#define DAQ_REG_SUBFRAME_PERIOD       	7 //also pg and fifo status register
+
+
+#define DAQ_REG_RO_OFFSET				12
+#define DAQ_REG_STATUS					(DAQ_REG_RO_OFFSET + 0) //also pg and fifo status register
+#define FEB_REG_STATUS              	(DAQ_REG_RO_OFFSET + 3)
+#define MEAS_SUBPERIOD_REG 	 			(DAQ_REG_RO_OFFSET + 4)
+#define MEAS_PERIOD_REG   				(DAQ_REG_RO_OFFSET + 5)
+
+
+
+#define DAQ_CTRL_RESET              0x80000000
+#define DAQ_CTRL_START              0x40000000
+#define ACQ_CTRL_START              0x50000000 //this is 0x10000000 (acq) | 0x40000000 (daq)
+#define DAQ_CTRL_STOP               0x00000000
+
+//direct chip commands to the DAQ_REG_CHIP_CMDS register
+#define DAQ_SET_STATIC_BIT          0x00000001
+#define DAQ_RESET_COMPLETELY        0x0000000E
+#define DAQ_RESET_PERIPHERY         0x00000002
+#define DAQ_RESET_PIXEL_COUNTERS    0x00000004
+#define DAQ_RESET_COLUMN_SELECT     0x00000008
+
+#define DAQ_STORE_IMAGE             0x00000010
+#define DAQ_RELEASE_IMAGE_STORE     0x00000020
+
+#define DAQ_SEND_A_TOKEN_IN         0x00000040
+#define DAQ_CLK_ROW_CLK_NTIMES      0x00000080
+#define DAQ_SERIALIN_SHIFT_IN_32    0x00000100
+#define DAQ_LOAD_16ROWS_OF_TRIMBITS 0x00000200
+
+#define DAQ_IGNORE_INITIAL_CRAP     0x00000400 //crap before readout
+#define DAQ_READOUT_NROWS           0x00000800
+#define DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START 0x00001000 //last 4 bit of data in the last frame
+
+#define DAQ_RELEASE_IMAGE_STORE_AFTER_READOUT  0x00002000
+#define DAQ_RESET_PIXEL_COUNTERS_AFTER_READOUT 0x00004000
+
+#define DAQ_CLK_ROW_CLK_TO_SELECT_NEXT_ROW     0x00008000
+#define DAQ_CLK_MAIN_CLK_TO_SELECT_NEXT_PIXEL  0x00010000
+#define DAQ_SEND_N_TEST_PULSES                 0x00020000
+
+#define DAQ_CHIP_CONTROLLER_HALF_SPEED         0x00040000 //everything at 100 MHz (50MHz ddr readout)
+#define DAQ_CHIP_CONTROLLER_QUARTER_SPEED      0x00080000 //everything at  50 MHz (25MHz ddr readout)
+#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED   0x000c0000 //everything at  ~200 kHz (200 kHz MHz ddr readout)
+
+//#define DAQ_FIFO_ENABLE                       0x00100000 commented out as it is not used anywhere
+#define DAQ_REG_CHIP_CMDS_INT_TRIGGER			0x00100000
+
+//direct chip commands to the DAQ_REG_CHIP_CMDS register
+#define DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE 0x00200000 //row clk is before main clk readout sequence
+#define DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE         0x00400000 //expose ->readout ->expose -> ..., with store is always closed
+#define DAQ_NEXPOSURERS_PARALLEL_MODE                   0x00600000 //parallel acquire/read mode
+
+//DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES is old now hard-wired in the firmware that every image comes with a header
+//#define DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES    0x00800000 //DAQ_IGNORE_INITIAL_CRAP and DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START
+
+#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING          0x01000000 
+#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING_POLARITY 0x02000000
+#define DAQ_NEXPOSURERS_EXTERNAL_TRIGGER_POLARITY  0x04000000
+
+#define DAQ_NEXPOSURERS_INTERNAL_ACQUISITION          0x00000000 //internally controlled
+#define DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START    0x08000000 //external acquisition start
+#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START          0x10000000 //external image start
+#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP 0x18000000 //externally controlly, external image start and stop
+
+#define DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING      0x20000000 
+#define DAQ_NEXPOSURERS_ACTIVATE_RATE_CORRECTION      0x40000000 
+
+//#define DAQ_MASTER_HALF_MODULE                        0x80000000 currently not used
+
+
+//chips static bits 
+#define DAQ_STATIC_BIT_PROGRAM      0x00000001
+#define DAQ_STATIC_BIT_M4           0x00000002 //these are the status bits, not bit mode
+#define DAQ_STATIC_BIT_M8           0x00000004 //these are the status bits, not bit mode
+#define DAQ_STATIC_BIT_M12          0x00000000 //these are the status bits, not bit mode, ie. "00" is 12 bit mode
+#define DAQ_STATIC_BIT_CHIP_TEST    0x00000008
+#define DAQ_STATIC_BIT_ROTEST       0x00000010
+#define DAQ_CS_BAR_LEFT             0x00000020
+#define DAQ_CS_BAR_RIGHT            0x00000040
+
+
+//status flags
+#define DAQ_STATUS_DAQ_RUNNING        0x01
+#define DAQ_DATA_COLLISION_ERROR      0x02
+
+
+#define DAQ_STATUS_CURRENT_M4         0x04 
+#define DAQ_STATUS_CURRENT_M8         0x08
+#define DAQ_STATUS_CURRENT_M12        0x00 //in 12 bit mode both are cleared
+#define DAQ_STATUS_CURRENT_TESTMODE   0x10
+#define DAQ_STATUS_TOKEN_OUT          0x20 
+#define DAQ_STATUS_SERIAL_OUT         0x40 
+#define DAQ_STATUS_PIXELS_ARE_ENABLED 0x80 
+#define DAQ_STATUS_DAQ_RUN_TOGGLE     0x200
+
+//data delay registers
+#define CHIP_DATA_OUT_DELAY_REG_CTRL       1
+#define CHIP_DATA_OUT_DELAY_REG2           2
+#define CHIP_DATA_OUT_DELAY_REG3           3
+#define CHIP_DATA_OUT_DELAY_REG4           4
+#define CHIP_DATA_OUT_DELAY_SET            0x20000000
+
+//module configuration
+#define TOP_BIT_MASK				0x00f
+#define MASTER_BIT_MASK				0x200
+#define NORMAL_MODULE_BIT_MASK		0x400
+
+// Master Slave Top Bottom Definition
+#define MODULE_CONFIGURATION_MASK 0x84
+//Software Configuration
+#define MASTERCONFIG_OFFSET			0x160		//0x20 * 11 (P11)
+#define MASTER_BIT					0x1
+#define	OVERWRITE_HARDWARE_BIT		0x2
+#define DEACTIVATE_BIT				0x4
+
+#define FPGA_TEMP_OFFSET			0x200
+
+#define TXM_DELAY_LEFT_OFFSET		0x180
+#define TXM_DELAY_RIGHT_OFFSET		0x1A0
+#define TXM_DELAY_FRAME_OFFSET		0x1C0
+#define FLOW_REG_OFFSET				0x140
+
+#define FLOW_REG_TXM_FLOW_CNTRL_10G_OFST	(0)
+#define FLOW_REG_TXM_FLOW_CNTRL_10G_MSK		(0x1 << FLOW_REG_TXM_FLOW_CNTRL_10G_OFST)
+#define FLOW_REG_OVERFLOW_32_BIT_OFST		(2)
+#define FLOW_REG_OVERFLOW_32_BIT_MSK		(0x1 << FLOW_REG_OVERFLOW_32_BIT_OFST)
+
+//command memory
+#define LEFT_OFFSET					0x0
+#define RIGHT_OFFSET				0x100
+
+#define FIRST_CMD_PART1_OFFSET		0x8
+#define FIRST_CMD_PART2_OFFSET		0xc
+#define SECOND_CMD_PART1_OFFSET		0x10
+#define SECOND_CMD_PART2_OFFSET		0x14
+#define COMMAND_COUNTER_OFFSET		0x18
+#define STOP_ACQ_OFFSET 			0x1c
+#define STOP_ACQ_BIT				0x40000000
+#define TWO_REQUESTS_OFFSET			0x1c
+#define TWO_REQUESTS_BIT			0x80000000
+
+//version
+#define FIRMWARE_VERSION_OFFSET		0x4
+#define FIRMWARESOFTWARE_API_OFFSET 0x0
+
+#define FRAME_NUM_RESET_OFFSET		0xA0
+
+//1g counters
+#define ONE_GIGA_LEFT_INDEX_LSB_COUNTER		0x04
+#define ONE_GIGA_LEFT_INDEX_MSB_COUNTER		0x24
+
+#define ONE_GIGA_LEFT_TXN_DELAY_COUNTER		0x104
+#define ONE_GIGA_LEFT_FRAME_DELAY_COUNTER	0x124
+
+#define ONE_GIGA_RIGHT_INDEX_LSB_COUNTER	0x44
+#define ONE_GIGA_RIGHT_INDEX_MSB_COUNTER	0x64
+
+#define ONE_GIGA_RIGHT_TXN_DELAY_COUNTER	0x144
+#define ONE_GIGA_RIGHT_FRAME_DELAY_COUNTER	0x164
+
+//10g counters
+#define TEN_GIGA_LEFT_INDEX_LSB_COUNTER		0x84
+#define TEN_GIGA_LEFT_INDEX_MSB_COUNTER		0xa4
+
+#define TEN_GIGA_LEFT_TXN_DELAY_COUNTER		0x184
+#define TEN_GIGA_LEFT_FRAME_DELAY_COUNTER	0x1a4
+
+#define TEN_GIGA_RIGHT_INDEX_LSB_COUNTER	0xc4
+#define TEN_GIGA_RIGHT_INDEX_MSB_COUNTER	0xe4
+
+#define TEN_GIGA_RIGHT_TXN_DELAY_COUNTER	0x1c4
+#define TEN_GIGA_RIGHT_FRAME_DELAY_COUNTER	0x1e4
+
+// udp header (position, id)
+#define UDP_HEADER_A_LEFT_OFST				0x00C0
+#define UDP_HEADER_B_LEFT_OFST				0x00E0
+#define UDP_HEADER_A_RIGHT_OFST				0x0100
+#define UDP_HEADER_B_RIGHT_OFST				0x0120
+
+#define UDP_HEADER_X_OFST					(0)
+#define UDP_HEADER_X_MSK					(0xFFFF << UDP_HEADER_X_OFST)
+#define UDP_HEADER_ID_OFST					(16)
+#define UDP_HEADER_ID_MSK					(0xFFFF << UDP_HEADER_ID_OFST)
+#define UDP_HEADER_Z_OFST					(0)
+#define UDP_HEADER_Z_MSK					(0xFFFF << UDP_HEADER_Z_OFST)
+#define UDP_HEADER_Y_OFST					(16)
+#define UDP_HEADER_Y_MSK					(0xFFFF << UDP_HEADER_Y_OFST)
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

slsDetectorServers/eigerDetectorServer/HardwareIO.c

@@ -0,0 +1,76 @@
+#include "HardwareIO.h"
+
+xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress)
+{
+    /* read the contents of the I/O location and then synchronize the I/O
+     * such that the I/O operation completes before proceeding on
+     */
+
+    xfs_u8 IoContents;
+    __asm__ volatile ("eieio; lbz %0,0(%1)":"=r" (IoContents):"b"
+              (InAddress));
+    return IoContents;
+}
+
+/*****************************************************************************/
+
+xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress)
+{
+    /* read the contents of the I/O location and then synchronize the I/O
+     * such that the I/O operation completes before proceeding on
+     */
+
+    xfs_u16 IoContents;
+    __asm__ volatile ("eieio; lhz %0,0(%1)":"=r" (IoContents):"b"
+              (InAddress));
+    return IoContents;
+}
+
+/*****************************************************************************/
+
+xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress)
+{
+    /* read the contents of the I/O location and then synchronize the I/O
+     * such that the I/O operation completes before proceeding on
+     */
+
+    xfs_u32 IoContents;
+    __asm__ volatile ("eieio; lwz %0,0(%1)":"=r" (IoContents):"b"
+              (InAddress));
+    return IoContents;
+}
+
+/*****************************************************************************/
+
+void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value)
+{
+    /* write the contents of the I/O location and then synchronize the I/O
+     * such that the I/O operation completes before proceeding on
+     */
+
+    __asm__ volatile ("stb %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
+}
+
+/*****************************************************************************/
+void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value)
+{
+    /* write the contents of the I/O location and then synchronize the I/O
+     * such that the I/O operation completes before proceeding on
+     */
+
+    __asm__ volatile ("sth %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
+}
+
+/*****************************************************************************/
+
+void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value)
+{
+    /* write the contents of the I/O location and then synchronize the I/O
+     * such that the I/O operation completes before proceeding on
+     */
+
+    __asm__ volatile ("stw %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
+}
+
+
+

slsDetectorServers/eigerDetectorServer/HardwareIO.h

@@ -0,0 +1,16 @@
+
+//Class initially from Gerd and was called mmap_test.c 
+#pragma once
+
+#include "xfs_types.h"
+
+
+
+  xfs_u8  HWIO_xfs_in8(xfs_u32 InAddress);
+  xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress);
+  xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress);
+
+  void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value);
+  void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value);
+  void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value);
+

slsDetectorServers/eigerDetectorServer/HardwareMMappingDefs.h

@@ -0,0 +1,62 @@
+
+
+//from Gerd and was called mmap_test.h
+
+#ifndef __PLB_LL_FIFO_H__
+#define __PLB_LL_FIFO_H__
+
+
+/******************************************************************************/
+/* definitions                                                                */
+/******************************************************************************/
+
+#define PLB_LL_FIFO_REG_CTRL   0
+#define PLB_LL_FIFO_REG_STATUS 1
+#define PLB_LL_FIFO_REG_FIFO   2
+
+#define PLB_LL_FIFO_CTRL_LL_REM_SHIFT    30
+#define PLB_LL_FIFO_CTRL_LL_REM          0xC0000000
+#define PLB_LL_FIFO_CTRL_LL_EOF          0x20000000
+#define PLB_LL_FIFO_CTRL_LL_SOF          0x10000000
+#define PLB_LL_FIFO_CTRL_LL_MASK         0xF0000000
+
+
+#define PLB_LL_FIFO_CTRL_TX_RESET        0x08000000
+#define PLB_LL_FIFO_CTRL_RX_RESET        0x04000000
+
+#define PLB_LL_FIFO_CTRL_RESET_STATUS    0x00800000
+#define PLB_LL_FIFO_CTRL_RESET_USER      0x00400000
+#define PLB_LL_FIFO_CTRL_RESET_LINK      0x00200000
+#define PLB_LL_FIFO_CTRL_RESET_GT        0x00100000
+
+#define PLB_LL_FIFO_CTRL_RESET_ALL       0x0CF00000
+
+// do not reset complete gtx dual in std. case
+// cause this would reset PLL and stop LL clk
+#define PLB_LL_FIFO_CTRL_RESET_STD       0x0CE00000
+
+// reset Rx and Tx Fifo and set User Reset
+#define PLB_LL_FIFO_CTRL_RESET_FIFO      0x0C400000
+
+
+#define PLB_LL_FIFO_CTRL_CONFIG_VECTOR   0x000FFFFF
+
+
+#define PLB_LL_FIFO_STATUS_LL_REM_SHIFT  30
+#define PLB_LL_FIFO_STATUS_LL_REM        0xC0000000
+#define PLB_LL_FIFO_STATUS_LL_EOF        0x20000000
+#define PLB_LL_FIFO_STATUS_LL_SOF        0x10000000
+
+#define PLB_LL_FIFO_STATUS_EMPTY         0x08000000
+#define PLB_LL_FIFO_STATUS_ALMOSTEMPTY   0x04000000
+#define PLB_LL_FIFO_STATUS_FULL          0x02000000
+#define PLB_LL_FIFO_STATUS_ALMOSTFULL    0x01000000
+
+#define PLB_LL_FIFO_STATUS_VECTOR        0x000FFFFF
+
+#define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS    100
+
+
+#endif // __PLB_LL_FIFO_H__
+
+

slsDetectorServers/eigerDetectorServer/LocalLinkInterface.c

@@ -0,0 +1,220 @@
+#include "LocalLinkInterface.h"
+#include "HardwareMMappingDefs.h"
+#include "logger.h"
+
+#include <unistd.h>
+#include <sys/mman.h>
+#include <fcntl.h>
+
+
+void Local_LocalLinkInterface1(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr) {
+	FILE_LOG(logDEBUG1, ("Initialize PLB LL FIFOs\n"));
+	ll->ll_fifo_base=0;
+	ll->ll_fifo_ctrl_reg=0;
+	if (Local_Init(ll,ll_fifo_badr)) {
+		Local_Reset(ll);
+		FILE_LOG(logDEBUG1, ("\tFIFO Status : 0x%08x\n\n\n", Local_StatusVector(ll)));
+	} else FILE_LOG(logERROR, ("\tCould not map LocalLink : 0x%08x\n\n\n", ll_fifo_badr));
+}
+
+
+void Local_LocalLinkInterface(struct LocalLinkInterface* ll) {
+	FILE_LOG(logDEBUG1, ("Initializing new memory\n"));
+}
+
+
+
+int Local_Init(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr) {
+	int fd;
+	void *plb_ll_fifo_ptr;
+
+	if ((fd=open("/dev/mem", O_RDWR)) < 0) {
+		fprintf(stderr, "Could not open /dev/mem\n");
+		return 0;
+	}
+
+	plb_ll_fifo_ptr =  mmap(0, getpagesize(), PROT_READ | PROT_WRITE, MAP_FILE | MAP_SHARED, fd, ll_fifo_badr);
+	close(fd);
+
+	if (plb_ll_fifo_ptr == MAP_FAILED) {
+		perror ("mmap");
+		return 0;
+	}
+
+	ll->ll_fifo_base = (xfs_u32) plb_ll_fifo_ptr;
+	ll->ll_fifo_ctrl_reg = 0;
+
+	return 1;
+}
+
+
+
+int Local_Reset(struct LocalLinkInterface* ll) {
+	return Local_Reset1(ll,PLB_LL_FIFO_CTRL_RESET_STD);
+}
+
+int Local_Reset1(struct LocalLinkInterface* ll,unsigned int rst_mask) {
+	ll->ll_fifo_ctrl_reg |= rst_mask;
+	FILE_LOG(logDEBUG1, ("\tCTRL Register bits: 0x%08x\n",ll->ll_fifo_ctrl_reg));
+
+	HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
+	HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
+	HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
+	HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
+
+	ll->ll_fifo_ctrl_reg &= (~rst_mask);
+
+	HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
+	return 1;
+}
+
+
+
+unsigned int Local_StatusVector(struct LocalLinkInterface* ll) {
+	return HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
+}
+
+int Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer) {
+	// note: buffer must be word (4 byte) aligned
+	// frame_len in byte
+	int vacancy=0;
+	int i;
+	int words_send = 0;
+	int last_word;
+	unsigned int *word_ptr;
+	unsigned int fifo_ctrl;
+	xfs_u32 status;
+
+	if (buffer_len < 1) return -1;
+
+	last_word = (buffer_len-1)/4;
+	word_ptr = (unsigned int *)buffer;
+
+	FILE_LOG(logDEBUG1, ("LL Write - Len: %2d - If: %X - Data: ",buffer_len, ll->ll_fifo_base));
+	for (i=0; i < buffer_len/4; i++)
+		FILE_LOG(logDEBUG1, ("%.8X ",*(((unsigned *) buffer)+i)));
+
+	while (words_send <= last_word)
+	{
+		while (!vacancy)//wait for Fifo to be empty again
+		{
+			status = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
+			if ((status & PLB_LL_FIFO_STATUS_ALMOSTFULL) == 0) vacancy = 1;
+			if (vacancy == 0) {
+				FILE_LOG(logERROR, ("Fifo full!\n"));
+			}
+		}
+
+		//Just to know: #define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS    100
+		for (i=0; ((i<PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS) && (words_send <= last_word)); i++)
+		{
+			fifo_ctrl = 0;
+			if (words_send == 0)
+			{
+				fifo_ctrl = PLB_LL_FIFO_CTRL_LL_SOF;//announce the start of file
+			}
+
+			if (words_send == last_word)
+			{
+				fifo_ctrl |= (PLB_LL_FIFO_CTRL_LL_EOF | (( (buffer_len-1)<<PLB_LL_FIFO_CTRL_LL_REM_SHIFT) & PLB_LL_FIFO_CTRL_LL_REM)  );
+			}
+			Local_ctrl_reg_write_mask(ll,PLB_LL_FIFO_CTRL_LL_MASK,fifo_ctrl);
+			HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_FIFO,word_ptr[words_send++]);
+		}
+	}
+	return buffer_len;
+}
+
+
+int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer) {
+	static unsigned int buffer_ptr = 0;
+	// note: buffer must be word (4 byte) aligned
+	// frame_len in byte
+	int len;
+	unsigned int *word_ptr;
+	unsigned int status;
+	volatile unsigned int fifo_val;
+	int sof = 0;
+
+	FILE_LOG(logDEBUG1, ("LL Read - If: %X - Data: ",ll->ll_fifo_base));
+
+	word_ptr = (unsigned int *)buffer;
+	do
+	{
+		status = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
+
+		if (!(status & PLB_LL_FIFO_STATUS_EMPTY))
+		{
+			if (status & PLB_LL_FIFO_STATUS_LL_SOF)
+			{
+				if (buffer_ptr)
+				{
+					buffer_ptr = 0;
+					return -1; // buffer overflow
+				}
+				buffer_ptr = 0;
+				sof = 1;
+			}
+
+			fifo_val = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_FIFO);  //read from fifo
+
+			if ((buffer_ptr > 0) || sof)
+			{
+				if ( (buffer_len >> 2) > buffer_ptr)
+				{
+					FILE_LOG(logDEBUG1, ("%.8X ", fifo_val));
+					word_ptr[buffer_ptr++] = fifo_val; //write to buffer
+				}
+				else
+				{
+					buffer_ptr = 0;
+					return -2; // buffer overflow
+				}
+
+				if (status & PLB_LL_FIFO_STATUS_LL_EOF)
+				{
+					len = (buffer_ptr << 2) -3 + ( (status & PLB_LL_FIFO_STATUS_LL_REM)>>PLB_LL_FIFO_STATUS_LL_REM_SHIFT );
+					FILE_LOG(logDEBUG1, ("Len: %d\n",len));
+					buffer_ptr = 0;
+					return len;
+				}
+
+			}
+		}
+	}
+	while(!(status & PLB_LL_FIFO_STATUS_EMPTY));
+
+	return 0;
+}
+
+int Local_ctrl_reg_write_mask(struct LocalLinkInterface* ll,unsigned int mask, unsigned int val) {
+	ll->ll_fifo_ctrl_reg &= (~mask);
+	ll->ll_fifo_ctrl_reg |= ( mask & val);
+	HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
+	return 1;
+}
+
+
+int Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer) {
+
+	int len;
+	unsigned int rec_buff_len = 4096;
+	unsigned int rec_buffer[4097];
+
+
+	Local_Write(ll,buffer_len,buffer);
+	usleep(10000);
+
+	do{
+		len = Local_Read(ll,rec_buff_len,rec_buffer);
+		FILE_LOG(logDEBUG1, ("receive length: %i\n",len));
+
+		if (len > 0) {
+			rec_buffer[len]=0;
+			FILE_LOG(logINFO, ("%s\n", (char*) rec_buffer));
+		}
+	} while(len > 0);
+
+	return 1;
+}
+

slsDetectorServers/eigerDetectorServer/LocalLinkInterface.h

@@ -0,0 +1,21 @@
+#pragma once
+
+#include "HardwareIO.h"
+
+
+struct LocalLinkInterface{
+	xfs_u32      ll_fifo_base;
+	unsigned int ll_fifo_ctrl_reg;
+};
+
+int Local_Init(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr);
+int Local_Reset1(struct LocalLinkInterface* ll,unsigned int rst_mask);
+int Local_ctrl_reg_write_mask(struct LocalLinkInterface* ll,unsigned int mask, unsigned int val);
+void Local_LocalLinkInterface1(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr);
+unsigned int Local_StatusVector(struct LocalLinkInterface* ll);
+int Local_Reset(struct LocalLinkInterface* ll);
+int  Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
+int  Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
+int  Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
+void Local_LocalLinkInterface(struct LocalLinkInterface* ll);
+

slsDetectorServers/eigerDetectorServer/Makefile

@@ -0,0 +1,41 @@
+CC			=	powerpc-4xx-softfloat-gcc
+BLACKFIN_CC = 	bfin-uclinux-gcc
+CFLAGS		+=  -Wall   -DEIGERD   -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE -DPCCOMPILE -DMARTIN
+LDLIBS		+= 	-lm  -lstdc++ 
+
+PROGS		= 	eigerDetectorServer 
+DESTDIR		?= 	bin
+INSTMODE	= 	0777
+
+
+SRC_CLNT	=	communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c  slsDetectorFunctionList.c  HardwareIO.c LocalLinkInterface.c  FebInterface.c FebControl.c Beb.c 
+OBJS 		= 	$(SRC_CLNT:.c=.o) 
+ 
+
+all: clean versioning $(PROGS) #hv9m_blackfin_server 
+
+	
+boot: $(OBJS) 
+
+version_name=APIEIGER
+version_path=slsDetectorServers/eigerDetectorServer
+versioning: 
+	cd ../../ && echo $(PWD) && echo `tput setaf 6; ./updateAPIVersion.sh $(version_name) $(version_path);  tput sgr0;`
+
+
+$(PROGS):  $(OBJS)
+#	echo $(OBJS) 
+	mkdir -p $(DESTDIR) 
+	$(CC)  	-o $@  $(SRC_CLNT) $(CFLAGS) $(LDLIBS) 
+	mv $(PROGS) $(DESTDIR)
+	
+
+hv9m_blackfin_server:9mhvserial_bf.c
+	$(BLACKFIN_CC) -o hv9m_blackfin_server 9mhvserial_bf.c -Wall #-DVERBOSE
+	mv hv9m_blackfin_server $(DESTDIR)	
+	rm hv9m_blackfin_server.gdb
+
+clean:
+	rm -rf $(DESTDIR)/$(PROGS)  *.o $(DESTDIR)/hv9m_blackfin_server 
+	
+	

slsDetectorServers/eigerDetectorServer/Makefile.virtual

@@ -0,0 +1,28 @@
+CC				=	gcc
+CFLAGS			+=  -Wall    -DEIGERD    -DPCCOMPILE -DSTOP_SERVER  #-DVERBOSE 
+CFLAGS			+= -DVIRTUAL -DVIRTUAL_9M
+MASTERFLAG		+= -DVIRTUAL_MASTER
+LDLIBS			+= 	-lm  -lstdc++ -pthread
+
+DESTDIR			?= 	bin
+
+SRC_CLNT		=	communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c  slsDetectorFunctionList.c 
+
+
+
+all: clean master slave
+
+	
+master: $(SRC_CLNT)
+	mkdir -p $(DESTDIR) 
+	$(CC)  -o eigerDetectorServer_virtualMaster $(SRC_CLNT) $(CFLAGS) $(MASTERFLAG) $(LDLIBS) 	
+	mv eigerDetectorServer_virtualMaster $(DESTDIR)
+	
+slave: $(SRC_CLNT)
+	mkdir -p $(DESTDIR) 
+	$(CC)  -o eigerDetectorServer_virtualSlave $(SRC_CLNT) $(CFLAGS) $(LDLIBS) 	
+	mv eigerDetectorServer_virtualSlave $(DESTDIR)
+
+clean:
+	rm -rf $(DESTDIR)/eigerDetectorServer_virtualMaster $(DESTDIR)/eigerDetectorServer_virtualSlave *.o
+	

slsDetectorServers/eigerDetectorServer/ansi.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/ansi.h

slsDetectorServers/eigerDetectorServer/common.h

@@ -0,0 +1 @@
+../slsDetectorServer/common.h

slsDetectorServers/eigerDetectorServer/communication_funcs.c

@@ -0,0 +1 @@
+../slsDetectorServer/communication_funcs.c

slsDetectorServers/eigerDetectorServer/communication_funcs.h

@@ -0,0 +1 @@
+../slsDetectorServer/communication_funcs.h

slsDetectorServers/eigerDetectorServer/logger.h

@@ -0,0 +1 @@
+../slsDetectorServer/logger.h

slsDetectorServers/eigerDetectorServer/renameServer.sh

@@ -0,0 +1,4 @@
+mv bin/eigerDetectorServer bin/$2
+cp bin/$2 /tftpboot
+git rm -f bin/$1
+git add bin/$2

slsDetectorServers/eigerDetectorServer/slsDetectorFunctionList.h

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorFunctionList.h

slsDetectorServers/eigerDetectorServer/slsDetectorServer.c

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer.c

slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h

@@ -0,0 +1,86 @@
+#pragma once
+#include "sls_detector_defs.h"
+
+#define REQUIRED_FIRMWARE_VERSION 	 		(22)
+#define IDFILECOMMAND						"more /home/root/executables/detid.txt"
+
+#define STATUS_IDLE		0
+#define STATUS_RUNNING	1
+#define STATUS_ERROR	2
+
+/* Enums */
+enum CLK_SPEED_INDEX						{FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
+enum DACINDEX					 			{SVP,VTR,VRF,VRS,SVN,VTGSTV,VCMP_LL,VCMP_LR,CAL,VCMP_RL,RXB_RB,RXB_LB,VCMP_RR,VCP,VCN,VIS,VTHRESHOLD};
+#define DEFAULT_DAC_VALS	 	 			{	\
+									 		0, 		/* SvP		*/	\
+								 			2480, 	/* Vtr		*/	\
+								 			3300, 	/* Vrf		*/	\
+								 			1400, 	/* Vrs		*/	\
+								 			4000, 	/* SvN		*/	\
+								 			2556, 	/* Vtgstv	*/	\
+								  			1000, 	/* Vcmp_ll	*/	\
+								 			1000, 	/* Vcmp_lr	*/	\
+								 			4000, 	/* cal		*/	\
+									 		1000, 	/* Vcmp_rl	*/	\
+									 		1100, 	/* rxb_rb	*/	\
+									 		1100, 	/* rxb_lb	*/	\
+									 		1000, 	/* Vcmp_rr	*/	\
+									 		1000, 	/* Vcp		*/	\
+									 		2000, 	/* Vcn		*/	\
+									 		1550 	/* Vis		*/	\
+									 		};
+enum ADCINDEX						 		{TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
+enum NETWORKINDEX				 			{TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
+enum										{E_PARALLEL, E_NON_PARALLEL, E_SAFE};
+
+/* Hardware Definitions */
+#define NCHAN 						 		(256 * 256)
+#define NCHIP 						 		(4)
+#define NDAC 						 		(16)
+
+
+#define TEN_GIGA_BUFFER_SIZE 				(4112)
+#define ONE_GIGA_BUFFER_SIZE 				(1040)
+#define TEN_GIGA_CONSTANT	 				(4)
+#define ONE_GIGA_CONSTANT 					(16)
+#define NORMAL_HIGHVOLTAGE_INPUTPORT 		"/sys/class/hwmon/hwmon5/device/in0_input"
+#define NORMAL_HIGHVOLTAGE_OUTPUTPORT 		"/sys/class/hwmon/hwmon5/device/out0_output"
+#define SPECIAL9M_HIGHVOLTAGE_PORT 			"/dev/ttyS1"
+#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE 	(16)
+
+/** Default Parameters */
+#define DEFAULT_NUM_FRAMES					(1)
+#define DEFAULT_NUM_CYCLES					(1)
+#define DEFAULT_EXPTIME						(1E9)			//ns
+#define DEFAULT_PERIOD						(1E9)			//ns
+#define DEFAULT_DELAY						(0)
+#define DEFAULT_HIGH_VOLTAGE				(0)
+#define DEFAULT_SETTINGS					(DYNAMICGAIN)
+#define DEFAULT_SUBFRAME_EXPOSURE 			(2621440) 		// 2.6ms
+#define DEFAULT_SUBFRAME_DEADTIME			(0)
+#define DEFAULT_DYNAMIC_RANGE				(16)
+
+#define DEFAULT_READOUT_MODE				(NONPARALLEL)
+#define DEFAULT_READOUT_STOREINRAM_MODE		(CONTINOUS_RO)
+#define DEFAULT_READOUT_OVERFLOW32_MODE		(NOOVERFLOW)
+#define DEFAULT_CLK_SPEED					(HALF_SPEED)
+#define DEFAULT_IO_DELAY					(650)
+#define DEFAULT_TIMING_MODE					(AUTO_TIMING)
+#define DEFAULT_PHOTON_ENERGY				(-1)
+#define DEFAULT_RATE_CORRECTION				(0)
+#define DEFAULT_EXT_GATING_ENABLE			(0)
+#define DEFAULT_EXT_GATING_POLARITY			(1)				//positive
+#define DEFAULT_TEST_MODE					(0)
+#define DEFAULT_HIGH_VOLTAGE				(0)
+
+#define DAC_MIN_MV                          (0)
+#define DAC_MAX_MV                          (2048)
+#define LTC2620_MIN_VAL                     (0)     // including LTC defines instead of LTC262.h (includes bit banging and blackfin read and write)
+#define LTC2620_MAX_VAL                     (4095) // 12 bits
+#define DAC_MAX_STEPS                       (4096)
+
+#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS	(0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
+
+#define SLAVE_HIGH_VOLTAGE_READ_VAL			(-999)
+#define HIGH_VOLTAGE_TOLERANCE				(5)
+

slsDetectorServers/eigerDetectorServer/slsDetectorServer_funcs.c

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer_funcs.c

slsDetectorServers/eigerDetectorServer/slsDetectorServer_funcs.h

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer_funcs.h

slsDetectorServers/eigerDetectorServer/sls_detector_defs.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/sls_detector_defs.h

slsDetectorServers/eigerDetectorServer/sls_detector_funcs.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/sls_detector_funcs.h

slsDetectorServers/eigerDetectorServer/versionAPI.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/versionAPI.h

slsDetectorServers/eigerDetectorServer/xfs_types.h

@@ -0,0 +1,48 @@
+#pragma once
+
+//#include "types.h"
+#include <stdint.h>
+/******************************************************************************/
+/* types                                                                      */
+/******************************************************************************/
+
+typedef unsigned int xfs_u32;
+typedef unsigned short xfs_u16;
+typedef unsigned char xfs_u8;
+
+typedef signed int xfs_i32;
+typedef signed short xfs_i16;
+typedef signed char xfs_i8;
+
+
+// UDP Header
+struct udp_header_type
+{
+  // ethternet frame  (14 byte)
+  uint8_t dst_mac[6];
+  uint8_t src_mac[6];
+  uint8_t len_type[2];
+  
+  // ip header    (20 byte)
+  uint8_t ver_headerlen[1];
+  uint8_t service_type[1];
+  uint8_t total_length[2];
+  uint8_t identification[2];
+  uint8_t flags[1];
+  uint8_t frag_offset[1];
+  uint8_t time_to_live[1];
+  uint8_t protocol[1];
+  uint8_t ip_header_checksum[2];
+  uint8_t src_ip[4];
+  uint8_t dst_ip[4];
+
+  // udp header   (8 byte)
+  uint8_t src_port[2];
+  uint8_t dst_port[2];
+  uint8_t udp_message_len[2];
+  uint8_t udp_checksum[2];
+
+};
+
+
+

slsDetectorServers/eigerDetectorServer/xparameters.h

@@ -0,0 +1,538 @@
+/* ONLY THOSE ARE USED IN THIS SOFTWARE. If one of those is modified in xilinx compilation, this file should be replaced with updated values
+XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR
+XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR
+XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR
+XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
+XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR
+XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
+*/
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by libgen.
+* Version: Xilinx EDK 12.4 EDK_MS4.81d
+* DO NOT EDIT.
+*
+* Copyright (c) 1995-2010 Xilinx, Inc.  All rights reserved.
+
+* 
+* Description: Driver parameters
+*
+*******************************************************************/
+
+#define STDIN_BASEADDRESS 0xC0000000
+#define STDOUT_BASEADDRESS 0xC0000000
+
+/******************************************************************/
+
+
+/* Definitions for peripheral BB_IO_SHIFT_REG_PPC440 */
+#define XPAR_BB_IO_SHIFT_REG_PPC440_BASEADDR 0xD3000000
+#define XPAR_BB_IO_SHIFT_REG_PPC440_HIGHADDR 0xD300FFFF
+
+
+/* Definitions for peripheral EIGER_BEB_SYNCH_IO_PPC440 */
+#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_BASEADDR 0xD3100000
+#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_HIGHADDR 0xD310FFFF
+
+
+/* Definitions for peripheral PLB_BRAM_10G */
+#define XPAR_PLB_BRAM_10G_MEM0_BASEADDR 0xD4100000
+#define XPAR_PLB_BRAM_10G_MEM0_HIGHADDR 0xD410FFFF
+
+
+/* Definitions for peripheral PLB_BRAM_TEMAC */
+#define XPAR_PLB_BRAM_TEMAC_MEM0_BASEADDR 0xD4000000
+#define XPAR_PLB_BRAM_TEMAC_MEM0_HIGHADDR 0xD400FFFF
+
+
+/* Definitions for peripheral PLB_GPIO_SYS */
+#define XPAR_PLB_GPIO_SYS_BASEADDR 0xD1000000
+#define XPAR_PLB_GPIO_SYS_HIGHADDR 0xD100FFFF
+
+/** Command Generator */
+#define XPAR_CMD_GENERATOR 0xC5000000
+
+
+/** Version Numbers */
+#define XPAR_VERSION 			0xc6000000
+
+/* Definitions for peripheral PLB_GPIO_TEST */
+#define XPAR_PLB_GPIO_TEST_BASEADDR 0xD1010000
+#define XPAR_PLB_GPIO_TEST_HIGHADDR 0xD101FFFF
+
+
+
+/* Definitions for packet, frame and delay down counters */
+#define XPAR_COUNTER_BASEADDR 0xD1020000
+#define XPAR_COUNTER_HIGHADDR 0xD102FFFF
+
+
+/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT */
+#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR 0xC4100000
+#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_HIGHADDR 0xC410FFFF
+
+/* Definitions for a new memory */
+//#define XPAR_PLB_LL_NEW_MEMORY        0xD1000000//0xD1000084//0xC4200000
+
+
+/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT */
+#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR 0xC4110000
+#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_HIGHADDR 0xC411FFFF
+
+
+/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_LEFT */
+#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR 0xC4120000
+#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_HIGHADDR 0xC412FFFF
+
+
+/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT */
+#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR 0xC4130000
+#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_HIGHADDR 0xC413FFFF
+
+
+/* Definitions for peripheral PLB_LL_FIFO_XAUI_10G */
+#define XPAR_PLB_LL_FIFO_XAUI_10G_BASEADDR 0xC4140000
+#define XPAR_PLB_LL_FIFO_XAUI_10G_HIGHADDR 0xC414FFFF
+
+
+/* Definitions for peripheral PLB_V46_CPU_TO_PLB_V46_BRIDGED */
+#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_BASEADDR 0xCFFF0000
+#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_HIGHADDR 0xCFFFFFFF
+#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_BASEADDR 0xD0000000
+#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_HIGHADDR 0xDFFFFFFF
+
+
+/* Definitions for peripheral PPC_SRAM */
+#define XPAR_PPC_SRAM_BASEADDR 0x00000000
+#define XPAR_PPC_SRAM_HIGHADDR 0x01FFFFFF
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral PFLASH */
+#define XPAR_PFLASH_NUM_BANKS_MEM 1
+
+
+/******************************************************************/
+
+/* Definitions for peripheral PFLASH */
+#define XPAR_PFLASH_MEM0_BASEADDR 0xE0000000
+#define XPAR_PFLASH_MEM0_HIGHADDR 0xE3FFFFFF
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral PFLASH */
+#define XPAR_EMC_0_NUM_BANKS_MEM 1
+#define XPAR_EMC_0_MEM0_BASEADDR 0xE0000000
+#define XPAR_EMC_0_MEM0_HIGHADDR 0xE3FFFFFF
+
+/******************************************************************/
+
+/* Definitions for driver PLB_SHT1X_IF */
+#define XPAR_PLB_SHT1X_IF_NUM_INSTANCES 2
+
+/* Definitions for peripheral PLB_SHT1X_IF_CH1 */
+#define XPAR_PLB_SHT1X_IF_CH1_DEVICE_ID 0
+#define XPAR_PLB_SHT1X_IF_CH1_BASEADDR 0xD2200000
+#define XPAR_PLB_SHT1X_IF_CH1_HIGHADDR 0xD220FFFF
+
+
+/* Definitions for peripheral PLB_SHT1X_IF_CH2 */
+#define XPAR_PLB_SHT1X_IF_CH2_DEVICE_ID 1
+#define XPAR_PLB_SHT1X_IF_CH2_BASEADDR 0xD2210000
+#define XPAR_PLB_SHT1X_IF_CH2_HIGHADDR 0xD221FFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver UARTLITE */
+#define XPAR_XUARTLITE_NUM_INSTANCES 1
+
+/* Definitions for peripheral RS232 */
+#define XPAR_RS232_BASEADDR 0xC0000000
+#define XPAR_RS232_HIGHADDR 0xC000FFFF
+#define XPAR_RS232_DEVICE_ID 0
+#define XPAR_RS232_BAUDRATE 115200
+#define XPAR_RS232_USE_PARITY 0
+#define XPAR_RS232_ODD_PARITY 0
+#define XPAR_RS232_DATA_BITS 8
+
+
+/******************************************************************/
+
+
+/* Canonical definitions for peripheral RS232 */
+#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_DEVICE_ID
+#define XPAR_UARTLITE_0_BASEADDR 0xC0000000
+#define XPAR_UARTLITE_0_HIGHADDR 0xC000FFFF
+#define XPAR_UARTLITE_0_BAUDRATE 115200
+#define XPAR_UARTLITE_0_USE_PARITY 0
+#define XPAR_UARTLITE_0_ODD_PARITY 0
+#define XPAR_UARTLITE_0_DATA_BITS 8
+#define XPAR_UARTLITE_0_SIO_CHAN 1
+
+
+/******************************************************************/
+
+/* Definitions for driver SPI */
+#define XPAR_XSPI_NUM_INSTANCES 2
+
+/* Definitions for peripheral SPI_FLASH */
+#define XPAR_SPI_FLASH_DEVICE_ID 0
+#define XPAR_SPI_FLASH_BASEADDR 0xD2000000
+#define XPAR_SPI_FLASH_HIGHADDR 0xD200FFFF
+#define XPAR_SPI_FLASH_FIFO_EXIST 1
+#define XPAR_SPI_FLASH_SPI_SLAVE_ONLY 0
+#define XPAR_SPI_FLASH_NUM_SS_BITS 1
+#define XPAR_SPI_FLASH_NUM_TRANSFER_BITS 8
+
+
+/* Definitions for peripheral XPS_SPI_FEB_CFG */
+#define XPAR_XPS_SPI_FEB_CFG_DEVICE_ID 1
+#define XPAR_XPS_SPI_FEB_CFG_BASEADDR 0xD2010000
+#define XPAR_XPS_SPI_FEB_CFG_HIGHADDR 0xD201FFFF
+#define XPAR_XPS_SPI_FEB_CFG_FIFO_EXIST 1
+#define XPAR_XPS_SPI_FEB_CFG_SPI_SLAVE_ONLY 0
+#define XPAR_XPS_SPI_FEB_CFG_NUM_SS_BITS 2
+#define XPAR_XPS_SPI_FEB_CFG_NUM_TRANSFER_BITS 8
+
+
+/******************************************************************/
+
+
+/* Canonical definitions for peripheral SPI_FLASH */
+#define XPAR_SPI_0_DEVICE_ID XPAR_SPI_FLASH_DEVICE_ID
+#define XPAR_SPI_0_BASEADDR 0xD2000000
+#define XPAR_SPI_0_HIGHADDR 0xD200FFFF
+#define XPAR_SPI_0_FIFO_EXIST 1
+#define XPAR_SPI_0_SPI_SLAVE_ONLY 0
+#define XPAR_SPI_0_NUM_SS_BITS 1
+#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
+
+
+/* Canonical definitions for peripheral XPS_SPI_FEB_CFG */
+#define XPAR_SPI_1_DEVICE_ID XPAR_XPS_SPI_FEB_CFG_DEVICE_ID
+#define XPAR_SPI_1_BASEADDR 0xD2010000
+#define XPAR_SPI_1_HIGHADDR 0xD201FFFF
+#define XPAR_SPI_1_FIFO_EXIST 1
+#define XPAR_SPI_1_SPI_SLAVE_ONLY 0
+#define XPAR_SPI_1_NUM_SS_BITS 2
+#define XPAR_SPI_1_NUM_TRANSFER_BITS 8
+
+
+/******************************************************************/
+
+/* Definitions for driver LLTEMAC */
+#define XPAR_XLLTEMAC_NUM_INSTANCES 1
+
+/* Definitions for peripheral TEMAC_INST Channel 0 */
+#define XPAR_TEMAC_INST_CHAN_0_DEVICE_ID 0
+#define XPAR_TEMAC_INST_CHAN_0_BASEADDR 0xC3000000
+#define XPAR_TEMAC_INST_CHAN_0_HIGHADDR 0xC30FFFFF
+#define XPAR_TEMAC_INST_CHAN_0_TXCSUM 0
+#define XPAR_TEMAC_INST_CHAN_0_RXCSUM 0
+#define XPAR_TEMAC_INST_CHAN_0_PHY_TYPE 4
+#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TRAN 0
+#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TRAN 0
+#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TAG 0
+#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TAG 0
+#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_STRP 0
+#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_STRP 0
+#define XPAR_TEMAC_INST_CHAN_0_MCAST_EXTEND 0
+
+/* Canonical definitions for peripheral TEMAC_INST Channel 0 */
+#define XPAR_LLTEMAC_0_DEVICE_ID 0
+#define XPAR_LLTEMAC_0_BASEADDR 0xC3000000
+#define XPAR_LLTEMAC_0_HIGHADDR 0xC30FFFFF
+#define XPAR_LLTEMAC_0_TXCSUM 0
+#define XPAR_LLTEMAC_0_RXCSUM 0
+#define XPAR_LLTEMAC_0_PHY_TYPE 4
+#define XPAR_LLTEMAC_0_TXVLAN_TRAN 0
+#define XPAR_LLTEMAC_0_RXVLAN_TRAN 0
+#define XPAR_LLTEMAC_0_TXVLAN_TAG 0
+#define XPAR_LLTEMAC_0_RXVLAN_TAG 0
+#define XPAR_LLTEMAC_0_TXVLAN_STRP 0
+#define XPAR_LLTEMAC_0_RXVLAN_STRP 0
+#define XPAR_LLTEMAC_0_MCAST_EXTEND 0
+#define XPAR_LLTEMAC_0_INTR 1
+
+
+/* LocalLink TYPE Enumerations */
+#define XPAR_LL_FIFO    1
+#define XPAR_LL_DMA     2
+
+
+/* Canonical LocalLink parameters for TEMAC_INST */
+
+
+/******************************************************************/
+
+
+/* Definitions for peripheral XPS_BRAM_IF_CNTLR_PPC440 */
+#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_BASEADDR 0xFFFC0000
+#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_HIGHADDR 0xFFFFFFFF
+
+
+/******************************************************************/
+
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 5
+#define XPAR_XINTC_HAS_IPR 1
+#define XPAR_XINTC_USE_DCR 0
+/* Definitions for driver INTC */
+#define XPAR_XINTC_NUM_INSTANCES 1
+
+/* Definitions for peripheral XPS_INTC_PPC440 */
+#define XPAR_XPS_INTC_PPC440_DEVICE_ID 0
+#define XPAR_XPS_INTC_PPC440_BASEADDR 0xC1000000
+#define XPAR_XPS_INTC_PPC440_HIGHADDR 0xC100FFFF
+#define XPAR_XPS_INTC_PPC440_KIND_OF_INTR 0xFFFFFFF4
+
+
+/******************************************************************/
+
+#define XPAR_INTC_SINGLE_BASEADDR 0xC1000000
+#define XPAR_INTC_SINGLE_HIGHADDR 0xC100FFFF
+#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
+#define XPAR_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_MASK 0X000001
+#define XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR 0
+#define XPAR_TEMAC_INST_TEMACINTC0_IRPT_MASK 0X000002
+#define XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR 1
+#define XPAR_XPS_TIMER_PPC440_INTERRUPT_MASK 0X000004
+#define XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR 2
+#define XPAR_SPI_FLASH_IP2INTC_IRPT_MASK 0X000008
+#define XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR 3
+#define XPAR_RS232_INTERRUPT_MASK 0X000010
+#define XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR 4
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral XPS_INTC_PPC440 */
+#define XPAR_INTC_0_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
+#define XPAR_INTC_0_BASEADDR 0xC1000000
+#define XPAR_INTC_0_HIGHADDR 0xC100FFFF
+#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFF4
+
+#define XPAR_INTC_0_LLFIFO_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
+#define XPAR_INTC_0_LLTEMAC_0_VEC_ID XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
+#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
+#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
+#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR
+
+/******************************************************************/
+
+/* Definitions for driver LLFIFO */
+#define XPAR_XLLFIFO_NUM_INSTANCES 1
+
+/* Definitions for peripheral XPS_LL_FIFO_TEMAC */
+#define XPAR_XPS_LL_FIFO_TEMAC_DEVICE_ID 0
+#define XPAR_XPS_LL_FIFO_TEMAC_BASEADDR 0xC4000000
+#define XPAR_XPS_LL_FIFO_TEMAC_HIGHADDR 0xC400FFFF
+
+
+/******************************************************************/
+
+/* Canonical definitions for peripheral XPS_LL_FIFO_TEMAC */
+#define XPAR_LLFIFO_0_DEVICE_ID XPAR_XPS_LL_FIFO_TEMAC_DEVICE_ID
+#define XPAR_LLFIFO_0_BASEADDR 0xC4000000
+#define XPAR_LLFIFO_0_HIGHADDR 0xC400FFFF
+
+
+/******************************************************************/
+
+/* Definitions for driver SYSMON */
+#define XPAR_XSYSMON_NUM_INSTANCES 1
+
+/* Definitions for peripheral XPS_SYSMON_ADC_PPC440 */
+#define XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID 0
+#define XPAR_XPS_SYSMON_ADC_PPC440_BASEADDR 0xD0010000
+#define XPAR_XPS_SYSMON_ADC_PPC440_HIGHADDR 0xD001FFFF
+#define XPAR_XPS_SYSMON_ADC_PPC440_INCLUDE_INTR 1
+
+
+/******************************************************************/
+
+
+/* Canonical definitions for peripheral XPS_SYSMON_ADC_PPC440 */
+#define XPAR_SYSMON_0_DEVICE_ID XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID
+#define XPAR_SYSMON_0_BASEADDR 0xD0010000
+#define XPAR_SYSMON_0_HIGHADDR 0xD001FFFF
+#define XPAR_SYSMON_0_INCLUDE_INTR 1
+
+
+/******************************************************************/
+
+/* Definitions for driver TMRCTR */
+#define XPAR_XTMRCTR_NUM_INSTANCES 1
+
+/* Definitions for peripheral XPS_TIMER_PPC440 */
+#define XPAR_XPS_TIMER_PPC440_DEVICE_ID 0
+#define XPAR_XPS_TIMER_PPC440_BASEADDR 0xC2000000
+#define XPAR_XPS_TIMER_PPC440_HIGHADDR 0xC200FFFF
+
+
+/******************************************************************/
+
+
+/* Canonical definitions for peripheral XPS_TIMER_PPC440 */
+#define XPAR_TMRCTR_0_DEVICE_ID XPAR_XPS_TIMER_PPC440_DEVICE_ID
+#define XPAR_TMRCTR_0_BASEADDR 0xC2000000
+#define XPAR_TMRCTR_0_HIGHADDR 0xC200FFFF
+
+
+/******************************************************************/
+
+/* Definitions for bus frequencies */
+#define XPAR_CPU_PPC440_MPLB_FREQ_HZ 100000000
+/******************************************************************/
+
+/* Canonical definitions for bus frequencies */
+#define XPAR_PROC_BUS_0_FREQ_HZ 100000000
+/******************************************************************/
+
+#define XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ 400000000
+#define XPAR_PPC440_VIRTEX5_CORE_CLOCK_FREQ_HZ 400000000
+#define XPAR_CPU_PPC440_IDCR_BASEADDR 0x00000000
+/******************************************************************/
+#define XPAR_CPU_ID 0
+#define XPAR_PPC440_VIRTEX5_ID 0
+#define XPAR_PPC440_VIRTEX5_PIR 0b1111
+#define XPAR_PPC440_VIRTEX5_ENDIAN_RESET 0
+#define XPAR_PPC440_VIRTEX5_USER_RESET 0b0000
+#define XPAR_PPC440_VIRTEX5_INTERCONNECT_IMASK 0xffffffff
+#define XPAR_PPC440_VIRTEX5_ICU_RD_FETCH_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_ICU_RD_SPEC_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_ICU_RD_TOUCH_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_DCU_RD_LD_CACHE_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_DCU_RD_NONCACHE_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_DCU_RD_TOUCH_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_DCU_RD_URGENT_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_DCU_WR_FLUSH_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_DCU_WR_STORE_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_DCU_WR_URGENT_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_DMA0_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_DMA1_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_DMA2_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_DMA3_PLB_PRIO 0b00
+#define XPAR_PPC440_VIRTEX5_IDCR_BASEADDR 0x00000000
+#define XPAR_PPC440_VIRTEX5_IDCR_HIGHADDR 0x000000FF
+#define XPAR_PPC440_VIRTEX5_APU_CONTROL 0b00010000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_0 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_1 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_2 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_3 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_4 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_5 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_6 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_7 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_8 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_9 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_10 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_11 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_12 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_13 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_14 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_APU_UDI_15 0b000000000000000000000000
+#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_BASE 0x00000000
+#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_HIGH 0X01FFFFFF
+#define XPAR_PPC440_VIRTEX5_PPC440MC_ROW_CONFLICT_MASK 0x00000000
+#define XPAR_PPC440_VIRTEX5_PPC440MC_BANK_CONFLICT_MASK 0x00000000
+#define XPAR_PPC440_VIRTEX5_PPC440MC_CONTROL 0X8140008F
+#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_ICU 4
+#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUW 3
+#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUR 2
+#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB1 0
+#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB0 1
+#define XPAR_PPC440_VIRTEX5_PPC440MC_ARB_MODE 0
+#define XPAR_PPC440_VIRTEX5_PPC440MC_MAX_BURST 8
+#define XPAR_PPC440_VIRTEX5_MPLB_AWIDTH 32
+#define XPAR_PPC440_VIRTEX5_MPLB_DWIDTH 128
+#define XPAR_PPC440_VIRTEX5_MPLB_NATIVE_DWIDTH 128
+#define XPAR_PPC440_VIRTEX5_MPLB_COUNTER 0x00000500
+#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_ICU 4
+#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUW 3
+#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUR 2
+#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB1 0
+#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB0 1
+#define XPAR_PPC440_VIRTEX5_MPLB_ARB_MODE 0
+#define XPAR_PPC440_VIRTEX5_MPLB_SYNC_TATTRIBUTE 0
+#define XPAR_PPC440_VIRTEX5_MPLB_MAX_BURST 8
+#define XPAR_PPC440_VIRTEX5_MPLB_ALLOW_LOCK_XFER 1
+#define XPAR_PPC440_VIRTEX5_MPLB_READ_PIPE_ENABLE 1
+#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_PIPE_ENABLE 1
+#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_POST_ENABLE 1
+#define XPAR_PPC440_VIRTEX5_MPLB_P2P 0
+#define XPAR_PPC440_VIRTEX5_MPLB_WDOG_ENABLE 1
+#define XPAR_PPC440_VIRTEX5_SPLB0_AWIDTH 32
+#define XPAR_PPC440_VIRTEX5_SPLB0_DWIDTH 128
+#define XPAR_PPC440_VIRTEX5_SPLB0_NATIVE_DWIDTH 128
+#define XPAR_PPC440_VIRTEX5_SPLB0_SUPPORT_BURSTS 1
+#define XPAR_PPC440_VIRTEX5_SPLB0_USE_MPLB_ADDR 0
+#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MPLB_ADDR_RNG 0
+#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_BASEADDR 0xFFFFFFFF
+#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_HIGHADDR 0x00000000
+#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_BASEADDR 0xFFFFFFFF
+#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_HIGHADDR 0x00000000
+#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_BASEADDR 0xFFFFFFFF
+#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_HIGHADDR 0x00000000
+#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_BASEADDR 0xFFFFFFFF
+#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_HIGHADDR 0x00000000
+#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_BASEADDR 0xFFFFFFFF
+#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_HIGHADDR 0x00000000
+#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MASTERS 1
+#define XPAR_PPC440_VIRTEX5_SPLB0_MID_WIDTH 1
+#define XPAR_PPC440_VIRTEX5_SPLB0_ALLOW_LOCK_XFER 1
+#define XPAR_PPC440_VIRTEX5_SPLB0_READ_PIPE_ENABLE 1
+#define XPAR_PPC440_VIRTEX5_SPLB0_PROPAGATE_MIRQ 0
+#define XPAR_PPC440_VIRTEX5_SPLB0_P2P -1
+#define XPAR_PPC440_VIRTEX5_SPLB1_AWIDTH 32
+#define XPAR_PPC440_VIRTEX5_SPLB1_DWIDTH 128
+#define XPAR_PPC440_VIRTEX5_SPLB1_NATIVE_DWIDTH 128
+#define XPAR_PPC440_VIRTEX5_SPLB1_SUPPORT_BURSTS 1
+#define XPAR_PPC440_VIRTEX5_SPLB1_USE_MPLB_ADDR 0
+#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MPLB_ADDR_RNG 0
+#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_BASEADDR 0xFFFFFFFF
+#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_HIGHADDR 0x00000000
+#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_BASEADDR 0xFFFFFFFF
+#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_HIGHADDR 0x00000000
+#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_BASEADDR 0xFFFFFFFF
+#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_HIGHADDR 0x00000000
+#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_BASEADDR 0xFFFFFFFF
+#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_HIGHADDR 0x00000000
+#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_BASEADDR 0xFFFFFFFF
+#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_HIGHADDR 0x00000000
+#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MASTERS 1
+#define XPAR_PPC440_VIRTEX5_SPLB1_MID_WIDTH 1
+#define XPAR_PPC440_VIRTEX5_SPLB1_ALLOW_LOCK_XFER 1
+#define XPAR_PPC440_VIRTEX5_SPLB1_READ_PIPE_ENABLE 1
+#define XPAR_PPC440_VIRTEX5_SPLB1_PROPAGATE_MIRQ 0
+#define XPAR_PPC440_VIRTEX5_SPLB1_P2P -1
+#define XPAR_PPC440_VIRTEX5_NUM_DMA 0
+#define XPAR_PPC440_VIRTEX5_DMA0_TXCHANNELCTRL 0x01010000
+#define XPAR_PPC440_VIRTEX5_DMA0_RXCHANNELCTRL 0x01010000
+#define XPAR_PPC440_VIRTEX5_DMA0_CONTROL 0b00000000
+#define XPAR_PPC440_VIRTEX5_DMA0_TXIRQTIMER 0b1111111111
+#define XPAR_PPC440_VIRTEX5_DMA0_RXIRQTIMER 0b1111111111
+#define XPAR_PPC440_VIRTEX5_DMA1_TXCHANNELCTRL 0x01010000
+#define XPAR_PPC440_VIRTEX5_DMA1_RXCHANNELCTRL 0x01010000
+#define XPAR_PPC440_VIRTEX5_DMA1_CONTROL 0b00000000
+#define XPAR_PPC440_VIRTEX5_DMA1_TXIRQTIMER 0b1111111111
+#define XPAR_PPC440_VIRTEX5_DMA1_RXIRQTIMER 0b1111111111
+#define XPAR_PPC440_VIRTEX5_DMA2_TXCHANNELCTRL 0x01010000
+#define XPAR_PPC440_VIRTEX5_DMA2_RXCHANNELCTRL 0x01010000
+#define XPAR_PPC440_VIRTEX5_DMA2_CONTROL 0b00000000
+#define XPAR_PPC440_VIRTEX5_DMA2_TXIRQTIMER 0b1111111111
+#define XPAR_PPC440_VIRTEX5_DMA2_RXIRQTIMER 0b1111111111
+#define XPAR_PPC440_VIRTEX5_DMA3_TXCHANNELCTRL 0x01010000
+#define XPAR_PPC440_VIRTEX5_DMA3_RXCHANNELCTRL 0x01010000
+#define XPAR_PPC440_VIRTEX5_DMA3_CONTROL 0b00000000
+#define XPAR_PPC440_VIRTEX5_DMA3_TXIRQTIMER 0b1111111111
+#define XPAR_PPC440_VIRTEX5_DMA3_RXIRQTIMER 0b1111111111
+#define XPAR_PPC440_VIRTEX5_DCR_AUTOLOCK_ENABLE 1
+#define XPAR_PPC440_VIRTEX5_PPCDM_ASYNCMODE 0
+#define XPAR_PPC440_VIRTEX5_PPCDS_ASYNCMODE 0
+#define XPAR_PPC440_VIRTEX5_GENERATE_PLB_TIMESPECS 1
+#define XPAR_PPC440_VIRTEX5_HW_VER "1.01.a"
+
+/******************************************************************/
+

slsDetectorServers/gotthardDetectorServer/.target-makefrag

@@ -0,0 +1 @@
+AXIS_BUILDTYPE ?= cris-axis-linux-gnu

slsDetectorServers/gotthardDetectorServer/AD9252.h

@@ -0,0 +1 @@
+../slsDetectorServer/AD9252.h

slsDetectorServers/gotthardDetectorServer/AD9257.h

@@ -0,0 +1 @@
+../slsDetectorServer/AD9257.h

slsDetectorServers/gotthardDetectorServer/LTC2620.h

@@ -0,0 +1 @@
+../slsDetectorServer/LTC2620.h

slsDetectorServers/gotthardDetectorServer/Makefile

@@ -0,0 +1,37 @@
+CROSS  		= 	bfin-uclinux-
+CC    		= 	$(CROSS)gcc
+CFLAGS 		+=	-Wall  -DGOTTHARDD  -DSTOP_SERVER  # -DVERBOSE 
+LDLIBS		+= 	-lm  -lstdc++ 
+
+PROGS		= 	gotthardDetectorServer 
+DESTDIR		?= 	bin
+INSTMODE	= 	0777
+
+SRCS 		= 	communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c  slsDetectorFunctionList.c 
+OBJS 		= 	$(SRCS:%.c=%.o)
+
+
+all: clean versioning $(PROGS) 
+
+boot: $(OBJS)
+
+version_name=APIGOTTHARD
+version_path=slsDetectorServers/gotthardDetectorServer
+versioning: 
+	cd ../../ && echo $(PWD) && echo `tput setaf 6; ./updateAPIVersion.sh $(version_name) $(version_path);  tput sgr0;`
+
+	
+$(PROGS): $(OBJS) 
+#	echo $(OBJS)
+	mkdir -p $(DESTDIR) 
+	$(CC) -o $@ $^ $(CFLAGS)   $(LDLIBS)
+	mv $(PROGS) $(DESTDIR)
+	rm *.gdb
+
+clean:
+	rm -rf $(DESTDIR)/$(PROGS) *.o *.gdb
+
+
+
+
+

slsDetectorServers/gotthardDetectorServer/Makefile.virtual

@@ -0,0 +1,27 @@
+CC          =   gcc
+CFLAGS      +=  -Wall -DGOTTHARDD -DVIRTUAL -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
+LDLIBS      +=  -lm  -lstdc++  -pthread
+
+PROGS       =   gotthardDetectorServer_virtual 
+DESTDIR     ?=  bin
+INSTMODE    =   0777
+
+SRC_CLNT    =   communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c  slsDetectorFunctionList.c 
+OBJS        =   $(SRC_CLNT:.c=.o) 
+ 
+all: clean versioning $(PROGS)
+
+boot: $(OBJS) 
+
+versioning: 
+    @echo `tput setaf 6;    ./updateGitVersion.sh; tput sgr0;`
+    
+$(PROGS): $(OBJS)
+#   echo $(OBJS) 
+    mkdir -p $(DESTDIR) 
+    $(CC) -o $@ $^ $(CFLAGS) $(LDLIBS) 
+    mv $(PROGS) $(DESTDIR)
+
+clean:
+    rm -rf $(DESTDIR)/$(PROGS)  *.o
+   

slsDetectorServers/gotthardDetectorServer/RegisterDefs.h

@@ -0,0 +1,369 @@
+#pragma once
+
+/* Definitions for FPGA*/
+#define MEM_MAP_SHIFT                   (11)
+
+/** Gain register */
+#define GAIN_REG                        (0x10 << MEM_MAP_SHIFT)
+
+#define GAIN_CONFGAIN_OFST              (0)
+#define GAIN_CONFGAIN_MSK               (0x000000FF << GAIN_CONFGAIN_OFST)
+#define GAIN_CONFGAIN_HGH_GAIN_VAL      ((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_DYNMC_GAIN_VAL    ((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_LW_GAIN_VAL       ((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_MDM_GAIN_VAL      ((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL  ((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
+
+/** Flow Control register */
+//#define FLOW_CONTROL_REG                (0x11 << MEM_MAP_SHIFT)
+
+/** Flow Status register */
+//#define FLOW_STATUS_REG                 (0x12 << MEM_MAP_SHIFT)
+
+/** Frame register */
+//#define FRAME_REG                       (0x13 << MEM_MAP_SHIFT)
+
+/** Multi Purpose register */
+#define MULTI_PURPOSE_REG               (0x14 << MEM_MAP_SHIFT)
+
+#define PHS_STP_OFST                    (0)
+#define PHS_STP_MSK                     (0x00000001 << PHS_STP_OFST)
+#define RST_CNTR_OFST                   (2)
+#define RST_CNTR_MSK                    (0x00000001 << RST_CNTR_OFST)
+#define SW1_OFST                        (5)
+#define SW1_MSK                         (0x00000001 << SW1_OFST)
+#define WRT_BCK_OFST                    (6)
+#define WRT_BCK_MSK                     (0x00000001 << WRT_BCK_OFST)
+#define RST_OFST                        (7)
+#define RST_MSK                         (0x00000001 << RST_OFST)
+#define PLL_CLK_SL_OFST                 (8)
+#define PLL_CLK_SL_MSK                  (0x00000007 << PLL_CLK_SL_OFST)
+#define PLL_CLK_SL_MSTR_VAL             ((0x1 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
+#define PLL_CLK_SL_MSTR_ADC_VAL         ((0x2 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
+#define PLL_CLK_SL_SLV_VAL              ((0x3 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
+#define PLL_CLK_SL_SLV_ADC_VAL          ((0x4 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
+#define ENT_RSTN_OFST                   (11)
+#define ENT_RSTN_MSK                    (0x00000001 << ENT_RSTN_OFST)
+#define INT_RSTN_OFST                   (12)
+#define INT_RSTN_MSK                    (0x00000001 << INT_RSTN_OFST)
+#define DGTL_TST_OFST                   (14)
+#define DGTL_TST_MSK                    (0x00000001 << DGTL_TST_OFST)
+#define CHNG_AT_PWR_ON_OFST             (15)                                    // Not used in SW
+#define CHNG_AT_PWR_ON_MSK              (0x00000001 << CHNG_AT_PWR_ON_OFST) // Not used in SW
+#define RST_TO_SW1_DLY_OFST             (16)
+#define RST_TO_SW1_DLY_MSK              (0x0000000F << RST_TO_SW1_DLY_OFST)
+#define STRT_ACQ_DLY_OFST               (20)
+#define STRT_ACQ_DLY_MSK                (0x0000000F << STRT_ACQ_DLY_OFST)
+
+/** DAQ register */
+#define DAQ_REG                         (0x15 << MEM_MAP_SHIFT)
+
+#define DAQ_TKN_TMNG_OFST               (0)
+#define DAQ_TKN_TMNG_MSK                (0x0000FFFF << DAQ_TKN_TMNG_OFST)
+#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL     ((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
+#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL     ((0x1f10 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
+#define DAQ_PCKT_LNGTH_OFST             (16)
+#define DAQ_PCKT_LNGTH_MSK              (0x0000FFFF << DAQ_PCKT_LNGTH_OFST)
+#define DAQ_PCKT_LNGTH_NO_ROI_VAL       ((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
+#define DAQ_PCKT_LNGTH_ROI_VAL          ((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
+
+/** Time From Start register */
+//#define TIME_FROM_START_REG             (0x16 << MEM_MAP_SHIFT)
+
+/** DAC Control register */
+#define SPI_REG                         (0x17 << MEM_MAP_SHIFT)
+
+#define SPI_DAC_SRL_CS_OTPT_OFST        (0)
+#define SPI_DAC_SRL_CS_OTPT_MSK         (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
+#define SPI_DAC_SRL_CLK_OTPT_OFST       (1)
+#define SPI_DAC_SRL_CLK_OTPT_MSK        (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
+#define SPI_DAC_SRL_DGTL_OTPT_OFST      (2)
+#define SPI_DAC_SRL_DGTL_OTPT_MSK       (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
+
+/** ADC SPI register */
+#define ADC_SPI_REG                     (0x18 << MEM_MAP_SHIFT)
+
+#define ADC_SPI_SRL_CLK_OTPT_OFST       (0)
+#define ADC_SPI_SRL_CLK_OTPT_MSK        (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
+#define ADC_SPI_SRL_DT_OTPT_OFST        (1)
+#define ADC_SPI_SRL_DT_OTPT_MSK         (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
+#define ADC_SPI_SRL_CS_OTPT_OFST        (2)
+#define ADC_SPI_SRL_CS_OTPT_MSK         (0x0000001F << ADC_SPI_SRL_CS_OTPT_OFST)
+
+/** ADC Sync register */
+#define ADC_SYNC_REG                    (0x19 << MEM_MAP_SHIFT)
+
+#define ADC_SYNC_ENET_STRT_DLY_OFST     (0)
+#define ADC_SYNC_ENET_STRT_DLY_MSK      (0x0000000F << ADC_SYNC_ENET_STRT_DLY_OFST)
+#define ADC_SYNC_ENET_STRT_DLY_VAL      ((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
+#define ADC_SYNC_TKN1_HGH_DLY_OFST      (4)
+#define ADC_SYNC_TKN1_HGH_DLY_MSK       (0x0000000F << ADC_SYNC_TKN1_HGH_DLY_OFST)
+#define ADC_SYNC_TKN1_HGH_DLY_VAL       ((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
+#define ADC_SYNC_TKN2_HGH_DLY_OFST      (8)
+#define ADC_SYNC_TKN2_HGH_DLY_MSK       (0x0000000F << ADC_SYNC_TKN2_HGH_DLY_OFST)
+#define ADC_SYNC_TKN2_HGH_DLY_VAL       ((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
+#define ADC_SYNC_TKN1_LOW_DLY_OFST      (12)
+#define ADC_SYNC_TKN1_LOW_DLY_MSK       (0x0000000F << ADC_SYNC_TKN1_LOW_DLY_OFST)
+#define ADC_SYNC_TKN1_LOW_DLY_VAL       ((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
+#define ADC_SYNC_TKN2_LOW_DLY_OFST      (16)
+#define ADC_SYNC_TKN2_LOW_DLY_MSK       (0x0000000F << ADC_SYNC_TKN2_LOW_DLY_OFST)
+#define ADC_SYNC_TKN2_LOW_DLY_VAL       ((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
+//0x32214
+#define ADC_SYNC_TKN_VAL                (ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL |  ADC_SYNC_TKN2_LOW_DLY_VAL)
+#define ADC_SYNC_CLEAN_FIFOS_OFST       (20)
+#define ADC_SYNC_CLEAN_FIFOS_MSK        (0x00000001 << ADC_SYNC_CLEAN_FIFOS_OFST)
+#define ADC_SYNC_ENET_DELAY_OFST        (24)
+#define ADC_SYNC_ENET_DELAY_MSK         (0x000000FF << ADC_SYNC_ENET_DELAY_OFST)
+#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL  ((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
+#define ADC_SYNC_ENET_DELAY_ROI_VAL     ((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
+
+/** Time From Start register */
+//#define MU_TIME_REG                     (0x1a << MEM_MAP_SHIFT)
+
+/** Temperatre SPI In register */
+#define TEMP_SPI_IN_REG                 (0x1b << MEM_MAP_SHIFT)
+
+#define TEMP_SPI_IN_T1_CLK_OFST         (0)
+#define TEMP_SPI_IN_T1_CLK_MSK          (0x00000001 << TEMP_SPI_IN_T1_CLK_OFST)
+#define TEMP_SPI_IN_T1_CS_OFST          (1)
+#define TEMP_SPI_IN_T1_CS_MSK           (0x00000001 << TEMP_SPI_IN_T1_CS_OFST)
+#define TEMP_SPI_IN_T2_CLK_OFST         (2)
+#define TEMP_SPI_IN_T2_CLK_MSK          (0x00000001 << TEMP_SPI_IN_T2_CLK_OFST)
+#define TEMP_SPI_IN_T2_CS_OFST          (3)
+#define TEMP_SPI_IN_T2_CS_MSK           (0x00000001 << TEMP_SPI_IN_T2_CS_OFST)
+#define TEMP_SPI_IN_IDLE_MSK            (TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CS_MSK | TEMP_SPI_IN_T1_CLK_MSK | TEMP_SPI_IN_T2_CLK_MSK)
+
+/** Temperatre SPI Out register */
+#define TEMP_SPI_OUT_REG                (0x1c << MEM_MAP_SHIFT)
+
+#define TEMP_SPI_OUT_T1_DT_OFST         (0)
+#define TEMP_SPI_OUT_T1_DT_MSK          (0x00000001 << TEMP_SPI_OUT_T1_DT_OFST)
+#define TEMP_SPI_OUT_T2_DT_OFST         (1)
+#define TEMP_SPI_OUT_T2_DT_MSK          (0x00000001 << TEMP_SPI_OUT_T2_DT_OFST)
+
+/** TSE Configure register */
+#define TSE_CONF_REG                    (0x1d << MEM_MAP_SHIFT)
+
+/** SPI Configure register */
+#define ENET_CONF_REG                   (0x1e << MEM_MAP_SHIFT)
+
+/** Write TSE Shadow register */
+//#define WRITE_TSE_SHADOW_REG            (0x1f << MEM_MAP_SHIFT)
+
+/** High Voltage register */
+#define HV_REG                          (0x20 << MEM_MAP_SHIFT)
+
+#define HV_ENBL_OFST                    (0)
+#define HV_ENBL_MSK                     (0x00000001 << HV_ENBL_OFST)
+#define HV_SEL_OFST                     (1)
+#define HV_SEL_MSK                      (0x00000007 << HV_SEL_OFST)
+#define HV_SEL_90_VAL                   ((0x0 << HV_SEL_OFST) & HV_SEL_MSK)
+#define HV_SEL_110_VAL                  ((0x1 << HV_SEL_OFST) & HV_SEL_MSK)
+#define HV_SEL_120_VAL                  ((0x2 << HV_SEL_OFST) & HV_SEL_MSK)
+#define HV_SEL_150_VAL                  ((0x3 << HV_SEL_OFST) & HV_SEL_MSK)
+#define HV_SEL_180_VAL                  ((0x4 << HV_SEL_OFST) & HV_SEL_MSK)
+#define HV_SEL_200_VAL                  ((0x5 << HV_SEL_OFST) & HV_SEL_MSK)
+
+/** Dummy register */
+#define DUMMY_REG                       (0x21 << MEM_MAP_SHIFT)
+
+/** Firmware Version register */
+#define FPGA_VERSION_REG                (0x22 << MEM_MAP_SHIFT)
+
+#define FPGA_VERSION_OFST               (0)
+#define FPGA_VERSION_MSK                (0x00FFFFFF << FPGA_VERSION_OFST)       // to get in format yymmdd
+
+/* Fix Pattern register */
+#define FIX_PATT_REG                    (0x23 << MEM_MAP_SHIFT)
+
+#define FIX_PATT_VAL                    (0xACDC1980)
+
+/** 16 bit Control register */
+#define CONTROL_REG                     (0x24 << MEM_MAP_SHIFT)
+
+#define CONTROL_STRT_ACQ_OFST           (0)
+#define CONTROL_STRT_ACQ_MSK            (0x00000001 << CONTROL_STRT_ACQ_OFST)
+#define CONTROL_STP_ACQ_OFST            (1)
+#define CONTROL_STP_ACQ_MSK             (0x00000001 << CONTROL_STP_ACQ_OFST)
+#define CONTROL_STRT_FF_TST_OFST        (2)                                          // Not used in FW & SW
+#define CONTROL_STRT_FF_TST_MSK         (0x00000001 << CONTROL_STRT_FF_TST_OFST)
+#define CONTROL_STP_FF_TST_OFST         (3)                                          // Not used in FW & SW
+#define CONTROL_STP_FF_TST_MSK          (0x00000001 << CONTROL_STP_FF_TST_OFST)
+#define CONTROL_STRT_RDT_OFST           (4)
+#define CONTROL_STRT_RDT_MSK            (0x00000001 << CONTROL_STRT_RDT_OFST)
+#define CONTROL_STP_RDT_OFST            (5)
+#define CONTROL_STP_RDT_MSK             (0x00000001 << CONTROL_STP_RDT_OFST)
+#define CONTROL_STRT_EXPSR_OFST         (6)
+#define CONTROL_STRT_EXPSR_MSK          (0x00000001 << CONTROL_STRT_EXPSR_OFST)
+#define CONTROL_STP_EXPSR_OFST          (7)
+#define CONTROL_STP_EXPSR_MSK           (0x00000001 << CONTROL_STP_EXPSR_OFST)
+#define CONTROL_STRT_TRN_OFST           (8)
+#define CONTROL_STRT_TRN_MSK            (0x00000001 << CONTROL_STRT_TRN_OFST)
+#define CONTROL_STP_TRN_OFST            (9)
+#define CONTROL_STP_TRN_MSK             (0x00000001 << CONTROL_STP_TRN_OFST)
+#define CONTROL_SYNC_RST_OFST           (10)
+#define CONTROL_SYNC_RST_MSK            (0x00000001 << CONTROL_SYNC_RST_OFST)
+
+/** Status register */
+#define STATUS_REG                      (0x25 << MEM_MAP_SHIFT)
+
+#define STATUS_RN_BSY_OFST              (0)
+#define STATUS_RN_BSY_MSK               (0x00000001 << STATUS_RN_BSY_OFST)
+#define STATUS_RDT_BSY_OFST             (1)
+#define STATUS_RDT_BSY_MSK              (0x00000001 << STATUS_RDT_BSY_OFST)
+#define STATUS_WTNG_FR_TRGGR_OFST       (3)
+#define STATUS_WTNG_FR_TRGGR_MSK        (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
+#define STATUS_DLY_BFR_OFST             (4)
+#define STATUS_DLY_BFR_MSK              (0x00000001 << STATUS_DLY_BFR_OFST)
+#define STATUS_DLY_AFTR_OFST            (5)
+#define STATUS_DLY_AFTR_MSK             (0x00000001 << STATUS_DLY_AFTR_OFST)
+#define STATUS_EXPSNG_OFST              (6)
+#define STATUS_EXPSNG_MSK               (0x00000001 << STATUS_EXPSNG_OFST)
+#define STATUS_CNT_ENBL_OFST            (7)
+#define STATUS_CNT_ENBL_MSK             (0x00000001 << STATUS_CNT_ENBL_OFST)
+#define STATUS_RD_STT_OFST              (8)
+#define STATUS_RD_STT_MSK               (0x00000007 << STATUS_RD_STT_OFST)
+#define STATUS_RN_STT_OFST              (12)
+#define STATUS_RN_STT_MSK               (0x00000007 << STATUS_RN_STT_OFST)
+#define STATUS_SM_FF_FLL_OFST           (15)
+#define STATUS_SM_FF_FLL_MSK            (0x00000001 << STATUS_SM_FF_FLL_OFST)
+#define STATUS_ALL_FF_EMPTY_OFST        (11)
+#define STATUS_ALL_FF_EMPTY_MSK         (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
+#define STATUS_RN_MSHN_BSY_OFST         (17)
+#define STATUS_RN_MSHN_BSY_MSK          (0x00000001 << STATUS_RN_MSHN_BSY_OFST)
+#define STATUS_RD_MSHN_BSY_OFST         (18)
+#define STATUS_RD_MSHN_BSY_MSK          (0x00000001 << STATUS_RD_MSHN_BSY_OFST)
+#define STATUS_RN_FNSHD_OFST            (20)
+#define STATUS_RN_FNSHD_MSK             (0x00000001 << STATUS_RN_FNSHD_OFST)
+#define STATUS_IDLE_MSK                 (0x0000FFFF << 0)
+
+/** Config register */
+#define CONFIG_REG                      (0x26 << MEM_MAP_SHIFT)
+
+#define CONFIG_SLAVE_OFST               (0)                                     // Not used in FW & SW
+#define CONFIG_SLAVE_MSK                (0x00000001 << CONFIG_SLAVE_OFST)
+#define CONFIG_MASTER_OFST              (1)                                     // Not used in FW & SW
+#define CONFIG_MASTER_MSK               (0x00000001 << CONFIG_MASTER_OFST)
+#define CONFIG_TM_GT_ENBL_OFST          (2)                                     // Not used in FW & SW
+#define CONFIG_TM_GT_ENBL_MSK           (0x00000001 << CONFIG_TM_GT_ENBL_OFST)
+#define CONFIG_CPU_RDT_OFST             (12)
+#define CONFIG_CPU_RDT_MSK              (0x00000001 << CONFIG_CPU_RDT_OFST)
+#define CONFIG_CNTNS_RDT_OFST           (23)                                    // Not used in FW & SW
+#define CONFIG_CNTNS_RDT_MSK            (0x00000001 << CONFIG_CNTNS_RDT_OFST)
+#define CONFIG_ACCMLT_CNTS_OFST         (24)                                    // Not used in FW & SW
+#define CONFIG_ACCMLT_CNTS_MSK          (0x00000001 << CONFIG_ACCMLT_CNTS_OFST)
+
+/** External Signal register */
+#define EXT_SIGNAL_REG                  (0x27 << MEM_MAP_SHIFT)
+
+#define EXT_SIGNAL_OFST                 (0)
+#define EXT_SIGNAL_MSK                  (0x00000007 << EXT_SIGNAL_OFST)
+#define EXT_SIGNAL_OFF_VAL              ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
+#define EXT_SIGNAL_TRGGR_IN_RSNG_VAL    ((0x3 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
+#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL   ((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
+
+/** Look at me register */
+//#define LOOK_AT_ME_REG                  (0x28 << MEM_MAP_SHIFT)
+
+/** FPGA SVN register */
+//#define FPGA_SVN_REG                    (0x29 << MEM_MAP_SHIFT)
+
+/** Chip of Interest register */
+#define CHIP_OF_INTRST_REG              (0x2a << MEM_MAP_SHIFT)
+
+#define CHIP_OF_INTRST_ADC_SEL_OFST     (0)
+#define CHIP_OF_INTRST_ADC_SEL_MSK      (0x0000001F << CHIP_OF_INTRST_ADC_SEL_OFST)
+#define CHIP_OF_INTRST_NUM_CHNNLS_OFST  (16)
+#define CHIP_OF_INTRST_NUM_CHNNLS_MSK   (0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
+
+/** Out MUX register */
+//#define OUT_MUX_REG                     (0x2b << MEM_MAP_SHIFT)
+
+/** Board Version register */
+#define BOARD_REVISION_REG              (0x2c << MEM_MAP_SHIFT)
+
+#define BOARD_REVISION_OFST             (0)
+#define BOARD_REVISION_MSK              (0x0000FFFF << BOARD_REVISION_OFST)
+#define DETECTOR_TYPE_OFST              (16)
+#define DETECTOR_TYPE_MSK               (0x0000000F << DETECTOR_TYPE_OFST)
+//#define DETECTOR_TYPE_GOTTHARD_VAL          (??)
+#define DETECTOR_TYPE_MOENCH_VAL        (2)
+
+/** Memory Test register */
+//#define MEMORY_TEST_REG                 (0x2d << MEM_MAP_SHIFT)
+
+/** Hit Threshold register */
+//#define HIT_THRESHOLD_REG               (0x2e << MEM_MAP_SHIFT)
+
+/** Hit Count register */
+//#define HIT_COUNT_REG                   (0x2f << MEM_MAP_SHIFT)
+
+/* 16 bit Fifo Data register */
+#define FIFO_DATA_REG                   (0x50 << MEM_MAP_SHIFT)                 // Not used in FW and SW (16bit)
+
+/** Dacs Set 1 register */
+//#define DACS_SET_1_REG                  (0x65 << MEM_MAP_SHIFT)
+
+/** Dacs Set 2 register */
+//#define DACS_SET_2_REG                  (0x66 << MEM_MAP_SHIFT)
+
+/** Dacs Set 3 register */
+//#define DACS_SET_3_REG                  (0x67 << MEM_MAP_SHIFT)
+
+/* Set Delay 64 bit register */
+#define SET_DELAY_LSB_REG               (0x68 << MEM_MAP_SHIFT)
+#define SET_DELAY_MSB_REG               (0x69 << MEM_MAP_SHIFT)
+
+/* Get Delay 64 bit register */
+#define GET_DELAY_LSB_REG               (0x6a << MEM_MAP_SHIFT)
+#define GET_DELAY_MSB_REG               (0x6b << MEM_MAP_SHIFT)
+
+/* Set Cycles 64 bit register */
+#define SET_TRAINS_LSB_REG              (0x6c << MEM_MAP_SHIFT)
+#define SET_TRAINS_MSB_REG              (0x6d << MEM_MAP_SHIFT)
+
+/* Get Cycles 64 bit register */
+#define GET_TRAINS_LSB_REG              (0x6e << MEM_MAP_SHIFT)
+#define GET_TRAINS_MSB_REG              (0x6f << MEM_MAP_SHIFT)
+
+/* Set Frames 64 bit register */
+#define SET_FRAMES_LSB_REG              (0x70 << MEM_MAP_SHIFT)
+#define SET_FRAMES_MSB_REG              (0x71 << MEM_MAP_SHIFT)
+
+/* Get Frames 64 bit register */
+#define GET_FRAMES_LSB_REG              (0x72 << MEM_MAP_SHIFT)
+#define GET_FRAMES_MSB_REG              (0x73 << MEM_MAP_SHIFT)
+
+/* Set Period 64 bit register */
+#define SET_PERIOD_LSB_REG              (0x74 << MEM_MAP_SHIFT)
+#define SET_PERIOD_MSB_REG              (0x75 << MEM_MAP_SHIFT)
+
+/* Get Period 64 bit register */
+#define GET_PERIOD_LSB_REG              (0x76 << MEM_MAP_SHIFT)
+#define GET_PERIOD_MSB_REG              (0x77 << MEM_MAP_SHIFT)
+
+/* Set Exptime 64 bit register */
+#define SET_EXPTIME_LSB_REG             (0x78 << MEM_MAP_SHIFT)
+#define SET_EXPTIME_MSB_REG             (0x79 << MEM_MAP_SHIFT)
+
+/* Get Exptime 64 bit register */
+#define GET_EXPTIME_LSB_REG             (0x7a << MEM_MAP_SHIFT)
+#define GET_EXPTIME_MSB_REG             (0x7b << MEM_MAP_SHIFT)
+
+/* Set Gates 64 bit register */
+//#define SET_GATES_LSB_REG               (0x7c << MEM_MAP_SHIFT)
+//#define SET_GATES_MSB_REG               (0x7d << MEM_MAP_SHIFT)
+
+/* Set Gates 64 bit register */
+//#define GET_GATES_LSB_REG               (0x7e << MEM_MAP_SHIFT)
+//#define GET_GATES_MSB_REG               (0x7f << MEM_MAP_SHIFT)
+
+/* Dark Image starting address */
+#define DARK_IMAGE_REG                  (0x81 << MEM_MAP_SHIFT)
+
+/* Gain Image starting address */
+#define GAIN_IMAGE_REG                  (0x82 << MEM_MAP_SHIFT)
+
+/* Counter Block Memory starting address */
+#define COUNTER_MEMORY_REG              (0x85 << MEM_MAP_SHIFT)
+

slsDetectorServers/gotthardDetectorServer/ansi.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/ansi.h

slsDetectorServers/gotthardDetectorServer/blackfin.h

@@ -0,0 +1 @@
+../slsDetectorServer/blackfin.h

slsDetectorServers/gotthardDetectorServer/common.h

@@ -0,0 +1 @@
+../slsDetectorServer/common.h

slsDetectorServers/gotthardDetectorServer/commonServerFunctions.h

@@ -0,0 +1 @@
+../slsDetectorServer/commonServerFunctions.h

slsDetectorServers/gotthardDetectorServer/communication_funcs.c

@@ -0,0 +1 @@
+../slsDetectorServer/communication_funcs.c

slsDetectorServers/gotthardDetectorServer/communication_funcs.h

@@ -0,0 +1 @@
+../slsDetectorServer/communication_funcs.h

slsDetectorServers/gotthardDetectorServer/config.txt

@@ -0,0 +1,23 @@
+#masterflags (no_master, is_master, is_slave)
+masterflags no_master
+
+#master default delay 
+masterdefaultdelay 70
+
+#patternphase 
+patternphase 0
+
+#adcphase 
+adcphase 0
+
+#slave pattern phase
+slavepatternphase 0
+
+#slave adc phase 
+slaveadcphase 0
+
+#rst to sw1 delay
+rsttosw1delay 2
+
+#start acquisition delay
+startacqdelay 1

slsDetectorServers/gotthardDetectorServer/logger.h

@@ -0,0 +1 @@
+../slsDetectorServer/logger.h

slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.h

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorFunctionList.h

slsDetectorServers/gotthardDetectorServer/slsDetectorServer.c

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer.c

slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h

@@ -0,0 +1,123 @@
+#pragma once
+#include "sls_detector_defs.h"
+#include <stdlib.h>
+
+/* Enums */
+enum ADCINDEX				        {TEMP_FPGA, TEMP_ADC};
+enum DACINDEX				        {VREF_DS, VCASCN_PB, VCASCP_PB, VOUT_CM, VCASC_OUT, VIN_CM, VREF_COMP, IB_TESTC};
+#define DEFAULT_DAC_VALS   	        { 	                        \
+                                    660,    /* VREF_DS */       \
+                                    650,    /* VCASCN_PB */     \
+                                    1480,   /* VCASCP_PB */     \
+                                    1520,   /* VOUT_CM */       \
+                                    1320,   /* VCASC_OUT */     \
+                                    1350,   /* VIN_CM */        \
+                                    350,    /* VREF_COMP */     \
+                                    2001    /* IB_TESTC */      \
+                                    };
+
+/* for 25 um */
+#define CONFIG_FILE                 "config.txt"
+
+/* Hardware Definitions */
+#define NCHAN 						(128)
+#define NCHIP 						(10)
+#define NDAC 						(8)
+#define NCHIPS_PER_ADC              (2)
+#define DYNAMIC_RANGE				(16)
+#define NUM_BITS_PER_PIXEL			(DYNAMIC_RANGE / 8)
+#define DATA_BYTES					(NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
+#define CLK_FREQ					(32.007729)	/* MHz */
+
+/** Firmware Definitions */
+#define IP_PACKET_SIZE_NO_ROI       (NCHIP * (NCHAN / 2) * 2 + 14 + 20)     // 2 packets, so divide by 2
+#define IP_PACKET_SIZE_ROI          (NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20)
+
+#define UDP_PACKETSIZE_NO_ROI       (NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2)  // 2 packets, so divide by 2
+#define UDP_PACKETSIZE_ROI          (NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2)
+
+/** Default Parameters */
+#define DEFAULT_NUM_FRAMES			(1)
+#define DEFAULT_NUM_CYCLES			(1)
+#define DEFAULT_EXPTIME				(1 * 1000 * 1000)	        // 1 ms
+#define DEFAULT_PERIOD				(1 * 1000 * 1000 * 1000)	// 1 s
+#define DEFAULT_DELAY				(0)
+#define DEFAULT_SETTINGS            (DYNAMICGAIN)
+#define DEFAULT_TIMING_MODE         (AUTO_TIMING)
+#define DEFAULT_TRIGGER_MODE        (TRIGGER_IN_RISING_EDGE)
+#define DEFAULT_HIGH_VOLTAGE		(0)
+#define DEFAULT_PHASE_SHIFT         (120)
+#define DEFAULT_TX_UDP_PORT         (0xE185)
+
+#define DAC_MIN_MV                  (0)
+#define DAC_MAX_MV                  (2500)
+
+/** ENEt conf structs */
+typedef struct mac_header_struct{
+    u_int8_t    mac_dest_mac2;
+    u_int8_t    mac_dest_mac1;
+    u_int8_t    mac_dummy1;
+    u_int8_t    mac_dummy2;
+    u_int8_t    mac_dest_mac6;
+    u_int8_t    mac_dest_mac5;
+    u_int8_t    mac_dest_mac4;
+    u_int8_t    mac_dest_mac3;
+    u_int8_t    mac_src_mac4;
+    u_int8_t    mac_src_mac3;
+    u_int8_t    mac_src_mac2;
+    u_int8_t    mac_src_mac1;
+    u_int16_t   mac_ether_type;
+    u_int8_t    mac_src_mac6;
+    u_int8_t    mac_src_mac5;
+} mac_header;
+
+typedef struct ip_header_struct {
+    u_int16_t     ip_len;
+    u_int8_t      ip_tos;
+    u_int8_t      ip_ihl:4 ,ip_ver:4;
+    u_int16_t     ip_offset:13,ip_flag:3;
+    u_int16_t     ip_ident;
+    u_int16_t     ip_chksum;
+    u_int8_t      ip_protocol;
+    u_int8_t      ip_ttl;
+    u_int32_t     ip_sourceip;
+    u_int32_t     ip_destip;
+} ip_header;
+
+typedef struct udp_header_struct{
+    u_int16_t   udp_destport;
+    u_int16_t   udp_srcport;
+    u_int16_t   udp_chksum;
+    u_int16_t   udp_len;
+} udp_header;
+
+typedef struct mac_conf_struct{
+    mac_header  mac;
+    ip_header   ip;
+    udp_header  udp;
+    u_int32_t   npack;
+    u_int32_t   lpack;
+    u_int32_t   npad;
+    u_int32_t   cdone;
+} mac_conf;
+
+typedef struct tse_conf_struct{
+    u_int32_t   rev;                    //0x0
+    u_int32_t   scratch;
+    u_int32_t   command_config;
+    u_int32_t   mac_0;                  //0x3
+    u_int32_t   mac_1;
+    u_int32_t   frm_length;
+    u_int32_t   pause_quant;
+    u_int32_t   rx_section_empty;       //0x7
+    u_int32_t   rx_section_full;
+    u_int32_t   tx_section_empty;
+    u_int32_t   tx_section_full;
+    u_int32_t   rx_almost_empty;        //0xB
+    u_int32_t   rx_almost_full;
+    u_int32_t   tx_almost_empty;
+    u_int32_t   tx_almost_full;
+    u_int32_t   mdio_addr0;             //0xF
+    u_int32_t   mdio_addr1;
+}tse_conf;
+

slsDetectorServers/gotthardDetectorServer/slsDetectorServer_funcs.c

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer_funcs.c

slsDetectorServers/gotthardDetectorServer/slsDetectorServer_funcs.h

@@ -0,0 +1 @@
+../slsDetectorServer/slsDetectorServer_funcs.h

slsDetectorServers/gotthardDetectorServer/sls_detector_defs.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/sls_detector_defs.h

slsDetectorServers/gotthardDetectorServer/sls_detector_funcs.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/sls_detector_funcs.h

slsDetectorServers/gotthardDetectorServer/versionAPI.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/versionAPI.h

slsDetectorServers/jungfrauDetectorServer/AD9257.h

@@ -0,0 +1 @@
+../slsDetectorServer/AD9257.h

slsDetectorServers/jungfrauDetectorServer/ALTERA_PLL.h

@@ -0,0 +1 @@
+../slsDetectorServer/ALTERA_PLL.h

slsDetectorServers/jungfrauDetectorServer/LTC2620.h

@@ -0,0 +1 @@
+../slsDetectorServer/LTC2620.h

slsDetectorServers/jungfrauDetectorServer/MAX1932.h

@@ -0,0 +1 @@
+../slsDetectorServer/MAX1932.h

slsDetectorServers/jungfrauDetectorServer/Makefile

@@ -0,0 +1,34 @@
+CROSS  		= bfin-uclinux-
+CC    		= $(CROSS)gcc
+CFLAGS		+=  -Wall -DJUNGFRAUD  -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
+LDLIBS		+= 	-lm  -lstdc++ 
+
+PROGS		= 	jungfrauDetectorServer 
+DESTDIR		?= 	bin
+INSTMODE	= 	0777
+
+SRC_CLNT	=	communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c  slsDetectorFunctionList.c 
+OBJS 		= 	$(SRC_CLNT:.c=.o) 
+ 
+all: clean versioning $(PROGS)
+
+boot: $(OBJS) 
+
+version_name=APIJUNGFRAU
+version_path=slsDetectorServers/jungfrauDetectorServer
+versioning: 
+	cd ../../ && echo $(PWD) && echo `tput setaf 6; ./updateAPIVersion.sh $(version_name) $(version_path);  tput sgr0;`
+
+
+$(PROGS): $(OBJS)
+#	echo $(OBJS) 
+	mkdir -p $(DESTDIR) 
+	$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS) 
+	mv $(PROGS) $(DESTDIR)
+	rm *.gdb
+
+clean:
+	rm -rf $(DESTDIR)/$(PROGS)  *.o *.gdb
+	
+
+	

slsDetectorServers/jungfrauDetectorServer/Makefile.virtual

@@ -0,0 +1,27 @@
+CC    		= gcc
+CFLAGS		+=  -Wall -DJUNGFRAUD -DVIRTUAL -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE
+LDLIBS		+= 	-lm  -lstdc++  -pthread
+
+PROGS		= 	jungfrauDetectorServer_virtual 
+DESTDIR		?= 	bin
+INSTMODE	= 	0777
+
+SRC_CLNT	=	communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c  slsDetectorFunctionList.c 
+OBJS 		= 	$(SRC_CLNT:.c=.o) 
+ 
+all: clean versioning $(PROGS)
+
+boot: $(OBJS) 
+
+versioning: 
+	@echo `tput setaf 6;	./updateGitVersion.sh; tput sgr0;`
+	
+$(PROGS): $(OBJS)
+#	echo $(OBJS) 
+	mkdir -p $(DESTDIR) 
+	$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS) 
+	mv $(PROGS) $(DESTDIR)
+
+clean:
+	rm -rf $(DESTDIR)/$(PROGS)  *.o
+	

slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h

@@ -0,0 +1,446 @@
+#pragma once
+
+/* Definitions for FPGA*/
+#define MEM_MAP_SHIFT 1
+
+/* FPGA Version register */
+#define FPGA_VERSION_REG      			(0x00 << MEM_MAP_SHIFT)
+
+#define BOARD_REVISION_OFST				(0)
+#define BOARD_REVISION_MSK				(0x00FFFFFF << BOARD_REVISION_OFST)
+#define DETECTOR_TYPE_OFST   			(24)
+#define DETECTOR_TYPE_MSK   			(0x000000FF << DETECTOR_TYPE_OFST)
+
+
+
+/* Fix pattern register */
+#define FIX_PATT_REG          			(0x01 << MEM_MAP_SHIFT)
+
+#define FIX_PATT_VAL                    (0xACDC2014)
+
+/* Status register */
+#define STATUS_REG            			(0x02 << MEM_MAP_SHIFT)
+
+#define RUN_BUSY_OFST					(0)
+#define RUN_BUSY_MSK      				(0x00000001 << RUN_BUSY_OFST)
+#define WAITING_FOR_TRIGGER_OFST  		(3)
+#define WAITING_FOR_TRIGGER_MSK  		(0x00000001 << WAITING_FOR_TRIGGER_OFST)
+#define DELAYBEFORE_OFST  				(4)											//Not used in software
+#define DELAYBEFORE_MSK  				(0x00000001 << DELAYBEFORE_OFST)			//Not used in software
+#define DELAYAFTER_OFST  				(5)											//Not used in software
+#define DELAYAFTER_MSK  				(0x00000001 << DELAYAFTER_OFST)				//Not used in software
+#define STOPPED_OFST  					(15)
+#define STOPPED_MSK  					(0x00000001 << STOPPED_OFST)
+#define RUNMACHINE_BUSY_OFST  			(17)
+#define RUNMACHINE_BUSY_MSK  			(0x00000001 << RUNMACHINE_BUSY_OFST)
+
+
+/* Look at me register */
+#define LOOK_AT_ME_REG          		(0x03 << MEM_MAP_SHIFT)								//Not used in firmware or software
+
+/* System Status register */
+#define SYSTEM_STATUS_REG       		(0x04 << MEM_MAP_SHIFT)								//Not used in software
+
+#define DDR3_CAL_DONE_OFST				(0)											//Not used in software
+#define DDR3_CAL_DONE_MSK 				(0x00000001 << DDR3_CAL_DONE_OFST)			//Not used in software
+#define DDR3_CAL_FAIL_OFST				(1)											//Not used in software
+#define DDR3_CAL_FAIL_MSK 				(0x00000001 << DDR3_CAL_FAIL_OFST)			//Not used in software
+#define DDR3_INIT_DONE_OFST				(2)											//Not used in software
+#define DDR3_INIT_DONE_MSK 				(0x00000001 << DDR3_INIT_DONE_OFST)			//Not used in software
+#define RECONFIG_PLL_LCK_OFST			(3)											//Not used in software
+#define RECONFIG_PLL_LCK_MSK 			(0x00000001 << RECONFIG_PLL_LCK_OFST)		//Not used in software
+#define PLL_A_LCK_OFST					(4)											//Not used in software
+#define PLL_A_LCK_MSK 					(0x00000001 << PLL_A_LCK_OFST)				//Not used in software
+#define DD3_PLL_LCK_OFST				(5)											//Not used in software
+#define DD3_PLL_LCK_MSK 				(0x00000001 << DD3_PLL_LCK_OFST)			//Not used in software
+
+
+/* Module Control Board Serial Number Register */
+#define MOD_SERIAL_NUM_REG				(0x0A << MEM_MAP_SHIFT)								//Not used in software
+
+#define HARDWARE_SERIAL_NUM_OFST		(0)											//Not used in software
+#define HARDWARE_SERIAL_NUM_MSK			(0x000000FF << HARDWARE_SERIAL_NUM_OFST)	//Not used in software
+#define HARDWARE_VERSION_NUM_OFST		(16)										//Not used in software
+#define HARDWARE_VERSION_NUM_MSK		(0x0000003F << HARDWARE_VERSION_NUM_OFST)	//Not used in software
+
+
+/* API Version Register */
+#define API_VERSION_REG                 (0x0F << MEM_MAP_SHIFT)
+
+#define API_VERSION_OFST                (0)
+#define API_VERSION_MSK                 (0x00FFFFFF << API_VERSION_OFST)
+#define API_VERSION_DETECTOR_TYPE_OFST  (24)                                            //Not used in software
+#define API_VERSION_DETECTOR_TYPE_MSK   (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST)  //Not used in software
+
+/* Time from Start 64 bit register */
+#define TIME_FROM_START_LSB_REG   		(0x10 << MEM_MAP_SHIFT)
+#define TIME_FROM_START_MSB_REG   		(0x11 << MEM_MAP_SHIFT)
+
+/* Get Delay 64 bit register */
+#define GET_DELAY_LSB_REG     			(0x12 << MEM_MAP_SHIFT)						// different kind of delay
+#define GET_DELAY_MSB_REG     			(0x13 << MEM_MAP_SHIFT)						// different kind of delay
+
+/* Get Cycles 64 bit register */
+#define GET_CYCLES_LSB_REG    			(0x14 << MEM_MAP_SHIFT)
+#define GET_CYCLES_MSB_REG    			(0x15 << MEM_MAP_SHIFT)
+
+/* Get Frames 64 bit register */
+#define GET_FRAMES_LSB_REG   			(0x16 << MEM_MAP_SHIFT)
+#define GET_FRAMES_MSB_REG    			(0x17 << MEM_MAP_SHIFT)
+
+/* Get Period 64 bit register tT = T x 50 ns */
+#define GET_PERIOD_LSB_REG    			(0x18 << MEM_MAP_SHIFT)
+#define GET_PERIOD_MSB_REG    			(0x19 << MEM_MAP_SHIFT)
+
+/** Get Temperature Carlos, incorrectl as get gates */
+#define GET_TEMPERATURE_TMP112_REG		(0x1c << MEM_MAP_SHIFT)							// (after multiplying by 625) in 10ths of millidegrees of TMP112
+
+#define TEMPERATURE_VALUE_BIT           (0)
+#define TEMPERATURE_VALUE_MSK           (0x000007FF << TEMPERATURE_VALUE_BIT)
+#define TEMPERATURE_POLARITY_BIT		(11)
+#define TEMPERATURE_POLARITY_MSK		(0x00000001 << TEMPERATURE_POLARITY_BIT)
+
+
+
+/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
+#define FRAMES_FROM_START_PG_LSB_REG	(0x24 << MEM_MAP_SHIFT)
+#define FRAMES_FROM_START_PG_MSB_REG 	(0x25 << MEM_MAP_SHIFT)
+
+/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
+#define START_FRAME_TIME_LSB_REG		(0x26 << MEM_MAP_SHIFT)
+#define START_FRAME_TIME_MSB_REG 		(0x27 << MEM_MAP_SHIFT)
+
+/* SPI (Serial Peripheral Interface) Register */
+#define SPI_REG							(0x40 << MEM_MAP_SHIFT)
+
+#define SPI_DAC_SRL_DGTL_OTPT_OFST          (0)
+#define SPI_DAC_SRL_DGTL_OTPT_MSK           (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
+#define SPI_DAC_SRL_CLK_OTPT_OFST           (1)
+#define SPI_DAC_SRL_CLK_OTPT_MSK            (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
+#define SPI_DAC_SRL_CS_OTPT_OFST            (2)
+#define SPI_DAC_SRL_CS_OTPT_MSK             (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
+#define SPI_HV_SRL_DGTL_OTPT_OFST           (8)
+#define SPI_HV_SRL_DGTL_OTPT_MSK            (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
+#define SPI_HV_SRL_CLK_OTPT_OFST            (9)
+#define SPI_HV_SRL_CLK_OTPT_MSK             (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
+#define SPI_HV_SRL_CS_OTPT_OFST             (10)
+#define SPI_HV_SRL_CS_OTPT_MSK              (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
+
+/* ADC SPI (Serial Peripheral Interface) Register */
+#define ADC_SPI_REG   					(0x41 << MEM_MAP_SHIFT)
+
+#define ADC_SPI_SRL_CLK_OTPT_OFST       (0)
+#define ADC_SPI_SRL_CLK_OTPT_MSK        (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
+#define ADC_SPI_SRL_DT_OTPT_OFST        (1)
+#define ADC_SPI_SRL_DT_OTPT_MSK         (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
+#define ADC_SPI_SRL_CS_OTPT_OFST        (2)
+#define ADC_SPI_SRL_CS_OTPT_MSK         (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
+
+/* ADC offset Register */
+#define ADC_OFST_REG 					(0x42 << MEM_MAP_SHIFT)
+
+/* ADC Port Invert Register */
+#define ADC_PORT_INVERT_REG   			(0x43 << MEM_MAP_SHIFT)
+
+#define ADC_PORT_INVERT_ADC_0_OFST      (0)
+#define ADC_PORT_INVERT_ADC_0_MSK       (0x000000FF << ADC_PORT_INVERT_ADC_0_OFST)
+#define ADC_PORT_INVERT_ADC_1_OFST      (8)
+#define ADC_PORT_INVERT_ADC_1_MSK       (0x000000FF << ADC_PORT_INVERT_ADC_1_OFST)
+#define ADC_PORT_INVERT_ADC_2_OFST      (16)
+#define ADC_PORT_INVERT_ADC_2_MSK       (0x000000FF << ADC_PORT_INVERT_ADC_2_OFST)
+#define ADC_PORT_INVERT_ADC_3_OFST      (24)
+#define ADC_PORT_INVERT_ADC_3_MSK       (0x000000FF << ADC_PORT_INVERT_ADC_3_OFST)
+
+/* Receiver IP Address Register */
+#define RX_IP_REG    					(0x45 << MEM_MAP_SHIFT)
+
+/* UDP Port */
+#define UDP_PORT_REG    				(0x46 << MEM_MAP_SHIFT)
+
+#define UDP_PORT_RX_OFST				(0)
+#define UDP_PORT_RX_MSK					(0x0000FFFF << UDP_PORT_RX_OFST)
+#define UDP_PORT_TX_OFST				(16)
+#define UDP_PORT_TX_MSK					(0x0000FFFF << UDP_PORT_TX_OFST)
+
+/* Receiver Mac Address 64 bit Register */
+#define RX_MAC_LSB_REG					(0x47 << MEM_MAP_SHIFT)
+#define RX_MAC_MSB_REG					(0x48 << MEM_MAP_SHIFT)
+
+#define RX_MAC_LSB_OFST					(0)
+#define RX_MAC_LSB_MSK					(0xFFFFFFFF << RX_MAC_LSB_OFST)
+#define RX_MAC_MSB_OFST					(0)
+#define RX_MAC_MSB_MSK					(0x0000FFFF << RX_MAC_MSB_OFST)
+
+/* Detector/ Transmitter Mac Address 64 bit Register */
+#define TX_MAC_LSB_REG					(0x49 << MEM_MAP_SHIFT)
+#define TX_MAC_MSB_REG					(0x4A << MEM_MAP_SHIFT)
+
+#define TX_MAC_LSB_OFST					(0)
+#define TX_MAC_LSB_MSK					(0xFFFFFFFF << TX_MAC_LSB_OFST)
+#define TX_MAC_MSB_OFST					(0)
+#define TX_MAC_MSB_MSK					(0x0000FFFF << TX_MAC_MSB_OFST)
+
+/* Detector/ Transmitter IP Address Register */
+#define TX_IP_REG						(0x4B << MEM_MAP_SHIFT)
+
+/* Detector/ Transmitter IP Checksum Register */
+#define TX_IP_CHECKSUM_REG				(0x4C << MEM_MAP_SHIFT)
+
+#define TX_IP_CHECKSUM_OFST				(0)
+#define TX_IP_CHECKSUM_MSK				(0x0000FFFF << TX_IP_CHECKSUM_OFST)
+
+/* Configuration Register */
+#define CONFIG_REG            			(0x4D << MEM_MAP_SHIFT)
+
+// readout timer (from chip) to stabilize (esp in burst acquisition mode) tRDT = (RDT + 1) * 25ns
+#define CONFIG_RDT_TMR_OFST             (0)
+#define CONFIG_RDT_TMR_MSK              (0x0000FFFF << CONFIG_RDT_TMR_OFST)
+#define CONFIG_OPRTN_MDE_2_X_10GbE_OFST (16)
+#define CONFIG_OPRTN_MDE_2_X_10GbE_MSK  (0x00000001 << CONFIG_OPRTN_MDE_2_X_10GbE_OFST)
+#define CONFIG_OPRTN_MDE_1_X_10GBE_VAL  ((0x0 << CONFIG_OPRTN_MDE_2_X_10GbE_OFST) & CONFIG_OPRTN_MDE_2_X_10GbE_MSK)
+#define CONFIG_READOUT_SPEED_OFST		(20)
+#define CONFIG_READOUT_SPEED_MSK		(0x00000003 << CONFIG_READOUT_SPEED_OFST)
+#define CONFIG_QUARTER_SPEED_10MHZ_VAL	((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
+#define CONFIG_HALF_SPEED_20MHZ_VAL		((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
+#define CONFIG_FULL_SPEED_40MHZ_VAL		((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
+#define CONFIG_TDMA_OFST				(24)
+#define CONFIG_TDMA_MSK					(0x00000001 << CONFIG_TDMA_OFST)
+#define CONFIG_TDMA_DISABLE_VAL         ((0x0 << CONFIG_TDMA_OFST) & CONFIG_TDMA_MSK)
+#define CONFIG_TDMA_TIMESLOT_OFST       (25)  // 1ms
+#define CONFIG_TDMA_TIMESLOT_MSK		(0x0000001F << CONFIG_TDMA_TIMESLOT_OFST)
+#define CONFIG_ETHRNT_FLW_CNTRL_OFST    (31)
+#define CONFIG_ETHRNT_FLW_CNTRL_MSK     (0x00000001 << CONFIG_ETHRNT_FLW_CNTRL_OFST)
+
+/* External Signal Register */
+#define EXT_SIGNAL_REG        			(0x4E << MEM_MAP_SHIFT)
+
+#define EXT_SIGNAL_OFST					(0)
+#define EXT_SIGNAL_MSK					(0x00000001 << EXT_SIGNAL_OFST)
+
+/* Control Register */
+#define CONTROL_REG           			(0x4F << MEM_MAP_SHIFT)
+
+#define CONTROL_START_ACQ_OFST       	(0)
+#define CONTROL_START_ACQ_MSK			(0x00000001 << CONTROL_START_ACQ_OFST)
+#define CONTROL_STOP_ACQ_OFST			(1)
+#define CONTROL_STOP_ACQ_MSK			(0x00000001 << CONTROL_STOP_ACQ_OFST)
+#define CONTROL_CORE_RST_OFST			(10)
+#define CONTROL_CORE_RST_MSK			(0x00000001 << CONTROL_CORE_RST_OFST)
+#define CONTROL_PERIPHERAL_RST_OFST		(11)										//DDR3 HMem Ctrlr, GBE, Temp
+#define CONTROL_PERIPHERAL_RST_MSK		(0x00000001 << CONTROL_PERIPHERAL_RST_OFST)	//DDR3 HMem Ctrlr, GBE, Temp
+#define CONTROL_DDR3_MEM_RST_OFST		(12)										//only PHY, not DDR3 PLL ,Not used in software
+#define CONTROL_DDR3_MEM_RST_MSK		(0x00000001 << CONTROL_DDR3_MEM_RST_OFST)	//only PHY, not DDR3 PLL ,Not used in software
+#define CONTROL_ACQ_FIFO_CLR_OFST		(14)
+#define CONTROL_ACQ_FIFO_CLR_MSK		(0x00000001 << CONTROL_ACQ_FIFO_CLR_OFST)
+#define CONTROL_STORAGE_CELL_NUM_OFST   (16)
+#define CONTROL_STORAGE_CELL_NUM_MSK    (0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
+
+/* Reconfiguratble PLL Paramater Register */
+#define PLL_PARAM_REG					(0x50 << MEM_MAP_SHIFT)
+
+/* Reconfiguratble PLL Control Regiser */
+#define PLL_CNTRL_REG					(0x51 << MEM_MAP_SHIFT)
+
+#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST	(0)											//parameter reset
+#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK	(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)	//parameter reset
+#define PLL_CNTRL_WR_PRMTR_OFST		    (2)
+#define PLL_CNTRL_WR_PRMTR_MSK		    (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
+#define PLL_CNTRL_PLL_RST_OFST			(3)
+#define PLL_CNTRL_PLL_RST_MSK			(0x00000001 << PLL_CNTRL_PLL_RST_OFST)
+#define PLL_CNTRL_ADDR_OFST				(16)
+#define PLL_CNTRL_ADDR_MSK				(0x0000003F << PLL_CNTRL_ADDR_OFST)
+
+/* Sample Register */
+#define SAMPLE_REG 						(0x59 << MEM_MAP_SHIFT)
+
+#define SAMPLE_ADC_SAMPLE_SEL_OFST		(0)
+#define SAMPLE_ADC_SAMPLE_SEL_MSK		(0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
+#define SAMPLE_ADC_SAMPLE_0_VAL			((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_1_VAL			((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_2_VAL			((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_3_VAL			((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_4_VAL			((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_5_VAL			((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_6_VAL			((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+#define SAMPLE_ADC_SAMPLE_7_VAL			((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
+// Decimation = ADF + 1
+#define SAMPLE_ADC_DECMT_FACTOR_OFST	(4)
+#define SAMPLE_ADC_DECMT_FACTOR_MSK		(0x00000007 << SAMPLE_ADC_DECMT_FACTOR_OFST)
+#define SAMPLE_ADC_DECMT_FACTOR_0_VAL	((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_1_VAL	((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_2_VAL	((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_3_VAL	((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_4_VAL	((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_5_VAL	((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_6_VAL	((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+#define SAMPLE_ADC_DECMT_FACTOR_7_VAL	((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
+
+#define SAMPLE_DGTL_SAMPLE_SEL_OFST		(8)
+#define SAMPLE_DGTL_SAMPLE_SEL_MSK		(0x0000000F << SAMPLE_DGTL_SAMPLE_SEL_OFST)
+#define SAMPLE_DGTL_SAMPLE_0_VAL		((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_1_VAL		((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_2_VAL		((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_3_VAL		((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_4_VAL		((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_5_VAL		((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_6_VAL		((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_7_VAL		((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_8_VAL		((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_9_VAL		((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_10_VAL		((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_11_VAL		((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_12_VAL		((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_13_VAL		((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_14_VAL		((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+#define SAMPLE_DGTL_SAMPLE_15_VAL		((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
+
+#define SAMPLE_DGTL_DECMT_FACTOR_OFST	(12)
+#define SAMPLE_DGTL_DECMT_FACTOR_MSK	(0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
+// 1 = full speed, 2 = half speed, 4 = quarter speed
+#define SAMPLE_DECMT_FACTOR_1_VAL		((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
+#define SAMPLE_DECMT_FACTOR_2_VAL		((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
+#define SAMPLE_DECMT_FACTOR_4_VAL		((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
+
+/** Vref Comp Mod Register */
+#define VREF_COMP_MOD_REG				(0x5C << MEM_MAP_SHIFT)
+
+#define VREF_COMP_MOD_OFST              (0)
+#define VREF_COMP_MOD_MSK               (0x00000FFF << VREF_COMP_MOD_OFST)
+#define VREF_COMP_MOD_ENABLE_OFST       (31)
+#define VREF_COMP_MOD_ENABLE_MSK        (0x00000001 << VREF_COMP_MOD_ENABLE_OFST)
+
+
+/** DAQ Register */
+#define DAQ_REG							(0x5D << MEM_MAP_SHIFT)
+
+#define DAQ_SETTINGS_MSK                (DAQ_HIGH_GAIN_MSK | DAQ_FIX_GAIN_MSK | DAQ_FRCE_SWTCH_GAIN_MSK)
+#define DAQ_HIGH_GAIN_OFST              (0)
+#define DAQ_HIGH_GAIN_MSK               (0x00000001 << DAQ_HIGH_GAIN_OFST)
+#define DAQ_FIX_GAIN_DYNMC_VAL          ((0x0 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
+#define DAQ_FIX_GAIN_HIGHGAIN_VAL       ((0x1 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
+#define DAQ_FIX_GAIN_OFST               (1)
+#define DAQ_FIX_GAIN_MSK                (0x00000003 << DAQ_FIX_GAIN_OFST)
+#define DAQ_FIX_GAIN_STG_1_VAL          ((0x1 << DAQ_FIX_GAIN_OFST) & DAQ_FIX_GAIN_MSK)
+#define DAQ_FIX_GAIN_STG_2_VAL          ((0x3 << DAQ_FIX_GAIN_OFST) & DAQ_FIX_GAIN_MSK)
+#define DAQ_CMP_RST_OFST                (4)
+#define DAQ_CMP_RST_MSK                 (0x00000001 << DAQ_CMP_RST_OFST)
+#define DAQ_STRG_CELL_SLCT_OFST         (8)
+#define DAQ_STRG_CELL_SLCT_MSK          (0x0000000F << DAQ_STRG_CELL_SLCT_OFST)
+#define DAQ_FRCE_SWTCH_GAIN_OFST        (12)
+#define DAQ_FRCE_SWTCH_GAIN_MSK         (0x00000003 << DAQ_FRCE_SWTCH_GAIN_OFST)
+#define DAQ_FRCE_GAIN_STG_1_VAL         ((0x1 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
+#define DAQ_FRCE_GAIN_STG_2_VAL         ((0x3 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
+#define DAQ_ELCTRN_CLLCTN_MDE_OFST      (14)
+#define DAQ_ELCTRN_CLLCTN_MDE_MSK       (0x00000001 << DAQ_ELCTRN_CLLCTN_MDE_OFST)
+#define DAQ_G2_CNNT_OFST                (15)
+#define DAQ_G2_CNNT_MSK                 (0x00000001 << DAQ_G2_CNNT_OFST)
+#define DAQ_CRRNT_SRC_ENBL_OFST         (16)
+#define DAQ_CRRNT_SRC_ENBL_MSK          (0x00000001 << DAQ_CRRNT_SRC_ENBL_OFST)
+#define DAQ_CRRNT_SRC_CLMN_FIX_OFST     (17)
+#define DAQ_CRRNT_SRC_CLMN_FIX_MSK      (0x00000001 << DAQ_CRRNT_SRC_CLMN_FIX_OFST)
+#define DAQ_CRRNT_SRC_CLMN_SLCT_OFST    (20)
+#define DAQ_CRRNT_SRC_CLMN_SLCT_MSK     (0x0000003F << DAQ_CRRNT_SRC_CLMN_SLCT_OFST)
+
+/** Chip Power Register */
+#define CHIP_POWER_REG					(0x5E << MEM_MAP_SHIFT)
+
+#define CHIP_POWER_ENABLE_OFST			(0)
+#define CHIP_POWER_ENABLE_MSK			(0x00000001 << CHIP_POWER_ENABLE_OFST)
+#define CHIP_POWER_STATUS_OFST          (1)
+#define CHIP_POWER_STATUS_MSK           (0x00000001 << CHIP_POWER_STATUS_OFST)
+
+
+/** Temperature Control Register */
+#define TEMP_CTRL_REG                   (0x5F << MEM_MAP_SHIFT)
+
+#define TEMP_CTRL_PROTCT_THRSHLD_OFST   (0)
+#define TEMP_CTRL_PROTCT_THRSHLD_MSK    (0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
+#define TEMP_CTRL_PROTCT_ENABLE_OFST    (16)
+#define TEMP_CTRL_PROTCT_ENABLE_MSK     (0x00000001 << TEMP_CTRL_PROTCT_ENABLE_OFST)
+// set when temp higher than over threshold, write 1 to clear it
+#define TEMP_CTRL_OVR_TMP_EVNT_OFST     (31)
+#define TEMP_CTRL_OVR_TMP_EVNT_MSK      (0x00000001 << TEMP_CTRL_OVR_TMP_EVNT_OFST)
+
+
+/* Set Delay 64 bit register */
+#define SET_DELAY_LSB_REG     			(0x60 << MEM_MAP_SHIFT)					// different kind of delay
+#define SET_DELAY_MSB_REG     			(0x61 << MEM_MAP_SHIFT)					// different kind of delay
+
+/* Set Cycles 64 bit register */
+#define SET_CYCLES_LSB_REG    			(0x62 << MEM_MAP_SHIFT)
+#define SET_CYCLES_MSB_REG    			(0x63 << MEM_MAP_SHIFT)
+
+/* Set Frames 64 bit register */
+#define SET_FRAMES_LSB_REG   			(0x64 << MEM_MAP_SHIFT)
+#define SET_FRAMES_MSB_REG    			(0x65 << MEM_MAP_SHIFT)
+
+/* Set Period 64 bit register tT = T x 50 ns */
+#define SET_PERIOD_LSB_REG    			(0x66 << MEM_MAP_SHIFT)
+#define SET_PERIOD_MSB_REG    			(0x67 << MEM_MAP_SHIFT)
+
+/* Set Exptime 64 bit register eEXP = Exp x 25 ns */
+#define SET_EXPTIME_LSB_REG    			(0x68 << MEM_MAP_SHIFT)
+#define SET_EXPTIME_MSB_REG    			(0x69 << MEM_MAP_SHIFT)
+
+/* Trigger Delay 32 bit register */
+#define SET_TRIGGER_DELAY_LSB_REG       (0x70 << MEM_MAP_SHIFT)
+#define SET_TRIGGER_DELAY_MSB_REG       (0x71 << MEM_MAP_SHIFT)
+
+/* Module Coordinates Register 0 */
+#define COORD_0_REG						(0x7C << MEM_MAP_SHIFT)
+
+#define COORD_0_Y_OFST					(0)
+#define COORD_0_Y_MSK					(0x0000FFFF << COORD_0_Y_OFST)
+#define COORD_0_X_OFST					(16)
+#define COORD_0_X_MSK					(0x0000FFFF << COORD_0_X_OFST)
+
+/* Module Coordinates Register 1 */
+#define COORD_1_REG						(0x7D << MEM_MAP_SHIFT)
+
+#define COORD_0_Z_OFST					(0)
+#define COORD_0_Z_MSK					(0x0000FFFF << COORD_0_Z_OFST)
+
+/* ASIC Control Register */
+#define ASIC_CTRL_REG                   (0x7F << MEM_MAP_SHIFT)
+// tPC = (PCT + 1) * 25ns
+#define ASIC_CTRL_PRCHRG_TMR_OFST       (0)
+#define ASIC_CTRL_PRCHRG_TMR_MSK        (0x000000FF << ASIC_CTRL_PRCHRG_TMR_OFST)
+#define ASIC_CTRL_PRCHRG_TMR_VAL        ((0x1F << ASIC_CTRL_PRCHRG_TMR_OFST) & ASIC_CTRL_PRCHRG_TMR_MSK)
+// tDS = (DST + 1) * 25ns
+#define ASIC_CTRL_DS_TMR_OFST           (8)
+#define ASIC_CTRL_DS_TMR_MSK            (0x000000FF << ASIC_CTRL_DS_TMR_OFST)
+#define ASIC_CTRL_DS_TMR_VAL            ((0x1F << ASIC_CTRL_DS_TMR_OFST) & ASIC_CTRL_DS_TMR_MSK)
+// tET = (ET + 1) * 25ns (increase timeout range between 2 consecutive storage cells)
+#define ASIC_CTRL_EXPSRE_TMR_STEPS		(25)
+#define ASIC_CTRL_EXPSRE_TMR_OFST       (16)
+#define ASIC_CTRL_EXPSRE_TMR_MSK        (0x0000FFFF << ASIC_CTRL_EXPSRE_TMR_OFST)
+
+
+
+/* ADC 0 Deserializer Control */
+#define ADC_DSRLZR_0_REG				(0xF0 << MEM_MAP_SHIFT)
+#define ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST (31)	/* Refresh alignment */
+#define ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK  (0x00000001 << ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST)
+
+/* ADC 0 Deserializer Control */
+#define ADC_DSRLZR_1_REG				(0xF1 << MEM_MAP_SHIFT)
+#define ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST (31)
+#define ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK  (0x00000001 << ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST)
+
+/* ADC 0 Deserializer Control */
+#define ADC_DSRLZR_2_REG				(0xF2 << MEM_MAP_SHIFT)
+#define ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST (31)
+#define ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK  (0x00000001 << ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST)
+
+/* ADC 0 Deserializer Control */
+#define ADC_DSRLZR_3_REG				(0xF3 << MEM_MAP_SHIFT)
+#define ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST (31)
+#define ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK  (0x00000001 << ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST)
+
+
+
+
+
+
+
+

slsDetectorServers/jungfrauDetectorServer/ansi.h

@@ -0,0 +1 @@
+../../slsSupportLib/include/ansi.h