From 885093f9901f49ca08e7e868409dc9130f8d4946 Mon Sep 17 00:00:00 2001 From: Alice Date: Thu, 5 Mar 2026 09:46:36 +0100 Subject: [PATCH] oops given in hex --- etc/generate_registerdefs.py | 64 ++++++++---------- .../matterhonServer/include/RegisterDefs.hpp | 66 +++++++++---------- 2 files changed, 62 insertions(+), 68 deletions(-) diff --git a/etc/generate_registerdefs.py b/etc/generate_registerdefs.py index d8202eee4..cbe84c3ba 100644 --- a/etc/generate_registerdefs.py +++ b/etc/generate_registerdefs.py @@ -5,21 +5,12 @@ def Ip_core_name_to_enum_type(ip_core_name : str) -> str: """Convert IP core name to enum type IPCore.""" if pd.isna(ip_core_name): return "IPCore::UNKNOWN" -<<<<<<< HEAD return f"IPCore::{ip_core_name.upper()}" def create_bitmask_and_offset(from_bit : int, to_bit : int) -> tuple[int, int]: """Create a bitmask for a register field given the from_bit and to_bit.""" if from_bit < 0 or to_bit < 0 or from_bit > to_bit or from_bit >= 32 or to_bit >= 32: -======= - else: - return f"IPCore::{ip_core_name.upper()}" - -def create_bitmask_and_offset(from_bit : int, to_bit : int) -> tuple[int, int]: - """Create a bitmask for a register field given the from_bit and to_bit.""" - if from_bit < 0 or to_bit < 0 or from_bit > to_bit: ->>>>>>> 370aada49 (generated register defs from csv file) raise ValueError(f"Invalid bit range: from_bit={from_bit}, to_bit={to_bit}") offset = from_bit @@ -41,37 +32,51 @@ def argument_parser(): # TODO: should be configurable header = r""" -<<<<<<< HEAD +#pragma once // clang-format off #include "RegisterHelperStructs.hpp" namespace sls { + + +namespace Reg { + /// @brief Enum for IP cores, value are adresses enum class IPCore : uint32_t { -======= -#include "RegisterHelperStructs.hpp" - -/// @brief Enum for IP cores, value are adresses -constexpr enum class IPCore : uint32_t { ->>>>>>> 370aada49 (generated register defs from csv file) - MH_RO_SM_AXI = 0, // dummy adresses for now - FHDR_AXI = 1, - AURORA_STATUS = 2, - AURORA_STATUS2 = 3, + MH_RO_SM_AXI = 0xB0010000, + FHDR_AXI = 0xB0011000, + AURORA_STATUS = 0xB0014000, + AURORA_STATUS2 = 0xB0015000, PACKETIZERREG = 4, - UNKNOWN = 5 + UNKNOWN = 0x00000000 // dont know yet }; + +constexpr size_t IPCORE_REGISTER_BLOCK_SIZE = + 0x1000; // size of each IP core address space in bytes // TODO: maybe add in + // other file definitions + +// clang-format off + """ -<<<<<<< HEAD postpend = r""" +constexpr RegisterField ModuleRow{ + Frame_HDR_ModCoord_LSB_Reg, 0, 0xffff}; + +constexpr RegisterField ModuleCol{ + Frame_HDR_ModCoord_LSB_Reg, 16, 0xffff}; + +constexpr RegisterField ModuleCoordz{ + Frame_HDR_ModCoord_MSB_Reg, 0, 0xffff}; + +constexpr RegisterField ModuleIndex{ + Frame_HDR_ModCoord_MSB_Reg, 16, 0xffff}; +} // namespace Reg } // namespace sls // clang-format on """ -======= ->>>>>>> 370aada49 (generated register defs from csv file) def main(): args = argument_parser() @@ -95,14 +100,10 @@ def main(): register_name = row["Reg_name"] ip_core_name = row["Interface"] -<<<<<<< HEAD define_register_string = ( f"constexpr Register {register_name}{{" f"{Ip_core_name_to_enum_type(ip_core_name)}, {hex(int(local_address_offset_in_bytes, 16))}}};" ) -======= - define_register_string = f'constexpr Register {register_name}{{{Ip_core_name_to_enum_type(ip_core_name)}, {local_address_offset_in_bytes}}};' ->>>>>>> 370aada49 (generated register defs from csv file) header_file.write(f"{define_register_string}\n") header_file.write("\n") @@ -120,22 +121,15 @@ def main(): to_bit = row["To_bit"] mask, offset = create_bitmask_and_offset(from_bit, to_bit) -<<<<<<< HEAD define_registerfield_string = ( f"constexpr RegisterField {field_name}{{\n" f" {register_name}, {offset}, {hex(mask)}}};" ) -======= - define_registerfield_string = f"constexpr RegisterField {field_name}{{{register_name}, {hex(mask)}, {offset}}};" ->>>>>>> 370aada49 (generated register defs from csv file) header_file.write(f"{define_registerfield_string}\n") header_file.write("\n") -<<<<<<< HEAD header_file.write(postpend) # TODO: have to take care xof it manually when in append mode - ugly -======= ->>>>>>> 370aada49 (generated register defs from csv file) header_file.close() diff --git a/slsDetectorServers/matterhonServer/include/RegisterDefs.hpp b/slsDetectorServers/matterhonServer/include/RegisterDefs.hpp index 6a8e38ee9..b979ee2e4 100644 --- a/slsDetectorServers/matterhonServer/include/RegisterDefs.hpp +++ b/slsDetectorServers/matterhonServer/include/RegisterDefs.hpp @@ -13,71 +13,71 @@ constexpr enum class IPCore : uint32_t { // Register definitions -constexpr Register CTRL_Reg{IPCore::UNKNOWN, 0}; +constexpr Register CTRL_Reg{IPCore::UNKNOWN, 0x0}; -constexpr Register Status_Reg{IPCore::UNKNOWN, 4}; +constexpr Register Status_Reg{IPCore::UNKNOWN, 0x4}; -constexpr Register FPGAVersionReg{IPCore::UNKNOWN, 8}; +constexpr Register FPGAVersionReg{IPCore::UNKNOWN, 0x8}; -constexpr Register FPGA_GIT_HEAD{IPCore::UNKNOWN, C}; +constexpr Register FPGA_GIT_HEAD{IPCore::UNKNOWN, 0xc}; -constexpr Register FixedPatternReg{IPCore::UNKNOWN, 10}; +constexpr Register FixedPatternReg{IPCore::UNKNOWN, 0x10}; -constexpr Register ApiVersionReg{IPCore::UNKNOWN, 14}; +constexpr Register ApiVersionReg{IPCore::UNKNOWN, 0x14}; -constexpr Register Chip_ID_Reg{IPCore::UNKNOWN, 18}; +constexpr Register Chip_ID_Reg{IPCore::UNKNOWN, 0x18}; -constexpr Register MH_SM_Ctrl_Reg{IPCore::MH_RO_SM_AXI, 0}; +constexpr Register MH_SM_Ctrl_Reg{IPCore::MH_RO_SM_AXI, 0x0}; -constexpr Register MH_SM_Exposure_Reg{IPCore::MH_RO_SM_AXI, 4}; +constexpr Register MH_SM_Exposure_Reg{IPCore::MH_RO_SM_AXI, 0x4}; -constexpr Register MH_SM_Period_Reg{IPCore::MH_RO_SM_AXI, 8}; +constexpr Register MH_SM_Period_Reg{IPCore::MH_RO_SM_AXI, 0x8}; -constexpr Register MH_SM_Frames_Reg{IPCore::MH_RO_SM_AXI, C}; +constexpr Register MH_SM_Frames_Reg{IPCore::MH_RO_SM_AXI, 0xc}; -constexpr Register MH_SM_StoreLength_Reg{IPCore::MH_RO_SM_AXI, 10}; +constexpr Register MH_SM_StoreLength_Reg{IPCore::MH_RO_SM_AXI, 0x10}; -constexpr Register MH_SM_ResetMHLength_Reg{IPCore::MH_RO_SM_AXI, 14}; +constexpr Register MH_SM_ResetMHLength_Reg{IPCore::MH_RO_SM_AXI, 0x14}; -constexpr Register Frame_HDR_Set_Reg{IPCore::FHDR_AXI, 0}; +constexpr Register Frame_HDR_Set_Reg{IPCore::FHDR_AXI, 0x0}; -constexpr Register Frame_HDR_FrameNumLSB_Reg{IPCore::FHDR_AXI, 4}; +constexpr Register Frame_HDR_FrameNumLSB_Reg{IPCore::FHDR_AXI, 0x4}; -constexpr Register Frame_HDR_FrameNumMSB_Reg{IPCore::FHDR_AXI, 8}; +constexpr Register Frame_HDR_FrameNumMSB_Reg{IPCore::FHDR_AXI, 0x8}; -constexpr Register Frame_HDR_TimestampLSB_Reg{IPCore::FHDR_AXI, C}; +constexpr Register Frame_HDR_TimestampLSB_Reg{IPCore::FHDR_AXI, 0xc}; -constexpr Register Frame_HDR_TimestampMSB_Reg{IPCore::FHDR_AXI, 10}; +constexpr Register Frame_HDR_TimestampMSB_Reg{IPCore::FHDR_AXI, 0x10}; -constexpr Register Frame_HDR_ModCoord_LSB_Reg{IPCore::FHDR_AXI, 14}; +constexpr Register Frame_HDR_ModCoord_LSB_Reg{IPCore::FHDR_AXI, 0x14}; -constexpr Register Frame_HDR_ModCoord_MSB_Reg{IPCore::FHDR_AXI, 18}; +constexpr Register Frame_HDR_ModCoord_MSB_Reg{IPCore::FHDR_AXI, 0x18}; -constexpr Register Frame_HDR_PktctrMax_Reg{IPCore::FHDR_AXI, 1C}; +constexpr Register Frame_HDR_PktctrMax_Reg{IPCore::FHDR_AXI, 0x1c}; -constexpr Register Aurora_Valid_DW_Reg{IPCore::AURORA_STATUS, 0}; +constexpr Register Aurora_Valid_DW_Reg{IPCore::AURORA_STATUS, 0x0}; -constexpr Register Aurora_Valid_Bytes_Reg{IPCore::AURORA_STATUS, 4}; +constexpr Register Aurora_Valid_Bytes_Reg{IPCore::AURORA_STATUS, 0x4}; -constexpr Register Aurora_Busy_Up_Cycles_Reg{IPCore::AURORA_STATUS, 8}; +constexpr Register Aurora_Busy_Up_Cycles_Reg{IPCore::AURORA_STATUS, 0x8}; -constexpr Register Aurora_Hard_Errors_Reg{IPCore::AURORA_STATUS, C}; +constexpr Register Aurora_Hard_Errors_Reg{IPCore::AURORA_STATUS, 0xc}; -constexpr Register Aurora_Soft_Errors_Reg{IPCore::AURORA_STATUS, 10}; +constexpr Register Aurora_Soft_Errors_Reg{IPCore::AURORA_STATUS, 0x10}; -constexpr Register Aurora_Channel_n_Lanes_Up_Reg{IPCore::AURORA_STATUS, 14}; +constexpr Register Aurora_Channel_n_Lanes_Up_Reg{IPCore::AURORA_STATUS, 0x14}; -constexpr Register Aurora_GT_PLL_Lock_Reg{IPCore::AURORA_STATUS2, 0}; +constexpr Register Aurora_GT_PLL_Lock_Reg{IPCore::AURORA_STATUS2, 0x0}; -constexpr Register PktPacketLengthReg{IPCore::PACKETIZERREG, A100}; +constexpr Register PktPacketLengthReg{IPCore::PACKETIZERREG, 0xa100}; -constexpr Register PktNoPacketsReg{IPCore::PACKETIZERREG, A104}; +constexpr Register PktNoPacketsReg{IPCore::PACKETIZERREG, 0xa104}; -constexpr Register PktCtrlReg{IPCore::PACKETIZERREG, A108}; +constexpr Register PktCtrlReg{IPCore::PACKETIZERREG, 0xa108}; -constexpr Register PktCoordReg1{IPCore::PACKETIZERREG, A10C}; +constexpr Register PktCoordReg1{IPCore::PACKETIZERREG, 0xa10c}; -constexpr Register PktCoordReg2{IPCore::PACKETIZERREG, A110}; +constexpr Register PktCoordReg2{IPCore::PACKETIZERREG, 0xa110};