gotthard2, mythen3: making them clkdivider dependant and not clkfrequency, binaries not loaded yet

This commit is contained in:
2020-04-28 17:04:57 +02:00
parent 337e56d9bf
commit 86b39853a3
6 changed files with 68 additions and 74 deletions

View File

@@ -44,12 +44,12 @@
#define DEFAULT_CURRENT_SOURCE (0)
#define DEFAULT_TIMING_SOURCE (TIMING_INTERNAL)
#define DEFAULT_READOUT_C0 (144444448) // rdo_clk, 144 MHz
#define DEFAULT_READOUT_C1 (144444448) // rdo_x2_clk, 144 MHz
#define DEFAULT_SYSTEM_C0 (144444448) // run_clk, 144 MHz
#define DEFAULT_SYSTEM_C1 (72222224) // chip_clk, 72 MHz
#define DEFAULT_SYSTEM_C2 (18055556) // sync_clk, 18 MHz
#define DEFAULT_SYSTEM_C3 (144444448) // str_clk, 144 MHz
#define DEFAULT_READOUT_C0 (6)//(144444448) // rdo_clk, 144 MHz
#define DEFAULT_READOUT_C1 (6)//(144444448) // rdo_x2_clk, 144 MHz
#define DEFAULT_SYSTEM_C0 (5)//(144444448) // run_clk, 144 MHz
#define DEFAULT_SYSTEM_C1 (10)//(72222224) // chip_clk, 72 MHz
#define DEFAULT_SYSTEM_C2 (40)//(18055556) // sync_clk, 18 MHz
#define DEFAULT_SYSTEM_C3 (5)//(144444448) // str_clk, 144 MHz
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)