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gotthard2, mythen3: making them clkdivider dependant and not clkfrequency, binaries not loaded yet
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@@ -44,12 +44,12 @@
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#define DEFAULT_CURRENT_SOURCE (0)
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#define DEFAULT_TIMING_SOURCE (TIMING_INTERNAL)
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#define DEFAULT_READOUT_C0 (144444448) // rdo_clk, 144 MHz
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#define DEFAULT_READOUT_C1 (144444448) // rdo_x2_clk, 144 MHz
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#define DEFAULT_SYSTEM_C0 (144444448) // run_clk, 144 MHz
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#define DEFAULT_SYSTEM_C1 (72222224) // chip_clk, 72 MHz
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#define DEFAULT_SYSTEM_C2 (18055556) // sync_clk, 18 MHz
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#define DEFAULT_SYSTEM_C3 (144444448) // str_clk, 144 MHz
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#define DEFAULT_READOUT_C0 (6)//(144444448) // rdo_clk, 144 MHz
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#define DEFAULT_READOUT_C1 (6)//(144444448) // rdo_x2_clk, 144 MHz
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#define DEFAULT_SYSTEM_C0 (5)//(144444448) // run_clk, 144 MHz
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#define DEFAULT_SYSTEM_C1 (10)//(72222224) // chip_clk, 72 MHz
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#define DEFAULT_SYSTEM_C2 (40)//(18055556) // sync_clk, 18 MHz
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#define DEFAULT_SYSTEM_C3 (5)//(144444448) // str_clk, 144 MHz
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/* Firmware Definitions */
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#define IP_HEADER_SIZE (20)
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