mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-12 12:57:13 +02:00
eiger: quad write/read reg (dr) and quad positions (#649)
* eiger: adding mask to read/write registers. useful for setting quad parameters as they might have different values for left and right fpga registers. ** fix quad position * fix quad flipping * formatting
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@ -1106,7 +1106,9 @@ int Beb_SetDetectorPosition(int pos[]) {
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int posRight[2] = {Beb_top ? pos[X] + 1 : pos[X], pos[Y]};
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if (Beb_quadEnable) {
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posRight[Y] = 1; // right is next row
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posLeft[Y] = 1; // left is next row
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posLeft[X] = 0; // left same first row
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posRight[Y] = 0; // right same first row
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posRight[X] = 0; // right same first column
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}
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@ -25,7 +25,7 @@ target_include_directories(eigerDetectorServer_virtual
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)
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target_compile_definitions(eigerDetectorServer_virtual
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PUBLIC EIGERD PCCOMPILE STOP_SERVER
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PUBLIC EIGERD PCCOMPILE STOP_SERVER #TEST_MOD_GEOMETRY
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PUBLIC VIRTUAL #VIRTUAL_9M
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)
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@ -1240,19 +1240,16 @@ int Feb_Control_GetDynamicRange(int *retval) {
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int Feb_Control_Disable16bitConversion(int disable) {
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LOG(logINFO, ("%s 16 bit expansion\n", disable ? "Disabling" : "Enabling"));
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uint32_t bitmask = DAQ_REG_HRDWRE_DSBL_16BIT_MSK;
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unsigned int regval = 0;
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if (!Feb_Control_ReadRegister(DAQ_REG_HRDWRE, ®val)) {
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LOG(logERROR, ("Could not %s 16 bit expansion (bit mode)\n",
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(disable ? "disable" : "enable")));
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return 0;
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}
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if (disable) {
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regval |= DAQ_REG_HRDWRE_DSBL_16BIT_MSK;
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regval |= bitmask;
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} else {
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regval &= ~DAQ_REG_HRDWRE_DSBL_16BIT_MSK;
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regval &= ~bitmask;
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}
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if (!Feb_Control_WriteRegister(DAQ_REG_HRDWRE, regval)) {
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if (!Feb_Control_WriteRegister_BitMask(DAQ_REG_HRDWRE, regval, bitmask)) {
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LOG(logERROR, ("Could not %s 16 bit expansion (bit mode)\n",
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(disable ? "disable" : "enable")));
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return 0;
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@ -1262,11 +1259,12 @@ int Feb_Control_Disable16bitConversion(int disable) {
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int Feb_Control_Get16bitConversionDisabled(int *ret) {
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unsigned int regval = 0;
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if (!Feb_Control_ReadRegister(DAQ_REG_HRDWRE, ®val)) {
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if (!Feb_Control_ReadRegister_BitMask(DAQ_REG_HRDWRE, ®val,
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DAQ_REG_HRDWRE_DSBL_16BIT_MSK)) {
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LOG(logERROR, ("Could not get 16 bit expansion (bit mode)\n"));
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return 0;
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}
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if (regval & DAQ_REG_HRDWRE_DSBL_16BIT_MSK) {
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if (regval) {
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*ret = 1;
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} else {
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*ret = 0;
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@ -1667,6 +1665,15 @@ int Feb_Control_GetReadNRows() {
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}
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int Feb_Control_WriteRegister(uint32_t offset, uint32_t data) {
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return Feb_Control_WriteRegister_BitMask(offset, data, BIT32_MSK);
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}
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int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval) {
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return Feb_Control_ReadRegister_BitMask(offset, retval, BIT32_MASK);
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}
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int Feb_Control_WriteRegister_BitMask(uint32_t offset, uint32_t data,
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uint32_t bitmask) {
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uint32_t actualOffset = offset;
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char side[2][10] = {"right", "left"};
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unsigned int addr[2] = {Feb_Control_rightAddress, Feb_Control_leftAddress};
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@ -1690,24 +1697,41 @@ int Feb_Control_WriteRegister(uint32_t offset, uint32_t data) {
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for (int iloop = 0; iloop < 2; ++iloop) {
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if (run[iloop]) {
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LOG(logDEBUG1,
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("Writing 0x%x to %s 0x%x\n", data, side[iloop], actualOffset));
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if (!Feb_Interface_WriteRegister(addr[iloop], actualOffset, data, 0,
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0)) {
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LOG(logERROR, ("Could not write 0x%x to %s addr 0x%x\n", data,
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LOG(logDEBUG1, ("Writing 0x%x to %s 0x%x (mask:0x%x)\n", data,
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side[iloop], actualOffset, bitmask));
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uint32_t writeVal = 0;
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if (!Feb_Interface_ReadRegister(addr[iloop], actualOffset,
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&writeVal)) {
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LOG(logERROR, ("Could not read %s addr 0x%x register\n",
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side[iloop], actualOffset));
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return 0;
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}
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uint32_t regVal = 0;
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if (!Feb_Interface_ReadRegister(addr[iloop], actualOffset,
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®Val)) {
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LOG(logERROR, ("Could not read %s register\n", addr[iloop]));
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// set only the bits in the mask
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writeVal &= ~(bitmask);
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writeVal |= (data & bitmask);
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LOG(logDEBUG1, ("writing 0x%x to 0x%x\n", writeVal, actualOffset));
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if (!Feb_Interface_WriteRegister(addr[iloop], actualOffset,
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writeVal, 0, 0)) {
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LOG(logERROR, ("Could not write 0x%x to %s addr 0x%x\n",
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writeVal, side[iloop], actualOffset));
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return 0;
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}
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if (regVal != data) {
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writeVal &= bitmask;
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uint32_t readVal = 0;
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if (!Feb_Interface_ReadRegister(addr[iloop], actualOffset,
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&readVal)) {
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return 0;
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}
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readVal &= bitmask;
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if (writeVal != readVal) {
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LOG(logERROR,
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("Could not write %s register. Write 0x%x, read 0x%x\n",
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addr[iloop], data, regVal));
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("Could not write %s addr 0x%x register. Wrote "
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"0x%x, read 0x%x (mask:0x%x)\n",
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side[iloop], actualOffset, writeVal, readVal, bitmask));
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return 0;
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}
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}
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@ -1716,7 +1740,8 @@ int Feb_Control_WriteRegister(uint32_t offset, uint32_t data) {
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return 1;
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}
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int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval) {
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int Feb_Control_ReadRegister_BitMask(uint32_t offset, uint32_t *retval,
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uint32_t bitmask) {
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uint32_t actualOffset = offset;
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char side[2][10] = {"right", "left"};
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unsigned int addr[2] = {Feb_Control_rightAddress, Feb_Control_leftAddress};
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@ -1746,8 +1771,9 @@ int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval) {
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side[iloop], actualOffset));
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return 0;
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}
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LOG(logDEBUG1, ("Read 0x%x from %s 0x%x\n", value[iloop],
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side[iloop], actualOffset));
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value[iloop] &= bitmask;
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LOG(logDEBUG1, ("Read 0x%x from %s 0x%x (mask:0x%x)\n",
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value[iloop], side[iloop], actualOffset, bitmask));
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*retval = value[iloop];
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// if not the other (left, not right OR right, not left), return the
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// value
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@ -1758,7 +1784,7 @@ int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval) {
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}
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// Inconsistent values when reading both registers
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if ((run[0] & run[1]) & (value[0] != value[1])) {
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LOG(logERROR, ("Inconsistent values read from %s 0x%x and %s 0x%x\n",
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LOG(logERROR, ("Inconsistent values read from %s: 0x%x and %s: 0x%x\n",
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side[0], value[0], side[1], value[1]));
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return 0;
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}
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@ -95,7 +95,10 @@ int Feb_Control_SetReadNRows(int value);
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int Feb_Control_GetReadNRows();
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int Feb_Control_WriteRegister(uint32_t offset, uint32_t data);
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int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval);
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int Feb_Control_WriteRegister_BitMask(uint32_t offset, uint32_t data,
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uint32_t bitmask);
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int Feb_Control_ReadRegister_BitMask(uint32_t offset, uint32_t *retval,
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uint32_t bitmask);
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// pulsing
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int Feb_Control_Pulse_Pixel(int npulses, int x, int y);
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int Feb_Control_PulsePixelNMove(int npulses, int inc_x_pos, int inc_y_pos);
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Binary file not shown.
@ -861,12 +861,15 @@ int setDynamicRange(int dr) {
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LOG(logINFO, ("Setting dynamic range: %d\n", dr));
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#else
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sharedMemory_lockLocalLink();
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if (Feb_Control_SetDynamicRange(dr)) {
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if (!Beb_SetUpTransferParameters(dr)) {
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LOG(logERROR, ("Could not set bit mode in the back end\n"));
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sharedMemory_unlockLocalLink();
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return eiger_dynamicrange;
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}
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if (!Feb_Control_SetDynamicRange(dr)) {
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LOG(logERROR, ("Could not set dynamic range in feb\n"));
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sharedMemory_unlockLocalLink();
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return FAIL;
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}
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if (!Beb_SetUpTransferParameters(dr)) {
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LOG(logERROR, ("Could not set bit mode in the back end\n"));
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sharedMemory_unlockLocalLink();
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return eiger_dynamicrange;
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}
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sharedMemory_unlockLocalLink();
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#endif
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@ -2664,6 +2667,10 @@ void *start_timer(void *arg) {
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header->modId = eiger_virtual_module_id;
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header->row = row;
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header->column = colLeft;
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if (eiger_virtual_quad_mode) {
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header->row = 1; // left is next row
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header->column = 0; // left same first column
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}
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char packetData2[packetsize];
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memset(packetData2, 0, packetsize);
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@ -2672,11 +2679,11 @@ void *start_timer(void *arg) {
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header->version = SLS_DETECTOR_HEADER_VERSION;
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header->frameNumber = frameNr + iframes;
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header->packetNumber = i;
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header->modId = eiger_virtual_module_id;
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header->modId = eiger_virtual_module_id + 1;
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header->row = row;
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header->column = colRight;
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if (eiger_virtual_quad_mode) {
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header->row = 1; // right is next row
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header->row = 0; // right is next row
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header->column = 0; // right same first column
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}
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@ -137,6 +137,7 @@ enum MASTERINDEX { MASTER_HARDWARE, OW_MASTER, OW_SLAVE };
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#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
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#define BIT16_MASK (0xFFFF)
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#define BIT32_MSK (0xFFFFFFFF)
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2048)
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