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format slsdetectorservers .c

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maliakal_d
2020-05-05 15:30:44 +02:00
parent 671cf45fd7
commit 7d94ad51ab
43 changed files with 20315 additions and 18726 deletions
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240
slsDetectorServers/slsDetectorServer/src/AD7689.c Executable file → Normal file
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@ -1,77 +1,99 @@
#include "AD7689.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "common.h"
#include "blackfin.h"
#include "clogger.h"
#include "common.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
/* AD7689 ADC DEFINES */
/** Read back CFG Register */
#define AD7689_CFG_RB_OFST (0)
#define AD7689_CFG_RB_MSK (0x00000001 << AD7689_CFG_RB_OFST)
#define AD7689_CFG_RB_OFST (0)
#define AD7689_CFG_RB_MSK (0x00000001 << AD7689_CFG_RB_OFST)
/** Channel sequencer */
#define AD7689_CFG_SEQ_OFST (1)
#define AD7689_CFG_SEQ_MSK (0x00000003 << AD7689_CFG_SEQ_OFST)
#define AD7689_CFG_SEQ_DSBLE_VAL ((0x0 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_UPDTE_DRNG_SQNCE_VAL ((0x1 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_SCN_WTH_TMP_VAL ((0x2 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_SCN_WTHT_TMP_VAL ((0x3 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_OFST (1)
#define AD7689_CFG_SEQ_MSK (0x00000003 << AD7689_CFG_SEQ_OFST)
#define AD7689_CFG_SEQ_DSBLE_VAL \
((0x0 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_UPDTE_DRNG_SQNCE_VAL \
((0x1 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_SCN_WTH_TMP_VAL \
((0x2 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
#define AD7689_CFG_SEQ_SCN_WTHT_TMP_VAL \
((0x3 << AD7689_CFG_SEQ_OFST) & AD7689_CFG_SEQ_MSK)
/** Reference/ buffer selection */
#define AD7689_CFG_REF_OFST (3)
#define AD7689_CFG_REF_MSK (0x00000007 << AD7689_CFG_REF_OFST)
/** Internal reference. REF = 2.5V buffered output. Temperature sensor enabled. */
#define AD7689_CFG_REF_INT_2500MV_VAL ((0x0 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_OFST)
/** Internal reference. REF = 4.096V buffered output. Temperature sensor enabled. */
#define AD7689_CFG_REF_INT_4096MV_VAL ((0x1 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
#define AD7689_CFG_REF_OFST (3)
#define AD7689_CFG_REF_MSK (0x00000007 << AD7689_CFG_REF_OFST)
/** Internal reference. REF = 2.5V buffered output. Temperature sensor enabled.
*/
#define AD7689_CFG_REF_INT_2500MV_VAL \
((0x0 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_OFST)
/** Internal reference. REF = 4.096V buffered output. Temperature sensor
* enabled. */
#define AD7689_CFG_REF_INT_4096MV_VAL \
((0x1 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor enabled. Internal buffer disabled. */
#define AD7689_CFG_REF_EXT_TMP_VAL ((0x2 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
#define AD7689_CFG_REF_EXT_TMP_VAL \
((0x2 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor enabled. Internal buffer enabled. */
#define AD7689_CFG_REF_EXT_TMP_INTBUF_VAL ((0x3 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor disabled. Internal buffer disabled. */
#define AD7689_CFG_REF_EXT_VAL ((0x6 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
#define AD7689_CFG_REF_EXT_TMP_INTBUF_VAL \
((0x3 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor disabled. Internal buffer disabled.
*/
#define AD7689_CFG_REF_EXT_VAL \
((0x6 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** External reference. Temperature sensor disabled. Internal buffer enabled. */
#define AD7689_CFG_REF_EXT_INTBUF_VAL ((0x7 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
#define AD7689_CFG_REF_EXT_INTBUF_VAL \
((0x7 << AD7689_CFG_REF_OFST) & AD7689_CFG_REF_MSK)
/** bandwidth of low pass filter */
#define AD7689_CFG_BW_OFST (6)
#define AD7689_CFG_BW_MSK (0x00000001 << AD7689_CFG_REF_OFST)
#define AD7689_CFG_BW_ONE_FOURTH_VAL ((0x0 << AD7689_CFG_BW_OFST) & AD7689_CFG_BW_MSK)
#define AD7689_CFG_BW_FULL_VAL ((0x1 << AD7689_CFG_BW_OFST) & AD7689_CFG_BW_MSK)
#define AD7689_CFG_BW_OFST (6)
#define AD7689_CFG_BW_MSK (0x00000001 << AD7689_CFG_REF_OFST)
#define AD7689_CFG_BW_ONE_FOURTH_VAL \
((0x0 << AD7689_CFG_BW_OFST) & AD7689_CFG_BW_MSK)
#define AD7689_CFG_BW_FULL_VAL ((0x1 << AD7689_CFG_BW_OFST) & AD7689_CFG_BW_MSK)
/** input channel selection IN0 - IN7 */
#define AD7689_CFG_IN_OFST (7)
#define AD7689_CFG_IN_MSK (0x00000007 << AD7689_CFG_IN_OFST)
#define AD7689_CFG_IN_OFST (7)
#define AD7689_CFG_IN_MSK (0x00000007 << AD7689_CFG_IN_OFST)
/** input channel configuration */
#define AD7689_CFG_INCC_OFST (10)
#define AD7689_CFG_INCC_MSK (0x00000007 << AD7689_CFG_INCC_OFST)
#define AD7689_CFG_INCC_BPLR_DFFRNTL_PRS_VAL ((0x0 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_BPLR_IN_COM_VAL ((0x2 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_TMP_VAL ((0x3 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_DFFRNTL_PRS_VAL ((0x4 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_IN_COM_VAL ((0x6 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_IN_GND_VAL ((0x7 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_OFST (10)
#define AD7689_CFG_INCC_MSK (0x00000007 << AD7689_CFG_INCC_OFST)
#define AD7689_CFG_INCC_BPLR_DFFRNTL_PRS_VAL \
((0x0 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_BPLR_IN_COM_VAL \
((0x2 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_TMP_VAL \
((0x3 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_DFFRNTL_PRS_VAL \
((0x4 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_IN_COM_VAL \
((0x6 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
#define AD7689_CFG_INCC_UNPLR_IN_GND_VAL \
((0x7 << AD7689_CFG_INCC_OFST) & AD7689_CFG_INCC_MSK)
/** configuration update */
#define AD7689_CFG_CFG_OFST (13)
#define AD7689_CFG_CFG_MSK (0x00000001 << AD7689_CFG_CFG_OFST)
#define AD7689_CFG_CFG_NO_UPDATE_VAL ((0x0 << AD7689_CFG_CFG_OFST) & AD7689_CFG_CFG_MSK)
#define AD7689_CFG_CFG_OVRWRTE_VAL ((0x1 << AD7689_CFG_CFG_OFST) & AD7689_CFG_CFG_MSK)
#define AD7689_CFG_CFG_OFST (13)
#define AD7689_CFG_CFG_MSK (0x00000001 << AD7689_CFG_CFG_OFST)
#define AD7689_CFG_CFG_NO_UPDATE_VAL \
((0x0 << AD7689_CFG_CFG_OFST) & AD7689_CFG_CFG_MSK)
#define AD7689_CFG_CFG_OVRWRTE_VAL \
((0x1 << AD7689_CFG_CFG_OFST) & AD7689_CFG_CFG_MSK)
#define AD7689_ADC_CFG_NUMBITS (14)
#define AD7689_ADC_DATA_NUMBITS (16)
#define AD7689_NUM_CHANNELS (8)
#define AD7689_NUM_INVALID_CONVERSIONS (3)
#define AD7689_ADC_CFG_NUMBITS (14)
#define AD7689_ADC_DATA_NUMBITS (16)
#define AD7689_NUM_CHANNELS (8)
#define AD7689_NUM_INVALID_CONVERSIONS (3)
#define AD7689_INT_REF_MAX_MV (2500) // chosen using reference buffer selection in config reg
#define AD7689_INT_REF_MIN_MV (0)
#define AD7689_INT_REF_MAX_UV (2500 * 1000)
#define AD7689_INT_REF_MIN_UV (0)
#define AD7689_INT_MAX_STEPS (0xFFFF + 1)
#define AD7689_TMP_C_FOR_1_MV (25.00 / 283.00)
#define AD7689_INT_REF_MAX_MV \
(2500) // chosen using reference buffer selection in config reg
#define AD7689_INT_REF_MIN_MV (0)
#define AD7689_INT_REF_MAX_UV (2500 * 1000)
#define AD7689_INT_REF_MIN_UV (0)
#define AD7689_INT_MAX_STEPS (0xFFFF + 1)
#define AD7689_TMP_C_FOR_1_MV (25.00 / 283.00)
// Definitions from the fpga
uint32_t AD7689_Reg = 0x0;
@ -81,9 +103,11 @@ uint32_t AD7689_ClkMask = 0x0;
uint32_t AD7689_DigMask = 0x0;
int AD7689_DigOffset = 0x0;
void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst) {
LOG(logDEBUG, ("AD7689: reg:0x%x roreg:0x%x cmsk:0x%x clkmsk:0x%x dmsk:0x%x dofst:%d\n",
reg, roreg, cmsk, clkmsk, dmsk, dofst));
void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk,
uint32_t clkmsk, uint32_t dmsk, int dofst) {
LOG(logDEBUG, ("AD7689: reg:0x%x roreg:0x%x cmsk:0x%x clkmsk:0x%x "
"dmsk:0x%x dofst:%d\n",
reg, roreg, cmsk, clkmsk, dmsk, dofst));
AD7689_Reg = reg;
AD7689_ROReg = roreg;
AD7689_CnvMask = cmsk;
@ -93,48 +117,49 @@ void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk, uint32_t clk
}
void AD7689_Disable() {
bus_w(AD7689_Reg, (bus_r(AD7689_Reg)
&~(AD7689_CnvMask)
&~AD7689_ClkMask
&~(AD7689_DigMask)));
bus_w(AD7689_Reg, (bus_r(AD7689_Reg) & ~(AD7689_CnvMask) & ~AD7689_ClkMask &
~(AD7689_DigMask)));
}
void AD7689_Set(uint32_t codata) {
LOG(logINFO, ("\tSetting ADC SPI Register. Writing 0x%08x to Config Reg\n", codata));
LOG(logINFO,
("\tSetting ADC SPI Register. Writing 0x%08x to Config Reg\n", codata));
serializeToSPI(AD7689_Reg, codata, AD7689_CnvMask, AD7689_ADC_CFG_NUMBITS,
AD7689_ClkMask, AD7689_DigMask, AD7689_DigOffset, 1);
AD7689_ClkMask, AD7689_DigMask, AD7689_DigOffset, 1);
}
uint16_t AD7689_Get() {
LOG(logINFO, ("\tGetting ADC SPI Register.\n"));
return (uint16_t)serializeFromSPI(AD7689_Reg, AD7689_CnvMask, AD7689_ADC_DATA_NUMBITS,
AD7689_ClkMask, AD7689_DigMask, AD7689_ROReg, 1);
return (uint16_t)serializeFromSPI(AD7689_Reg, AD7689_CnvMask,
AD7689_ADC_DATA_NUMBITS, AD7689_ClkMask,
AD7689_DigMask, AD7689_ROReg, 1);
}
int AD7689_GetTemperature() {
AD7689_Set(
// read back
AD7689_CFG_RB_MSK |
// disable sequencer (different from config)
AD7689_CFG_SEQ_DSBLE_VAL |
// Internal reference. REF = 2.5V buffered output. Temperature sensor enabled.
AD7689_CFG_REF_INT_2500MV_VAL |
// full bandwidth of low pass filter
AD7689_CFG_BW_FULL_VAL |
// all channel (different from config)
AD7689_CFG_IN_MSK |
// temperature sensor (different from config)
AD7689_CFG_INCC_TMP_VAL |
// overwrite configuration
AD7689_CFG_CFG_OVRWRTE_VAL);
// read back
AD7689_CFG_RB_MSK |
// disable sequencer (different from config)
AD7689_CFG_SEQ_DSBLE_VAL |
// Internal reference. REF = 2.5V buffered output. Temperature sensor
// enabled.
AD7689_CFG_REF_INT_2500MV_VAL |
// full bandwidth of low pass filter
AD7689_CFG_BW_FULL_VAL |
// all channel (different from config)
AD7689_CFG_IN_MSK |
// temperature sensor (different from config)
AD7689_CFG_INCC_TMP_VAL |
// overwrite configuration
AD7689_CFG_CFG_OVRWRTE_VAL);
int regval = AD7689_Get();
// value in mV FIXME: page 17? reference voltage temperature coefficient or t do with -40 to 85 °C
// value in mV FIXME: page 17? reference voltage temperature coefficient or
// t do with -40 to 85 °C
int retval = 0;
ConvertToDifferentRange(0, AD7689_INT_MAX_STEPS,
AD7689_INT_REF_MIN_MV, AD7689_INT_REF_MAX_MV,
regval, &retval);
ConvertToDifferentRange(0, AD7689_INT_MAX_STEPS, AD7689_INT_REF_MIN_MV,
AD7689_INT_REF_MAX_MV, regval, &retval);
LOG(logDEBUG1, ("voltage read for temp: %d mV\n", retval));
// value in °C
@ -142,52 +167,58 @@ int AD7689_GetTemperature() {
LOG(logINFO, ("\ttemp read : %f °C (%d unit)\n", tempValue, regval));
return tempValue;
}
int AD7689_GetChannel(int ichan) {
// filter channels val
if (ichan < 0 || ichan >= AD7689_NUM_CHANNELS) {
LOG(logERROR, ("Cannot get slow adc channel. "
"%d out of bounds (0 to %d)\n", ichan, AD7689_NUM_CHANNELS - 1));
return -1;
LOG(logERROR, ("Cannot get slow adc channel. "
"%d out of bounds (0 to %d)\n",
ichan, AD7689_NUM_CHANNELS - 1));
return -1;
}
AD7689_Set(
// read back
AD7689_CFG_RB_MSK |
// disable sequencer (different from config)
AD7689_CFG_SEQ_DSBLE_VAL |
// Internal reference. REF = 2.5V buffered output. Temperature sensor enabled.
AD7689_CFG_REF_INT_2500MV_VAL |
// full bandwidth of low pass filter
AD7689_CFG_BW_FULL_VAL |
// specific channel (different from config)
((ichan << AD7689_CFG_IN_OFST) & AD7689_CFG_IN_MSK) |
// input channel configuration (unipolar. inx to gnd)
AD7689_CFG_INCC_UNPLR_IN_GND_VAL |
// overwrite configuration
AD7689_CFG_CFG_OVRWRTE_VAL);
// read back
AD7689_CFG_RB_MSK |
// disable sequencer (different from config)
AD7689_CFG_SEQ_DSBLE_VAL |
// Internal reference. REF = 2.5V buffered output. Temperature sensor
// enabled.
AD7689_CFG_REF_INT_2500MV_VAL |
// full bandwidth of low pass filter
AD7689_CFG_BW_FULL_VAL |
// specific channel (different from config)
((ichan << AD7689_CFG_IN_OFST) & AD7689_CFG_IN_MSK) |
// input channel configuration (unipolar. inx to gnd)
AD7689_CFG_INCC_UNPLR_IN_GND_VAL |
// overwrite configuration
AD7689_CFG_CFG_OVRWRTE_VAL);
int regval = AD7689_Get();
// value in uV
int retval = ((double)(regval - 0) * (double)(AD7689_INT_REF_MAX_UV - AD7689_INT_REF_MIN_UV))
/ (double)(AD7689_INT_MAX_STEPS - 0) + AD7689_INT_REF_MIN_UV;
int retval = ((double)(regval - 0) *
(double)(AD7689_INT_REF_MAX_UV - AD7689_INT_REF_MIN_UV)) /
(double)(AD7689_INT_MAX_STEPS - 0) +
AD7689_INT_REF_MIN_UV;
/*ConvertToDifferentRange(0, AD7689_INT_MAX_STEPS,
AD7689_INT_REF_MIN_MV, AD7689_INT_REF_MAX_MV,
regval, &retval);*/
LOG(logINFO, ("\tvoltage read for chan %d: %d uV (regVal: %d)\n", ichan, retval, regval));
return retval;
LOG(logINFO, ("\tvoltage read for chan %d: %d uV (regVal: %d)\n", ichan,
retval, regval));
return retval;
}
void AD7689_Configure(){
void AD7689_Configure() {
LOG(logINFOBLUE, ("Configuring AD7689 (Slow ADCs): \n"));
// from power up, 3 invalid conversions
LOG(logINFO, ("\tConfiguring %d x due to invalid conversions from power up\n", AD7689_NUM_INVALID_CONVERSIONS));
LOG(logINFO,
("\tConfiguring %d x due to invalid conversions from power up\n",
AD7689_NUM_INVALID_CONVERSIONS));
int i = 0;
for (i = 0; i < AD7689_NUM_INVALID_CONVERSIONS; ++i) {
AD7689_Set(
@ -195,7 +226,8 @@ void AD7689_Configure(){
AD7689_CFG_RB_MSK |
// scan sequence IN0-IN7 then temperature sensor
AD7689_CFG_SEQ_SCN_WTH_TMP_VAL |
// Internal reference. REF = 2.5V buffered output. Temperature sensor enabled.
// Internal reference. REF = 2.5V buffered output. Temperature
// sensor enabled.
AD7689_CFG_REF_INT_2500MV_VAL |
// full bandwidth of low pass filter
AD7689_CFG_BW_FULL_VAL |

218
slsDetectorServers/slsDetectorServer/src/AD9252.c Executable file → Normal file
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@ -1,102 +1,134 @@
#include "AD9252.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "blackfin.h"
#include "clogger.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
/* AD9252 ADC DEFINES */
#define AD9252_ADC_NUMBITS (24)
#define AD9252_ADC_NUMBITS (24)
// default value is 0xF
#define AD9252_DEV_IND_2_REG (0x04)
#define AD9252_CHAN_H_OFST (0)
#define AD9252_CHAN_H_MSK (0x00000001 << AD9252_CHAN_H_OFST)
#define AD9252_CHAN_G_OFST (1)
#define AD9252_CHAN_G_MSK (0x00000001 << AD9252_CHAN_G_OFST)
#define AD9252_CHAN_F_OFST (2)
#define AD9252_CHAN_F_MSK (0x00000001 << AD9252_CHAN_F_OFST)
#define AD9252_CHAN_E_OFST (3)
#define AD9252_CHAN_E_MSK (0x00000001 << AD9252_CHAN_E_OFST)
#define AD9252_DEV_IND_2_REG (0x04)
#define AD9252_CHAN_H_OFST (0)
#define AD9252_CHAN_H_MSK (0x00000001 << AD9252_CHAN_H_OFST)
#define AD9252_CHAN_G_OFST (1)
#define AD9252_CHAN_G_MSK (0x00000001 << AD9252_CHAN_G_OFST)
#define AD9252_CHAN_F_OFST (2)
#define AD9252_CHAN_F_MSK (0x00000001 << AD9252_CHAN_F_OFST)
#define AD9252_CHAN_E_OFST (3)
#define AD9252_CHAN_E_MSK (0x00000001 << AD9252_CHAN_E_OFST)
// default value is 0x0F
#define AD9252_DEV_IND_1_REG (0x05)
#define AD9252_CHAN_D_OFST (0)
#define AD9252_CHAN_D_MSK (0x00000001 << AD9252_CHAN_D_OFST)
#define AD9252_CHAN_C_OFST (1)
#define AD9252_CHAN_C_MSK (0x00000001 << AD9252_CHAN_C_OFST)
#define AD9252_CHAN_B_OFST (2)
#define AD9252_CHAN_B_MSK (0x00000001 << AD9252_CHAN_B_OFST)
#define AD9252_CHAN_A_OFST (3)
#define AD9252_CHAN_A_MSK (0x00000001 << AD9252_CHAN_A_OFST)
#define AD9252_CLK_CH_DCO_OFST (4)
#define AD9252_CLK_CH_DCO_MSK (0x00000001 << AD9252_CLK_CH_DCO_OFST)
#define AD9252_CLK_CH_IFCO_OFST (5)
#define AD9252_CLK_CH_IFCO_MSK (0x00000001 << AD9252_CLK_CH_IFCO_OFST)
#define AD9252_DEV_IND_1_REG (0x05)
#define AD9252_CHAN_D_OFST (0)
#define AD9252_CHAN_D_MSK (0x00000001 << AD9252_CHAN_D_OFST)
#define AD9252_CHAN_C_OFST (1)
#define AD9252_CHAN_C_MSK (0x00000001 << AD9252_CHAN_C_OFST)
#define AD9252_CHAN_B_OFST (2)
#define AD9252_CHAN_B_MSK (0x00000001 << AD9252_CHAN_B_OFST)
#define AD9252_CHAN_A_OFST (3)
#define AD9252_CHAN_A_MSK (0x00000001 << AD9252_CHAN_A_OFST)
#define AD9252_CLK_CH_DCO_OFST (4)
#define AD9252_CLK_CH_DCO_MSK (0x00000001 << AD9252_CLK_CH_DCO_OFST)
#define AD9252_CLK_CH_IFCO_OFST (5)
#define AD9252_CLK_CH_IFCO_MSK (0x00000001 << AD9252_CLK_CH_IFCO_OFST)
// default value is 0x00
#define AD9252_POWER_MODE_REG (0x08)
#define AD9252_POWER_INTERNAL_OFST (0)
#define AD9252_POWER_INTERNAL_MSK (0x00000007 << AD9252_POWER_INTERNAL_OFST)
#define AD9252_INT_CHIP_RUN_VAL ((0x0 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_FULL_PWR_DWN_VAL ((0x1 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_STANDBY_VAL ((0x2 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_RESET_VAL ((0x3 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_POWER_MODE_REG (0x08)
#define AD9252_POWER_INTERNAL_OFST (0)
#define AD9252_POWER_INTERNAL_MSK (0x00000007 << AD9252_POWER_INTERNAL_OFST)
#define AD9252_INT_CHIP_RUN_VAL \
((0x0 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_FULL_PWR_DWN_VAL \
((0x1 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_STANDBY_VAL \
((0x2 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_RESET_VAL \
((0x3 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
// default value is 0x0
#define AD9252_TEST_MODE_REG (0x0D)
#define AD9252_OUT_TEST_OFST (0)
#define AD9252_OUT_TEST_MSK (0x0000000F << AD9252_OUT_TEST_OFST)
#define AD9252_TST_OFF_VAL ((0x0 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_MDSCL_SHRT_VAL ((0x1 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PSTV_FS_VAL ((0x2 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_NGTV_FS_VAL ((0x3 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_ALTRNTNG_CHKRBRD_VAL ((0x4 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PN_23_SQNC_VAL ((0x5 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PN_9_SQNC__VAL ((0x6 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_0_WRD_TGGL_VAL ((0x7 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_USR_INPT_VAL ((0x8 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_0_BT_TGGL_VAL ((0x9 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_x_SYNC_VAL ((0xa << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_BIT_HGH_VAL ((0xb << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_MXD_BT_FRQ_VAL ((0xc << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TEST_MODE_REG (0x0D)
#define AD9252_OUT_TEST_OFST (0)
#define AD9252_OUT_TEST_MSK (0x0000000F << AD9252_OUT_TEST_OFST)
#define AD9252_TST_OFF_VAL ((0x0 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_MDSCL_SHRT_VAL \
((0x1 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PSTV_FS_VAL \
((0x2 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_NGTV_FS_VAL \
((0x3 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_ALTRNTNG_CHKRBRD_VAL \
((0x4 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PN_23_SQNC_VAL \
((0x5 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PN_9_SQNC__VAL \
((0x6 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_0_WRD_TGGL_VAL \
((0x7 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_USR_INPT_VAL \
((0x8 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_0_BT_TGGL_VAL \
((0x9 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_x_SYNC_VAL \
((0xa << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_BIT_HGH_VAL \
((0xb << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_MXD_BT_FRQ_VAL \
((0xc << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_RST_SHRT_GN_OFST (4)
#define AD9252_TST_RST_SHRT_GN_MSK (0x00000001 << AD9252_TST_RST_SHRT_GN_OFST)
#define AD9252_TST_RST_LNG_GN_OFST (5)
#define AD9252_TST_RST_LNG_GN_MSK (0x00000001 << AD9252_TST_RST_LNG_GN_OFST)
#define AD9252_USER_IN_MODE_OFST (6)
#define AD9252_USER_IN_MODE_MSK (0x00000003 << AD9252_USER_IN_MODE_OFST)
#define AD9252_USR_IN_SNGL_VAL ((0x0 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_ALTRNT_VAL ((0x1 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_SNGL_ONC_VAL ((0x2 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_ALTRNT_ONC_VAL ((0x3 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_SNGL_VAL \
((0x0 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_ALTRNT_VAL \
((0x1 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_SNGL_ONC_VAL \
((0x2 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_ALTRNT_ONC_VAL \
((0x3 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
// default value is 0x00
#define AD9252_OUT_MODE_REG (0x14)
#define AD9252_OUT_FORMAT_OFST (0)
#define AD9252_OUT_FORMAT_MSK (0x00000003 << AD9252_OUT_FORMAT_OFST)
#define AD9252_OUT_BINARY_OFST_VAL ((0x0 << AD9252_OUT_FORMAT_OFST) & AD9252_OUT_FORMAT_MSK)
#define AD9252_OUT_TWOS_COMPL_VAL ((0x1 << AD9252_OUT_FORMAT_OFST) & AD9252_OUT_FORMAT_MSK)
#define AD9252_OUT_OTPT_INVRT_OFST (2)
#define AD9252_OUT_OTPT_INVRT_MSK (0x00000001 << AD9252_OUT_OTPT_INVRT_OFST)
#define AD9252_OUT_LVDS_OPT_OFST (6)
#define AD9252_OUT_LVDS_OPT_MSK (0x00000001 << AD9252_OUT_LVDS_OPT_OFST)
#define AD9252_OUT_LVDS_ANSI_VAL ((0x0 << AD9252_OUT_LVDS_OPT_OFST) & AD9252_OUT_LVDS_OPT_MSK)
#define AD9252_OUT_LVDS_IEEE_VAL ((0x1 << AD9252_OUT_LVDS_OPT_OFST) & AD9252_OUT_LVDS_OPT_MSK)
#define AD9252_OUT_MODE_REG (0x14)
#define AD9252_OUT_FORMAT_OFST (0)
#define AD9252_OUT_FORMAT_MSK (0x00000003 << AD9252_OUT_FORMAT_OFST)
#define AD9252_OUT_BINARY_OFST_VAL \
((0x0 << AD9252_OUT_FORMAT_OFST) & AD9252_OUT_FORMAT_MSK)
#define AD9252_OUT_TWOS_COMPL_VAL \
((0x1 << AD9252_OUT_FORMAT_OFST) & AD9252_OUT_FORMAT_MSK)
#define AD9252_OUT_OTPT_INVRT_OFST (2)
#define AD9252_OUT_OTPT_INVRT_MSK (0x00000001 << AD9252_OUT_OTPT_INVRT_OFST)
#define AD9252_OUT_LVDS_OPT_OFST (6)
#define AD9252_OUT_LVDS_OPT_MSK (0x00000001 << AD9252_OUT_LVDS_OPT_OFST)
#define AD9252_OUT_LVDS_ANSI_VAL \
((0x0 << AD9252_OUT_LVDS_OPT_OFST) & AD9252_OUT_LVDS_OPT_MSK)
#define AD9252_OUT_LVDS_IEEE_VAL \
((0x1 << AD9252_OUT_LVDS_OPT_OFST) & AD9252_OUT_LVDS_OPT_MSK)
// default value is 0x3
#define AD9252_OUT_PHASE_REG (0x16)
#define AD9252_OUT_CLK_OFST (0)
#define AD9252_OUT_CLK_MSK (0x0000000F << AD9252_OUT_CLK_OFST)
#define AD9252_OUT_CLK_0_VAL ((0x0 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_60_VAL ((0x1 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_120_VAL ((0x2 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_180_VAL ((0x3 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_300_VAL ((0x5 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_360_VAL ((0x6 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_480_VAL ((0x8 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_540_VAL ((0x9 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_600_VAL ((0xa << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_660_VAL ((0xb << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK) // 0xb - 0xf is 660
#define AD9252_OUT_PHASE_REG (0x16)
#define AD9252_OUT_CLK_OFST (0)
#define AD9252_OUT_CLK_MSK (0x0000000F << AD9252_OUT_CLK_OFST)
#define AD9252_OUT_CLK_0_VAL ((0x0 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_60_VAL \
((0x1 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_120_VAL \
((0x2 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_180_VAL \
((0x3 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_300_VAL \
((0x5 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_360_VAL \
((0x6 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_480_VAL \
((0x8 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_540_VAL \
((0x9 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_600_VAL \
((0xa << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_660_VAL \
((0xb << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK) // 0xb - 0xf is 660
// defines from the fpga
uint32_t AD9252_Reg = 0x0;
@ -105,7 +137,8 @@ uint32_t AD9252_ClkMask = 0x0;
uint32_t AD9252_DigMask = 0x0;
int AD9252_DigOffset = 0x0;
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst) {
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst) {
AD9252_Reg = reg;
AD9252_CsMask = cmsk;
AD9252_ClkMask = clkmsk;
@ -114,29 +147,28 @@ void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dm
}
void AD9252_Disable() {
bus_w(AD9252_Reg, (bus_r(AD9252_Reg)
| AD9252_CsMask
| AD9252_ClkMask)
&~(AD9252_DigMask));
bus_w(AD9252_Reg, (bus_r(AD9252_Reg) | AD9252_CsMask | AD9252_ClkMask) &
~(AD9252_DigMask));
}
void AD9252_Set(int addr, int val) {
u_int32_t codata;
codata = val + (addr << 8);
LOG(logINFO, ("\tSetting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr));
LOG(logINFO,
("\tSetting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr));
serializeToSPI(AD9252_Reg, codata, AD9252_CsMask, AD9252_ADC_NUMBITS,
AD9252_ClkMask, AD9252_DigMask, AD9252_DigOffset, 0);
AD9252_ClkMask, AD9252_DigMask, AD9252_DigOffset, 0);
}
void AD9252_Configure(){
void AD9252_Configure() {
LOG(logINFOBLUE, ("Configuring ADC9252:\n"));
//power mode reset
// power mode reset
LOG(logINFO, ("\tPower mode reset\n"));
AD9252_Set(AD9252_POWER_MODE_REG, AD9252_INT_RESET_VAL);
//power mode chip run
// power mode chip run
LOG(logINFO, ("\tPower mode chip run\n"));
AD9252_Set(AD9252_POWER_MODE_REG, AD9252_INT_CHIP_RUN_VAL);
@ -144,7 +176,7 @@ void AD9252_Configure(){
LOG(logINFO, ("\tBinary offset\n"));
AD9252_Set(AD9252_OUT_MODE_REG, AD9252_OUT_BINARY_OFST_VAL);
//output clock phase
// output clock phase
#ifdef GOTTHARDD
LOG(logINFO, ("\tOutput clock phase is at default: 180\n"));
#else
@ -158,11 +190,12 @@ void AD9252_Configure(){
// all devices on chip to receive next command
LOG(logINFO, ("\tAll devices on chip to receive next command\n"));
AD9252_Set(AD9252_DEV_IND_2_REG,
AD9252_CHAN_H_MSK | AD9252_CHAN_G_MSK | AD9252_CHAN_F_MSK | AD9252_CHAN_E_MSK);
AD9252_Set(AD9252_DEV_IND_1_REG,
AD9252_CHAN_D_MSK | AD9252_CHAN_C_MSK | AD9252_CHAN_B_MSK | AD9252_CHAN_A_MSK |
AD9252_CLK_CH_DCO_MSK | AD9252_CLK_CH_IFCO_MSK);
AD9252_Set(AD9252_DEV_IND_2_REG, AD9252_CHAN_H_MSK | AD9252_CHAN_G_MSK |
AD9252_CHAN_F_MSK | AD9252_CHAN_E_MSK);
AD9252_Set(AD9252_DEV_IND_1_REG, AD9252_CHAN_D_MSK | AD9252_CHAN_C_MSK |
AD9252_CHAN_B_MSK | AD9252_CHAN_A_MSK |
AD9252_CLK_CH_DCO_MSK |
AD9252_CLK_CH_IFCO_MSK);
// no test mode
LOG(logINFO, ("\tNo test mode\n"));
@ -175,4 +208,3 @@ void AD9252_Configure(){
AD9252_Set(AD9252_TEST_MODE_REG, AD9252_TST_MXD_BT_FRQ_VAL);
#endif
}

439
slsDetectorServers/slsDetectorServer/src/AD9257.c Executable file → Normal file
View File

@ -1,129 +1,166 @@
#include "AD9257.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "blackfin.h"
#include "clogger.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "sls_detector_defs.h"
/* AD9257 ADC DEFINES */
#define AD9257_ADC_NUMBITS (24)
#define AD9257_ADC_NUMBITS (24)
// default value is 0xF
#define AD9257_DEV_IND_2_REG (0x04)
#define AD9257_CHAN_H_OFST (0)
#define AD9257_CHAN_H_MSK (0x00000001 << AD9257_CHAN_H_OFST)
#define AD9257_CHAN_G_OFST (1)
#define AD9257_CHAN_G_MSK (0x00000001 << AD9257_CHAN_G_OFST)
#define AD9257_CHAN_F_OFST (2)
#define AD9257_CHAN_F_MSK (0x00000001 << AD9257_CHAN_F_OFST)
#define AD9257_CHAN_E_OFST (3)
#define AD9257_CHAN_E_MSK (0x00000001 << AD9257_CHAN_E_OFST)
#define AD9257_DEV_IND_2_REG (0x04)
#define AD9257_CHAN_H_OFST (0)
#define AD9257_CHAN_H_MSK (0x00000001 << AD9257_CHAN_H_OFST)
#define AD9257_CHAN_G_OFST (1)
#define AD9257_CHAN_G_MSK (0x00000001 << AD9257_CHAN_G_OFST)
#define AD9257_CHAN_F_OFST (2)
#define AD9257_CHAN_F_MSK (0x00000001 << AD9257_CHAN_F_OFST)
#define AD9257_CHAN_E_OFST (3)
#define AD9257_CHAN_E_MSK (0x00000001 << AD9257_CHAN_E_OFST)
// default value is 0x3F
#define AD9257_DEV_IND_1_REG (0x05)
#define AD9257_CHAN_D_OFST (0)
#define AD9257_CHAN_D_MSK (0x00000001 << AD9257_CHAN_D_OFST)
#define AD9257_CHAN_C_OFST (1)
#define AD9257_CHAN_C_MSK (0x00000001 << AD9257_CHAN_C_OFST)
#define AD9257_CHAN_B_OFST (2)
#define AD9257_CHAN_B_MSK (0x00000001 << AD9257_CHAN_B_OFST)
#define AD9257_CHAN_A_OFST (3)
#define AD9257_CHAN_A_MSK (0x00000001 << AD9257_CHAN_A_OFST)
#define AD9257_CLK_CH_DCO_OFST (4)
#define AD9257_CLK_CH_DCO_MSK (0x00000001 << AD9257_CLK_CH_DCO_OFST)
#define AD9257_CLK_CH_IFCO_OFST (5)
#define AD9257_CLK_CH_IFCO_MSK (0x00000001 << AD9257_CLK_CH_IFCO_OFST)
#define AD9257_DEV_IND_1_REG (0x05)
#define AD9257_CHAN_D_OFST (0)
#define AD9257_CHAN_D_MSK (0x00000001 << AD9257_CHAN_D_OFST)
#define AD9257_CHAN_C_OFST (1)
#define AD9257_CHAN_C_MSK (0x00000001 << AD9257_CHAN_C_OFST)
#define AD9257_CHAN_B_OFST (2)
#define AD9257_CHAN_B_MSK (0x00000001 << AD9257_CHAN_B_OFST)
#define AD9257_CHAN_A_OFST (3)
#define AD9257_CHAN_A_MSK (0x00000001 << AD9257_CHAN_A_OFST)
#define AD9257_CLK_CH_DCO_OFST (4)
#define AD9257_CLK_CH_DCO_MSK (0x00000001 << AD9257_CLK_CH_DCO_OFST)
#define AD9257_CLK_CH_IFCO_OFST (5)
#define AD9257_CLK_CH_IFCO_MSK (0x00000001 << AD9257_CLK_CH_IFCO_OFST)
// default value is 0x00
#define AD9257_POWER_MODE_REG (0x08)
#define AD9257_POWER_INTERNAL_OFST (0)
#define AD9257_POWER_INTERNAL_MSK (0x00000003 << AD9257_POWER_INTERNAL_OFST)
#define AD9257_INT_CHIP_RUN_VAL ((0x0 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_FULL_PWR_DWN_VAL ((0x1 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_STANDBY_VAL ((0x2 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_RESET_VAL ((0x3 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_POWER_EXTERNAL_OFST (5)
#define AD9257_POWER_EXTERNAL_MSK (0x00000001 << AD9257_POWER_EXTERNAL_OFST)
#define AD9257_EXT_FULL_POWER_VAL ((0x0 << AD9257_POWER_EXTERNAL_OFST) & AD9257_POWER_EXTERNAL_MSK)
#define AD9257_EXT_STANDBY_VAL ((0x1 << AD9257_POWER_EXTERNAL_OFST) & AD9257_POWER_EXTERNAL_MSK)
#define AD9257_POWER_MODE_REG (0x08)
#define AD9257_POWER_INTERNAL_OFST (0)
#define AD9257_POWER_INTERNAL_MSK (0x00000003 << AD9257_POWER_INTERNAL_OFST)
#define AD9257_INT_CHIP_RUN_VAL \
((0x0 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_FULL_PWR_DWN_VAL \
((0x1 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_STANDBY_VAL \
((0x2 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_INT_RESET_VAL \
((0x3 << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK)
#define AD9257_POWER_EXTERNAL_OFST (5)
#define AD9257_POWER_EXTERNAL_MSK (0x00000001 << AD9257_POWER_EXTERNAL_OFST)
#define AD9257_EXT_FULL_POWER_VAL \
((0x0 << AD9257_POWER_EXTERNAL_OFST) & AD9257_POWER_EXTERNAL_MSK)
#define AD9257_EXT_STANDBY_VAL \
((0x1 << AD9257_POWER_EXTERNAL_OFST) & AD9257_POWER_EXTERNAL_MSK)
// default value is 0x0
#define AD9257_TEST_MODE_REG (0x0D)
#define AD9257_OUT_TEST_OFST (0)
#define AD9257_OUT_TEST_MSK (0x0000000F << AD9257_OUT_TEST_OFST)
#define AD9257_TST_OFF_VAL ((0x0 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_MDSCL_SHRT_VAL ((0x1 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_PSTV_FS_VAL ((0x2 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_NGTV_FS_VAL ((0x3 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_ALTRNTNG_CHKRBRD_VAL ((0x4 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_PN_23_SQNC_VAL ((0x5 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_PN_9_SQNC__VAL ((0x6 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_0_WRD_TGGL_VAL ((0x7 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_USR_INPT_VAL ((0x8 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_0_BT_TGGL_VAL ((0x9 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_x_SYNC_VAL ((0xa << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_BIT_HGH_VAL ((0xb << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_MXD_BT_FRQ_VAL ((0xc << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TEST_MODE_REG (0x0D)
#define AD9257_OUT_TEST_OFST (0)
#define AD9257_OUT_TEST_MSK (0x0000000F << AD9257_OUT_TEST_OFST)
#define AD9257_TST_OFF_VAL ((0x0 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_MDSCL_SHRT_VAL \
((0x1 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_PSTV_FS_VAL \
((0x2 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_NGTV_FS_VAL \
((0x3 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_ALTRNTNG_CHKRBRD_VAL \
((0x4 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_PN_23_SQNC_VAL \
((0x5 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_PN_9_SQNC__VAL \
((0x6 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_0_WRD_TGGL_VAL \
((0x7 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_USR_INPT_VAL \
((0x8 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_0_BT_TGGL_VAL \
((0x9 << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_x_SYNC_VAL \
((0xa << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_1_BIT_HGH_VAL \
((0xb << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_MXD_BT_FRQ_VAL \
((0xc << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK)
#define AD9257_TST_RST_SHRT_GN_OFST (4)
#define AD9257_TST_RST_SHRT_GN_MSK (0x00000001 << AD9257_TST_RST_SHRT_GN_OFST)
#define AD9257_TST_RST_LNG_GN_OFST (5)
#define AD9257_TST_RST_LNG_GN_MSK (0x00000001 << AD9257_TST_RST_LNG_GN_OFST)
#define AD9257_USER_IN_MODE_OFST (6)
#define AD9257_USER_IN_MODE_MSK (0x00000003 << AD9257_USER_IN_MODE_OFST)
#define AD9257_USR_IN_SNGL_VAL ((0x0 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_ALTRNT_VAL ((0x1 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_SNGL_ONC_VAL ((0x2 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_ALTRNT_ONC_VAL ((0x3 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_SNGL_VAL \
((0x0 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_ALTRNT_VAL \
((0x1 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_SNGL_ONC_VAL \
((0x2 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
#define AD9257_USR_IN_ALTRNT_ONC_VAL \
((0x3 << AD9257_USER_IN_MODE_OFST) & AD9257_USER_IN_MODE_MSK)
// default value is 0x01
#define AD9257_OUT_MODE_REG (0x14)
#define AD9257_OUT_FORMAT_OFST (0)
#define AD9257_OUT_FORMAT_MSK (0x00000001 << AD9257_OUT_FORMAT_OFST)
#define AD9257_OUT_BINARY_OFST_VAL ((0x0 << AD9257_OUT_FORMAT_OFST) & AD9257_OUT_FORMAT_MSK)
#define AD9257_OUT_TWOS_COMPL_VAL ((0x1 << AD9257_OUT_FORMAT_OFST) & AD9257_OUT_FORMAT_MSK)
#define AD9257_OUT_OTPT_INVRT_OFST (2)
#define AD9257_OUT_OTPT_INVRT_MSK (0x00000001 << AD9257_OUT_OTPT_INVRT_OFST)
#define AD9257_OUT_LVDS_OPT_OFST (6)
#define AD9257_OUT_LVDS_OPT_MSK (0x00000001 << AD9257_OUT_LVDS_OPT_OFST)
#define AD9257_OUT_LVDS_ANSI_VAL ((0x0 << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK)
#define AD9257_OUT_LVDS_IEEE_VAL ((0x1 << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK)
#define AD9257_OUT_MODE_REG (0x14)
#define AD9257_OUT_FORMAT_OFST (0)
#define AD9257_OUT_FORMAT_MSK (0x00000001 << AD9257_OUT_FORMAT_OFST)
#define AD9257_OUT_BINARY_OFST_VAL \
((0x0 << AD9257_OUT_FORMAT_OFST) & AD9257_OUT_FORMAT_MSK)
#define AD9257_OUT_TWOS_COMPL_VAL \
((0x1 << AD9257_OUT_FORMAT_OFST) & AD9257_OUT_FORMAT_MSK)
#define AD9257_OUT_OTPT_INVRT_OFST (2)
#define AD9257_OUT_OTPT_INVRT_MSK (0x00000001 << AD9257_OUT_OTPT_INVRT_OFST)
#define AD9257_OUT_LVDS_OPT_OFST (6)
#define AD9257_OUT_LVDS_OPT_MSK (0x00000001 << AD9257_OUT_LVDS_OPT_OFST)
#define AD9257_OUT_LVDS_ANSI_VAL \
((0x0 << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK)
#define AD9257_OUT_LVDS_IEEE_VAL \
((0x1 << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK)
// default value is 0x3
#define AD9257_OUT_PHASE_REG (0x16)
#define AD9257_OUT_CLK_OFST (0)
#define AD9257_OUT_CLK_MSK (0x0000000F << AD9257_OUT_CLK_OFST)
#define AD9257_OUT_CLK_0_VAL ((0x0 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_60_VAL ((0x1 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_120_VAL ((0x2 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_180_VAL ((0x3 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_240_VAL ((0x4 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_300_VAL ((0x5 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_360_VAL ((0x6 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_420_VAL ((0x7 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_480_VAL ((0x8 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_540_VAL ((0x9 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_600_VAL ((0xa << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_660_VAL ((0xb << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_IN_CLK_OFST (4)
#define AD9257_IN_CLK_MSK (0x00000007 << AD9257_IN_CLK_OFST)
#define AD9257_IN_CLK_0_VAL ((0x0 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_1_VAL ((0x1 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_2_VAL ((0x2 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_3_VAL ((0x3 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_4_VAL ((0x4 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_5_VAL ((0x5 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_6_VAL ((0x6 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_7_VAL ((0x7 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_OUT_PHASE_REG (0x16)
#define AD9257_OUT_CLK_OFST (0)
#define AD9257_OUT_CLK_MSK (0x0000000F << AD9257_OUT_CLK_OFST)
#define AD9257_OUT_CLK_0_VAL ((0x0 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_60_VAL \
((0x1 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_120_VAL \
((0x2 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_180_VAL \
((0x3 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_240_VAL \
((0x4 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_300_VAL \
((0x5 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_360_VAL \
((0x6 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_420_VAL \
((0x7 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_480_VAL \
((0x8 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_540_VAL \
((0x9 << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_600_VAL \
((0xa << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_OUT_CLK_660_VAL \
((0xb << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK)
#define AD9257_IN_CLK_OFST (4)
#define AD9257_IN_CLK_MSK (0x00000007 << AD9257_IN_CLK_OFST)
#define AD9257_IN_CLK_0_VAL ((0x0 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_1_VAL ((0x1 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_2_VAL ((0x2 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_3_VAL ((0x3 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_4_VAL ((0x4 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_5_VAL ((0x5 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_6_VAL ((0x6 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
#define AD9257_IN_CLK_7_VAL ((0x7 << AD9257_IN_CLK_OFST) & AD9257_IN_CLK_MSK)
// default value is 0x4
#define AD9257_VREF_REG (0x18)
#define AD9257_VREF_OFST (0)
#define AD9257_VREF_MSK (0x00000007 << AD9257_VREF_OFST)
#define AD9257_VREF_DEFAULT_VAL (AD9257_VREF_2_0_VAL)
#define AD9257_VREF_1_0_VAL ((0x0 << AD9257_VREF_OFST) & AD9257_VREF_MSK)
#define AD9257_VREF_1_14_VAL ((0x1 << AD9257_VREF_OFST) & AD9257_VREF_MSK)
#define AD9257_VREF_1_33_VAL ((0x2 << AD9257_VREF_OFST) & AD9257_VREF_MSK)
#define AD9257_VREF_1_6_VAL ((0x3 << AD9257_VREF_OFST) & AD9257_VREF_MSK)
#define AD9257_VREF_2_0_VAL ((0x4 << AD9257_VREF_OFST) & AD9257_VREF_MSK)
#define AD9257_VREF_REG (0x18)
#define AD9257_VREF_OFST (0)
#define AD9257_VREF_MSK (0x00000007 << AD9257_VREF_OFST)
#define AD9257_VREF_DEFAULT_VAL (AD9257_VREF_2_0_VAL)
#define AD9257_VREF_1_0_VAL ((0x0 << AD9257_VREF_OFST) & AD9257_VREF_MSK)
#define AD9257_VREF_1_14_VAL ((0x1 << AD9257_VREF_OFST) & AD9257_VREF_MSK)
#define AD9257_VREF_1_33_VAL ((0x2 << AD9257_VREF_OFST) & AD9257_VREF_MSK)
#define AD9257_VREF_1_6_VAL ((0x3 << AD9257_VREF_OFST) & AD9257_VREF_MSK)
#define AD9257_VREF_2_0_VAL ((0x4 << AD9257_VREF_OFST) & AD9257_VREF_MSK)
// defines from the fpga
uint32_t AD9257_Reg = 0x0;
@ -133,7 +170,8 @@ uint32_t AD9257_DigMask = 0x0;
int AD9257_DigOffset = 0x0;
int AD9257_VrefVoltage = 0;
void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst) {
void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst) {
AD9257_Reg = reg;
AD9257_CsMask = cmsk;
AD9257_ClkMask = clkmsk;
@ -142,137 +180,138 @@ void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dm
}
void AD9257_Disable() {
bus_w(AD9257_Reg, (bus_r(AD9257_Reg)
| AD9257_CsMask
| AD9257_ClkMask)
& ~(AD9257_DigMask));
bus_w(AD9257_Reg, (bus_r(AD9257_Reg) | AD9257_CsMask | AD9257_ClkMask) &
~(AD9257_DigMask));
}
int AD9257_GetVrefVoltage(int mV) {
if (mV == 0)
return AD9257_VrefVoltage;
switch(AD9257_VrefVoltage) {
case 0:
return 1000;
case 1:
return 1140;
case 2:
return 1330;
case 3:
return 1600;
case 4:
return 2000;
default:
LOG(logERROR, ("Could not convert Adc Vpp from mode to mV\n"));
return -1;
}
if (mV == 0)
return AD9257_VrefVoltage;
switch (AD9257_VrefVoltage) {
case 0:
return 1000;
case 1:
return 1140;
case 2:
return 1330;
case 3:
return 1600;
case 4:
return 2000;
default:
LOG(logERROR, ("Could not convert Adc Vpp from mode to mV\n"));
return -1;
}
}
int AD9257_SetVrefVoltage(int val, int mV) {
int mode = val;
// convert to mode
if (mV) {
switch(val) {
case 1000:
mode = 0;
break;
case 1140:
mode = 1;
break;
case 1330:
mode = 2;
break;
case 1600:
mode = 3;
break;
case 2000:
mode = 4;
break;
// validation for mV
default:
LOG(logERROR, ("mv:%d doesnt exist\n", val));
return FAIL;
}
}
int mode = val;
// convert to mode
if (mV) {
switch (val) {
case 1000:
mode = 0;
break;
case 1140:
mode = 1;
break;
case 1330:
mode = 2;
break;
case 1600:
mode = 3;
break;
case 2000:
mode = 4;
break;
// validation for mV
default:
LOG(logERROR, ("mv:%d doesnt exist\n", val));
return FAIL;
}
}
// validation for mode
switch(mode) {
case 0:
LOG(logINFO, ("Setting ADC Vref to 1.0 V (Mode:%d)\n", mode));
break;
case 1:
LOG(logINFO, ("Setting ADC Vref to 1.14 V (Mode:%d)\n", mode));
break;
case 2:
LOG(logINFO, ("Setting ADC Vref to 1.33 V (Mode:%d)\n", mode));
break;
case 3:
LOG(logINFO, ("Setting ADC Vref to 1.6 V (Mode:%d)\n", mode));
break;
case 4:
LOG(logINFO, ("Setting ADC Vref to 2.0 V (Mode:%d)\n", mode));
break;
default:
return FAIL;
}
// set vref voltage
// validation for mode
switch (mode) {
case 0:
LOG(logINFO, ("Setting ADC Vref to 1.0 V (Mode:%d)\n", mode));
break;
case 1:
LOG(logINFO, ("Setting ADC Vref to 1.14 V (Mode:%d)\n", mode));
break;
case 2:
LOG(logINFO, ("Setting ADC Vref to 1.33 V (Mode:%d)\n", mode));
break;
case 3:
LOG(logINFO, ("Setting ADC Vref to 1.6 V (Mode:%d)\n", mode));
break;
case 4:
LOG(logINFO, ("Setting ADC Vref to 2.0 V (Mode:%d)\n", mode));
break;
default:
return FAIL;
}
// set vref voltage
AD9257_Set(AD9257_VREF_REG, mode);
AD9257_VrefVoltage = mode;
return OK;
AD9257_VrefVoltage = mode;
return OK;
}
void AD9257_Set(int addr, int val) {
u_int32_t codata;
codata = val + (addr << 8);
LOG(logINFO, ("\tSetting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr));
serializeToSPI(AD9257_Reg, codata, AD9257_CsMask, AD9257_ADC_NUMBITS,
AD9257_ClkMask, AD9257_DigMask, AD9257_DigOffset, 0);
u_int32_t codata;
codata = val + (addr << 8);
LOG(logINFO,
("\tSetting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr));
serializeToSPI(AD9257_Reg, codata, AD9257_CsMask, AD9257_ADC_NUMBITS,
AD9257_ClkMask, AD9257_DigMask, AD9257_DigOffset, 0);
}
void AD9257_Configure(){
void AD9257_Configure() {
LOG(logINFOBLUE, ("Configuring ADC9257:\n"));
//power mode reset
// power mode reset
LOG(logINFO, ("\tPower mode reset\n"));
AD9257_Set(AD9257_POWER_MODE_REG, AD9257_INT_RESET_VAL);
//power mode chip run
LOG(logINFO, ("\tPower mode chip run\n"));
AD9257_Set(AD9257_POWER_MODE_REG, AD9257_INT_CHIP_RUN_VAL);
// power mode chip run
LOG(logINFO, ("\tPower mode chip run\n"));
AD9257_Set(AD9257_POWER_MODE_REG, AD9257_INT_CHIP_RUN_VAL);
// binary offset, lvds-iee reduced
// binary offset, lvds-iee reduced
LOG(logINFO, ("\tBinary offset, Lvds-ieee reduced\n"));
AD9257_Set(AD9257_OUT_MODE_REG, AD9257_OUT_BINARY_OFST_VAL | AD9257_OUT_LVDS_IEEE_VAL);
AD9257_Set(AD9257_OUT_MODE_REG,
AD9257_OUT_BINARY_OFST_VAL | AD9257_OUT_LVDS_IEEE_VAL);
//output clock phase
// output clock phase
LOG(logINFO, ("\tOutput clock phase: 180\n"));
AD9257_Set(AD9257_OUT_PHASE_REG, AD9257_OUT_CLK_180_VAL);
AD9257_Set(AD9257_OUT_PHASE_REG, AD9257_OUT_CLK_180_VAL);
// all devices on chip to receive next command
LOG(logINFO, ("\tAll devices on chip to receive next command\n"));
AD9257_Set(AD9257_DEV_IND_2_REG,
AD9257_CHAN_H_MSK | AD9257_CHAN_G_MSK | AD9257_CHAN_F_MSK | AD9257_CHAN_E_MSK);
// all devices on chip to receive next command
LOG(logINFO, ("\tAll devices on chip to receive next command\n"));
AD9257_Set(AD9257_DEV_IND_2_REG, AD9257_CHAN_H_MSK | AD9257_CHAN_G_MSK |
AD9257_CHAN_F_MSK | AD9257_CHAN_E_MSK);
AD9257_Set(AD9257_DEV_IND_1_REG,
AD9257_CHAN_D_MSK | AD9257_CHAN_C_MSK | AD9257_CHAN_B_MSK | AD9257_CHAN_A_MSK |
AD9257_CLK_CH_DCO_MSK | AD9257_CLK_CH_IFCO_MSK);
AD9257_Set(AD9257_DEV_IND_1_REG, AD9257_CHAN_D_MSK | AD9257_CHAN_C_MSK |
AD9257_CHAN_B_MSK | AD9257_CHAN_A_MSK |
AD9257_CLK_CH_DCO_MSK |
AD9257_CLK_CH_IFCO_MSK);
// vref
// vref
#ifdef GOTTHARDD
LOG(logINFO, ("\tVref default at 2.0\n"));
AD9257_SetVrefVoltage(AD9257_VREF_DEFAULT_VAL, 0);
LOG(logINFO, ("\tVref default at 2.0\n"));
AD9257_SetVrefVoltage(AD9257_VREF_DEFAULT_VAL, 0);
#else
LOG(logINFO, ("\tVref 1.33\n"));
AD9257_SetVrefVoltage(AD9257_VREF_1_33_VAL, 0);
LOG(logINFO, ("\tVref 1.33\n"));
AD9257_SetVrefVoltage(AD9257_VREF_1_33_VAL, 0);
#endif
// no test mode
LOG(logINFO, ("\tNo test mode\n"));
AD9257_Set(AD9257_TEST_MODE_REG, AD9257_TST_OFF_VAL);
// no test mode
LOG(logINFO, ("\tNo test mode\n"));
AD9257_Set(AD9257_TEST_MODE_REG, AD9257_TST_OFF_VAL);
#ifdef TESTADC
LOG(logINFOBLUE, ("Putting ADC in Test Mode!\n");
LOG(logINFOBLUE, ("Putting ADC in Test Mode!\n");
// mixed bit frequency test mode
LOG(logINFO, ("\tMixed bit frequency test mode\n"));
AD9257_Set(AD9257_TEST_MODE_REG, AD9257_TST_MXD_BT_FRQ_VAL);

282
slsDetectorServers/slsDetectorServer/src/ALTERA_PLL.c Executable file → Normal file
View File

@ -1,78 +1,124 @@
#include "ALTERA_PLL.h"
#include "clogger.h"
#include "blackfin.h"
#include "clogger.h"
#include <unistd.h> // usleep
#include <unistd.h> // usleep
/* Altera PLL DEFINES */
/** PLL Reconfiguration Registers */
//https://www.altera.com/documentation/mcn1424769382940.html
#define ALTERA_PLL_MODE_REG (0x00)
// https://www.altera.com/documentation/mcn1424769382940.html
#define ALTERA_PLL_MODE_REG (0x00)
#define ALTERA_PLL_MODE_WT_RQUST_VAL (0)
#define ALTERA_PLL_MODE_PLLNG_MD_VAL (1)
#define ALTERA_PLL_MODE_WT_RQUST_VAL (0)
#define ALTERA_PLL_MODE_PLLNG_MD_VAL (1)
#define ALTERA_PLL_STATUS_REG (0x01)
#define ALTERA_PLL_START_REG (0x02)
#define ALTERA_PLL_N_COUNTER_REG (0x03)
#define ALTERA_PLL_M_COUNTER_REG (0x04)
#define ALTERA_PLL_C_COUNTER_REG (0x05)
#define ALTERA_PLL_STATUS_REG (0x01)
#define ALTERA_PLL_START_REG (0x02)
#define ALTERA_PLL_N_COUNTER_REG (0x03)
#define ALTERA_PLL_M_COUNTER_REG (0x04)
#define ALTERA_PLL_C_COUNTER_REG (0x05)
#define ALTERA_PLL_C_COUNTER_LW_CNT_OFST (0)
#define ALTERA_PLL_C_COUNTER_LW_CNT_MSK (0x000000FF << ALTERA_PLL_C_COUNTER_LW_CNT_OFST)
#define ALTERA_PLL_C_COUNTER_HGH_CNT_OFST (8)
#define ALTERA_PLL_C_COUNTER_HGH_CNT_MSK (0x000000FF << ALTERA_PLL_C_COUNTER_HGH_CNT_OFST)
#define ALTERA_PLL_C_COUNTER_LW_CNT_OFST (0)
#define ALTERA_PLL_C_COUNTER_LW_CNT_MSK \
(0x000000FF << ALTERA_PLL_C_COUNTER_LW_CNT_OFST)
#define ALTERA_PLL_C_COUNTER_HGH_CNT_OFST (8)
#define ALTERA_PLL_C_COUNTER_HGH_CNT_MSK \
(0x000000FF << ALTERA_PLL_C_COUNTER_HGH_CNT_OFST)
/* total_div = lw_cnt + hgh_cnt */
#define ALTERA_PLL_C_COUNTER_BYPSS_ENBL_OFST (16)
#define ALTERA_PLL_C_COUNTER_BYPSS_ENBL_MSK (0x00000001 << ALTERA_PLL_C_COUNTER_BYPSS_ENBL_OFST)
/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is bypassed) */
#define ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST (17)
#define ALTERA_PLL_C_COUNTER_ODD_DVSN_MSK (0x00000001 << ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST)
/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle = (hgh_cnt - 0.5) / total_div */
#define ALTERA_PLL_C_COUNTER_SLCT_OFST (18)
#define ALTERA_PLL_C_COUNTER_SLCT_MSK (0x0000001F << ALTERA_PLL_C_COUNTER_SLCT_OFST)
#define ALTERA_PLL_C_COUNTER_BYPSS_ENBL_OFST (16)
#define ALTERA_PLL_C_COUNTER_BYPSS_ENBL_MSK \
(0x00000001 << ALTERA_PLL_C_COUNTER_BYPSS_ENBL_OFST)
/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is
* bypassed) */
#define ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST (17)
#define ALTERA_PLL_C_COUNTER_ODD_DVSN_MSK \
(0x00000001 << ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST)
/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle =
* (hgh_cnt - 0.5) / total_div */
#define ALTERA_PLL_C_COUNTER_SLCT_OFST (18)
#define ALTERA_PLL_C_COUNTER_SLCT_MSK \
(0x0000001F << ALTERA_PLL_C_COUNTER_SLCT_OFST)
#define ALTERA_PLL_PHASE_SHIFT_REG (0x06)
#define ALTERA_PLL_PHASE_SHIFT_REG (0x06)
#define ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST (0)
#define ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK (0x0000FFFF << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST)
#define ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST (0)
#define ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK \
(0x0000FFFF << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST)
#define ALTERA_PLL_SHIFT_CNT_SELECT_OFST (16)
#define ALTERA_PLL_SHIFT_CNT_SELECT_MSK (0x0000001F << ALTERA_PLL_SHIFT_CNT_SELECT_OFST)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C0_VAL ((0x0 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C1_VAL ((0x1 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C2_VAL ((0x2 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C3_VAL ((0x3 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C4_VAL ((0x4 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C5_VAL ((0x5 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C6_VAL ((0x6 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C7_VAL ((0x7 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C8_VAL ((0x8 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C9_VAL ((0x9 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C10_VAL ((0x10 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C11_VAL ((0x11 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C12_VAL ((0x12 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C13_VAL ((0x13 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C14_VAL ((0x14 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C15_VAL ((0x15 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C16_VAL ((0x16 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C17_VAL ((0x17 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SELECT_OFST (16)
#define ALTERA_PLL_SHIFT_CNT_SELECT_MSK \
(0x0000001F << ALTERA_PLL_SHIFT_CNT_SELECT_OFST)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C0_VAL \
((0x0 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C1_VAL \
((0x1 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C2_VAL \
((0x2 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C3_VAL \
((0x3 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C4_VAL \
((0x4 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C5_VAL \
((0x5 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C6_VAL \
((0x6 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C7_VAL \
((0x7 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C8_VAL \
((0x8 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C9_VAL \
((0x9 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C10_VAL \
((0x10 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C11_VAL \
((0x11 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C12_VAL \
((0x12 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C13_VAL \
((0x13 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C14_VAL \
((0x14 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C15_VAL \
((0x15 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C16_VAL \
((0x16 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_CNT_SLCT_C17_VAL \
((0x17 << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & \
ALTERA_PLL_SHIFT_CNT_SELECT_MSK)
#define ALTERA_PLL_SHIFT_UP_DOWN_OFST (21)
#define ALTERA_PLL_SHIFT_UP_DOWN_MSK (0x00000001 << ALTERA_PLL_SHIFT_UP_DOWN_OFST)
#define ALTERA_PLL_SHIFT_UP_DOWN_NEG_VAL ((0x0 << ALTERA_PLL_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_SHIFT_UP_DOWN_POS_VAL ((0x1 << ALTERA_PLL_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_SHIFT_UP_DOWN_OFST (21)
#define ALTERA_PLL_SHIFT_UP_DOWN_MSK \
(0x00000001 << ALTERA_PLL_SHIFT_UP_DOWN_OFST)
#define ALTERA_PLL_SHIFT_UP_DOWN_NEG_VAL \
((0x0 << ALTERA_PLL_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_SHIFT_UP_DOWN_POS_VAL \
((0x1 << ALTERA_PLL_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_K_COUNTER_REG (0x07)
#define ALTERA_PLL_BANDWIDTH_REG (0x08)
#define ALTERA_PLL_CHARGEPUMP_REG (0x09)
#define ALTERA_PLL_VCO_DIV_REG (0x1c)
#define ALTERA_PLL_MIF_REG (0x1f)
#define ALTERA_PLL_WAIT_TIME_US (10 * 1000)
#define ALTERA_PLL_K_COUNTER_REG (0x07)
#define ALTERA_PLL_BANDWIDTH_REG (0x08)
#define ALTERA_PLL_CHARGEPUMP_REG (0x09)
#define ALTERA_PLL_VCO_DIV_REG (0x1c)
#define ALTERA_PLL_MIF_REG (0x1f)
#define ALTERA_PLL_WAIT_TIME_US (10 * 1000)
// defines from the fpga
uint32_t ALTERA_PLL_Cntrl_Reg = 0x0;
@ -89,7 +135,9 @@ uint32_t ALTERA_PLL_Cntrl_AddrMask = 0x0;
int ALTERA_PLL_Cntrl_AddrOfst = 0;
#ifdef JUNGFRAUD
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst, uint32_t wd2msk, int clk2Index) {
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst, uint32_t wd2msk, int clk2Index) {
ALTERA_PLL_Cntrl_Reg = creg;
ALTERA_PLL_Param_Reg = preg;
ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = rprmsk;
@ -101,7 +149,9 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32
ALTERA_PLL_Cntrl_DBIT_ClkIndex = clk2Index;
}
#else
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst) {
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst) {
ALTERA_PLL_Cntrl_Reg = creg;
ALTERA_PLL_Param_Reg = preg;
ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = rprmsk;
@ -112,31 +162,41 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32
}
#endif
void ALTERA_PLL_ResetPLL () {
void ALTERA_PLL_ResetPLL() {
LOG(logINFO, ("Resetting only PLL\n"));
LOG(logDEBUG2, ("pllrstmsk:0x%x\n", ALTERA_PLL_Cntrl_PLLRstMask));
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_PLLRstMask);
LOG(logDEBUG2, ("Set PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg)));
bus_w(ALTERA_PLL_Cntrl_Reg,
bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_PLLRstMask);
LOG(logDEBUG2, ("Set PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_PLLRstMask);
LOG(logDEBUG2, ("UnSet PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg)));
bus_w(ALTERA_PLL_Cntrl_Reg,
bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_PLLRstMask);
LOG(logDEBUG2, ("UnSet PLL Reset mSk: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
}
void ALTERA_PLL_ResetPLLAndReconfiguration () {
void ALTERA_PLL_ResetPLLAndReconfiguration() {
LOG(logINFO, ("Resetting PLL and Reconfiguration\n"));
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask | ALTERA_PLL_Cntrl_PLLRstMask);
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) |
ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask |
ALTERA_PLL_Cntrl_PLLRstMask);
usleep(ALTERA_PLL_WAIT_TIME_US);
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask & ~ALTERA_PLL_Cntrl_PLLRstMask);
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) &
~ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask &
~ALTERA_PLL_Cntrl_PLLRstMask);
}
void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val, int useSecondWRMask) {
LOG(logDEBUG1, ("Setting PLL Reconfig Reg, reg:0x%x, val:0x%x, useSecondWRMask:%d)\n", reg, val, useSecondWRMask));
void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
int useSecondWRMask) {
LOG(logDEBUG1,
("Setting PLL Reconfig Reg, reg:0x%x, val:0x%x, useSecondWRMask:%d)\n",
reg, val, useSecondWRMask));
uint32_t wrmask = ALTERA_PLL_Cntrl_WrPrmtrMask;
#ifdef JUNGFRAUD
@ -145,36 +205,47 @@ void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val, int useSecondWRMas
}
#endif
LOG(logDEBUG2, ("pllparamreg:0x%x pllcontrolreg:0x%x addrofst:%d addrmsk:0x%x wrmask:0x%x\n",
ALTERA_PLL_Param_Reg, ALTERA_PLL_Cntrl_Reg, ALTERA_PLL_Cntrl_AddrOfst, ALTERA_PLL_Cntrl_AddrMask, wrmask));
LOG(logDEBUG2,
("pllparamreg:0x%x pllcontrolreg:0x%x addrofst:%d addrmsk:0x%x "
"wrmask:0x%x\n",
ALTERA_PLL_Param_Reg, ALTERA_PLL_Cntrl_Reg, ALTERA_PLL_Cntrl_AddrOfst,
ALTERA_PLL_Cntrl_AddrMask, wrmask));
// set parameter
bus_w(ALTERA_PLL_Param_Reg, val);
LOG(logDEBUG2, ("Set Parameter: ALTERA_PLL_Param_Reg:0x%x\n", bus_r(ALTERA_PLL_Param_Reg)));
LOG(logDEBUG2, ("Set Parameter: ALTERA_PLL_Param_Reg:0x%x\n",
bus_r(ALTERA_PLL_Param_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
// set address
bus_w(ALTERA_PLL_Cntrl_Reg, (reg << ALTERA_PLL_Cntrl_AddrOfst) & ALTERA_PLL_Cntrl_AddrMask);
LOG(logDEBUG2, ("Set Address: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg)));
bus_w(ALTERA_PLL_Cntrl_Reg,
(reg << ALTERA_PLL_Cntrl_AddrOfst) & ALTERA_PLL_Cntrl_AddrMask);
LOG(logDEBUG2, ("Set Address: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
//write parameter
// write parameter
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) | wrmask);
LOG(logDEBUG2, ("Set WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg)));
LOG(logDEBUG2, ("Set WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
bus_w(ALTERA_PLL_Cntrl_Reg, bus_r(ALTERA_PLL_Cntrl_Reg) & ~wrmask);
LOG(logDEBUG2, ("Unset WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n", bus_r(ALTERA_PLL_Cntrl_Reg)));
LOG(logDEBUG2, ("Unset WR bit: ALTERA_PLL_Cntrl_Reg:0x%x\n",
bus_r(ALTERA_PLL_Cntrl_Reg)));
usleep(ALTERA_PLL_WAIT_TIME_US);
}
void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos) {
LOG(logINFO, ("\tWriting PLL Phase Shift\n"));
uint32_t value = (((phase << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST) & ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK) |
((clkIndex << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) & ALTERA_PLL_SHIFT_CNT_SELECT_MSK) |
(pos ? ALTERA_PLL_SHIFT_UP_DOWN_POS_VAL : ALTERA_PLL_SHIFT_UP_DOWN_NEG_VAL));
uint32_t value = (((phase << ALTERA_PLL_SHIFT_NUM_SHIFTS_OFST) &
ALTERA_PLL_SHIFT_NUM_SHIFTS_MSK) |
((clkIndex << ALTERA_PLL_SHIFT_CNT_SELECT_OFST) &
ALTERA_PLL_SHIFT_CNT_SELECT_MSK) |
(pos ? ALTERA_PLL_SHIFT_UP_DOWN_POS_VAL
: ALTERA_PLL_SHIFT_UP_DOWN_NEG_VAL));
LOG(logDEBUG1, ("C%d phase word:0x%08x\n", clkIndex, value));
@ -186,19 +257,22 @@ void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos) {
#endif
// write phase shift
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_PHASE_SHIFT_REG, value, useSecondWR);
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_PHASE_SHIFT_REG, value,
useSecondWR);
}
void ALTERA_PLL_SetModePolling() {
LOG(logINFO, ("\tSetting Polling Mode\n"));
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_MODE_REG, ALTERA_PLL_MODE_PLLNG_MD_VAL, 0);
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_MODE_REG,
ALTERA_PLL_MODE_PLLNG_MD_VAL, 0);
}
int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
LOG(logDEBUG1, ("C%d: Setting output frequency to %d (pllvcofreq: %dMhz)\n", clkIndex, value, pllVCOFreqMhz));
int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value) {
LOG(logDEBUG1, ("C%d: Setting output frequency to %d (pllvcofreq: %dMhz)\n",
clkIndex, value, pllVCOFreqMhz));
// calculate output frequency
float total_div = (float)pllVCOFreqMhz / (float)value;
float total_div = (float)pllVCOFreqMhz / (float)value;
// assume 50% duty cycle
uint32_t low_count = total_div / 2;
@ -210,28 +284,32 @@ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
++high_count;
odd_division = 1;
}
LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", clkIndex, low_count, high_count, odd_division));
LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", clkIndex, low_count,
high_count, odd_division));
// command to set output frequency
uint32_t val = (((low_count << ALTERA_PLL_C_COUNTER_LW_CNT_OFST) & ALTERA_PLL_C_COUNTER_LW_CNT_MSK) |
((high_count << ALTERA_PLL_C_COUNTER_HGH_CNT_OFST) & ALTERA_PLL_C_COUNTER_HGH_CNT_MSK) |
((odd_division << ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST) & ALTERA_PLL_C_COUNTER_ODD_DVSN_MSK) |
((clkIndex << ALTERA_PLL_C_COUNTER_SLCT_OFST) & ALTERA_PLL_C_COUNTER_SLCT_MSK));
uint32_t val = (((low_count << ALTERA_PLL_C_COUNTER_LW_CNT_OFST) &
ALTERA_PLL_C_COUNTER_LW_CNT_MSK) |
((high_count << ALTERA_PLL_C_COUNTER_HGH_CNT_OFST) &
ALTERA_PLL_C_COUNTER_HGH_CNT_MSK) |
((odd_division << ALTERA_PLL_C_COUNTER_ODD_DVSN_OFST) &
ALTERA_PLL_C_COUNTER_ODD_DVSN_MSK) |
((clkIndex << ALTERA_PLL_C_COUNTER_SLCT_OFST) &
ALTERA_PLL_C_COUNTER_SLCT_MSK));
LOG(logDEBUG1, ("C%d word:0x%08x\n", clkIndex, val));
// write frequency (post-scale output counter C)
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_C_COUNTER_REG, val, 0);
// reset required to keep the phase (must reconfigure adcs again after this as adc clock is stopped temporarily when resetting pll)
ALTERA_PLL_ResetPLL ();
// reset required to keep the phase (must reconfigure adcs again after this
// as adc clock is stopped temporarily when resetting pll)
ALTERA_PLL_ResetPLL();
/*double temp = ((double)pllVCOFreqMhz / (double)(low_count + high_count));
if ((temp - (int)temp) > 0.0001) {
temp += 0.5;
}
return (int)temp;
*/
return value;
if ((temp - (int)temp) > 0.0001) {
temp += 0.5;
}
return (int)temp;
*/
return value;
}

126
slsDetectorServers/slsDetectorServer/src/ALTERA_PLL_CYCLONE10.c Executable file → Normal file
View File

@ -3,46 +3,55 @@
#include "nios.h"
#include "sls_detector_defs.h"
#include <unistd.h> // usleep
#include <unistd.h> // usleep
/* Altera PLL CYCLONE 10 DEFINES */
/** PLL Reconfiguration Registers */
// https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an728.pdf
// c counter (C0-C8 (+1 to base address))
#define ALTERA_PLL_C10_C_COUNTER_BASE_REG (0x0C0)
#define ALTERA_PLL_C10_C_COUNTER_BASE_REG (0x0C0)
#define ALTERA_PLL_C10_C_COUNTER_MAX_DIVIDER_VAL (512)
#define ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST (0)
#define ALTERA_PLL_C10_C_COUNTER_LW_CNT_MSK (0x000000FF << ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST)
#define ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST (8)
#define ALTERA_PLL_C10_C_COUNTER_HGH_CNT_MSK (0x000000FF << ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST)
#define ALTERA_PLL_C10_C_COUNTER_MAX_DIVIDER_VAL (512)
#define ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST (0)
#define ALTERA_PLL_C10_C_COUNTER_LW_CNT_MSK \
(0x000000FF << ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST)
#define ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST (8)
#define ALTERA_PLL_C10_C_COUNTER_HGH_CNT_MSK \
(0x000000FF << ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST)
/* total_div = lw_cnt + hgh_cnt */
#define ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_OFST (16)
#define ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_MSK (0x00000001 << ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_OFST)
/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is bypassed) */
#define ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST (17)
#define ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_MSK (0x00000001 << ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST)
/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle = (hgh_cnt - 0.5) / total_div */
#define ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_OFST (16)
#define ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_MSK \
(0x00000001 << ALTERA_PLL_C10_C_COUNTER_BYPSS_ENBL_OFST)
/* if bypss_enbl = 0, fout = f(vco)/total_div; else fout = f(vco) (c counter is
* bypassed) */
#define ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST (17)
#define ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_MSK \
(0x00000001 << ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST)
/** if odd_dvsn = 0 (even), duty cycle = hgh_cnt/ total_div; else duty cycle =
* (hgh_cnt - 0.5) / total_div */
// dynamic phase shift (C0-C8 (+1 to base address), 0xF for all counters)
#define ALTERA_PLL_C10_PHASE_SHIFT_BASE_REG (0x100)
#define ALTERA_PLL_C10_PHASE_SHIFT_BASE_REG (0x100)
#define ALTERA_PLL_C10_MAX_SHIFTS_PER_OPERATION (7)
#define ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST (0)
#define ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_MSK (0x00000007 << ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST)
#define ALTERA_PLL_C10_MAX_SHIFTS_PER_OPERATION (7)
#define ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST (0)
#define ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_MSK \
(0x00000007 << ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST (3)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK (0x00000001 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_NEG_VAL ((0x0 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_POS_VAL ((0x1 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST) & ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_C10_PHASE_SHIFT_STEP_OF_VCO (8)
#define ALTERA_PLL_C10_WAIT_TIME_US (1 * 1000) // 1 ms
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST (3)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK \
(0x00000001 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_NEG_VAL \
((0x0 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST) & \
ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_C10_SHIFT_UP_DOWN_POS_VAL \
((0x1 << ALTERA_PLL_C10_SHIFT_UP_DOWN_OFST) & \
ALTERA_PLL_C10_SHIFT_UP_DOWN_MSK)
#define ALTERA_PLL_C10_PHASE_SHIFT_STEP_OF_VCO (8)
#define ALTERA_PLL_C10_WAIT_TIME_US (1 * 1000) // 1 ms
int ALTERA_PLL_C10_Reg_offset = 0x0;
const int ALTERA_PLL_C10_NUM = 2;
@ -51,7 +60,10 @@ uint32_t ALTERA_PLL_C10_Reset_Reg[2] = {0x0, 0x0};
uint32_t ALTERA_PLL_C10_Reset_Msk[2] = {0x0, 0x0};
int ALTERA_PLL_C10_VCO_FREQ[2] = {0, 0};
void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0, uint32_t baseaddr1, uint32_t resetreg0, uint32_t resetreg1, uint32_t resetmsk0, uint32_t resetmsk1, int vcofreq0, int vcofreq1) {
void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0,
uint32_t baseaddr1, uint32_t resetreg0,
uint32_t resetreg1, uint32_t resetmsk0,
uint32_t resetmsk1, int vcofreq0, int vcofreq1) {
ALTERA_PLL_C10_Reg_offset = regofst;
ALTERA_PLL_C10_BaseAddress[0] = baseaddr0;
ALTERA_PLL_C10_BaseAddress[1] = baseaddr1;
@ -68,7 +80,7 @@ int ALTERA_PLL_C10_GetMaxClockDivider() {
}
int ALTERA_PLL_C10_GetVCOFrequency(int pllIndex) {
return ALTERA_PLL_C10_VCO_FREQ[pllIndex];
return ALTERA_PLL_C10_VCO_FREQ[pllIndex];
}
int ALTERA_PLL_C10_GetMaxPhaseShiftStepsofVCO() {
@ -79,42 +91,52 @@ void ALTERA_PLL_C10_Reconfigure(int pllIndex) {
LOG(logINFO, ("\tReconfiguring PLL %d\n", pllIndex));
// write anything to base address to start reconfiguring
LOG(logDEBUG1, ("\tWriting 1 to base address 0x%x to start reconfiguring\n", ALTERA_PLL_C10_BaseAddress[pllIndex]));
LOG(logDEBUG1, ("\tWriting 1 to base address 0x%x to start reconfiguring\n",
ALTERA_PLL_C10_BaseAddress[pllIndex]));
bus_w_csp1(ALTERA_PLL_C10_BaseAddress[pllIndex], 0x1);
usleep(ALTERA_PLL_C10_WAIT_TIME_US);
}
void ALTERA_PLL_C10_ResetPLL (int pllIndex) {
void ALTERA_PLL_C10_ResetPLL(int pllIndex) {
uint32_t resetreg = ALTERA_PLL_C10_Reset_Reg[pllIndex];
uint32_t resetmsk = ALTERA_PLL_C10_Reset_Msk[pllIndex];
LOG(logINFO, ("Resetting PLL %d\n", pllIndex));
bus_w_csp1(resetreg, bus_r_csp1(resetreg) | resetmsk);
usleep(ALTERA_PLL_C10_WAIT_TIME_US);
usleep(ALTERA_PLL_C10_WAIT_TIME_US);
}
void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase,
int pos) {
LOG(logINFO, ("\tC%d: Writing PLL %d Phase Shift [phase:%d, pos dir:%d]\n",
clkIndex, pllIndex, phase, pos));
void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos) {
LOG(logINFO, ("\tC%d: Writing PLL %d Phase Shift [phase:%d, pos dir:%d]\n", clkIndex, pllIndex, phase, pos));
uint32_t addr = ALTERA_PLL_C10_BaseAddress[pllIndex] + (ALTERA_PLL_C10_PHASE_SHIFT_BASE_REG + (int)clkIndex) * ALTERA_PLL_C10_Reg_offset;
uint32_t addr = ALTERA_PLL_C10_BaseAddress[pllIndex] +
(ALTERA_PLL_C10_PHASE_SHIFT_BASE_REG + (int)clkIndex) *
ALTERA_PLL_C10_Reg_offset;
int maxshifts = ALTERA_PLL_C10_MAX_SHIFTS_PER_OPERATION;
// only 7 shifts at a time
while (phase > 0) {
int phaseToDo = (phase > maxshifts) ? maxshifts : phase;
uint32_t value = (((phaseToDo << ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST) & ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_MSK) |
(pos ? ALTERA_PLL_C10_SHIFT_UP_DOWN_POS_VAL : ALTERA_PLL_C10_SHIFT_UP_DOWN_NEG_VAL));
LOG(logDEBUG1, ("\t[addr:0x%x, phaseTodo:%d phaseleft:%d phase word:0x%08x]\n", addr, phaseToDo, phase, value));
uint32_t value = (((phaseToDo << ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_OFST) &
ALTERA_PLL_C10_SHIFT_NUM_SHIFTS_MSK) |
(pos ? ALTERA_PLL_C10_SHIFT_UP_DOWN_POS_VAL
: ALTERA_PLL_C10_SHIFT_UP_DOWN_NEG_VAL));
LOG(logDEBUG1,
("\t[addr:0x%x, phaseTodo:%d phaseleft:%d phase word:0x%08x]\n",
addr, phaseToDo, phase, value));
bus_w_csp1(addr, value);
ALTERA_PLL_C10_Reconfigure(pllIndex);
phase -= phaseToDo;
}
}
void ALTERA_PLL_C10_SetOuputClockDivider (int pllIndex, int clkIndex, int value) {
LOG(logDEBUG1, ("\tC%d: Setting output clock divider for pll%d to %d\n", clkIndex, pllIndex, value));
void ALTERA_PLL_C10_SetOuputClockDivider(int pllIndex, int clkIndex,
int value) {
LOG(logDEBUG1, ("\tC%d: Setting output clock divider for pll%d to %d\n",
clkIndex, pllIndex, value));
// assume 50% duty cycle
uint32_t low_count = value / 2;
@ -126,20 +148,26 @@ void ALTERA_PLL_C10_SetOuputClockDivider (int pllIndex, int clkIndex, int value)
++high_count;
odd_division = 1;
}
LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", clkIndex, low_count, high_count, odd_division));
LOG(logINFO, ("\tC%d: Low:%d, High:%d, Odd:%d\n", clkIndex, low_count,
high_count, odd_division));
// command to set output frequency
uint32_t addr = ALTERA_PLL_C10_BaseAddress[pllIndex] + (ALTERA_PLL_C10_C_COUNTER_BASE_REG + (int)clkIndex) * ALTERA_PLL_C10_Reg_offset;
uint32_t val = (((low_count << ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST) & ALTERA_PLL_C10_C_COUNTER_LW_CNT_MSK) |
((high_count << ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST) & ALTERA_PLL_C10_C_COUNTER_HGH_CNT_MSK) |
((odd_division << ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST) & ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_MSK));
uint32_t addr = ALTERA_PLL_C10_BaseAddress[pllIndex] +
(ALTERA_PLL_C10_C_COUNTER_BASE_REG + (int)clkIndex) *
ALTERA_PLL_C10_Reg_offset;
uint32_t val = (((low_count << ALTERA_PLL_C10_C_COUNTER_LW_CNT_OFST) &
ALTERA_PLL_C10_C_COUNTER_LW_CNT_MSK) |
((high_count << ALTERA_PLL_C10_C_COUNTER_HGH_CNT_OFST) &
ALTERA_PLL_C10_C_COUNTER_HGH_CNT_MSK) |
((odd_division << ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_OFST) &
ALTERA_PLL_C10_C_COUNTER_ODD_DVSN_MSK));
LOG(logDEBUG1, ("\t[addr:0x%x, word:0x%08x]\n", addr, val));
// write frequency
// write frequency
bus_w_csp1(addr, val);
ALTERA_PLL_C10_Reconfigure(pllIndex);
// reset required to keep the phase relationships
ALTERA_PLL_C10_ResetPLL (pllIndex);
// reset required to keep the phase relationships
ALTERA_PLL_C10_ResetPLL(pllIndex);
}

32
slsDetectorServers/slsDetectorServer/src/ASIC_Driver.c Executable file → Normal file
View File

@ -3,36 +3,36 @@
#include "common.h"
#include "sls_detector_defs.h"
#include <getopt.h>
#include <stdint.h>
#include <stdio.h>
#include <stdlib.h>
#include <getopt.h>
#include <string.h>
#include <unistd.h>
#include <fcntl.h>
#include <sys/ioctl.h>
#include <linux/types.h>
#include <linux/spi/spidev.h>
#include <linux/types.h>
#include <string.h>
#include <sys/ioctl.h>
#include <unistd.h>
// defines from the fpga
char ASIC_Driver_DriverFileName[MAX_STR_LENGTH];
void ASIC_Driver_SetDefines(char* driverfname) {
void ASIC_Driver_SetDefines(char *driverfname) {
LOG(logINFOBLUE, ("Configuring ASIC Driver to %s\n", driverfname));
memset(ASIC_Driver_DriverFileName, 0, MAX_STR_LENGTH);
strcpy(ASIC_Driver_DriverFileName, driverfname);
}
int ASIC_Driver_Set (int index, int length, char* buffer) {
int ASIC_Driver_Set(int index, int length, char *buffer) {
char temp[20];
memset(temp, 0, sizeof(temp));
sprintf(temp, "%d", index + 1);
char fname[MAX_STR_LENGTH];
strcpy(fname, ASIC_Driver_DriverFileName);
strcat(fname, temp);
LOG(logDEBUG2, ("\t[chip index: %d, length: %d, fname: %s]\n", index, length, fname));
LOG(logDEBUG2,
("\t[chip index: %d, length: %d, fname: %s]\n", index, length, fname));
{
LOG(logDEBUG2, ("\t[values: \n"));
int i;
@ -41,19 +41,21 @@ int ASIC_Driver_Set (int index, int length, char* buffer) {
}
LOG(logDEBUG2, ("\t]\n"));
}
#ifndef VIRTUAL
int fd=open(fname, O_RDWR);
int fd = open(fname, O_RDWR);
if (fd == -1) {
LOG(logERROR, ("Could not open file %s for writing to control ASIC (%d)\n", fname, index));
LOG(logERROR,
("Could not open file %s for writing to control ASIC (%d)\n", fname,
index));
return FAIL;
}
struct spi_ioc_transfer transfer;
memset(&transfer, 0, sizeof(transfer));
transfer.tx_buf = (unsigned long) buffer;
transfer.tx_buf = (unsigned long)buffer;
transfer.len = length;
transfer.cs_change = 0;
transfer.cs_change = 0;
// transfer command
int status = ioctl(fd, SPI_IOC_MESSAGE(1), &transfer);
@ -65,6 +67,6 @@ int ASIC_Driver_Set (int index, int length, char* buffer) {
}
close(fd);
#endif
return OK;
}

34
slsDetectorServers/slsDetectorServer/src/DAC6571.c Executable file → Normal file
View File

@ -6,51 +6,47 @@
#include "string.h"
/* DAC6571 HV DEFINES */
#define DAC6571_MIN_DAC_VAL (0x0)
#define DAC6571_MAX_DAC_VAL (0x3FF)
#define DAC6571_MIN_DAC_VAL (0x0)
#define DAC6571_MAX_DAC_VAL (0x3FF)
// defines from the hardware
int DAC6571_HardMaxVoltage = 0;
char DAC6571_DriverFileName[MAX_STR_LENGTH];
void DAC6571_SetDefines(int hardMaxV, char* driverfname) {
LOG(logINFOBLUE, ("Configuring High Voltage to %s (hard max: %dV)\n", driverfname, hardMaxV));
void DAC6571_SetDefines(int hardMaxV, char *driverfname) {
LOG(logINFOBLUE, ("Configuring High Voltage to %s (hard max: %dV)\n",
driverfname, hardMaxV));
DAC6571_HardMaxVoltage = hardMaxV;
memset(DAC6571_DriverFileName, 0, MAX_STR_LENGTH);
strcpy(DAC6571_DriverFileName, driverfname);
}
int DAC6571_Set (int val) {
int DAC6571_Set(int val) {
LOG(logDEBUG1, ("Setting high voltage to %d\n", val));
if (val < 0)
return FAIL;
int dacvalue = 0;
// convert value
ConvertToDifferentRange(0, DAC6571_HardMaxVoltage,
DAC6571_MIN_DAC_VAL, DAC6571_MAX_DAC_VAL,
val, &dacvalue);
ConvertToDifferentRange(0, DAC6571_HardMaxVoltage, DAC6571_MIN_DAC_VAL,
DAC6571_MAX_DAC_VAL, val, &dacvalue);
LOG(logINFO, ("\t%dV (dacval %d)\n", val, dacvalue));
#ifndef VIRTUAL
//open file
FILE* fd=fopen(DAC6571_DriverFileName,"w");
if (fd==NULL) {
LOG(logERROR, ("Could not open file %s for writing to set high voltage\n", DAC6571_DriverFileName));
// open file
FILE *fd = fopen(DAC6571_DriverFileName, "w");
if (fd == NULL) {
LOG(logERROR,
("Could not open file %s for writing to set high voltage\n",
DAC6571_DriverFileName));
return FAIL;
}
//convert to string, add 0 and write to file
// convert to string, add 0 and write to file
fprintf(fd, "%d\n", dacvalue);
fclose(fd);
#endif
return OK;
}

227
slsDetectorServers/slsDetectorServer/src/I2C.c Executable file → Normal file
View File

@ -2,7 +2,7 @@
#include "blackfin.h"
#include "clogger.h"
#include <unistd.h> // usleep
#include <unistd.h> // usleep
/**
* Intel: Embedded Peripherals IP User Guide
@ -23,69 +23,90 @@
* I2C_RX_DATA_FIFO_REG
*/
#define I2C_DATA_RATE_KBPS (200)
#define I2C_DATA_RATE_KBPS (200)
/** Control Register */
#define I2C_CTRL_ENBLE_CORE_OFST (0)
#define I2C_CTRL_ENBLE_CORE_MSK (0x00000001 << I2C_CTRL_ENBLE_CORE_OFST)
#define I2C_CTRL_BUS_SPEED_OFST (1)
#define I2C_CTRL_BUS_SPEED_MSK (0x00000001 << I2C_CTRL_BUS_SPEED_OFST)
#define I2C_CTRL_BUS_SPEED_STNDRD_100_VAL ((0x0 << I2C_CTRL_BUS_SPEED_OFST) & I2C_CTRL_BUS_SPEED_MSK) // standard mode (up to 100 kbps)
#define I2C_CTRL_BUS_SPEED_FAST_400_VAL ((0x1 << I2C_CTRL_BUS_SPEED_OFST) & I2C_CTRL_BUS_SPEED_MSK) // fast mode (up to 400 kbps)
/** if actual level of transfer command fifo <= thd level, TX_READY interrupt asserted */
#define I2C_CTRL_TFR_CMD_FIFO_THD_OFST (2)
#define I2C_CTRL_TFR_CMD_FIFO_THD_MSK (0x00000003 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST)
#define I2C_CTRL_TFR_CMD_EMPTY_VAL ((0x0 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_ONE_FOURTH_VAL ((0x1 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_ONE_HALF_VAL ((0x2 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_NOT_FULL_VAL ((0x3 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
/** if actual level of receive data fifo <= thd level, RX_READY interrupt asserted */
#define I2C_CTRL_RX_DATA_FIFO_THD_OFST (4)
#define I2C_CTRL_RX_DATA_FIFO_THD_MSK (0x00000003 << I2C_CTRL_RX_DATA_FIFO_THD_OFST)
#define I2C_CTRL_RX_DATA_1_VALID_ENTRY_VAL ((0x0 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_ONE_FOURTH_VAL ((0x1 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_ONE_HALF_VAL ((0x2 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_FULL_VAL ((0x3 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_ENBLE_CORE_OFST (0)
#define I2C_CTRL_ENBLE_CORE_MSK (0x00000001 << I2C_CTRL_ENBLE_CORE_OFST)
#define I2C_CTRL_BUS_SPEED_OFST (1)
#define I2C_CTRL_BUS_SPEED_MSK (0x00000001 << I2C_CTRL_BUS_SPEED_OFST)
#define I2C_CTRL_BUS_SPEED_STNDRD_100_VAL \
((0x0 << I2C_CTRL_BUS_SPEED_OFST) & \
I2C_CTRL_BUS_SPEED_MSK) // standard mode (up to 100 kbps)
#define I2C_CTRL_BUS_SPEED_FAST_400_VAL \
((0x1 << I2C_CTRL_BUS_SPEED_OFST) & \
I2C_CTRL_BUS_SPEED_MSK) // fast mode (up to 400 kbps)
/** if actual level of transfer command fifo <= thd level, TX_READY interrupt
* asserted */
#define I2C_CTRL_TFR_CMD_FIFO_THD_OFST (2)
#define I2C_CTRL_TFR_CMD_FIFO_THD_MSK \
(0x00000003 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST)
#define I2C_CTRL_TFR_CMD_EMPTY_VAL \
((0x0 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_ONE_FOURTH_VAL \
((0x1 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_ONE_HALF_VAL \
((0x2 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
#define I2C_CTRL_TFR_CMD_NOT_FULL_VAL \
((0x3 << I2C_CTRL_TFR_CMD_FIFO_THD_OFST) & I2C_CTRL_TFR_CMD_FIFO_THD_MSK)
/** if actual level of receive data fifo <= thd level, RX_READY interrupt
* asserted */
#define I2C_CTRL_RX_DATA_FIFO_THD_OFST (4)
#define I2C_CTRL_RX_DATA_FIFO_THD_MSK \
(0x00000003 << I2C_CTRL_RX_DATA_FIFO_THD_OFST)
#define I2C_CTRL_RX_DATA_1_VALID_ENTRY_VAL \
((0x0 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_ONE_FOURTH_VAL \
((0x1 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_ONE_HALF_VAL \
((0x2 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
#define I2C_CTRL_RX_DATA_FULL_VAL \
((0x3 << I2C_CTRL_RX_DATA_FIFO_THD_OFST) & I2C_CTRL_RX_DATA_FIFO_THD_MSK)
/** Transfer Command Fifo register */
#define I2C_TFR_CMD_RW_OFST (0)
#define I2C_TFR_CMD_RW_MSK (0x00000001 << I2C_TFR_CMD_RW_OFST)
#define I2C_TFR_CMD_RW_WRITE_VAL ((0x0 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
#define I2C_TFR_CMD_RW_READ_VAL ((0x1 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
#define I2C_TFR_CMD_ADDR_OFST (1)
#define I2C_TFR_CMD_ADDR_MSK (0x0000007F << I2C_TFR_CMD_ADDR_OFST)
#define I2C_TFR_CMD_RW_OFST (0)
#define I2C_TFR_CMD_RW_MSK (0x00000001 << I2C_TFR_CMD_RW_OFST)
#define I2C_TFR_CMD_RW_WRITE_VAL \
((0x0 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
#define I2C_TFR_CMD_RW_READ_VAL \
((0x1 << I2C_TFR_CMD_RW_OFST) & I2C_TFR_CMD_RW_MSK)
#define I2C_TFR_CMD_ADDR_OFST (1)
#define I2C_TFR_CMD_ADDR_MSK (0x0000007F << I2C_TFR_CMD_ADDR_OFST)
/** when writing, rw and addr converts to data to be written mask */
#define I2C_TFR_CMD_DATA_FR_WR_OFST (0)
#define I2C_TFR_CMD_DATA_FR_WR_MSK (0x000000FF << I2C_TFR_CMD_DATA_FR_WR_OFST)
#define I2C_TFR_CMD_STOP_OFST (8)
#define I2C_TFR_CMD_STOP_MSK (0x00000001 << I2C_TFR_CMD_STOP_OFST)
#define I2C_TFR_CMD_RPTD_STRT_OFST (9)
#define I2C_TFR_CMD_RPTD_STRT_MSK (0x00000001 << I2C_TFR_CMD_RPTD_STRT_OFST)
#define I2C_TFR_CMD_DATA_FR_WR_OFST (0)
#define I2C_TFR_CMD_DATA_FR_WR_MSK (0x000000FF << I2C_TFR_CMD_DATA_FR_WR_OFST)
#define I2C_TFR_CMD_STOP_OFST (8)
#define I2C_TFR_CMD_STOP_MSK (0x00000001 << I2C_TFR_CMD_STOP_OFST)
#define I2C_TFR_CMD_RPTD_STRT_OFST (9)
#define I2C_TFR_CMD_RPTD_STRT_MSK (0x00000001 << I2C_TFR_CMD_RPTD_STRT_OFST)
/** Receive DataFifo register */
#define I2C_RX_DATA_FIFO_RXDATA_OFST (0)
#define I2C_RX_DATA_FIFO_RXDATA_MSK (0x000000FF << I2C_RX_DATA_FIFO_RXDATA_OFST)
#define I2C_RX_DATA_FIFO_RXDATA_OFST (0)
#define I2C_RX_DATA_FIFO_RXDATA_MSK (0x000000FF << I2C_RX_DATA_FIFO_RXDATA_OFST)
/** Status register */
#define I2C_STATUS_BUSY_OFST (0)
#define I2C_STATUS_BUSY_MSK (0x00000001 << I2C_STATUS_BUSY_OFST)
#define I2C_STATUS_BUSY_OFST (0)
#define I2C_STATUS_BUSY_MSK (0x00000001 << I2C_STATUS_BUSY_OFST)
/** SCL Low Count register */
#define I2C_SCL_LOW_COUNT_PERIOD_OFST (0)
#define I2C_SCL_LOW_COUNT_PERIOD_MSK (0x0000FFFF << I2C_SCL_LOW_COUNT_PERIOD_OFST)
#define I2C_SCL_LOW_COUNT_PERIOD_OFST (0)
#define I2C_SCL_LOW_COUNT_PERIOD_MSK \
(0x0000FFFF << I2C_SCL_LOW_COUNT_PERIOD_OFST)
/** SCL High Count register */
#define I2C_SCL_HIGH_COUNT_PERIOD_OFST (0)
#define I2C_SCL_HIGH_COUNT_PERIOD_MSK (0x0000FFFF << I2C_SCL_HIGH_COUNT_PERIOD_OFST)
#define I2C_SCL_HIGH_COUNT_PERIOD_OFST (0)
#define I2C_SCL_HIGH_COUNT_PERIOD_MSK \
(0x0000FFFF << I2C_SCL_HIGH_COUNT_PERIOD_OFST)
/** SDA Hold Count register */
#define I2C_SDA_HOLD_COUNT_PERIOD_OFST (0)
#define I2C_SDA_HOLD_COUNT_PERIOD_MSK (0x0000FFFF << I2C_SDA_HOLD_COUNT_PERIOD_OFST)
#define I2C_SDA_HOLD_COUNT_PERIOD_OFST (0)
#define I2C_SDA_HOLD_COUNT_PERIOD_MSK \
(0x0000FFFF << I2C_SDA_HOLD_COUNT_PERIOD_OFST)
/** Receive Data Fifo Level register */
//#define I2C_RX_DATA_FIFO_LVL_OFST (0)
//#define I2C_RX_DATA_FIFO_LVL_MSK (0x000000FF << I2C_RX_DATA_FIFO_LVL_OFST)
//#define I2C_RX_DATA_FIFO_LVL_MSK (0x000000FF <<
//I2C_RX_DATA_FIFO_LVL_OFST)
// defines in the fpga
uint32_t I2C_Control_Reg = 0x0;
@ -97,15 +118,15 @@ uint32_t I2C_Scl_High_Count_Reg = 0x0;
uint32_t I2C_Sda_Hold_Reg = 0x0;
uint32_t I2C_Transfer_Command_Fifo_Reg = 0x0;
void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg,
uint32_t rreg, uint32_t rlvlreg,
uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg) {
void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg, uint32_t rreg,
uint32_t rlvlreg, uint32_t slreg, uint32_t shreg,
uint32_t sdreg, uint32_t treg) {
LOG(logINFO, ("\tConfiguring I2C Core for %d kbps:\n", I2C_DATA_RATE_KBPS));
LOG(logDEBUG1,("controlreg,:0x%x, statusreg,:0x%x, "
"rxrdatafiforeg: 0x%x, rxdatafifocountreg,:0x%x, "
"scllow,:0x%x, sclhighreg,:0x%x, sdaholdreg,:0x%x, transfercmdreg,:0x%x\n",
creg, sreg, rreg, rlvlreg, slreg, shreg, sdreg, treg));
LOG(logDEBUG1, ("controlreg,:0x%x, statusreg,:0x%x, "
"rxrdatafiforeg: 0x%x, rxdatafifocountreg,:0x%x, "
"scllow,:0x%x, sclhighreg,:0x%x, sdaholdreg,:0x%x, "
"transfercmdreg,:0x%x\n",
creg, sreg, rreg, rlvlreg, slreg, shreg, sdreg, treg));
I2C_Control_Reg = creg;
I2C_Status_Reg = sreg;
@ -117,57 +138,77 @@ void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg,
I2C_Transfer_Command_Fifo_Reg = treg;
// calculate scl low and high period count
uint32_t sclPeriodNs = ((1000.00 * 1000.00 * 1000.00) / ((double)I2C_DATA_RATE_KBPS * 1000.00));
uint32_t sclPeriodNs = ((1000.00 * 1000.00 * 1000.00) /
((double)I2C_DATA_RATE_KBPS * 1000.00));
// scl low period same as high period
uint32_t sclLowPeriodNs = sclPeriodNs / 2;
// convert to us, then to clock (defined in blackfin.h)
uint32_t sclLowPeriodCount = (sclLowPeriodNs / 1000.00) * I2C_CLOCK_MHZ;
// calculate sda hold data count
uint32_t sdaDataHoldTimeNs = (sclLowPeriodNs / 2); // scl low period same as high period
uint32_t sdaDataHoldTimeNs =
(sclLowPeriodNs / 2); // scl low period same as high period
// convert to us, then to clock (defined in blackfin.h)
uint32_t sdaDataHoldCount = ((sdaDataHoldTimeNs / 1000.00) * I2C_CLOCK_MHZ);
LOG(logINFO, ("\tSetting SCL Low Period: %d ns (%d clocks)\n", sclLowPeriodNs, sclLowPeriodCount));
bus_w(I2C_Scl_Low_Count_Reg, bus_r(I2C_Scl_Low_Count_Reg) |
((sclLowPeriodCount << I2C_SCL_LOW_COUNT_PERIOD_OFST) & I2C_SCL_LOW_COUNT_PERIOD_MSK));
LOG(logINFO, ("\tSetting SCL Low Period: %d ns (%d clocks)\n",
sclLowPeriodNs, sclLowPeriodCount));
bus_w(I2C_Scl_Low_Count_Reg,
bus_r(I2C_Scl_Low_Count_Reg) |
((sclLowPeriodCount << I2C_SCL_LOW_COUNT_PERIOD_OFST) &
I2C_SCL_LOW_COUNT_PERIOD_MSK));
LOG(logDEBUG1, ("SCL Low reg:0x%x\n", bus_r(I2C_Scl_Low_Count_Reg)));
LOG(logINFO, ("\tSetting SCL High Period: %d ns (%d clocks)\n", sclLowPeriodNs, sclLowPeriodCount));
bus_w(I2C_Scl_High_Count_Reg, bus_r(I2C_Scl_High_Count_Reg) |
((sclLowPeriodCount << I2C_SCL_HIGH_COUNT_PERIOD_OFST) & I2C_SCL_HIGH_COUNT_PERIOD_MSK));
LOG(logINFO, ("\tSetting SCL High Period: %d ns (%d clocks)\n",
sclLowPeriodNs, sclLowPeriodCount));
bus_w(I2C_Scl_High_Count_Reg,
bus_r(I2C_Scl_High_Count_Reg) |
((sclLowPeriodCount << I2C_SCL_HIGH_COUNT_PERIOD_OFST) &
I2C_SCL_HIGH_COUNT_PERIOD_MSK));
LOG(logDEBUG1, ("SCL High reg:0x%x\n", bus_r(I2C_Scl_High_Count_Reg)));
LOG(logINFO, ("\tSetting SDA Hold Time: %d ns (%d clocks)\n", sdaDataHoldTimeNs, sdaDataHoldCount));
bus_w(I2C_Sda_Hold_Reg, bus_r(I2C_Sda_Hold_Reg) |
((sdaDataHoldCount << I2C_SDA_HOLD_COUNT_PERIOD_OFST) & I2C_SDA_HOLD_COUNT_PERIOD_MSK));
LOG(logINFO, ("\tSetting SDA Hold Time: %d ns (%d clocks)\n",
sdaDataHoldTimeNs, sdaDataHoldCount));
bus_w(I2C_Sda_Hold_Reg,
bus_r(I2C_Sda_Hold_Reg) |
((sdaDataHoldCount << I2C_SDA_HOLD_COUNT_PERIOD_OFST) &
I2C_SDA_HOLD_COUNT_PERIOD_MSK));
LOG(logDEBUG1, ("SDA Hold reg:0x%x\n", bus_r(I2C_Sda_Hold_Reg)));
LOG(logINFO, ("\tEnabling core and bus speed to fast (up to 400 kbps)\n"));
bus_w(I2C_Control_Reg, bus_r(I2C_Control_Reg) |
I2C_CTRL_ENBLE_CORE_MSK | I2C_CTRL_BUS_SPEED_FAST_400_VAL);// fixme: (works?)
bus_w(I2C_Control_Reg,
bus_r(I2C_Control_Reg) | I2C_CTRL_ENBLE_CORE_MSK |
I2C_CTRL_BUS_SPEED_FAST_400_VAL); // fixme: (works?)
LOG(logDEBUG1, ("Control reg:0x%x\n", bus_r(I2C_Control_Reg)));
//The INA226 supports the transmission protocol for fast mode (1 kHz to 400 kHz) and high-speed mode (1 kHz to 2.94 MHz).
// The INA226 supports the transmission protocol for fast mode (1 kHz to 400
// kHz) and high-speed mode (1 kHz to 2.94 MHz).
}
uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
LOG(logDEBUG2, (" ================================================\n"));
LOG(logDEBUG2, (" Reading from I2C device 0x%x and reg 0x%x\n", devId, addr));
LOG(logDEBUG2,
(" Reading from I2C device 0x%x and reg 0x%x\n", devId, addr));
// device Id mask
uint32_t devIdMask = ((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
uint32_t devIdMask =
((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
LOG(logDEBUG2, (" devId:0x%x\n", devIdMask));
// write I2C ID
bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask & ~(I2C_TFR_CMD_RW_MSK)));
LOG(logDEBUG2, (" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
LOG(logDEBUG2,
(" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
// write register addr
bus_w(I2C_Transfer_Command_Fifo_Reg, addr);
LOG(logDEBUG2, (" write addr:0x%x\n", addr));
// repeated start with read (repeated start needed here because it was in write operation mode earlier, for the device ID)
bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL));
LOG(logDEBUG2, (" repeated start:0x%x\n", (devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL)));
// repeated start with read (repeated start needed here because it was in
// write operation mode earlier, for the device ID)
bus_w(I2C_Transfer_Command_Fifo_Reg,
(devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL));
LOG(logDEBUG2,
(" repeated start:0x%x\n",
(devIdMask | I2C_TFR_CMD_RPTD_STRT_MSK | I2C_TFR_CMD_RW_READ_VAL)));
// continue reading
bus_w(I2C_Transfer_Command_Fifo_Reg, 0x0);
@ -180,10 +221,11 @@ uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
// read value
uint32_t retval = 0;
//In case one wants to do something more general (INA226 receives only 2 bytes)
// In case one wants to do something more general (INA226 receives only 2
// bytes)
// wait till status is idle
int status = 1;
while(status) {
while (status) {
status = bus_r(I2C_Status_Reg) & I2C_STATUS_BUSY_MSK;
LOG(logDEBUG2, (" status:%d\n", status));
usleep(0);
@ -196,7 +238,8 @@ uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
// level bytes to read, read 1 byte at a time
for (iloop = level - 1; iloop >= 0; --iloop) {
u_int16_t byte = bus_r(I2C_Rx_Data_Fifo_Reg) & I2C_RX_DATA_FIFO_RXDATA_MSK;
u_int16_t byte =
bus_r(I2C_Rx_Data_Fifo_Reg) & I2C_RX_DATA_FIFO_RXDATA_MSK;
LOG(logDEBUG2, (" byte nr %d:0x%x\n", iloop, byte));
// push by 1 byte at a time
retval |= (byte << (8 * iloop));
@ -208,33 +251,43 @@ uint32_t I2C_Read(uint32_t devId, uint32_t addr) {
void I2C_Write(uint32_t devId, uint32_t addr, uint16_t data) {
LOG(logDEBUG2, (" ================================================\n"));
LOG(logDEBUG2, (" Writing to I2C (Device:0x%x, reg:0x%x, data:%d)\n", devId, addr, data));
LOG(logDEBUG2, (" Writing to I2C (Device:0x%x, reg:0x%x, data:%d)\n", devId,
addr, data));
// device Id mask
uint32_t devIdMask = ((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
uint32_t devIdMask =
((devId << I2C_TFR_CMD_ADDR_OFST) & I2C_TFR_CMD_ADDR_MSK);
LOG(logDEBUG2, (" devId:0x%x\n", devId));
// write I2C ID
bus_w(I2C_Transfer_Command_Fifo_Reg, (devIdMask & ~(I2C_TFR_CMD_RW_MSK)));
LOG(logDEBUG2, (" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
LOG(logDEBUG2,
(" write devID and R/-W:0x%x\n", (devIdMask & ~(I2C_TFR_CMD_RW_MSK))));
// write register addr
bus_w(I2C_Transfer_Command_Fifo_Reg, addr);
LOG(logDEBUG2, (" write addr:0x%x\n", addr));
// do not do the repeated start as it is already in write operation mode (else it wont work)
// do not do the repeated start as it is already in write operation mode
// (else it wont work)
uint8_t msb = (uint8_t)((data & 0xFF00) >> 8);
uint8_t lsb = (uint8_t)(data & 0x00FF);
LOG(logDEBUG2, (" msb:0x%02x, lsb:0x%02x\n", msb, lsb));
// writing data MSB
bus_w(I2C_Transfer_Command_Fifo_Reg, ((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK));
LOG(logDEBUG2, (" write msb:0x%02x\n", ((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK)));
bus_w(I2C_Transfer_Command_Fifo_Reg,
((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK));
LOG(logDEBUG2,
(" write msb:0x%02x\n",
((msb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK)));
// writing data LSB and stop writing bit
bus_w(I2C_Transfer_Command_Fifo_Reg, ((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) | I2C_TFR_CMD_STOP_MSK);
LOG(logDEBUG2, (" write lsb and stop writing:0x%x\n", ((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) | I2C_TFR_CMD_STOP_MSK));
bus_w(I2C_Transfer_Command_Fifo_Reg,
((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) |
I2C_TFR_CMD_STOP_MSK);
LOG(logDEBUG2,
(" write lsb and stop writing:0x%x\n",
((lsb << I2C_TFR_CMD_DATA_FR_WR_OFST) & I2C_TFR_CMD_DATA_FR_WR_MSK) |
I2C_TFR_CMD_STOP_MSK));
LOG(logDEBUG2, (" ================================================\n"));
}

101
slsDetectorServers/slsDetectorServer/src/INA226.c Executable file → Normal file
View File

@ -16,43 +16,46 @@
/** INA226 defines */
/** Register set */
#define INA226_CONFIGURATION_REG (0x00) //R/W
#define INA226_SHUNT_VOLTAGE_REG (0x01) //R
#define INA226_BUS_VOLTAGE_REG (0x02) //R
#define INA226_POWER_REG (0x03) //R
#define INA226_CURRENT_REG (0x04) //R
#define INA226_CALIBRATION_REG (0x05) //R/W
#define INA226_MASK_ENABLE_REG (0x06) //R/W
#define INA226_ALERT_LIMIT_REG (0x07) //R/W
#define INA226_MANUFACTURER_ID_REG (0xFE) //R
#define INA226_DIE_ID_REG (0xFF) //R
#define INA226_CONFIGURATION_REG (0x00) // R/W
#define INA226_SHUNT_VOLTAGE_REG (0x01) // R
#define INA226_BUS_VOLTAGE_REG (0x02) // R
#define INA226_POWER_REG (0x03) // R
#define INA226_CURRENT_REG (0x04) // R
#define INA226_CALIBRATION_REG (0x05) // R/W
#define INA226_MASK_ENABLE_REG (0x06) // R/W
#define INA226_ALERT_LIMIT_REG (0x07) // R/W
#define INA226_MANUFACTURER_ID_REG (0xFE) // R
#define INA226_DIE_ID_REG (0xFF) // R
/** bus voltage register */
#define INA226_BUS_VOLTAGE_VMIN_UV (1250) // 1.25mV
#define INA226_BUS_VOLTAGE_MX_STPS (0x7FFF + 1)
#define INA226_BUS_VOLTAGE_VMAX_UV (INA226_BUS_VOLTAGE_VMIN_UV * INA226_BUS_VOLTAGE_MX_STPS) // 40960000uV, 40.96V
#define INA226_BUS_VOLTAGE_VMIN_UV (1250) // 1.25mV
#define INA226_BUS_VOLTAGE_MX_STPS (0x7FFF + 1)
#define INA226_BUS_VOLTAGE_VMAX_UV \
(INA226_BUS_VOLTAGE_VMIN_UV * \
INA226_BUS_VOLTAGE_MX_STPS) // 40960000uV, 40.96V
/** shunt voltage register */
#define INA226_SHUNT_VOLTAGE_VMIN_NV (2500) // 2.5uV
#define INA226_SHUNT_VOLTAGE_MX_STPS (0x7FFF + 1)
#define INA226_SHUNT_VOLTAGE_VMAX_NV (INA226_SHUNT_VOLTAGE_VMIN_NV * INA226_SHUNT_VOLTAGE_MX_STPS) // 81920000nV, 81.92mV
#define INA226_SHUNT_NEGATIVE_MSK (1 << 15)
#define INA226_SHUNT_ABS_VALUE_MSK (0x7FFF)
#define INA226_SHUNT_VOLTAGE_VMIN_NV (2500) // 2.5uV
#define INA226_SHUNT_VOLTAGE_MX_STPS (0x7FFF + 1)
#define INA226_SHUNT_VOLTAGE_VMAX_NV \
(INA226_SHUNT_VOLTAGE_VMIN_NV * \
INA226_SHUNT_VOLTAGE_MX_STPS) // 81920000nV, 81.92mV
#define INA226_SHUNT_NEGATIVE_MSK (1 << 15)
#define INA226_SHUNT_ABS_VALUE_MSK (0x7FFF)
/** current precision for calibration register */
#define INA226_CURRENT_IMIN_UA (100) //100uA can be changed
#define INA226_CURRENT_IMIN_UA (100) // 100uA can be changed
/** calibration register */
#define INA226_CALIBRATION_MSK (0x7FFF)
#define INA226_CALIBRATION_MSK (0x7FFF)
/** get calibration register value to be set */
#define INA226_getCalibrationValue(rOhm) (0.00512 /(INA226_CURRENT_IMIN_UA * 1e-6 * rOhm))
#define INA226_getCalibrationValue(rOhm) \
(0.00512 / (INA226_CURRENT_IMIN_UA * 1e-6 * rOhm))
/** get current unit */
#define INA226_getConvertedCurrentUnits(shuntV, calibReg) ((double)shuntV * (double)calibReg / (double)2048)
#define INA226_getConvertedCurrentUnits(shuntV, calibReg) \
((double)shuntV * (double)calibReg / (double)2048)
// defines from the fpga
double INA226_Shunt_Resistor_Ohm = 0.0;
@ -61,8 +64,8 @@ int INA226_Calibration_Register_Value = 0;
#define INA226_CALIBRATION_CURRENT_TOLERANCE (1.2268)
void INA226_ConfigureI2CCore(double rOhm, uint32_t creg, uint32_t sreg,
uint32_t rreg, uint32_t rlvlreg,
uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg) {
uint32_t rreg, uint32_t rlvlreg, uint32_t slreg,
uint32_t shreg, uint32_t sdreg, uint32_t treg) {
LOG(logINFOBLUE, ("Configuring INA226\n"));
LOG(logDEBUG1, ("Shunt ohm resistor: %f\n", rOhm));
INA226_Shunt_Resistor_Ohm = rOhm;
@ -71,13 +74,19 @@ void INA226_ConfigureI2CCore(double rOhm, uint32_t creg, uint32_t sreg,
}
void INA226_CalibrateCurrentRegister(uint32_t deviceId) {
LOG(logINFO, ("Calibrating Current Register for Device ID: 0x%x\n", deviceId));
LOG(logINFO,
("Calibrating Current Register for Device ID: 0x%x\n", deviceId));
// get calibration value based on shunt resistor
uint16_t calVal = ((uint16_t)INA226_getCalibrationValue(INA226_Shunt_Resistor_Ohm)) & INA226_CALIBRATION_MSK;
LOG(logINFO, ("\tCalculated calibration reg value: 0x%0x (%d)\n", calVal, calVal));
uint16_t calVal =
((uint16_t)INA226_getCalibrationValue(INA226_Shunt_Resistor_Ohm)) &
INA226_CALIBRATION_MSK;
LOG(logINFO,
("\tCalculated calibration reg value: 0x%0x (%d)\n", calVal, calVal));
calVal = ((double)calVal / INA226_CALIBRATION_CURRENT_TOLERANCE) + 0.5;
LOG(logINFO, ("\tRealculated (for tolerance) calibration reg value: 0x%0x (%d)\n", calVal, calVal));
LOG(logINFO,
("\tRealculated (for tolerance) calibration reg value: 0x%0x (%d)\n",
calVal, calVal));
INA226_Calibration_Register_Value = calVal;
// calibrate current register
@ -86,7 +95,9 @@ void INA226_CalibrateCurrentRegister(uint32_t deviceId) {
// read back calibration register
int retval = I2C_Read(deviceId, INA226_CALIBRATION_REG);
if (retval != calVal) {
LOG(logERROR, ("Cannot set calibration register for I2C. Set 0x%x, read 0x%x\n", calVal, retval));
LOG(logERROR,
("Cannot set calibration register for I2C. Set 0x%x, read 0x%x\n",
calVal, retval));
}
}
@ -98,14 +109,15 @@ int INA226_ReadVoltage(uint32_t deviceId) {
// value in uV
int voltageuV = 0;
ConvertToDifferentRange(0, INA226_BUS_VOLTAGE_MX_STPS,
INA226_BUS_VOLTAGE_VMIN_UV, INA226_BUS_VOLTAGE_VMAX_UV,
regval, &voltageuV);
INA226_BUS_VOLTAGE_VMIN_UV,
INA226_BUS_VOLTAGE_VMAX_UV, regval, &voltageuV);
LOG(logDEBUG1, (" voltage: 0x%d uV\n", voltageuV));
// value in mV
int voltagemV = voltageuV / 1000;
int voltagemV = voltageuV / 1000;
LOG(logDEBUG1, (" voltage: %d mV\n", voltagemV));
LOG(logINFO, ("Voltage via I2C (Device: 0x%x): %d mV\n", deviceId, voltagemV));
LOG(logINFO,
("Voltage via I2C (Device: 0x%x): %d mV\n", deviceId, voltagemV));
return voltagemV;
}
@ -122,13 +134,13 @@ int INA226_ReadCurrent(uint32_t deviceId) {
if (shuntVoltageRegVal == 0xFFFF) {
LOG(logDEBUG1, (" Reading shunt voltage reg again\n"));
shuntVoltageRegVal = I2C_Read(deviceId, INA226_SHUNT_VOLTAGE_REG);
LOG(logDEBUG1, (" shunt voltage reg: %d\n", shuntVoltageRegVal));
LOG(logDEBUG1, (" shunt voltage reg: %d\n", shuntVoltageRegVal));
}
// value for current
int retval = INA226_getConvertedCurrentUnits(shuntVoltageRegVal, INA226_Calibration_Register_Value);
int retval = INA226_getConvertedCurrentUnits(
shuntVoltageRegVal, INA226_Calibration_Register_Value);
LOG(logDEBUG1, (" current unit value: %d\n", retval));
// reading directly the current reg
LOG(logDEBUG1, (" Reading current reg\n"));
int cuurentRegVal = I2C_Read(deviceId, INA226_CURRENT_REG);
@ -137,20 +149,23 @@ int INA226_ReadCurrent(uint32_t deviceId) {
if (cuurentRegVal >= 0xFFF0) {
LOG(logDEBUG1, (" Reading current reg again\n"));
cuurentRegVal = I2C_Read(deviceId, INA226_CURRENT_REG);
LOG(logDEBUG1, (" current reg: %d\n", cuurentRegVal));
LOG(logDEBUG1, (" current reg: %d\n", cuurentRegVal));
}
// should be the same
LOG(logDEBUG1, (" ===============current reg: %d, current unit cal:%d=================================\n", cuurentRegVal, retval));
LOG(logDEBUG1, (" ===============current reg: %d, current unit "
"cal:%d=================================\n",
cuurentRegVal, retval));
// current in uA
int currentuA = cuurentRegVal * INA226_CURRENT_IMIN_UA;
LOG(logDEBUG1, (" current: %d uA\n", currentuA));
// current in mA
int currentmA = (currentuA / 1000.00) + 0.5;
int currentmA = (currentuA / 1000.00) + 0.5;
LOG(logDEBUG1, (" current: %d mA\n", currentmA));
LOG(logINFO, ("Current via I2C (Device: 0x%x): %d mA\n", deviceId, currentmA));
LOG(logINFO,
("Current via I2C (Device: 0x%x): %d mA\n", deviceId, currentmA));
return currentmA;
}

169
slsDetectorServers/slsDetectorServer/src/LTC2620.c Executable file → Normal file
View File

@ -1,35 +1,46 @@
#include "LTC2620.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "common.h"
#include "blackfin.h"
#include "clogger.h"
#include "common.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "sls_detector_defs.h"
#include <string.h>
/* LTC2620 DAC DEFINES */
// first 4 bits are 0 as this is a 12 bit dac
#define LTC2620_DAC_DATA_OFST (4)
#define LTC2620_DAC_DATA_MSK (0x00000FFF << LTC2620_DAC_DATA_OFST)
#define LTC2620_DAC_ADDR_OFST (16)
#define LTC2620_DAC_ADDR_MSK (0x0000000F << LTC2620_DAC_ADDR_OFST)
#define LTC2620_DAC_CMD_OFST (20)
#define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST)
#define LTC2620_DAC_DATA_OFST (4)
#define LTC2620_DAC_DATA_MSK (0x00000FFF << LTC2620_DAC_DATA_OFST)
#define LTC2620_DAC_ADDR_OFST (16)
#define LTC2620_DAC_ADDR_MSK (0x0000000F << LTC2620_DAC_ADDR_OFST)
#define LTC2620_DAC_CMD_OFST (20)
#define LTC2620_DAC_CMD_MSK (0x0000000F << LTC2620_DAC_CMD_OFST)
#define LTC2620_DAC_CMD_WR_IN_VAL ((0x0 << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK) // write to input register
#define LTC2620_DAC_CMD_UPDTE_DAC_VAL ((0x1 << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK) // update dac (power up)
#define LTC2620_DAC_CMD_WR_IN_UPDTE_DAC_VAL ((0x2 << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK) // write to input register and update dac (power up)
#define LTC2620_DAC_CMD_WR_UPDTE_DAC_VAL ((0x3 << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK) // write to and update dac (power up)
#define LTC2620_DAC_CMD_PWR_DWN_VAL ((0x4 << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK)
#define LTC2620_DAC_CMD_NO_OPRTN_VAL ((0xF << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK)
#define LTC2620_DAC_CMD_WR_IN_VAL \
((0x0 << LTC2620_DAC_CMD_OFST) & \
LTC2620_DAC_CMD_MSK) // write to input register
#define LTC2620_DAC_CMD_UPDTE_DAC_VAL \
((0x1 << LTC2620_DAC_CMD_OFST) & \
LTC2620_DAC_CMD_MSK) // update dac (power up)
#define LTC2620_DAC_CMD_WR_IN_UPDTE_DAC_VAL \
((0x2 << LTC2620_DAC_CMD_OFST) & \
LTC2620_DAC_CMD_MSK) // write to input register and update dac (power up)
#define LTC2620_DAC_CMD_WR_UPDTE_DAC_VAL \
((0x3 << LTC2620_DAC_CMD_OFST) & \
LTC2620_DAC_CMD_MSK) // write to and update dac (power up)
#define LTC2620_DAC_CMD_PWR_DWN_VAL \
((0x4 << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK)
#define LTC2620_DAC_CMD_NO_OPRTN_VAL \
((0xF << LTC2620_DAC_CMD_OFST) & LTC2620_DAC_CMD_MSK)
#define LTC2620_NUMBITS (24)
#define LTC2620_DAISY_CHAIN_NUMBITS (32) // due to shift register FIXME: was 33 earlier
#define LTC2620_NUMCHANNELS (8)
#define LTC2620_PWR_DOWN_VAL (-100)
#define LTC2620_MIN_VAL (0)
#define LTC2620_MAX_VAL (4095) // 12 bits
#define LTC2620_MAX_STEPS (LTC2620_MAX_VAL + 1)
#define LTC2620_NUMBITS (24)
#define LTC2620_DAISY_CHAIN_NUMBITS \
(32) // due to shift register FIXME: was 33 earlier
#define LTC2620_NUMCHANNELS (8)
#define LTC2620_PWR_DOWN_VAL (-100)
#define LTC2620_MIN_VAL (0)
#define LTC2620_MAX_VAL (4095) // 12 bits
#define LTC2620_MAX_STEPS (LTC2620_MAX_VAL + 1)
#ifdef CHIPTESTBOARDD
#include "slsDetectorServer_defs.h"
@ -45,7 +56,9 @@ int LTC2620_Ndac = 0;
int LTC2620_MinVoltage = 0;
int LTC2620_MaxVoltage = 0;
void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst, int nd, int minMV, int maxMV) {
void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst, int nd, int minMV,
int maxMV) {
LTC2620_Reg = reg;
LTC2620_CsMask = cmsk;
LTC2620_ClkMask = clkmsk;
@ -57,75 +70,68 @@ void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t d
}
void LTC2620_Disable() {
bus_w(LTC2620_Reg, (bus_r(LTC2620_Reg)
| LTC2620_CsMask
| LTC2620_ClkMask)
& ~(LTC2620_DigMask));
bus_w(LTC2620_Reg, (bus_r(LTC2620_Reg) | LTC2620_CsMask | LTC2620_ClkMask) &
~(LTC2620_DigMask));
}
int LTC2620_GetPowerDownValue() {
return LTC2620_PWR_DOWN_VAL;
}
int LTC2620_GetPowerDownValue() { return LTC2620_PWR_DOWN_VAL; }
int LTC2620_GetMinInput() {
return LTC2620_MIN_VAL;
}
int LTC2620_GetMinInput() { return LTC2620_MIN_VAL; }
int LTC2620_GetMaxInput() {
return LTC2620_MAX_VAL;
}
int LTC2620_GetMaxInput() { return LTC2620_MAX_VAL; }
int LTC2620_GetMaxNumSteps() {
return LTC2620_MAX_STEPS;
}
int LTC2620_GetMaxNumSteps() { return LTC2620_MAX_STEPS; }
int LTC2620_VoltageToDac(int voltage, int* dacval) {
int LTC2620_VoltageToDac(int voltage, int *dacval) {
return ConvertToDifferentRange(LTC2620_MinVoltage, LTC2620_MaxVoltage,
LTC2620_MIN_VAL, LTC2620_MAX_VAL,
voltage, dacval);
LTC2620_MIN_VAL, LTC2620_MAX_VAL, voltage,
dacval);
}
int LTC2620_DacToVoltage(int dacval, int* voltage) {
return ConvertToDifferentRange( LTC2620_MIN_VAL, LTC2620_MAX_VAL,
LTC2620_MinVoltage, LTC2620_MaxVoltage,
dacval, voltage);
int LTC2620_DacToVoltage(int dacval, int *voltage) {
return ConvertToDifferentRange(LTC2620_MIN_VAL, LTC2620_MAX_VAL,
LTC2620_MinVoltage, LTC2620_MaxVoltage,
dacval, voltage);
}
void LTC2620_SetSingle(int cmd, int data, int dacaddr) {
LOG(logDEBUG2, ("(Single) dac addr:%d, dac value:%d, cmd:%d\n", dacaddr, data, cmd));
void LTC2620_SetSingle(int cmd, int data, int dacaddr) {
LOG(logDEBUG2,
("(Single) dac addr:%d, dac value:%d, cmd:%d\n", dacaddr, data, cmd));
uint32_t codata = (((data << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK) |
((dacaddr << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) |
cmd);
uint32_t codata =
(((data << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK) |
((dacaddr << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) | cmd);
LOG(logDEBUG2, ("codata: 0x%x\n", codata));
serializeToSPI (LTC2620_Reg, codata, LTC2620_CsMask, LTC2620_NUMBITS,
LTC2620_ClkMask, LTC2620_DigMask, LTC2620_DigOffset, 0);
serializeToSPI(LTC2620_Reg, codata, LTC2620_CsMask, LTC2620_NUMBITS,
LTC2620_ClkMask, LTC2620_DigMask, LTC2620_DigOffset, 0);
}
void LTC2620_SendDaisyData(uint32_t* valw, uint32_t val) {
void LTC2620_SendDaisyData(uint32_t *valw, uint32_t val) {
sendDataToSPI(valw, LTC2620_Reg, val, LTC2620_DAISY_CHAIN_NUMBITS,
LTC2620_ClkMask, LTC2620_DigMask, LTC2620_DigOffset);
LTC2620_ClkMask, LTC2620_DigMask, LTC2620_DigOffset);
}
void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex) {
void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex) {
int nchip = LTC2620_Ndac / LTC2620_NUMCHANNELS;
uint32_t valw = 0;
int ichip = 0;
LOG(logDEBUG2, ("(Daisy) desired chip index:%d, nchip:%d, dac ch:%d, val:%d, cmd:0x%x \n",
chipIndex, nchip, dacaddr, data, cmd));
LOG(logDEBUG2, ("(Daisy) desired chip index:%d, nchip:%d, dac ch:%d, "
"val:%d, cmd:0x%x \n",
chipIndex, nchip, dacaddr, data, cmd));
// data to be bit banged
uint32_t codata = (((data << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK) |
((dacaddr << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) |
cmd);
uint32_t codata =
(((data << LTC2620_DAC_DATA_OFST) & LTC2620_DAC_DATA_MSK) |
((dacaddr << LTC2620_DAC_ADDR_OFST) & LTC2620_DAC_ADDR_MSK) | cmd);
LOG(logDEBUG2, ("codata: 0x%x\n", codata));
// select all chips (ctb daisy chain; others 1 chip)
LOG(logDEBUG2, ("Selecting LTC2620\n"));
SPIChipSelect (&valw, LTC2620_Reg, LTC2620_CsMask, LTC2620_ClkMask, LTC2620_DigMask, 0);
SPIChipSelect(&valw, LTC2620_Reg, LTC2620_CsMask, LTC2620_ClkMask,
LTC2620_DigMask, 0);
// send same data to all
if (chipIndex < 0) {
@ -138,7 +144,8 @@ void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex) {
// send to one chip, nothing to others
else {
// send nothing to subsequent ichips (daisy chain) (if any chips after desired chip)
// send nothing to subsequent ichips (daisy chain) (if any chips after
// desired chip)
for (ichip = chipIndex + 1; ichip < nchip; ++ichip) {
LOG(logDEBUG2, ("Send nothing to ichip %d\n", ichip));
LTC2620_SendDaisyData(&valw, LTC2620_DAC_CMD_NO_OPRTN_VAL);
@ -148,7 +155,8 @@ void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex) {
LOG(logDEBUG2, ("Send data (0x%x) to ichip %d\n", codata, chipIndex));
LTC2620_SendDaisyData(&valw, codata);
// send nothing to preceding ichips (daisy chain) (if any chips in front of desired chip)
// send nothing to preceding ichips (daisy chain) (if any chips in front
// of desired chip)
for (ichip = 0; ichip < chipIndex; ++ichip) {
LOG(logDEBUG2, ("Send nothing to ichip %d\n", ichip));
LTC2620_SendDaisyData(&valw, LTC2620_DAC_CMD_NO_OPRTN_VAL);
@ -157,11 +165,13 @@ void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex) {
// deselect all chips (ctb daisy chain; others 1 chip)
LOG(logDEBUG2, ("Deselecting LTC2620\n"));
SPIChipDeselect(&valw, LTC2620_Reg, LTC2620_CsMask, LTC2620_ClkMask, LTC2620_DigMask, 0);
SPIChipDeselect(&valw, LTC2620_Reg, LTC2620_CsMask, LTC2620_ClkMask,
LTC2620_DigMask, 0);
}
void LTC2620_Set(int cmd, int data, int dacaddr, int chipIndex) {
LOG(logDEBUG1, ("cmd:0x%x, data:%d, dacaddr:%d, chipIndex:%d\n", cmd, data, dacaddr, chipIndex));
void LTC2620_Set(int cmd, int data, int dacaddr, int chipIndex) {
LOG(logDEBUG1, ("cmd:0x%x, data:%d, dacaddr:%d, chipIndex:%d\n", cmd, data,
dacaddr, chipIndex));
LOG(logDEBUG2, (" ================================================\n"));
// ctb
if (LTC2620_Ndac > LTC2620_NUMCHANNELS)
@ -172,7 +182,7 @@ void LTC2620_Set(int cmd, int data, int dacaddr, int chipIndex) {
LOG(logDEBUG2, (" ================================================\n"));
}
void LTC2620_Configure(){
void LTC2620_Configure() {
LOG(logINFOBLUE, ("Configuring LTC2620\n"));
// dac channel - all channels
@ -182,16 +192,17 @@ void LTC2620_Configure(){
int data = 0x6;
// command
int cmd = LTC2620_DAC_CMD_WR_IN_VAL; //FIXME: should be command update and not write(does not power up)
int cmd = LTC2620_DAC_CMD_WR_IN_VAL; // FIXME: should be command update and
// not write(does not power up)
// also why do we need to power up (for jctb, we power down next)
LTC2620_Set(cmd, data, addr, -1);
}
void LTC2620_SetDAC (int dacnum, int data) {
void LTC2620_SetDAC(int dacnum, int data) {
LOG(logDEBUG1, ("Setting dac %d to %d\n", dacnum, data));
// LTC2620 index
int ichip = dacnum / LTC2620_NUMCHANNELS;
int ichip = dacnum / LTC2620_NUMCHANNELS;
// dac channel
int addr = dacnum % LTC2620_NUMCHANNELS;
@ -204,17 +215,18 @@ void LTC2620_SetDAC (int dacnum, int data) {
cmd = LTC2620_DAC_CMD_PWR_DWN_VAL;
LOG(logDEBUG1, ("POWER DOWN\n"));
} else {
LOG(logDEBUG1,("Write to Input Register and Update\n"));
LOG(logDEBUG1, ("Write to Input Register and Update\n"));
}
LTC2620_Set(cmd, data, addr, ichip);
}
int LTC2620_SetDACValue (int dacnum, int val, int mV, int* dacval) {
int LTC2620_SetDACValue(int dacnum, int val, int mV, int *dacval) {
LOG(logDEBUG1, ("dacnum:%d, val:%d, ismV:%d\n", dacnum, val, mV));
// validate index
if (dacnum < 0 || dacnum >= LTC2620_Ndac) {
LOG(logERROR, ("Dac index %d is out of bounds (0 to %d)\n", dacnum, LTC2620_Ndac - 1));
LOG(logERROR, ("Dac index %d is out of bounds (0 to %d)\n", dacnum,
LTC2620_Ndac - 1));
return FAIL;
}
@ -234,19 +246,22 @@ int LTC2620_SetDACValue (int dacnum, int val, int mV, int* dacval) {
ret = LTC2620_VoltageToDac(val, dacval);
} else if (val >= 0 && dacnum <= ndacsonly) {
// do not convert power down dac val
//(if not ndacsonly (pwr/vchip): dont need to print mV value as it will be wrong (wrong limits))
//(if not ndacsonly (pwr/vchip): dont need to print mV value as it will
//be wrong (wrong limits))
ret = LTC2620_DacToVoltage(val, &dacmV);
}
// conversion out of bounds
if (ret == FAIL) {
LOG(logERROR, ("Setting Dac %d %s is out of bounds\n", dacnum, (mV ? "mV" : "dac units")));
LOG(logERROR, ("Setting Dac %d %s is out of bounds\n", dacnum,
(mV ? "mV" : "dac units")));
return FAIL;
}
// set
if ( (*dacval >= 0) || (*dacval == LTC2620_PWR_DOWN_VAL)) {
LOG(logINFO, ("Setting DAC %d: %d dac (%d mV)\n",dacnum, *dacval, dacmV));
if ((*dacval >= 0) || (*dacval == LTC2620_PWR_DOWN_VAL)) {
LOG(logINFO,
("Setting DAC %d: %d dac (%d mV)\n", dacnum, *dacval, dacmV));
LTC2620_SetDAC(dacnum, *dacval);
}
return OK;

63
slsDetectorServers/slsDetectorServer/src/LTC2620_Driver.c Executable file → Normal file
View File

@ -6,44 +6,44 @@
#include <string.h>
/* LTC2620 DAC DEFINES */
#define LTC2620_D_PWR_DOWN_VAL (-100)
#define LTC2620_D_MAX_DAC_VAL (4095) // 12 bits
#define LTC2620_D_MAX_STEPS (LTC2620_D_MAX_DAC_VAL + 1)
#define LTC2620_D_PWR_DOWN_VAL (-100)
#define LTC2620_D_MAX_DAC_VAL (4095) // 12 bits
#define LTC2620_D_MAX_STEPS (LTC2620_D_MAX_DAC_VAL + 1)
// defines from the fpga
int LTC2620_D_HardMaxVoltage = 0;
char LTC2620_D_DriverFileName[MAX_STR_LENGTH];
int LTC2620_D_NumDacs = 0;
void LTC2620_D_SetDefines(int hardMaxV, char* driverfname, int numdacs) {
LOG(logINFOBLUE, ("Configuring DACs (LTC2620) to %s (numdacs:%d, hard max: %dmV)\n", driverfname, numdacs, hardMaxV));
void LTC2620_D_SetDefines(int hardMaxV, char *driverfname, int numdacs) {
LOG(logINFOBLUE,
("Configuring DACs (LTC2620) to %s (numdacs:%d, hard max: %dmV)\n",
driverfname, numdacs, hardMaxV));
LTC2620_D_HardMaxVoltage = hardMaxV;
memset(LTC2620_D_DriverFileName, 0, MAX_STR_LENGTH);
strcpy(LTC2620_D_DriverFileName, driverfname);
LTC2620_D_NumDacs = numdacs;
}
int LTC2620_D_GetMaxNumSteps() {
return LTC2620_D_MAX_STEPS;
int LTC2620_D_GetMaxNumSteps() { return LTC2620_D_MAX_STEPS; }
int LTC2620_D_VoltageToDac(int voltage, int *dacval) {
return ConvertToDifferentRange(0, LTC2620_D_HardMaxVoltage, 0,
LTC2620_D_MAX_DAC_VAL, voltage, dacval);
}
int LTC2620_D_VoltageToDac(int voltage, int* dacval) {
return ConvertToDifferentRange(0, LTC2620_D_HardMaxVoltage, 0, LTC2620_D_MAX_DAC_VAL,
voltage, dacval);
int LTC2620_D_DacToVoltage(int dacval, int *voltage) {
return ConvertToDifferentRange(0, LTC2620_D_MAX_DAC_VAL, 0,
LTC2620_D_HardMaxVoltage, dacval, voltage);
}
int LTC2620_D_DacToVoltage(int dacval, int* voltage) {
return ConvertToDifferentRange( 0, LTC2620_D_MAX_DAC_VAL, 0, LTC2620_D_HardMaxVoltage,
dacval, voltage);
}
int LTC2620_D_SetDACValue (int dacnum, int val, int mV, char* dacname, int* dacval) {
int LTC2620_D_SetDACValue(int dacnum, int val, int mV, char *dacname,
int *dacval) {
LOG(logDEBUG1, ("dacnum:%d, val:%d, ismV:%d\n", dacnum, val, mV));
// validate index
if (dacnum < 0 || dacnum >= LTC2620_D_NumDacs) {
LOG(logERROR, ("Dac index %d is out of bounds (0 to %d)\n", dacnum, LTC2620_D_NumDacs - 1));
LOG(logERROR, ("Dac index %d is out of bounds (0 to %d)\n", dacnum,
LTC2620_D_NumDacs - 1));
return FAIL;
}
@ -64,14 +64,15 @@ int LTC2620_D_SetDACValue (int dacnum, int val, int mV, char* dacname, int* dacv
// conversion out of bounds
if (ret == FAIL) {
LOG(logERROR, ("Setting Dac %d %s is out of bounds\n", dacnum, (mV ? "mV" : "dac units")));
LOG(logERROR, ("Setting Dac %d %s is out of bounds\n", dacnum,
(mV ? "mV" : "dac units")));
return FAIL;
}
// set
if ( (*dacval >= 0) || (*dacval == LTC2620_D_PWR_DOWN_VAL)) {
LOG(logINFO, ("Setting DAC %2d [%-12s] : %d dac (%d mV)\n",dacnum, dacname, *dacval, dacmV));
if ((*dacval >= 0) || (*dacval == LTC2620_D_PWR_DOWN_VAL)) {
LOG(logINFO, ("Setting DAC %2d [%-12s] : %d dac (%d mV)\n", dacnum,
dacname, *dacval, dacmV));
#ifndef VIRTUAL
char fname[MAX_STR_LENGTH];
@ -80,19 +81,19 @@ int LTC2620_D_SetDACValue (int dacnum, int val, int mV, char* dacname, int* dacv
memset(temp, 0, sizeof(temp));
sprintf(temp, "%d", dacnum);
strcat(fname, temp);
LOG(logDEBUG1, ("fname %s\n",fname));
//open file
FILE* fd=fopen(fname,"w");
if (fd==NULL) {
LOG(logERROR, ("Could not open file %s for writing to set dac %d\n", fname, dacnum));
LOG(logDEBUG1, ("fname %s\n", fname));
// open file
FILE *fd = fopen(fname, "w");
if (fd == NULL) {
LOG(logERROR, ("Could not open file %s for writing to set dac %d\n",
fname, dacnum));
return FAIL;
}
//convert to string, add 0 and write to file
// convert to string, add 0 and write to file
fprintf(fd, "%d\n", *dacval);
fclose(fd);
#endif
}
return OK;
}

36
slsDetectorServers/slsDetectorServer/src/MAX1932.c Executable file → Normal file
View File

@ -1,19 +1,19 @@
#include "MAX1932.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "blackfin.h"
#include "clogger.h"
#include "common.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
#include "sls_detector_defs.h"
/* MAX1932 HV DEFINES */
#define MAX1932_HV_NUMBITS (8)
#define MAX1932_HV_DATA_OFST (0)
#define MAX1932_HV_DATA_MSK (0x000000FF << MAX1932_HV_DATA_OFST)
#define MAX1932_HV_NUMBITS (8)
#define MAX1932_HV_DATA_OFST (0)
#define MAX1932_HV_DATA_MSK (0x000000FF << MAX1932_HV_DATA_OFST)
// higher voltage requires lower dac value, 0 is off
#define MAX1932_MIN_DAC_VAL (0xFF)
#define MAX1932_MAX_DAC_VAL (0x1)
#define MAX1932_POWER_OFF_DAC_VAL (0x0)
#define MAX1932_MIN_DAC_VAL (0xFF)
#define MAX1932_MAX_DAC_VAL (0x1)
#define MAX1932_POWER_OFF_DAC_VAL (0x0)
// defines from the fpga
uint32_t MAX1932_Reg = 0x0;
@ -24,8 +24,8 @@ int MAX1932_DigOffset = 0x0;
int MAX1932_MinVoltage = 0;
int MAX1932_MaxVoltage = 0;
void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst,
int minMV, int maxMV) {
void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst, int minMV, int maxMV) {
LOG(logINFOBLUE, ("Configuring High Voltage\n"));
MAX1932_Reg = reg;
MAX1932_CsMask = cmsk;
@ -37,13 +37,11 @@ void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t d
}
void MAX1932_Disable() {
bus_w(MAX1932_Reg, (bus_r(MAX1932_Reg)
| MAX1932_CsMask
| MAX1932_ClkMask)
& ~(MAX1932_DigMask));
bus_w(MAX1932_Reg, (bus_r(MAX1932_Reg) | MAX1932_CsMask | MAX1932_ClkMask) &
~(MAX1932_DigMask));
}
int MAX1932_Set (int* val) {
int MAX1932_Set(int *val) {
LOG(logDEBUG1, ("Setting high voltage to %d\n", *val));
if (*val < 0)
return FAIL;
@ -64,17 +62,13 @@ int MAX1932_Set (int* val) {
else {
// no failure in conversion as limits handled (range from 0x1 to 0xFF)
ConvertToDifferentRange(MAX1932_MinVoltage, MAX1932_MaxVoltage,
MAX1932_MIN_DAC_VAL, MAX1932_MAX_DAC_VAL,
*val, &dacvalue);
MAX1932_MIN_DAC_VAL, MAX1932_MAX_DAC_VAL, *val,
&dacvalue);
dacvalue &= MAX1932_HV_DATA_MSK;
}
LOG(logINFO, ("\t%dV (dacval %d)\n", *val, dacvalue));
serializeToSPI(MAX1932_Reg, dacvalue, MAX1932_CsMask, MAX1932_HV_NUMBITS,
MAX1932_ClkMask, MAX1932_DigMask, MAX1932_DigOffset, 0);
MAX1932_ClkMask, MAX1932_DigMask, MAX1932_DigOffset, 0);
return OK;
}

195
slsDetectorServers/slsDetectorServer/src/UDPPacketHeaderGenerator.c Executable file → Normal file
View File

@ -2,117 +2,122 @@
#include "clogger.h"
#include "sls_detector_defs.h"
#include <stdio.h>
#include <stdlib.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <arpa/inet.h>
#include <netinet/in.h>
#include <string.h>
#include <unistd.h>
#include <errno.h>
#include <netdb.h>
#include <netinet/in.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/socket.h>
#include <sys/types.h>
#include <unistd.h>
#define UDP_PACKET_HEADER_VERSION (0x1)
#define UDP_PACKET_HEADER_VERSION (0x1)
extern const enum detectorType myDetectorType;
extern int analogDataBytes;
extern int digitalDataBytes;
extern char* analogData;
extern char* digitalData;
extern char *analogData;
extern char *digitalData;
int analogOffset = 0;
int digitalOffset = 0;
uint32_t udpPacketNumber = 0;
uint64_t udpFrameNumber = 0;
uint32_t getUDPPacketNumber() { return udpPacketNumber; }
uint32_t getUDPPacketNumber() {
return udpPacketNumber;
uint64_t getUDPFrameNumber() { return udpFrameNumber; }
void createUDPPacketHeader(char *buffer, uint16_t id) {
memset(buffer, 0, sizeof(sls_detector_header));
sls_detector_header *header = (sls_detector_header *)(buffer);
header->modId = id;
// row and column remains 0 (only used by ctb now)
// uint64_t timestamp FIXME: needed?
header->detType = (uint16_t)myDetectorType;
header->version = UDP_PACKET_HEADER_VERSION;
// reset offset
analogOffset = 0;
digitalOffset = 0;
// reset frame number
udpFrameNumber = 0;
}
uint64_t getUDPFrameNumber() {
return udpFrameNumber;
}
void createUDPPacketHeader(char* buffer, uint16_t id) {
memset(buffer, 0, sizeof(sls_detector_header));
sls_detector_header* header = (sls_detector_header*)(buffer);
header->modId = id;
// row and column remains 0 (only used by ctb now)
// uint64_t timestamp FIXME: needed?
header->detType = (uint16_t)myDetectorType;
header->version = UDP_PACKET_HEADER_VERSION;
// reset offset
analogOffset = 0;
digitalOffset = 0;
// reset frame number
udpFrameNumber = 0;
}
int fillUDPPacket(char* buffer) {
LOG(logDEBUG2, ("Analog (databytes:%d, offset:%d)\n Digital (databytes:%d offset:%d)\n",
analogDataBytes, analogOffset, digitalDataBytes, digitalOffset));
// reached end of data for one frame
if (analogOffset >= analogDataBytes && digitalOffset >= digitalDataBytes) {
// reset offset
analogOffset = 0;
digitalOffset = 0;
return 0;
}
sls_detector_header* header = (sls_detector_header*)(buffer);
// update frame number, starts at 1 (reset packet number)
if (analogOffset == 0 && digitalOffset == 0) {
++udpFrameNumber;
header->frameNumber = udpFrameNumber;
udpPacketNumber = -1;
}
// increment and copy udp packet number (starts at 0)
++udpPacketNumber;
header->packetNumber = udpPacketNumber;
LOG(logDEBUG2, ("Creating packet number %d (fnum:%lld)\n", udpPacketNumber, (long long int) udpFrameNumber));
int freeBytes = UDP_PACKET_DATA_BYTES;
// analog data
int analogBytes = 0;
if (analogOffset < analogDataBytes) {
// bytes to copy
analogBytes = ((analogOffset + freeBytes) <= analogDataBytes) ?
freeBytes : (analogDataBytes - analogOffset);
// copy
memcpy(buffer + sizeof(sls_detector_header), analogData + analogOffset, analogBytes);
// increment offset
analogOffset += analogBytes;
// decrement free bytes
freeBytes -= analogBytes;
}
// digital data
int digitalBytes = 0;
if (freeBytes && digitalOffset < digitalDataBytes) {
// bytes to copy
digitalBytes = ((digitalOffset + freeBytes) <= digitalDataBytes) ?
freeBytes : (digitalDataBytes - digitalOffset);
// copy
memcpy(buffer + sizeof(sls_detector_header) + analogBytes, digitalData + digitalOffset, digitalBytes);
// increment offset
digitalOffset += digitalBytes;
// decrement free bytes
freeBytes -= digitalBytes;
}
// pad data
if (freeBytes) {
memset(buffer + sizeof(sls_detector_header) + analogBytes + digitalBytes, 0, freeBytes);
LOG(logDEBUG1, ("Padding %d bytes for fnum:%lld pnum:%d\n", freeBytes, (long long int)udpFrameNumber, udpPacketNumber));
}
return UDP_PACKET_DATA_BYTES + sizeof(sls_detector_header);
int fillUDPPacket(char *buffer) {
LOG(logDEBUG2,
("Analog (databytes:%d, offset:%d)\n Digital (databytes:%d "
"offset:%d)\n",
analogDataBytes, analogOffset, digitalDataBytes, digitalOffset));
// reached end of data for one frame
if (analogOffset >= analogDataBytes && digitalOffset >= digitalDataBytes) {
// reset offset
analogOffset = 0;
digitalOffset = 0;
return 0;
}
sls_detector_header *header = (sls_detector_header *)(buffer);
// update frame number, starts at 1 (reset packet number)
if (analogOffset == 0 && digitalOffset == 0) {
++udpFrameNumber;
header->frameNumber = udpFrameNumber;
udpPacketNumber = -1;
}
// increment and copy udp packet number (starts at 0)
++udpPacketNumber;
header->packetNumber = udpPacketNumber;
LOG(logDEBUG2, ("Creating packet number %d (fnum:%lld)\n", udpPacketNumber,
(long long int)udpFrameNumber));
int freeBytes = UDP_PACKET_DATA_BYTES;
// analog data
int analogBytes = 0;
if (analogOffset < analogDataBytes) {
// bytes to copy
analogBytes = ((analogOffset + freeBytes) <= analogDataBytes)
? freeBytes
: (analogDataBytes - analogOffset);
// copy
memcpy(buffer + sizeof(sls_detector_header), analogData + analogOffset,
analogBytes);
// increment offset
analogOffset += analogBytes;
// decrement free bytes
freeBytes -= analogBytes;
}
// digital data
int digitalBytes = 0;
if (freeBytes && digitalOffset < digitalDataBytes) {
// bytes to copy
digitalBytes = ((digitalOffset + freeBytes) <= digitalDataBytes)
? freeBytes
: (digitalDataBytes - digitalOffset);
// copy
memcpy(buffer + sizeof(sls_detector_header) + analogBytes,
digitalData + digitalOffset, digitalBytes);
// increment offset
digitalOffset += digitalBytes;
// decrement free bytes
freeBytes -= digitalBytes;
}
// pad data
if (freeBytes) {
memset(buffer + sizeof(sls_detector_header) + analogBytes +
digitalBytes,
0, freeBytes);
LOG(logDEBUG1, ("Padding %d bytes for fnum:%lld pnum:%d\n", freeBytes,
(long long int)udpFrameNumber, udpPacketNumber));
}
return UDP_PACKET_DATA_BYTES + sizeof(sls_detector_header);
}

159
slsDetectorServers/slsDetectorServer/src/blackfin.c Executable file → Normal file
View File

@ -1,85 +1,84 @@
#include "blackfin.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#include "ansi.h"
#include "clogger.h"
#include "sls_detector_defs.h"
#include <fcntl.h> // open
#include <sys/mman.h> // mmap
#include <fcntl.h> // open
#include <sys/mman.h> // mmap
/* global variables */
u_int32_t* csp0base = 0;
#define CSP0 0x20200000
u_int32_t *csp0base = 0;
#define CSP0 0x20200000
#define MEM_SIZE 0x100000
void bus_w16(u_int32_t offset, u_int16_t data) {
volatile u_int16_t *ptr1;
ptr1=(u_int16_t*)(csp0base + offset / 2);
*ptr1=data;
volatile u_int16_t *ptr1;
ptr1 = (u_int16_t *)(csp0base + offset / 2);
*ptr1 = data;
}
u_int16_t bus_r16(u_int32_t offset){
volatile u_int16_t *ptr1;
ptr1=(u_int16_t*)(csp0base + offset / 2);
return *ptr1;
u_int16_t bus_r16(u_int32_t offset) {
volatile u_int16_t *ptr1;
ptr1 = (u_int16_t *)(csp0base + offset / 2);
return *ptr1;
}
void bus_w(u_int32_t offset, u_int32_t data) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp0base + offset / 2);
*ptr1=data;
volatile u_int32_t *ptr1;
ptr1 = (u_int32_t *)(csp0base + offset / 2);
*ptr1 = data;
}
u_int32_t bus_r(u_int32_t offset) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp0base + offset / 2);
return *ptr1;
volatile u_int32_t *ptr1;
ptr1 = (u_int32_t *)(csp0base + offset / 2);
return *ptr1;
}
int64_t get64BitReg(int aLSB, int aMSB){
int64_t v64;
u_int32_t vLSB,vMSB;
vLSB=bus_r(aLSB);
vMSB=bus_r(aMSB);
v64=vMSB;
v64=(v64<<32) | vLSB;
LOG(logDEBUG5, (" reg64(%x,%x) %x %x %llx\n", aLSB, aMSB, vLSB, vMSB, (long long unsigned int)v64));
return v64;
int64_t get64BitReg(int aLSB, int aMSB) {
int64_t v64;
u_int32_t vLSB, vMSB;
vLSB = bus_r(aLSB);
vMSB = bus_r(aMSB);
v64 = vMSB;
v64 = (v64 << 32) | vLSB;
LOG(logDEBUG5, (" reg64(%x,%x) %x %x %llx\n", aLSB, aMSB, vLSB, vMSB,
(long long unsigned int)v64));
return v64;
}
int64_t set64BitReg(int64_t value, int aLSB, int aMSB){
int64_t v64;
u_int32_t vLSB,vMSB;
if (value!=-1) {
vLSB=value&(0xffffffff);
bus_w(aLSB,vLSB);
v64=value>> 32;
vMSB=v64&(0xffffffff);
bus_w(aMSB,vMSB);
}
return get64BitReg(aLSB, aMSB);
int64_t set64BitReg(int64_t value, int aLSB, int aMSB) {
int64_t v64;
u_int32_t vLSB, vMSB;
if (value != -1) {
vLSB = value & (0xffffffff);
bus_w(aLSB, vLSB);
v64 = value >> 32;
vMSB = v64 & (0xffffffff);
bus_w(aMSB, vMSB);
}
return get64BitReg(aLSB, aMSB);
}
uint64_t getU64BitReg(int aLSB, int aMSB){
uint64_t retval = bus_r(aMSB);
retval = (retval << 32) | bus_r(aLSB);
return retval;
uint64_t getU64BitReg(int aLSB, int aMSB) {
uint64_t retval = bus_r(aMSB);
retval = (retval << 32) | bus_r(aLSB);
return retval;
}
void setU64BitReg(uint64_t value, int aLSB, int aMSB){
bus_w(aLSB, value & (0xffffffff));
bus_w(aMSB, (value >> 32) & (0xffffffff));
void setU64BitReg(uint64_t value, int aLSB, int aMSB) {
bus_w(aLSB, value & (0xffffffff));
bus_w(aMSB, (value >> 32) & (0xffffffff));
}
u_int32_t readRegister(u_int32_t offset) {
return bus_r(offset << MEM_MAP_SHIFT);
return bus_r(offset << MEM_MAP_SHIFT);
}
u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
bus_w(offset << MEM_MAP_SHIFT, data);
return readRegister(offset);
bus_w(offset << MEM_MAP_SHIFT, data);
return readRegister(offset);
}
u_int32_t readRegister16(u_int32_t offset) {
@ -92,39 +91,37 @@ u_int32_t writeRegister16(u_int32_t offset, u_int32_t data) {
}
int mapCSP0(void) {
// if not mapped
if (csp0base == 0) {
LOG(logINFO, ("Mapping memory\n"));
// if not mapped
if (csp0base == 0) {
LOG(logINFO, ("Mapping memory\n"));
#ifdef VIRTUAL
csp0base = malloc(MEM_SIZE);
if (csp0base == NULL) {
LOG(logERROR, ("Could not allocate virtual memory.\n"));
return FAIL;
}
LOG(logINFO, ("memory allocated\n"));
csp0base = malloc(MEM_SIZE);
if (csp0base == NULL) {
LOG(logERROR, ("Could not allocate virtual memory.\n"));
return FAIL;
}
LOG(logINFO, ("memory allocated\n"));
#else
int fd;
fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
if (fd == -1) {
LOG(logERROR, ("Can't find /dev/mem\n"));
return FAIL;
}
LOG(logDEBUG1, ("/dev/mem opened\n"));
csp0base = mmap(0, MEM_SIZE, PROT_READ|PROT_WRITE, MAP_FILE|MAP_SHARED, fd, CSP0);
if (csp0base == MAP_FAILED) {
LOG(logERROR, ("Can't map memmory area\n"));
return FAIL;
}
int fd;
fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
if (fd == -1) {
LOG(logERROR, ("Can't find /dev/mem\n"));
return FAIL;
}
LOG(logDEBUG1, ("/dev/mem opened\n"));
csp0base = mmap(0, MEM_SIZE, PROT_READ | PROT_WRITE,
MAP_FILE | MAP_SHARED, fd, CSP0);
if (csp0base == MAP_FAILED) {
LOG(logERROR, ("Can't map memmory area\n"));
return FAIL;
}
#endif
LOG(logINFO, ("csp0base mapped from %p to %p\n",
csp0base, (csp0base + MEM_SIZE)));
LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
}else
LOG(logINFO, ("Memory already mapped before\n"));
return OK;
LOG(logINFO, ("csp0base mapped from %p to %p\n", csp0base,
(csp0base + MEM_SIZE)));
LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
} else
LOG(logINFO, ("Memory already mapped before\n"));
return OK;
}
uint32_t* Blackfin_getBaseAddress() {
return csp0base;
}
uint32_t *Blackfin_getBaseAddress() { return csp0base; }

19
slsDetectorServers/slsDetectorServer/src/common.c Executable file → Normal file
View File

@ -2,13 +2,14 @@
#include "clogger.h"
#include "sls_detector_defs.h"
int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin, int outputMax,
int inputValue, int* outputValue) {
int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin,
int outputMax, int inputValue, int *outputValue) {
LOG(logDEBUG1, (" Input Value: %d (Input:(%d - %d), Output:(%d - %d))\n",
inputValue, inputMin, inputMax, outputMin, outputMax));
inputValue, inputMin, inputMax, outputMin, outputMax));
// validate within bounds
// eg. MAX1932 range is v(60 - 200) to dac(255 - 1), here inputMin > inputMax (when dac to voltage)
// eg. MAX1932 range is v(60 - 200) to dac(255 - 1), here inputMin >
// inputMax (when dac to voltage)
int smaller = inputMin;
int bigger = inputMax;
if (smaller > bigger) {
@ -16,13 +17,16 @@ int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin, int outpu
bigger = inputMin;
}
if ((inputValue < smaller) || (inputValue > bigger)) {
LOG(logERROR, ("Input Value is outside bounds (%d to %d): %d\n", smaller, bigger, inputValue));
LOG(logERROR, ("Input Value is outside bounds (%d to %d): %d\n",
smaller, bigger, inputValue));
*outputValue = -1;
return FAIL;
}
double value = ((double)(inputValue - inputMin) * (double)(outputMax - outputMin))
/ (double)(inputMax - inputMin) + outputMin;
double value =
((double)(inputValue - inputMin) * (double)(outputMax - outputMin)) /
(double)(inputMax - inputMin) +
outputMin;
// double to integer conversion (if decimal places, round to integer)
if ((value - (int)value) > 0.0001) {
@ -33,4 +37,3 @@ int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin, int outpu
LOG(logDEBUG1, (" Converted Output Value: %d\n", *outputValue));
return OK;
}

124
slsDetectorServers/slsDetectorServer/src/commonServerFunctions.c Executable file → Normal file
View File

@ -2,97 +2,114 @@
#include "blackfin.h"
#include "clogger.h"
#include <unistd.h> // usleep
#include <unistd.h> // usleep
void SPIChipSelect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask, int convBit) {
LOG(logDEBUG2, ("SPI chip select. valw:0x%08x addr:0x%x csmask:0x%x, clkmask:0x%x digmask:0x%x convbit:%d\n",
*valw, addr, csmask, clkmask, digoutmask, convBit));
void SPIChipSelect(uint32_t *valw, uint32_t addr, uint32_t csmask,
uint32_t clkmask, uint32_t digoutmask, int convBit) {
LOG(logDEBUG2, ("SPI chip select. valw:0x%08x addr:0x%x csmask:0x%x, "
"clkmask:0x%x digmask:0x%x convbit:%d\n",
*valw, addr, csmask, clkmask, digoutmask, convBit));
// start point
if (convBit) {
// needed for the slow adcs for apprx 20 ns before and after rising of convbit (usleep val is vague assumption)
usleep(20);
// clkmask has to be down for conversion to have correct value (for conv bit = 1)
(*valw) = (((bus_r(addr) | csmask) &(~clkmask)) &(~digoutmask));
// needed for the slow adcs for apprx 20 ns before and after rising of
// convbit (usleep val is vague assumption)
usleep(20);
// clkmask has to be down for conversion to have correct value (for conv
// bit = 1)
(*valw) = (((bus_r(addr) | csmask) & (~clkmask)) & (~digoutmask));
} else {
(*valw) = ((bus_r(addr) | csmask | clkmask) &(~digoutmask));
(*valw) = ((bus_r(addr) | csmask | clkmask) & (~digoutmask));
}
bus_w (addr, (*valw));
bus_w(addr, (*valw));
LOG(logDEBUG2, ("startpoint. valw:0x%08x\n", *valw));
// needed for the slow adcs for apprx 10 ns before and after rising of convbit (usleep val is vague assumption)
// needed for the slow adcs for apprx 10 ns before and after rising of
// convbit (usleep val is vague assumption)
if (convBit)
usleep(10);
usleep(10);
// chip sel bar down
(*valw) &= ~csmask;
bus_w (addr, (*valw));
bus_w(addr, (*valw));
LOG(logDEBUG2, ("chip sel bar down. valw:0x%08x\n", *valw));
}
void SPIChipDeselect(uint32_t *valw, uint32_t addr, uint32_t csmask,
uint32_t clkmask, uint32_t digoutmask, int convBit) {
LOG(logDEBUG2, ("SPI chip deselect. valw:0x%08x addr:0x%x csmask:0x%x, "
"clkmask:0x%x digmask:0x%x convbit:%d\n",
*valw, addr, csmask, clkmask, digoutmask, convBit));
void SPIChipDeselect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask, int convBit) {
LOG(logDEBUG2, ("SPI chip deselect. valw:0x%08x addr:0x%x csmask:0x%x, clkmask:0x%x digmask:0x%x convbit:%d\n",
*valw, addr, csmask, clkmask, digoutmask, convBit));
// needed for the slow adcs for apprx 20 ns before and after rising of convbit (usleep val is vague assumption)
// needed for the slow adcs for apprx 20 ns before and after rising of
// convbit (usleep val is vague assumption)
if (convBit)
usleep(20);
usleep(20);
// chip sel bar up
(*valw) |= csmask;
bus_w (addr, (*valw));
bus_w(addr, (*valw));
LOG(logDEBUG2, ("chip sel bar up. valw:0x%08x\n", *valw));
// needed for the slow adcs for apprx 10 ns before and after rising of convbit (usleep val is vague assumption)
// needed for the slow adcs for apprx 10 ns before and after rising of
// convbit (usleep val is vague assumption)
if (convBit)
usleep(10);
usleep(10);
//clk down
// clk down
(*valw) &= ~clkmask;
bus_w (addr, (*valw));
bus_w(addr, (*valw));
LOG(logDEBUG2, ("clk down. valw:0x%08x\n", *valw));
// stop point = start point of course
(*valw) &= ~digoutmask;
// slow adcs use convBit (has to go high and then low) instead of csmask
if (convBit) {
(*valw) &= ~csmask;
(*valw) &= ~csmask;
} else {
(*valw) |= csmask;
(*valw) |= csmask;
}
bus_w (addr, (*valw)); //FIXME: for ctb slow adcs, might need to set it to low again
bus_w(
addr,
(*valw)); // FIXME: for ctb slow adcs, might need to set it to low again
LOG(logDEBUG2, ("stop point. valw:0x%08x\n", *valw));
}
void sendDataToSPI (uint32_t* valw, uint32_t addr, uint32_t val, int numbitstosend, uint32_t clkmask, uint32_t digoutmask, int digofset) {
LOG(logDEBUG2, ("SPI send data. valw:0x%08x addr:0x%x val:0x%x, numbitstosend:%d, clkmask:0x%x digmask:0x%x digofst:%d\n",
*valw, addr, val, numbitstosend, clkmask, digoutmask, digofset));
void sendDataToSPI(uint32_t *valw, uint32_t addr, uint32_t val,
int numbitstosend, uint32_t clkmask, uint32_t digoutmask,
int digofset) {
LOG(logDEBUG2,
("SPI send data. valw:0x%08x addr:0x%x val:0x%x, numbitstosend:%d, "
"clkmask:0x%x digmask:0x%x digofst:%d\n",
*valw, addr, val, numbitstosend, clkmask, digoutmask, digofset));
int i = 0;
for (i = 0; i < numbitstosend; ++i) {
// clk down
(*valw) &= ~clkmask;
bus_w (addr, (*valw));
bus_w(addr, (*valw));
LOG(logDEBUG2, ("clk down. valw:0x%08x\n", *valw));
// write data (i)
(*valw) = (((*valw) & ~digoutmask) + // unset bit
(((val >> (numbitstosend - 1 - i)) & 0x1) << digofset)); // each bit from val starting from msb
bus_w (addr, (*valw));
(*valw) = (((*valw) & ~digoutmask) + // unset bit
(((val >> (numbitstosend - 1 - i)) & 0x1)
<< digofset)); // each bit from val starting from msb
bus_w(addr, (*valw));
LOG(logDEBUG2, ("write data %d. valw:0x%08x\n", i, *valw));
// clk up
(*valw) |= clkmask ;
bus_w (addr, (*valw));
(*valw) |= clkmask;
bus_w(addr, (*valw));
LOG(logDEBUG2, ("clk up. valw:0x%08x\n", *valw));
}
}
uint32_t receiveDataFromSPI (uint32_t* valw, uint32_t addr, int numbitstoreceive, uint32_t clkmask, uint32_t readaddr) {
LOG(logDEBUG2, ("SPI send data. valw:0x%08x addr:0x%x numbitstoreceive:%d, clkmask:0x%x readaddr:0x%x \n",
*valw, addr, numbitstoreceive, clkmask, readaddr));
uint32_t receiveDataFromSPI(uint32_t *valw, uint32_t addr, int numbitstoreceive,
uint32_t clkmask, uint32_t readaddr) {
LOG(logDEBUG2, ("SPI send data. valw:0x%08x addr:0x%x numbitstoreceive:%d, "
"clkmask:0x%x readaddr:0x%x \n",
*valw, addr, numbitstoreceive, clkmask, readaddr));
uint32_t retval = 0;
int i = 0;
@ -101,7 +118,7 @@ uint32_t receiveDataFromSPI (uint32_t* valw, uint32_t addr, int numbitstoreceive
// clk down
(*valw) &= ~clkmask;
bus_w (addr, (*valw));
bus_w(addr, (*valw));
LOG(logDEBUG2, ("clk down. valw:0x%08x\n", *valw));
// read data (i)
@ -111,17 +128,19 @@ uint32_t receiveDataFromSPI (uint32_t* valw, uint32_t addr, int numbitstoreceive
usleep(20);
// clk up
(*valw) |= clkmask ;
bus_w (addr, (*valw));
(*valw) |= clkmask;
bus_w(addr, (*valw));
LOG(logDEBUG2, ("clk up. valw:0x%08x\n", *valw));
usleep(20);
}
return retval;
}
void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask, int numbitstosend, uint32_t clkmask, uint32_t digoutmask, int digofset, int convBit) {
void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask,
int numbitstosend, uint32_t clkmask, uint32_t digoutmask,
int digofset, int convBit) {
if (numbitstosend == 16) {
LOG(logDEBUG2, ("Writing to SPI Register: 0x%04x\n", val));
} else {
@ -129,23 +148,28 @@ void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask, int numbitstos
}
uint32_t valw;
SPIChipSelect (&valw, addr, csmask, clkmask, digoutmask, convBit);
SPIChipSelect(&valw, addr, csmask, clkmask, digoutmask, convBit);
sendDataToSPI(&valw, addr, val, numbitstosend, clkmask, digoutmask, digofset);
sendDataToSPI(&valw, addr, val, numbitstosend, clkmask, digoutmask,
digofset);
SPIChipDeselect(&valw, addr, csmask, clkmask, digoutmask, convBit);
}
uint32_t serializeFromSPI(uint32_t addr, uint32_t csmask, int numbitstoreceive, uint32_t clkmask, uint32_t digoutmask, uint32_t readaddr, int convBit) {
uint32_t serializeFromSPI(uint32_t addr, uint32_t csmask, int numbitstoreceive,
uint32_t clkmask, uint32_t digoutmask,
uint32_t readaddr, int convBit) {
uint32_t valw;
SPIChipSelect (&valw, addr, csmask, clkmask, digoutmask, convBit);
SPIChipSelect(&valw, addr, csmask, clkmask, digoutmask, convBit);
uint32_t retval = receiveDataFromSPI(&valw, addr, numbitstoreceive, clkmask, readaddr);
uint32_t retval =
receiveDataFromSPI(&valw, addr, numbitstoreceive, clkmask, readaddr);
// not needed for conv bit (not a chip select)
//SPIChipDeselect(&valw, addr, csmask, clkmask, digoutmask, convBit); // moving this before bringin up earlier changes temp of slow adc
// SPIChipDeselect(&valw, addr, csmask, clkmask, digoutmask, convBit); //
// moving this before bringin up earlier changes temp of slow adc
if (numbitstoreceive == 16) {
LOG(logDEBUG2, ("Read From SPI Register: 0x%04x\n", retval));

1010
slsDetectorServers/slsDetectorServer/src/communication_funcs.c Executable file → Normal file
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File diff suppressed because it is too large Load Diff

179
slsDetectorServers/slsDetectorServer/src/communication_funcs_UDP.c Executable file → Normal file
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@ -2,111 +2,122 @@
#include "clogger.h"
#include "sls_detector_defs.h"
#include <stdio.h>
#include <stdlib.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <arpa/inet.h>
#include <netinet/in.h>
#include <string.h>
#include <unistd.h>
#include <errno.h>
#include <netdb.h>
#include <netinet/in.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/socket.h>
#include <sys/types.h>
#include <unistd.h>
int udpSockfd[2] = {-1, -1};
struct addrinfo* udpServerAddrInfo[2] = {0, 0};
struct addrinfo *udpServerAddrInfo[2] = {0, 0};
unsigned short int udpDestinationPort[2] = {0, 0};
char udpDestinationIp[2][INET_ADDRSTRLEN] = {"", ""};
//DEFAULT_TX_UDP_PORT;// src port
int getUdPSocketDescriptor(int index) {
return udpSockfd[index];
}
// DEFAULT_TX_UDP_PORT;// src port
int getUdPSocketDescriptor(int index) { return udpSockfd[index]; }
int setUDPDestinationDetails(int index, const char* ip, unsigned short int port) {
udpDestinationPort[index] = port;
size_t len = strlen(ip);
memset(udpDestinationIp[index], 0, INET_ADDRSTRLEN);
strncpy(udpDestinationIp[index], ip, len > INET_ADDRSTRLEN ? INET_ADDRSTRLEN : len );
int setUDPDestinationDetails(int index, const char *ip,
unsigned short int port) {
udpDestinationPort[index] = port;
size_t len = strlen(ip);
memset(udpDestinationIp[index], 0, INET_ADDRSTRLEN);
strncpy(udpDestinationIp[index], ip,
len > INET_ADDRSTRLEN ? INET_ADDRSTRLEN : len);
if (udpServerAddrInfo[index]) {
freeaddrinfo(udpServerAddrInfo[index]);
udpServerAddrInfo[index] = 0;
}
if (udpServerAddrInfo[index]) {
freeaddrinfo(udpServerAddrInfo[index]);
udpServerAddrInfo[index] = 0;
}
// convert ip to internet address
struct addrinfo hints;
memset(&hints, 0, sizeof(hints));
hints.ai_family = AF_INET;
hints.ai_socktype = SOCK_DGRAM;
hints.ai_flags = 0;
hints.ai_protocol = 0;
char sport[100];
memset(sport, 0, 100);
sprintf(sport, "%d", udpDestinationPort[index]);
int err = getaddrinfo(udpDestinationIp[index], sport, &hints, &udpServerAddrInfo[index]);
if (err != 0) {
LOG(logERROR, ("Failed to resolve remote socket address %s at port %d. "
"(Error code:%d, %s)\n", udpDestinationIp[index], udpDestinationPort[index], err, gai_strerror(err)));
return FAIL;
}
if (udpServerAddrInfo[index] == NULL) {
LOG(logERROR, ("Failed to resolve remote socket address %s at port %d "
"(getaddrinfo returned NULL)\n", udpDestinationIp[index], udpDestinationPort[index]));
udpServerAddrInfo[index] = 0;
return FAIL;
}
// convert ip to internet address
struct addrinfo hints;
memset(&hints, 0, sizeof(hints));
hints.ai_family = AF_INET;
hints.ai_socktype = SOCK_DGRAM;
hints.ai_flags = 0;
hints.ai_protocol = 0;
char sport[100];
memset(sport, 0, 100);
sprintf(sport, "%d", udpDestinationPort[index]);
int err = getaddrinfo(udpDestinationIp[index], sport, &hints,
&udpServerAddrInfo[index]);
if (err != 0) {
LOG(logERROR, ("Failed to resolve remote socket address %s at port %d. "
"(Error code:%d, %s)\n",
udpDestinationIp[index], udpDestinationPort[index], err,
gai_strerror(err)));
return FAIL;
}
if (udpServerAddrInfo[index] == NULL) {
LOG(logERROR, ("Failed to resolve remote socket address %s at port %d "
"(getaddrinfo returned NULL)\n",
udpDestinationIp[index], udpDestinationPort[index]));
udpServerAddrInfo[index] = 0;
return FAIL;
}
return OK;
return OK;
}
int createUDPSocket(int index) {
LOG(logDEBUG2, ("Creating UDP Socket %d\n", index));
if (!strlen(udpDestinationIp[index])) {
LOG(logERROR, ("No destination UDP ip specified.\n"));
return FAIL;
}
LOG(logDEBUG2, ("Creating UDP Socket %d\n", index));
if (!strlen(udpDestinationIp[index])) {
LOG(logERROR, ("No destination UDP ip specified.\n"));
return FAIL;
}
if (udpSockfd[index] != -1) {
LOG(logERROR, ("Strange that Udp socket was still open. Closing it to create a new one\n"));
close(udpSockfd[index]);
udpSockfd[index] = -1;
}
if (udpSockfd[index] != -1) {
LOG(logERROR, ("Strange that Udp socket was still open. Closing it to "
"create a new one\n"));
close(udpSockfd[index]);
udpSockfd[index] = -1;
}
// Creating socket file descriptor
udpSockfd[index] = socket(udpServerAddrInfo[index]->ai_family, udpServerAddrInfo[index]->ai_socktype, udpServerAddrInfo[index]->ai_protocol);
if (udpSockfd[index] == -1 ) {
LOG(logERROR, ("UDP socket at port %d failed. (Error code:%d, %s)\n",
udpDestinationPort[index], errno, gai_strerror(errno)));
return FAIL;
}
LOG(logINFO, ("Udp client socket created for server (port %d, ip:%s)\n",
udpDestinationPort[index], udpDestinationIp[index]));
// Creating socket file descriptor
udpSockfd[index] = socket(udpServerAddrInfo[index]->ai_family,
udpServerAddrInfo[index]->ai_socktype,
udpServerAddrInfo[index]->ai_protocol);
if (udpSockfd[index] == -1) {
LOG(logERROR, ("UDP socket at port %d failed. (Error code:%d, %s)\n",
udpDestinationPort[index], errno, gai_strerror(errno)));
return FAIL;
}
LOG(logINFO, ("Udp client socket created for server (port %d, ip:%s)\n",
udpDestinationPort[index], udpDestinationIp[index]));
// Using connect expects that the receiver (udp server) exists to listen to these packets
// connecting allows to use "send/write" instead of "sendto", avoiding checking for server address for each packet
// using write without a connect will end in segv
LOG(logINFO, ("Udp client socket connected\n",
udpDestinationPort[index], udpDestinationIp[index]));
return OK;
// Using connect expects that the receiver (udp server) exists to listen to
// these packets connecting allows to use "send/write" instead of "sendto",
// avoiding checking for server address for each packet using write without
// a connect will end in segv
LOG(logINFO, ("Udp client socket connected\n", udpDestinationPort[index],
udpDestinationIp[index]));
return OK;
}
int sendUDPPacket(int index, const char* buf, int length) {
int n = sendto(udpSockfd[index], buf, length, 0, udpServerAddrInfo[index]->ai_addr, udpServerAddrInfo[index]->ai_addrlen);
// udp sends atomically, no need to handle partial data
if (n == -1) {
LOG(logERROR, ("Could not send udp packet for socket %d. (Error code:%d, %s)\n",
index, n, errno, gai_strerror(errno)));
} else {
LOG(logDEBUG2, ("%d bytes sent\n", n));
}
return n;
int sendUDPPacket(int index, const char *buf, int length) {
int n = sendto(udpSockfd[index], buf, length, 0,
udpServerAddrInfo[index]->ai_addr,
udpServerAddrInfo[index]->ai_addrlen);
// udp sends atomically, no need to handle partial data
if (n == -1) {
LOG(logERROR,
("Could not send udp packet for socket %d. (Error code:%d, %s)\n",
index, n, errno, gai_strerror(errno)));
} else {
LOG(logDEBUG2, ("%d bytes sent\n", n));
}
return n;
}
void closeUDPSocket(int index) {
if (udpSockfd[index] != -1) {
LOG(logINFO, ("Udp client socket closed\n"));
close(udpSockfd[index]);
udpSockfd[index] = -1;
}
if (udpSockfd[index] != -1) {
LOG(logINFO, ("Udp client socket closed\n"));
close(udpSockfd[index]);
udpSockfd[index] = -1;
}
}

89
slsDetectorServers/slsDetectorServer/src/communication_virtual.c Executable file → Normal file
View File

@ -1,120 +1,121 @@
#ifdef VIRTUAL
#include "communication_virtual.h"
#include "communication_virtual.h"
#include "clogger.h"
#include <string.h>
#include <unistd.h> // usleep
#include <unistd.h> // usleep
#define FILE_STATUS "/tmp/sls_virtual_server_status_"
#define FILE_STOP "/tmp/sls_virtual_server_stop_"
#define FD_STATUS 0
#define FD_STOP 1
#define FILE_STATUS "/tmp/sls_virtual_server_status_"
#define FILE_STOP "/tmp/sls_virtual_server_stop_"
#define FD_STATUS 0
#define FD_STOP 1
#define FILE_NAME_LENGTH 1000
FILE* fd[2] = {NULL, NULL};
FILE *fd[2] = {NULL, NULL};
char fnameStatus[FILE_NAME_LENGTH];
char fnameStop[FILE_NAME_LENGTH];
int portNumber = 0;
int ComVirtual_createFiles(const int port) {
portNumber = port;
portNumber = port;
// control server writign status file
memset(fnameStatus, 0, FILE_NAME_LENGTH);
sprintf(fnameStatus, "%s%d", FILE_STATUS, port);
FILE* fd = NULL;
memset(fnameStatus, 0, FILE_NAME_LENGTH);
sprintf(fnameStatus, "%s%d", FILE_STATUS, port);
FILE *fd = NULL;
if (NULL == (fd = fopen(fnameStatus, "w"))) {
LOG(logERROR, ("Could not open the file %s for virtual communication\n",
fnameStatus));
LOG(logERROR, ("Could not open the file %s for virtual communication\n",
fnameStatus));
return 0;
}
fclose(fd);
LOG(logINFOBLUE, ("Created status file %s\n", fnameStatus));
fclose(fd);
LOG(logINFOBLUE, ("Created status file %s\n", fnameStatus));
// stop server writing stop file
// stop server writing stop file
memset(fnameStop, 0, FILE_NAME_LENGTH);
sprintf(fnameStop, "%s%d", FILE_STOP, port);
sprintf(fnameStop, "%s%d", FILE_STOP, port);
if (NULL == (fd = fopen(fnameStop, "w"))) {
LOG(logERROR, ("Could not open the file %s for virtual communication\n",
fnameStop));
LOG(logERROR, ("Could not open the file %s for virtual communication\n",
fnameStop));
return 0;
}
fclose(fd);
LOG(logINFOBLUE, ("Created stop file %s\n", fnameStop));
fclose(fd);
LOG(logINFOBLUE, ("Created stop file %s\n", fnameStop));
return 1;
return 1;
}
void ComVirtual_setFileNames(const int port) {
portNumber = port;
portNumber = port;
memset(fnameStatus, 0, FILE_NAME_LENGTH);
memset(fnameStop, 0, FILE_NAME_LENGTH);
sprintf(fnameStatus, "%s%d", FILE_STATUS, port);
sprintf(fnameStop, "%s%d", FILE_STOP, port);
sprintf(fnameStatus, "%s%d", FILE_STATUS, port);
sprintf(fnameStop, "%s%d", FILE_STOP, port);
}
void ComVirtual_setStatus(int value) {
while (!ComVirtual_writeToFile(value, fnameStatus, "Control")) {
while (!ComVirtual_writeToFile(value, fnameStatus, "Control")) {
usleep(100);
}
}
int ComVirtual_getStatus() {
int retval = 0;
while (!ComVirtual_readFromFile(&retval, fnameStatus, "Stop")) {
while (!ComVirtual_readFromFile(&retval, fnameStatus, "Stop")) {
usleep(100);
}
return retval;
}
void ComVirtual_setStop(int value) {
while (!ComVirtual_writeToFile(value, fnameStop, "Stop")) {
while (!ComVirtual_writeToFile(value, fnameStop, "Stop")) {
usleep(100);
}
}
int ComVirtual_getStop() {
int retval = 0;
while (!ComVirtual_readFromFile(&retval, fnameStop, "Control")) {
while (!ComVirtual_readFromFile(&retval, fnameStop, "Control")) {
usleep(100);
}
return retval;
}
int ComVirtual_writeToFile(int value, const char* fname, const char* serverName) {
FILE* fd = NULL;
int ComVirtual_writeToFile(int value, const char *fname,
const char *serverName) {
FILE *fd = NULL;
if (NULL == (fd = fopen(fname, "w"))) {
LOG(logERROR, ("Vritual %s Server [%d] could not open "
"the file %s for writing\n",
serverName, portNumber, fname));
"the file %s for writing\n",
serverName, portNumber, fname));
return 0;
}
while (fwrite(&value, sizeof(value), 1, fd) < 1) {
LOG(logERROR, ("Vritual %s Server [%d] could not write "
"to file %s\n",
serverName, portNumber, fname));
"to file %s\n",
serverName, portNumber, fname));
return 0;
}
fclose(fd);
return 1;
return 1;
}
int ComVirtual_readFromFile(int* value, const char* fname, const char* serverName) {
FILE* fd = NULL;
int ComVirtual_readFromFile(int *value, const char *fname,
const char *serverName) {
FILE *fd = NULL;
if (NULL == (fd = fopen(fname, "r"))) {
LOG(logERROR, ("Vritual %s Server [%d] could not open "
"the file %s for reading\n",
serverName, portNumber, fname));
"the file %s for reading\n",
serverName, portNumber, fname));
return 0;
}
while (fread(value, sizeof(int), 1, fd) < 1) {
LOG(logERROR, ("Vritual %s Server [%d] could not read "
"from file %s\n",
serverName, portNumber, fname));
"from file %s\n",
serverName, portNumber, fname));
return 0;
}
fclose(fd);
return 1;
return 1;
}
#endif

177
slsDetectorServers/slsDetectorServer/src/nios.c Executable file → Normal file
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@ -1,131 +1,130 @@
#include "nios.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#include "ansi.h"
#include "clogger.h"
#include "sls_detector_defs.h"
#include <fcntl.h> // open
#include <sys/mman.h> // mmap
#include <fcntl.h> // open
#include <sys/mman.h> // mmap
/* global variables */
u_int32_t* csp0base = 0;
u_int32_t *csp0base = 0;
#define CSP0 0x18060000
#define MEM_SIZE 0x100000 //TODO (1804 0000 - 1804 07FF = 800 * 4 = 2000), (1806 0000 = 10000* 4 = 40000)
#define MEM_SIZE \
0x100000 // TODO (1804 0000 - 1804 07FF = 800 * 4 = 2000), (1806 0000 =
// 10000* 4 = 40000)
u_int32_t* csp1base = 0;
u_int32_t *csp1base = 0;
#define CSP1 0x18040000
void bus_w_csp1(u_int32_t offset, u_int32_t data) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp1base + offset/(sizeof(u_int32_t)));
*ptr1=data;
volatile u_int32_t *ptr1;
ptr1 = (u_int32_t *)(csp1base + offset / (sizeof(u_int32_t)));
*ptr1 = data;
}
u_int32_t bus_r_csp1(u_int32_t offset) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp1base + offset/(sizeof(u_int32_t)));
return *ptr1;
volatile u_int32_t *ptr1;
ptr1 = (u_int32_t *)(csp1base + offset / (sizeof(u_int32_t)));
return *ptr1;
}
void bus_w(u_int32_t offset, u_int32_t data) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp0base + offset/(sizeof(u_int32_t)));
*ptr1=data;
volatile u_int32_t *ptr1;
ptr1 = (u_int32_t *)(csp0base + offset / (sizeof(u_int32_t)));
*ptr1 = data;
}
u_int32_t bus_r(u_int32_t offset) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp0base + offset/(sizeof(u_int32_t)));
return *ptr1;
volatile u_int32_t *ptr1;
ptr1 = (u_int32_t *)(csp0base + offset / (sizeof(u_int32_t)));
return *ptr1;
}
int64_t get64BitReg(int aLSB, int aMSB){
int64_t v64;
u_int32_t vLSB,vMSB;
vLSB=bus_r(aLSB);
vMSB=bus_r(aMSB);
v64=vMSB;
v64=(v64<<32) | vLSB;
LOG(logDEBUG5, (" reg64(%x,%x) %x %x %llx\n", aLSB, aMSB, vLSB, vMSB, (long long unsigned int)v64));
return v64;
int64_t get64BitReg(int aLSB, int aMSB) {
int64_t v64;
u_int32_t vLSB, vMSB;
vLSB = bus_r(aLSB);
vMSB = bus_r(aMSB);
v64 = vMSB;
v64 = (v64 << 32) | vLSB;
LOG(logDEBUG5, (" reg64(%x,%x) %x %x %llx\n", aLSB, aMSB, vLSB, vMSB,
(long long unsigned int)v64));
return v64;
}
int64_t set64BitReg(int64_t value, int aLSB, int aMSB){
int64_t v64;
u_int32_t vLSB,vMSB;
if (value!=-1) {
vLSB=value&(0xffffffff);
bus_w(aLSB,vLSB);
v64=value>> 32;
vMSB=v64&(0xffffffff);
bus_w(aMSB,vMSB);
}
return get64BitReg(aLSB, aMSB);
int64_t set64BitReg(int64_t value, int aLSB, int aMSB) {
int64_t v64;
u_int32_t vLSB, vMSB;
if (value != -1) {
vLSB = value & (0xffffffff);
bus_w(aLSB, vLSB);
v64 = value >> 32;
vMSB = v64 & (0xffffffff);
bus_w(aMSB, vMSB);
}
return get64BitReg(aLSB, aMSB);
}
uint64_t getU64BitReg(int aLSB, int aMSB){
uint64_t retval = bus_r(aMSB);
retval = (retval << 32) | bus_r(aLSB);
return retval;
uint64_t getU64BitReg(int aLSB, int aMSB) {
uint64_t retval = bus_r(aMSB);
retval = (retval << 32) | bus_r(aLSB);
return retval;
}
void setU64BitReg(uint64_t value, int aLSB, int aMSB){
bus_w(aLSB, value & (0xffffffff));
bus_w(aMSB, (value >> 32) & (0xffffffff));
void setU64BitReg(uint64_t value, int aLSB, int aMSB) {
bus_w(aLSB, value & (0xffffffff));
bus_w(aMSB, (value >> 32) & (0xffffffff));
}
u_int32_t readRegister(u_int32_t offset) {
return bus_r(offset);
}
u_int32_t readRegister(u_int32_t offset) { return bus_r(offset); }
u_int32_t writeRegister(u_int32_t offset, u_int32_t data) {
bus_w(offset, data);
return readRegister(offset);
bus_w(offset, data);
return readRegister(offset);
}
int mapCSP0(void) {
u_int32_t csps[2] = {CSP0, CSP1};
u_int32_t** cspbases[2] = {&csp0base, &csp1base};
char names[2][10]={"csp0base","csp1base"};
u_int32_t csps[2] = {CSP0, CSP1};
u_int32_t **cspbases[2] = {&csp0base, &csp1base};
char names[2][10] = {"csp0base", "csp1base"};
int i = 0;
for (i = 0; i < 2; ++i) {
// if not mapped
if (*cspbases[i] == 0) {
LOG(logINFO, ("Mapping memory for %s\n", names[i]));
int i = 0;
for (i = 0; i < 2; ++i) {
// if not mapped
if (*cspbases[i] == 0) {
LOG(logINFO, ("Mapping memory for %s\n", names[i]));
#ifdef VIRTUAL
*cspbases[i] = malloc(MEM_SIZE);
if (*cspbases[i] == NULL) {
LOG(logERROR, ("Could not allocate virtual memory for %s.\n", names[i]));
return FAIL;
}
LOG(logINFO, ("memory allocated for %s\n", names[i]));
*cspbases[i] = malloc(MEM_SIZE);
if (*cspbases[i] == NULL) {
LOG(logERROR,
("Could not allocate virtual memory for %s.\n", names[i]));
return FAIL;
}
LOG(logINFO, ("memory allocated for %s\n", names[i]));
#else
int fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
if (fd == -1) {
LOG(logERROR, ("Can't find /dev/mem for %s\n", names[i]));
return FAIL;
}
LOG(logDEBUG1, ("/dev/mem opened for %s, (CSP:0x%x)\n", names[i], csps[i]));
*cspbases[i] = (u_int32_t*)mmap(0, MEM_SIZE, PROT_READ|PROT_WRITE, MAP_FILE|MAP_SHARED, fd, csps[i]);
if (*cspbases[i] == MAP_FAILED) {
LOG(logERROR, ("Can't map memmory area for %s\n", names[i]));
return FAIL;
}
int fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
if (fd == -1) {
LOG(logERROR, ("Can't find /dev/mem for %s\n", names[i]));
return FAIL;
}
LOG(logDEBUG1,
("/dev/mem opened for %s, (CSP:0x%x)\n", names[i], csps[i]));
*cspbases[i] =
(u_int32_t *)mmap(0, MEM_SIZE, PROT_READ | PROT_WRITE,
MAP_FILE | MAP_SHARED, fd, csps[i]);
if (*cspbases[i] == MAP_FAILED) {
LOG(logERROR, ("Can't map memmory area for %s\n", names[i]));
return FAIL;
}
#endif
LOG(logINFO, ("%s mapped from %p to %p,(CSP:0x%x) \n",
names[i], *cspbases[i], *cspbases[i]+MEM_SIZE, csps[i]));
//LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
} else
LOG(logINFO, ("Memory %s already mapped before\n", names[i]));
}
return OK;
LOG(logINFO, ("%s mapped from %p to %p,(CSP:0x%x) \n", names[i],
*cspbases[i], *cspbases[i] + MEM_SIZE, csps[i]));
// LOG(logINFO, ("Status Register: %08x\n", bus_r(STATUS_REG)));
} else
LOG(logINFO, ("Memory %s already mapped before\n", names[i]));
}
return OK;
}
u_int32_t* Nios_getBaseAddress() {
return csp0base;
}
u_int32_t *Nios_getBaseAddress() { return csp0base; }

207
slsDetectorServers/slsDetectorServer/src/programFpgaBlackfin.c Executable file → Normal file
View File

@ -3,139 +3,142 @@
#include "clogger.h"
#include "slsDetectorServer_defs.h"
#include <unistd.h> // usleep
#include <string.h>
#include <unistd.h> // usleep
/* global variables */
#define MTDSIZE 10
#define MTDSIZE 10
int gpioDefined = 0;
char mtdvalue[MTDSIZE] = {0};
void defineGPIOpins(){
if (!gpioDefined) {
//define the gpio pins
system("echo 7 > /sys/class/gpio/export");
system("echo 9 > /sys/class/gpio/export");
//define their direction
system("echo in > /sys/class/gpio/gpio7/direction");
system("echo out > /sys/class/gpio/gpio9/direction");
LOG(logINFO, ("gpio pins defined\n"));
gpioDefined = 1;
}else LOG(logDEBUG1, ("gpio pins already defined earlier\n"));
void defineGPIOpins() {
if (!gpioDefined) {
// define the gpio pins
system("echo 7 > /sys/class/gpio/export");
system("echo 9 > /sys/class/gpio/export");
// define their direction
system("echo in > /sys/class/gpio/gpio7/direction");
system("echo out > /sys/class/gpio/gpio9/direction");
LOG(logINFO, ("gpio pins defined\n"));
gpioDefined = 1;
} else
LOG(logDEBUG1, ("gpio pins already defined earlier\n"));
}
void FPGAdontTouchFlash(){
//tell FPGA to not touch flash
system("echo 0 > /sys/class/gpio/gpio9/value");
//usleep(100*1000);
void FPGAdontTouchFlash() {
// tell FPGA to not touch flash
system("echo 0 > /sys/class/gpio/gpio9/value");
// usleep(100*1000);
}
void FPGATouchFlash(){
//tell FPGA to touch flash to program itself
system("echo 1 > /sys/class/gpio/gpio9/value");
void FPGATouchFlash() {
// tell FPGA to touch flash to program itself
system("echo 1 > /sys/class/gpio/gpio9/value");
}
void resetFPGA(){
void resetFPGA() {
LOG(logINFOBLUE, ("Reseting FPGA\n"));
FPGAdontTouchFlash();
FPGATouchFlash();
usleep(CTRL_SRVR_INIT_TIME_US);
FPGAdontTouchFlash();
FPGATouchFlash();
usleep(CTRL_SRVR_INIT_TIME_US);
}
void eraseFlash(){
void eraseFlash() {
LOG(logDEBUG1, ("Erasing Flash\n"));
char command[255];
memset(command, 0, 255);
sprintf(command,"flash_eraseall %s",mtdvalue);
system(command);
LOG(logINFO, ("Flash erased\n"));
char command[255];
memset(command, 0, 255);
sprintf(command, "flash_eraseall %s", mtdvalue);
system(command);
LOG(logINFO, ("Flash erased\n"));
}
int startWritingFPGAprogram(FILE** filefp){
int startWritingFPGAprogram(FILE **filefp) {
LOG(logDEBUG1, ("Start Writing of FPGA program\n"));
//getting the drive
//root:/> cat /proc/mtd
//dev: size erasesize name
//mtd0: 00040000 00020000 "bootloader(nor)"
//mtd1: 00100000 00020000 "linux kernel(nor)"
//mtd2: 002c0000 00020000 "file system(nor)"
//mtd3: 01000000 00010000 "bitfile(spi)"
char output[255];
memset(output, 0, 255);
FILE* fp = popen("awk \'$4== \"\\\"bitfile(spi)\\\"\" {print $1}\' /proc/mtd", "r");
if (fp == NULL) {
LOG(logERROR, ("popen returned NULL. Need that to get mtd drive.\n"));
return 1;
}
if (fgets(output, sizeof(output), fp) == NULL) {
LOG(logERROR, ("fgets returned NULL. Need that to get mtd drive.\n"));
return 1;
}
pclose(fp);
memset(mtdvalue, 0, MTDSIZE);
strcpy(mtdvalue,"/dev/");
char* pch = strtok(output,":");
if(pch == NULL){
LOG(logERROR, ("Could not get mtd value\n"));
return 1;
}
strcat(mtdvalue,pch);
LOG(logINFO, ("Flash drive found: %s\n", mtdvalue));
// getting the drive
// root:/> cat /proc/mtd
// dev: size erasesize name
// mtd0: 00040000 00020000 "bootloader(nor)"
// mtd1: 00100000 00020000 "linux kernel(nor)"
// mtd2: 002c0000 00020000 "file system(nor)"
// mtd3: 01000000 00010000 "bitfile(spi)"
char output[255];
memset(output, 0, 255);
FILE *fp = popen(
"awk \'$4== \"\\\"bitfile(spi)\\\"\" {print $1}\' /proc/mtd", "r");
if (fp == NULL) {
LOG(logERROR, ("popen returned NULL. Need that to get mtd drive.\n"));
return 1;
}
if (fgets(output, sizeof(output), fp) == NULL) {
LOG(logERROR, ("fgets returned NULL. Need that to get mtd drive.\n"));
return 1;
}
pclose(fp);
memset(mtdvalue, 0, MTDSIZE);
strcpy(mtdvalue, "/dev/");
char *pch = strtok(output, ":");
if (pch == NULL) {
LOG(logERROR, ("Could not get mtd value\n"));
return 1;
}
strcat(mtdvalue, pch);
LOG(logINFO, ("Flash drive found: %s\n", mtdvalue));
FPGAdontTouchFlash();
FPGAdontTouchFlash();
//writing the program to flash
*filefp = fopen(mtdvalue, "w");
if(*filefp == NULL){
LOG(logERROR, ("Unable to open %s in write mode\n", mtdvalue));
return 1;
}
LOG(logINFO, ("Flash ready for writing\n"));
// writing the program to flash
*filefp = fopen(mtdvalue, "w");
if (*filefp == NULL) {
LOG(logERROR, ("Unable to open %s in write mode\n", mtdvalue));
return 1;
}
LOG(logINFO, ("Flash ready for writing\n"));
return 0;
return 0;
}
void stopWritingFPGAprogram(FILE* filefp){
void stopWritingFPGAprogram(FILE *filefp) {
LOG(logDEBUG1, ("Stopping of writing FPGA program\n"));
int wait = 0;
if(filefp!= NULL){
fclose(filefp);
wait = 1;
}
int wait = 0;
if (filefp != NULL) {
fclose(filefp);
wait = 1;
}
//touch and program
FPGATouchFlash();
// touch and program
FPGATouchFlash();
if(wait){
LOG(logDEBUG1, ("Waiting for FPGA to program from flash\n"));
//waiting for success or done
char output[255];
int res=0;
while(res == 0){
FILE* sysFile = popen("cat /sys/class/gpio/gpio7/value", "r");
fgets(output, sizeof(output), sysFile);
pclose(sysFile);
sscanf(output,"%d",&res);
LOG(logDEBUG1, ("gpi07 returned %d\n", res));
}
}
LOG(logINFO, ("FPGA has picked up the program from flash\n"));
if (wait) {
LOG(logDEBUG1, ("Waiting for FPGA to program from flash\n"));
// waiting for success or done
char output[255];
int res = 0;
while (res == 0) {
FILE *sysFile = popen("cat /sys/class/gpio/gpio7/value", "r");
fgets(output, sizeof(output), sysFile);
pclose(sysFile);
sscanf(output, "%d", &res);
LOG(logDEBUG1, ("gpi07 returned %d\n", res));
}
}
LOG(logINFO, ("FPGA has picked up the program from flash\n"));
}
int writeFPGAProgram(char* fpgasrc, uint64_t fsize, FILE* filefp){
LOG(logDEBUG1, ("Writing of FPGA Program\n"
"\taddress of fpgasrc:%p\n"
"\tfsize:%llu\n\tpointer:%p\n",
(void *)fpgasrc, (long long unsigned int)fsize, (void*)filefp));
int writeFPGAProgram(char *fpgasrc, uint64_t fsize, FILE *filefp) {
LOG(logDEBUG1,
("Writing of FPGA Program\n"
"\taddress of fpgasrc:%p\n"
"\tfsize:%llu\n\tpointer:%p\n",
(void *)fpgasrc, (long long unsigned int)fsize, (void *)filefp));
if(fwrite((void*)fpgasrc , sizeof(char) , fsize , filefp )!= fsize){
LOG(logERROR, ("Could not write FPGA source to flash (size:%llu)\n", (long long unsigned int)fsize));
return 1;
}
LOG(logDEBUG1, ("program written to flash\n"));
return 0;
if (fwrite((void *)fpgasrc, sizeof(char), fsize, filefp) != fsize) {
LOG(logERROR, ("Could not write FPGA source to flash (size:%llu)\n",
(long long unsigned int)fsize));
return 1;
}
LOG(logDEBUG1, ("program written to flash\n"));
return 0;
}

222
slsDetectorServers/slsDetectorServer/src/programFpgaNios.c Executable file → Normal file
View File

@ -3,150 +3,154 @@
#include "clogger.h"
#include "slsDetectorServer_defs.h"
#include <unistd.h> // usleep
#include <string.h>
#include <unistd.h> // usleep
/* global variables */
#define MTDSIZE 10
#define MTDSIZE 10
char mtdvalue[MTDSIZE] = {0};
#define NOTIFICATION_FILE "/tmp/block_shutdown"
#define MICROCONTROLLER_FILE "/dev/ttyAL0"
#define NOTIFICATION_FILE "/tmp/block_shutdown"
#define MICROCONTROLLER_FILE "/dev/ttyAL0"
void NotifyServerStartSuccess() {
LOG(logINFOBLUE, ("Server started successfully\n"));
char command[255];
memset(command, 0, 255);
sprintf(command,"echo r > %s",MICROCONTROLLER_FILE);
system(command);
char command[255];
memset(command, 0, 255);
sprintf(command, "echo r > %s", MICROCONTROLLER_FILE);
system(command);
}
void CreateNotificationForCriticalTasks() {
FILE* fd = fopen(NOTIFICATION_FILE, "r");
if (fd == NULL) {
fd = fopen(NOTIFICATION_FILE, "w");
if (fd == NULL) {
LOG(logERROR, ("Could not create notication file: %s\n", NOTIFICATION_FILE));
return;
}
LOG(logINFOBLUE, ("Created notification file: %s\n", NOTIFICATION_FILE));
}
fclose(fd);
NotifyCriticalTaskDone();
FILE *fd = fopen(NOTIFICATION_FILE, "r");
if (fd == NULL) {
fd = fopen(NOTIFICATION_FILE, "w");
if (fd == NULL) {
LOG(logERROR,
("Could not create notication file: %s\n", NOTIFICATION_FILE));
return;
}
LOG(logINFOBLUE,
("Created notification file: %s\n", NOTIFICATION_FILE));
}
fclose(fd);
NotifyCriticalTaskDone();
}
void NotifyCriticalTask() {
LOG(logINFO, ("\tNotifying Critical Task Ongoing\n"));
char command[255];
memset(command, 0, 255);
sprintf(command,"echo 1 > %s",NOTIFICATION_FILE);
system(command);
char command[255];
memset(command, 0, 255);
sprintf(command, "echo 1 > %s", NOTIFICATION_FILE);
system(command);
}
void NotifyCriticalTaskDone() {
LOG(logINFO, ("\tNotifying Critical Task Done\n"));
char command[255];
memset(command, 0, 255);
sprintf(command,"echo 0 > %s",NOTIFICATION_FILE);
system(command);
char command[255];
memset(command, 0, 255);
sprintf(command, "echo 0 > %s", NOTIFICATION_FILE);
system(command);
}
void rebootControllerAndFPGA() {
LOG(logDEBUG1, ("Reseting FPGA...\n"));
char command[255];
memset(command, 0, 255);
sprintf(command,"echo z > %s",MICROCONTROLLER_FILE);
system(command);
char command[255];
memset(command, 0, 255);
sprintf(command, "echo z > %s", MICROCONTROLLER_FILE);
system(command);
}
int findFlash(char* mess) {
LOG(logDEBUG1, ("Finding flash drive...\n"));
//getting the drive
// # cat /proc/mtd
// dev: size erasesize name
// mtd0: 00580000 00010000 "qspi BootInfo + Factory Image"
// mtd1: 00580000 00010000 "qspi Application Image"
// mtd2: 00800000 00010000 "qspi Linux Kernel with initramfs"
// mtd3: 00800000 00010000 "qspi Linux Kernel with initramfs Backup"
// mtd4: 02500000 00010000 "qspi ubi filesystem"
// mtd5: 04000000 00010000 "qspi Complete Flash"
char output[255];
memset(output, 0, 255);
FILE* fp = popen("awk \'$5== \"Application\" {print $1}\' /proc/mtd", "r");
if (fp == NULL) {
strcpy(mess, "popen returned NULL. Need that to get mtd drive.\n");
LOG(logERROR, (mess));
return RO_TRIGGER_IN_FALLING_EDGE;
}
if (fgets(output, sizeof(output), fp) == NULL) {
strcpy(mess, "fgets returned NULL. Need that to get mtd drive.\n");
LOG(logERROR, (mess));
return FAIL;
}
pclose(fp);
memset(mtdvalue, 0, MTDSIZE);
strcpy(mtdvalue, "/dev/");
char* pch = strtok(output, ":");
if (pch == NULL){
strcpy (mess, "Could not get mtd value\n");
LOG(logERROR, (mess));
return FAIL;
}
strcat(mtdvalue, pch);
LOG(logINFO, ("\tFlash drive found: %s\n", mtdvalue));
return OK;
int findFlash(char *mess) {
LOG(logDEBUG1, ("Finding flash drive...\n"));
// getting the drive
// # cat /proc/mtd
// dev: size erasesize name
// mtd0: 00580000 00010000 "qspi BootInfo + Factory Image"
// mtd1: 00580000 00010000 "qspi Application Image"
// mtd2: 00800000 00010000 "qspi Linux Kernel with initramfs"
// mtd3: 00800000 00010000 "qspi Linux Kernel with initramfs Backup"
// mtd4: 02500000 00010000 "qspi ubi filesystem"
// mtd5: 04000000 00010000 "qspi Complete Flash"
char output[255];
memset(output, 0, 255);
FILE *fp = popen("awk \'$5== \"Application\" {print $1}\' /proc/mtd", "r");
if (fp == NULL) {
strcpy(mess, "popen returned NULL. Need that to get mtd drive.\n");
LOG(logERROR, (mess));
return RO_TRIGGER_IN_FALLING_EDGE;
}
if (fgets(output, sizeof(output), fp) == NULL) {
strcpy(mess, "fgets returned NULL. Need that to get mtd drive.\n");
LOG(logERROR, (mess));
return FAIL;
}
pclose(fp);
memset(mtdvalue, 0, MTDSIZE);
strcpy(mtdvalue, "/dev/");
char *pch = strtok(output, ":");
if (pch == NULL) {
strcpy(mess, "Could not get mtd value\n");
LOG(logERROR, (mess));
return FAIL;
}
strcat(mtdvalue, pch);
LOG(logINFO, ("\tFlash drive found: %s\n", mtdvalue));
return OK;
}
void eraseFlash() {
LOG(logDEBUG1, ("Erasing Flash...\n"));
char command[255];
memset(command, 0, 255);
sprintf(command,"flash_erase %s 0 0",mtdvalue);
system(command);
LOG(logINFO, ("\tFlash erased\n"));
char command[255];
memset(command, 0, 255);
sprintf(command, "flash_erase %s 0 0", mtdvalue);
system(command);
LOG(logINFO, ("\tFlash erased\n"));
}
int eraseAndWriteToFlash(char* mess, char* fpgasrc, uint64_t fsize) {
if (findFlash(mess) == FAIL) {
return FAIL;
}
NotifyCriticalTask();
eraseFlash();
int eraseAndWriteToFlash(char *mess, char *fpgasrc, uint64_t fsize) {
if (findFlash(mess) == FAIL) {
return FAIL;
}
NotifyCriticalTask();
eraseFlash();
// open file pointer to flash
FILE *filefp = fopen(mtdvalue, "w");
if(filefp == NULL){
NotifyCriticalTaskDone();
sprintf (mess, "Unable to open %s in write mode\n", mtdvalue);
LOG(logERROR, (mess));
return FAIL;
}
LOG(logINFO, ("\tFlash ready for writing\n"));
// open file pointer to flash
FILE *filefp = fopen(mtdvalue, "w");
if (filefp == NULL) {
NotifyCriticalTaskDone();
sprintf(mess, "Unable to open %s in write mode\n", mtdvalue);
LOG(logERROR, (mess));
return FAIL;
}
LOG(logINFO, ("\tFlash ready for writing\n"));
// write to flash
if (writeFPGAProgram(mess, fpgasrc, fsize, filefp) == FAIL) {
NotifyCriticalTaskDone();
fclose(filefp);
return FAIL;
}
// write to flash
if (writeFPGAProgram(mess, fpgasrc, fsize, filefp) == FAIL) {
NotifyCriticalTaskDone();
fclose(filefp);
return FAIL;
}
fclose(filefp);
NotifyCriticalTaskDone();
return OK;
fclose(filefp);
NotifyCriticalTaskDone();
return OK;
}
int writeFPGAProgram(char* mess, char* fpgasrc, uint64_t fsize, FILE* filefp) {
int writeFPGAProgram(char *mess, char *fpgasrc, uint64_t fsize, FILE *filefp) {
LOG(logDEBUG1, ("Writing to flash...\n"
"\taddress of fpgasrc:%p\n"
"\tfsize:%lu\n\tpointer:%p\n",
(void *)fpgasrc, fsize, (void*)filefp));
"\taddress of fpgasrc:%p\n"
"\tfsize:%lu\n\tpointer:%p\n",
(void *)fpgasrc, fsize, (void *)filefp));
uint64_t retval = fwrite((void*)fpgasrc , sizeof(char) , fsize , filefp);
if (retval != fsize) {
sprintf (mess, "Could not write FPGA source to flash (size:%llu), write %llu\n", (long long unsigned int) fsize, (long long unsigned int)retval);
LOG(logERROR, (mess));
return FAIL;
}
LOG(logINFO, ("\tProgram written to flash\n"));
return OK;
uint64_t retval = fwrite((void *)fpgasrc, sizeof(char), fsize, filefp);
if (retval != fsize) {
sprintf(
mess,
"Could not write FPGA source to flash (size:%llu), write %llu\n",
(long long unsigned int)fsize, (long long unsigned int)retval);
LOG(logERROR, (mess));
return FAIL;
}
LOG(logINFO, ("\tProgram written to flash\n"));
return OK;
}

471
slsDetectorServers/slsDetectorServer/src/readDefaultPattern.c Executable file → Normal file
View File

@ -1,8 +1,8 @@
#include "readDefaultPattern.h"
#include "sls_detector_defs.h"
#include "slsDetectorServer_defs.h"
#include "ansi.h"
#include "clogger.h"
#include "slsDetectorServer_defs.h"
#include "sls_detector_defs.h"
#include <string.h>
@ -14,24 +14,23 @@ extern uint64_t writePatternClkControl(uint64_t word);
extern uint64_t writePatternWord(int addr, uint64_t word);
extern int setPatternWaitAddress(int level, int addr);
extern uint64_t setPatternWaitTime(int level, uint64_t t);
extern void setPatternLoop(int level, int *startAddr, int *stopAddr, int *nLoop);
extern void setPatternLoop(int level, int *startAddr, int *stopAddr,
int *nLoop);
int loadDefaultPattern(char *fname) {
if (initError == FAIL) {
return initError;
}
int loadDefaultPattern(char* fname) {
if (initError == FAIL) {
return initError;
}
FILE* fd = fopen(fname, "r");
if(fd == NULL) {
sprintf(initErrorMessage, "Could not open pattern file [%s].\n", fname);
initError = FAIL;
LOG(logERROR, ("%s\n\n", initErrorMessage));
FILE *fd = fopen(fname, "r");
if (fd == NULL) {
sprintf(initErrorMessage, "Could not open pattern file [%s].\n", fname);
initError = FAIL;
LOG(logERROR, ("%s\n\n", initErrorMessage));
return FAIL;
}
LOG(logINFOBLUE, ("Reading default pattern file %s\n", fname));
// Initialization
const size_t LZ = 256;
char line[LZ];
@ -41,61 +40,63 @@ int loadDefaultPattern(char* fname) {
// keep reading a line
while (fgets(line, LZ, fd)) {
// ignore comments
// ignore comments
if (line[0] == '#') {
LOG(logDEBUG1, ("Ignoring Comment\n"));
LOG(logDEBUG1, ("Ignoring Comment\n"));
continue;
}
}
// ignore empty lines
if (strlen(line) <= 1) {
LOG(logDEBUG1, ("Ignoring Empty line\n"));
continue;
}
// ignore empty lines
if (strlen(line) <= 1) {
LOG(logDEBUG1, ("Ignoring Empty line\n"));
continue;
}
// removing leading spaces
if (line[0] == ' ' || line[0] == '\t') {
int len = strlen(line);
// find first valid character
int i = 0;
for (i = 0; i < len; ++i) {
if (line[i] != ' ' && line[i] != '\t') {
break;
}
}
// ignore the line full of spaces (last char \n)
if (i >= len - 1) {
LOG(logDEBUG1, ("Ignoring line full of spaces\n"));
continue;
}
// copying only valid char
char temp[LZ];
memset(temp, 0, LZ);
memcpy(temp, line + i, strlen(line) - i);
memset(line, 0, LZ);
memcpy(line, temp, strlen(temp));
LOG(logDEBUG1, ("Removing leading spaces.\n"));
}
LOG(logDEBUG1, ("Command to process: (size:%d) %.*s\n",
strlen(line), strlen(line) -1, line));
memset(command, 0, LZ);
// removing leading spaces
if (line[0] == ' ' || line[0] == '\t') {
int len = strlen(line);
// find first valid character
int i = 0;
for (i = 0; i < len; ++i) {
if (line[i] != ' ' && line[i] != '\t') {
break;
}
}
// ignore the line full of spaces (last char \n)
if (i >= len - 1) {
LOG(logDEBUG1, ("Ignoring line full of spaces\n"));
continue;
}
// copying only valid char
char temp[LZ];
memset(temp, 0, LZ);
memcpy(temp, line + i, strlen(line) - i);
memset(line, 0, LZ);
memcpy(line, temp, strlen(temp));
LOG(logDEBUG1, ("Removing leading spaces.\n"));
}
LOG(logDEBUG1, ("Command to process: (size:%d) %.*s\n", strlen(line),
strlen(line) - 1, line));
memset(command, 0, LZ);
// patword
if (!strncmp(line, "patword", strlen("patword"))) {
if (!strncmp(line, "patword", strlen("patword"))) {
uint32_t addr = 0;
uint64_t word = 0;
// cannot scan values
// cannot scan values
#ifdef VIRTUAL
if (sscanf(line, "%s 0x%x 0x%lx", command, &addr, &word) != 3) {
if (sscanf(line, "%s 0x%x 0x%lx", command, &addr, &word) != 3) {
#else
if (sscanf(line, "%s 0x%x 0x%llx", command, &addr, &word) != 3) {
if (sscanf(line, "%s 0x%x 0x%llx", command, &addr, &word) != 3) {
#endif
sprintf(initErrorMessage, "Could not scan patword arguments from default "
"pattern file. Line:[%s].\n", line);
break;
}
sprintf(initErrorMessage,
"Could not scan patword arguments from default "
"pattern file. Line:[%s].\n",
line);
break;
}
if (default_writePatternWord(line, addr, word) == FAIL) {
break;
@ -103,19 +104,21 @@ int loadDefaultPattern(char* fname) {
}
// patioctrl
if (!strncmp(line, "patioctrl", strlen("patioctrl"))) {
if (!strncmp(line, "patioctrl", strlen("patioctrl"))) {
uint64_t arg = 0;
// cannot scan values
// cannot scan values
#ifdef VIRTUAL
if (sscanf(line, "%s 0x%lx", command, &arg) != 2) {
if (sscanf(line, "%s 0x%lx", command, &arg) != 2) {
#else
if (sscanf(line, "%s 0x%llx", command, &arg) != 2) {
if (sscanf(line, "%s 0x%llx", command, &arg) != 2) {
#endif
sprintf(initErrorMessage, "Could not scan patioctrl arguments from default "
"pattern file. Line:[%s].\n", line);
break;
}
sprintf(initErrorMessage,
"Could not scan patioctrl arguments from default "
"pattern file. Line:[%s].\n",
line);
break;
}
if (default_writePatternIOControl(line, arg) == FAIL) {
break;
@ -123,19 +126,21 @@ int loadDefaultPattern(char* fname) {
}
// patclkctrl
if (!strncmp(line, "patclkctrl", strlen("patclkctrl"))) {
if (!strncmp(line, "patclkctrl", strlen("patclkctrl"))) {
uint64_t arg = 0;
// cannot scan values
// cannot scan values
#ifdef VIRTUAL
if (sscanf(line, "%s 0x%lx", command, &arg) != 2) {
if (sscanf(line, "%s 0x%lx", command, &arg) != 2) {
#else
if (sscanf(line, "%s 0x%llx", command, &arg) != 2) {
if (sscanf(line, "%s 0x%llx", command, &arg) != 2) {
#endif
sprintf(initErrorMessage, "Could not scan patclkctrl arguments from default "
"pattern file. Line:[%s].\n", line);
break;
}
sprintf(initErrorMessage,
"Could not scan patclkctrl arguments from default "
"pattern file. Line:[%s].\n",
line);
break;
}
if (default_writePatternClkControl(line, arg) == FAIL) {
break;
@ -143,27 +148,31 @@ int loadDefaultPattern(char* fname) {
}
// patlimits
if (!strncmp(line, "patlimits", strlen("patlimits"))) {
if (!strncmp(line, "patlimits", strlen("patlimits"))) {
uint32_t startAddr = 0;
uint32_t stopAddr = 0;
// cannot scan values
if (sscanf(line, "%s 0x%x 0x%x", command, &startAddr, &stopAddr) != 3) {
sprintf(initErrorMessage, "Could not scan patlimits arguments from default "
"pattern file. Line:[%s].\n", line);
break;
}
// cannot scan values
if (sscanf(line, "%s 0x%x 0x%x", command, &startAddr, &stopAddr) !=
3) {
sprintf(initErrorMessage,
"Could not scan patlimits arguments from default "
"pattern file. Line:[%s].\n",
line);
break;
}
if (default_setPatternLoopLimits(line, startAddr, stopAddr) == FAIL) {
if (default_setPatternLoopLimits(line, startAddr, stopAddr) ==
FAIL) {
break;
}
}
// patloop
if ((!strncmp(line, "patloop0", strlen("patloop0"))) ||
if ((!strncmp(line, "patloop0", strlen("patloop0"))) ||
(!strncmp(line, "patloop1", strlen("patloop1"))) ||
(!strncmp(line, "patloop2", strlen("patloop2")))) {
// level
int level = -1;
if (!strncmp(line, "patloop0", strlen("patloop0"))) {
@ -176,23 +185,27 @@ int loadDefaultPattern(char* fname) {
uint32_t startAddr = 0;
uint32_t stopAddr = 0;
// cannot scan values
if (sscanf(line, "%s 0x%x 0x%x", command, &startAddr, &stopAddr) != 3) {
sprintf(initErrorMessage, "Could not scan patloop%d arguments from default "
"pattern file. Line:[%s].\n", level, line);
break;
}
if (default_setPatternLoopAddresses(line, level, startAddr, stopAddr) == FAIL) {
// cannot scan values
if (sscanf(line, "%s 0x%x 0x%x", command, &startAddr, &stopAddr) !=
3) {
sprintf(initErrorMessage,
"Could not scan patloop%d arguments from default "
"pattern file. Line:[%s].\n",
level, line);
break;
}
}
if (default_setPatternLoopAddresses(line, level, startAddr,
stopAddr) == FAIL) {
break;
}
}
// patnloop
if ((!strncmp(line, "patnloop0", strlen("patnloop0"))) ||
if ((!strncmp(line, "patnloop0", strlen("patnloop0"))) ||
(!strncmp(line, "patnloop1", strlen("patnloop1"))) ||
(!strncmp(line, "patnloop2", strlen("patnloop2")))) {
// level
int level = -1;
if (!strncmp(line, "patnloop0", strlen("patnloop0"))) {
@ -204,20 +217,22 @@ int loadDefaultPattern(char* fname) {
}
int numLoops = -1;
// cannot scan values
if (sscanf(line, "%s %d", command, &numLoops) != 2) {
sprintf(initErrorMessage, "Could not scan patnloop%d arguments from default "
"pattern file. Line:[%s].\n", level, line);
break;
}
// cannot scan values
if (sscanf(line, "%s %d", command, &numLoops) != 2) {
sprintf(initErrorMessage,
"Could not scan patnloop%d arguments from default "
"pattern file. Line:[%s].\n",
level, line);
break;
}
if (default_setPatternLoopCycles(line, level, numLoops) == FAIL) {
break;
}
}
}
// patwait
if ((!strncmp(line, "patwait0", strlen("patwait0"))) ||
if ((!strncmp(line, "patwait0", strlen("patwait0"))) ||
(!strncmp(line, "patwait1", strlen("patwait1"))) ||
(!strncmp(line, "patwait2", strlen("patwait2")))) {
@ -232,20 +247,22 @@ int loadDefaultPattern(char* fname) {
}
uint32_t addr = 0;
// cannot scan values
if (sscanf(line, "%s 0x%x", command, &addr) != 2) {
sprintf(initErrorMessage, "Could not scan patwait%d arguments from default "
"pattern file. Line:[%s].\n", level, line);
break;
}
// cannot scan values
if (sscanf(line, "%s 0x%x", command, &addr) != 2) {
sprintf(initErrorMessage,
"Could not scan patwait%d arguments from default "
"pattern file. Line:[%s].\n",
level, line);
break;
}
if (default_setPatternWaitAddresses(line, level, addr) == FAIL) {
break;
}
}
}
// patwaittime
if ((!strncmp(line, "patwaittime0", strlen("patwaittime0"))) ||
if ((!strncmp(line, "patwaittime0", strlen("patwaittime0"))) ||
(!strncmp(line, "patwaittime1", strlen("patwaittime1"))) ||
(!strncmp(line, "patwaittime2", strlen("patwaittime2")))) {
@ -261,42 +278,44 @@ int loadDefaultPattern(char* fname) {
uint64_t waittime = 0;
// cannot scan values
// cannot scan values
#ifdef VIRTUAL
if (sscanf(line, "%s %ld", command, &waittime) != 2) {
if (sscanf(line, "%s %ld", command, &waittime) != 2) {
#else
if (sscanf(line, "%s %lld", command, &waittime) != 2) {
if (sscanf(line, "%s %lld", command, &waittime) != 2) {
#endif
sprintf(initErrorMessage, "Could not scan patwaittime%d arguments from default "
"pattern file. Line:[%s].\n", level, line);
break;
}
sprintf(initErrorMessage,
"Could not scan patwaittime%d arguments from default "
"pattern file. Line:[%s].\n",
level, line);
break;
}
if (default_setPatternWaitTime(line, level, waittime) == FAIL) {
break;
}
}
}
memset(line, 0, LZ);
}
fclose(fd);
fclose(fd);
if (strlen(initErrorMessage)) {
initError = FAIL;
LOG(logERROR, ("%s\n\n", initErrorMessage));
} else {
LOG(logINFOBLUE, ("Successfully read default pattern file\n"));
}
if (strlen(initErrorMessage)) {
initError = FAIL;
LOG(logERROR, ("%s\n\n", initErrorMessage));
} else {
LOG(logINFOBLUE, ("Successfully read default pattern file\n"));
}
return initError;
}
int default_writePatternWord(char* line, uint32_t addr, uint64_t word) {
//validations
int default_writePatternWord(char *line, uint32_t addr, uint64_t word) {
// validations
if ((int32_t)addr < 0 || addr >= MAX_PATTERN_LENGTH) {
sprintf(initErrorMessage, "Cannot set pattern word from default "
"pattern file. Addr must be between 0 and 0x%x. Line:[%s]\n",
MAX_PATTERN_LENGTH, line);
sprintf(initErrorMessage,
"Cannot set pattern word from default "
"pattern file. Addr must be between 0 and 0x%x. Line:[%s]\n",
MAX_PATTERN_LENGTH, line);
return FAIL;
}
writePatternWord(addr, word);
@ -304,151 +323,173 @@ int default_writePatternWord(char* line, uint32_t addr, uint64_t word) {
return OK;
}
int default_writePatternIOControl(char* line, uint64_t arg) {
int default_writePatternIOControl(char *line, uint64_t arg) {
uint64_t retval = writePatternIOControl(arg);
if (retval != arg) {
#ifdef VIRTUAL
sprintf(initErrorMessage, "Could not set patioctrl from default pattern "
"file. Set 0x%lx, read 0x%lx. Line:[%s]\n", arg, retval, line);
sprintf(initErrorMessage,
"Could not set patioctrl from default pattern "
"file. Set 0x%lx, read 0x%lx. Line:[%s]\n",
arg, retval, line);
#else
sprintf(initErrorMessage, "Could not set patioctrl from default pattern "
"file. Set 0x%llx, read 0x%llx. Line:[%s]\n", arg, retval, line);
sprintf(initErrorMessage,
"Could not set patioctrl from default pattern "
"file. Set 0x%llx, read 0x%llx. Line:[%s]\n",
arg, retval, line);
#endif
return FAIL;
}
return FAIL;
}
return OK;
}
int default_writePatternClkControl(char* line, uint64_t arg) {
int default_writePatternClkControl(char *line, uint64_t arg) {
uint64_t retval = writePatternClkControl(arg);
if (retval != arg) {
#ifdef VIRTUAL
sprintf(initErrorMessage, "Could not set patclkctrl from default pattern "
"file. Set 0x%lx, read 0x%lx. Line:[%s]\n", arg, retval, line);
sprintf(initErrorMessage,
"Could not set patclkctrl from default pattern "
"file. Set 0x%lx, read 0x%lx. Line:[%s]\n",
arg, retval, line);
#else
sprintf(initErrorMessage, "Could not set patclkctrl from default pattern "
"file. Set 0x%llx, read 0x%llx. Line:[%s]\n", arg, retval, line);
sprintf(initErrorMessage,
"Could not set patclkctrl from default pattern "
"file. Set 0x%llx, read 0x%llx. Line:[%s]\n",
arg, retval, line);
#endif
return FAIL;
}
return FAIL;
}
return OK;
}
int default_setPatternLoopLimits(char* line, uint32_t startAddr, uint32_t stopAddr) {
//validations
if ((int32_t)startAddr < 0 || startAddr >= MAX_PATTERN_LENGTH ||
int default_setPatternLoopLimits(char *line, uint32_t startAddr,
uint32_t stopAddr) {
// validations
if ((int32_t)startAddr < 0 || startAddr >= MAX_PATTERN_LENGTH ||
(int32_t)stopAddr < 0 || stopAddr >= MAX_PATTERN_LENGTH) {
sprintf(initErrorMessage, "Cannot set patlimits from default "
"pattern file. Addr must be between 0 and 0x%x. Line:[%s]\n",
MAX_PATTERN_LENGTH, line);
sprintf(initErrorMessage,
"Cannot set patlimits from default "
"pattern file. Addr must be between 0 and 0x%x. Line:[%s]\n",
MAX_PATTERN_LENGTH, line);
return FAIL;
}
}
int numLoops = -1;
int r_startAddr = startAddr, r_stopAddr = stopAddr;
setPatternLoop(-1, &r_startAddr, &r_stopAddr, &numLoops);
// validate
if (r_startAddr != (int)startAddr || r_stopAddr != (int)stopAddr) {
sprintf(initErrorMessage, "Could not set patlimits from default pattern "
"file. Read start addr:0x%x, stop addr: 0x%x. Line:[%s]\n",
r_startAddr, r_stopAddr, line);
sprintf(initErrorMessage,
"Could not set patlimits from default pattern "
"file. Read start addr:0x%x, stop addr: 0x%x. Line:[%s]\n",
r_startAddr, r_stopAddr, line);
return FAIL;
}
}
return OK;
}
int default_setPatternLoopAddresses(char* line, int level, uint32_t startAddr, uint32_t stopAddr) {
//validations
int default_setPatternLoopAddresses(char *line, int level, uint32_t startAddr,
uint32_t stopAddr) {
// validations
if (level < 0 || level > 2) {
sprintf(initErrorMessage, "Cannot set patloop from default "
"pattern file. Level must be between 0 and 2. Line:[%s]\n",
line);
sprintf(initErrorMessage,
"Cannot set patloop from default "
"pattern file. Level must be between 0 and 2. Line:[%s]\n",
line);
return FAIL;
}
if ((int32_t)startAddr < 0 || startAddr >= MAX_PATTERN_LENGTH ||
if ((int32_t)startAddr < 0 || startAddr >= MAX_PATTERN_LENGTH ||
(int32_t)stopAddr < 0 || stopAddr >= MAX_PATTERN_LENGTH) {
sprintf(initErrorMessage, "Cannot set patloop (level: %d) from default "
"pattern file. Addr must be between 0 and 0x%x. Line:[%s]\n",
level, MAX_PATTERN_LENGTH, line);
sprintf(initErrorMessage,
"Cannot set patloop (level: %d) from default "
"pattern file. Addr must be between 0 and 0x%x. Line:[%s]\n",
level, MAX_PATTERN_LENGTH, line);
return FAIL;
}
}
int numLoops = -1;
int r_startAddr = startAddr, r_stopAddr = stopAddr;
setPatternLoop(level, &r_startAddr, &r_stopAddr, &numLoops);
// validate
if (r_startAddr != (int)startAddr || r_stopAddr != (int)stopAddr) {
sprintf(initErrorMessage, "Could not set patloop (level: %d) from default "
"pattern file. Read start addr:0x%x, stop addr: 0x%x. Line:[%s]\n",
level, r_startAddr, r_stopAddr, line);
sprintf(
initErrorMessage,
"Could not set patloop (level: %d) from default "
"pattern file. Read start addr:0x%x, stop addr: 0x%x. Line:[%s]\n",
level, r_startAddr, r_stopAddr, line);
return FAIL;
}
return OK;
}
return OK;
}
int default_setPatternLoopCycles(char* line, int level, int numLoops) {
//validations
int default_setPatternLoopCycles(char *line, int level, int numLoops) {
// validations
if (level < 0 || level > 2) {
sprintf(initErrorMessage, "Cannot set patnloop from default "
"pattern file. Level must be between 0 and 2. Line:[%s]\n",
line);
sprintf(initErrorMessage,
"Cannot set patnloop from default "
"pattern file. Level must be between 0 and 2. Line:[%s]\n",
line);
return FAIL;
}
if (numLoops < 0) {
sprintf(initErrorMessage, "Cannot set patnloop from default "
"pattern file. Iterations must be between > 0. Line:[%s]\n",
line);
return FAIL;
sprintf(initErrorMessage,
"Cannot set patnloop from default "
"pattern file. Iterations must be between > 0. Line:[%s]\n",
line);
return FAIL;
}
int startAddr = -1;
int stopAddr = -1;
int stopAddr = -1;
int r_numLoops = numLoops;
setPatternLoop(level, &startAddr, &stopAddr, &r_numLoops);
// validate
if (r_numLoops != numLoops) {
sprintf(initErrorMessage, "Could not set patnloop (level: %d) from default "
"pattern file. Read %d loops. Line:[%s]\n",
level, r_numLoops, line);
sprintf(initErrorMessage,
"Could not set patnloop (level: %d) from default "
"pattern file. Read %d loops. Line:[%s]\n",
level, r_numLoops, line);
return FAIL;
}
return OK;
}
return OK;
}
int default_setPatternWaitAddresses(char* line, int level, uint32_t addr) {
//validations
int default_setPatternWaitAddresses(char *line, int level, uint32_t addr) {
// validations
if (level < 0 || level > 2) {
sprintf(initErrorMessage, "Cannot set patwait address from default "
"pattern file. Level must be between 0 and 2. Line:[%s]\n",
line);
sprintf(initErrorMessage,
"Cannot set patwait address from default "
"pattern file. Level must be between 0 and 2. Line:[%s]\n",
line);
return FAIL;
}
if ((int32_t)addr < 0 || addr >= MAX_PATTERN_LENGTH) {
sprintf(initErrorMessage, "Cannot set patwait address (level: %d) from default "
"pattern file. Addr must be between 0 and 0x%x. Line:[%s]\n",
level, MAX_PATTERN_LENGTH, line);
sprintf(initErrorMessage,
"Cannot set patwait address (level: %d) from default "
"pattern file. Addr must be between 0 and 0x%x. Line:[%s]\n",
level, MAX_PATTERN_LENGTH, line);
return FAIL;
}
}
uint32_t retval = setPatternWaitAddress(level, addr);
// validate
if (retval != addr) {
sprintf(initErrorMessage, "Could not set patwait address (level: %d) from default "
"pattern file. Read addr: 0x%x. Line:[%s]\n",
level, retval, line);
sprintf(initErrorMessage,
"Could not set patwait address (level: %d) from default "
"pattern file. Read addr: 0x%x. Line:[%s]\n",
level, retval, line);
return FAIL;
}
return OK;
}
return OK;
}
int default_setPatternWaitTime(char* line, int level, uint64_t waittime) {
//validations
int default_setPatternWaitTime(char *line, int level, uint64_t waittime) {
// validations
if (level < 0 || level > 2) {
sprintf(initErrorMessage, "Cannot set patwaittime from default "
"pattern file. Level must be between 0 and 2. Line:[%s]\n",
line);
sprintf(initErrorMessage,
"Cannot set patwaittime from default "
"pattern file. Level must be between 0 and 2. Line:[%s]\n",
line);
return FAIL;
}
uint64_t retval = setPatternWaitTime(level, waittime);
@ -456,15 +497,17 @@ int default_setPatternWaitTime(char* line, int level, uint64_t waittime) {
// validate
if (retval != waittime) {
#ifdef VIRTUAL
sprintf(initErrorMessage, "Could not set patwaittime (level: %d) from default "
"pattern file. Read %ld wait time. Line:[%s]\n",
level, retval, line);
sprintf(initErrorMessage,
"Could not set patwaittime (level: %d) from default "
"pattern file. Read %ld wait time. Line:[%s]\n",
level, retval, line);
#else
sprintf(initErrorMessage, "Could not set patwaittime (level: %d) from default "
"pattern file. Read %lld wait time. Line:[%s]\n",
level, retval, line);
sprintf(initErrorMessage,
"Could not set patwaittime (level: %d) from default "
"pattern file. Read %lld wait time. Line:[%s]\n",
level, retval, line);
#endif
return FAIL;
}
return OK;
}
return OK;
}

238
slsDetectorServers/slsDetectorServer/src/slsDetectorServer.c Executable file → Normal file
View File

@ -1,11 +1,11 @@
/* A simple server in the internet domain using TCP
The port number is passed as an argument */
#include "sls_detector_defs.h"
#include "clogger.h"
#include "communication_funcs.h"
#include "slsDetectorServer_funcs.h"
#include "slsDetectorServer_defs.h"
#include "slsDetectorServer_funcs.h"
#include "sls_detector_defs.h"
#include "versionAPI.h"
#ifdef VIRTUAL
#include "communication_virtual.h"
@ -24,166 +24,162 @@ extern int sockfd;
extern int debugflag;
extern int checkModuleFlag;
// Global variables from slsDetectorFunctionList
#ifdef GOTTHARDD
extern int phaseShift;
#endif
void error(char *msg){
perror(msg);
}
void error(char *msg) { perror(msg); }
int main(int argc, char *argv[]) {
// print version
if (argc > 1 && !strcasecmp(argv[1], "-version")) {
// print version
if (argc > 1 && !strcasecmp(argv[1], "-version")) {
int version = 0;
#ifdef GOTTHARDD
version = APIGOTTHARD;
#elif EIGERD
version = APIEIGER;
version = APIEIGER;
#elif JUNGFRAUD
version = APIJUNGFRAU;
version = APIJUNGFRAU;
#elif CHIPTESTBOARDD
version = APICTB;
version = APICTB;
#elif MOENCHD
version = APIMOENCH;
version = APIMOENCH;
#endif
LOG(logINFO, ("SLS Detector Server %s (0x%x)\n", GITBRANCH, version));
}
LOG(logINFO, ("SLS Detector Server %s (0x%x)\n", GITBRANCH, version));
}
int portno = DEFAULT_PORTNO;
isControlServer = 1;
debugflag = 0;
checkModuleFlag = 1;
isControlServer = 1;
debugflag = 0;
checkModuleFlag = 1;
// if socket crash, ignores SISPIPE, prevents global signal handler
// subsequent read/write to socket gives error - must handle locally
signal(SIGPIPE, SIG_IGN);
// if socket crash, ignores SISPIPE, prevents global signal handler
// subsequent read/write to socket gives error - must handle locally
signal(SIGPIPE, SIG_IGN);
// circumvent the basic tests
{
int i;
for (i = 1; i < argc; ++i) {
if(!strcasecmp(argv[i],"-stopserver")) {
LOG(logINFO, ("Detected stop server\n"));
isControlServer = 0;
}
else if(!strcasecmp(argv[i],"-devel")){
{
int i;
for (i = 1; i < argc; ++i) {
if (!strcasecmp(argv[i], "-stopserver")) {
LOG(logINFO, ("Detected stop server\n"));
isControlServer = 0;
} else if (!strcasecmp(argv[i], "-devel")) {
LOG(logINFO, ("Detected developer mode\n"));
debugflag = 1;
}
else if(!strcasecmp(argv[i],"-nomodule")){
} else if (!strcasecmp(argv[i], "-nomodule")) {
LOG(logINFO, ("Detected No Module mode\n"));
checkModuleFlag = 0;
}
else if(!strcasecmp(argv[i],"-port")){
if ((i + 1) >= argc) {
LOG(logERROR, ("no port value given. Exiting.\n"));
return -1;
}
if (sscanf(argv[i + 1], "%d", &portno) == 0) {
LOG(logERROR, ("cannot decode port value %s. Exiting.\n", argv[i + 1]));
return -1;
}
LOG(logINFO, ("Detected port: %d\n", portno));
} else if (!strcasecmp(argv[i], "-port")) {
if ((i + 1) >= argc) {
LOG(logERROR, ("no port value given. Exiting.\n"));
return -1;
}
if (sscanf(argv[i + 1], "%d", &portno) == 0) {
LOG(logERROR, ("cannot decode port value %s. Exiting.\n",
argv[i + 1]));
return -1;
}
LOG(logINFO, ("Detected port: %d\n", portno));
}
#ifdef GOTTHARDD
else if(!strcasecmp(argv[i],"-phaseshift")){
if ((i + 1) >= argc) {
LOG(logERROR, ("no phase shift value given. Exiting.\n"));
return -1;
}
if (sscanf(argv[i + 1], "%d", &phaseShift) == 0) {
LOG(logERROR, ("cannot decode phase shift value %s. Exiting.\n", argv[i + 1]));
return -1;
}
LOG(logINFO, ("Detected phase shift of %d\n", phaseShift));
}
else if (!strcasecmp(argv[i], "-phaseshift")) {
if ((i + 1) >= argc) {
LOG(logERROR, ("no phase shift value given. Exiting.\n"));
return -1;
}
if (sscanf(argv[i + 1], "%d", &phaseShift) == 0) {
LOG(logERROR,
("cannot decode phase shift value %s. Exiting.\n",
argv[i + 1]));
return -1;
}
LOG(logINFO, ("Detected phase shift of %d\n", phaseShift));
}
#endif
}
}
}
}
// control server
if (isControlServer) {
// control server
if (isControlServer) {
#ifdef STOP_SERVER
// start stop server process
char cmd[MAX_STR_LENGTH];
memset(cmd, 0, MAX_STR_LENGTH);
{
int i;
for (i = 0; i < argc; ++i) {
if (!strcasecmp(argv[i], "-port")) {
i +=2;
continue;
}
if (i > 0) {
strcat(cmd, " ");
}
strcat(cmd, argv[i]);
}
char temp[50];
memset(temp, 0, sizeof(temp));
sprintf(temp, " -stopserver -port %d &", portno + 1);
strcat(cmd, temp);
LOG(logDEBUG1, ("Command to start stop server:%s\n", cmd));
system(cmd);
}
LOG(logINFOBLUE, ("Control Server [%d]\n", portno));
// start stop server process
char cmd[MAX_STR_LENGTH];
memset(cmd, 0, MAX_STR_LENGTH);
{
int i;
for (i = 0; i < argc; ++i) {
if (!strcasecmp(argv[i], "-port")) {
i += 2;
continue;
}
if (i > 0) {
strcat(cmd, " ");
}
strcat(cmd, argv[i]);
}
char temp[50];
memset(temp, 0, sizeof(temp));
sprintf(temp, " -stopserver -port %d &", portno + 1);
strcat(cmd, temp);
LOG(logDEBUG1, ("Command to start stop server:%s\n", cmd));
system(cmd);
}
LOG(logINFOBLUE, ("Control Server [%d]\n", portno));
#ifdef VIRTUAL
// creating files for virtual servers to communicate with each other
if (!ComVirtual_createFiles(portno)) {
return -1;
}
// creating files for virtual servers to communicate with each other
if (!ComVirtual_createFiles(portno)) {
return -1;
}
#endif
#endif
}
// stop server
else {
LOG(logINFOBLUE, ("Stop Server [%d]\n", portno));
}
// stop server
else {
LOG(logINFOBLUE, ("Stop Server [%d]\n", portno));
#ifdef VIRTUAL
ComVirtual_setFileNames(portno - 1);
ComVirtual_setFileNames(portno - 1);
#endif
}
}
init_detector();
// bind socket
sockfd = bindSocket(portno);
if (ret == FAIL)
return -1;
// assign function table
function_table();
init_detector();
// bind socket
sockfd = bindSocket(portno);
if (ret == FAIL)
return -1;
// assign function table
function_table();
if (isControlServer) {
LOG(logINFOBLUE, ("Control Server Ready...\n\n"));
} else {
LOG(logINFOBLUE, ("Stop Server Ready...\n\n"));
}
if (isControlServer) {
LOG(logINFOBLUE, ("Control Server Ready...\n\n"));
} else {
LOG(logINFOBLUE, ("Stop Server Ready...\n\n"));
}
// waits for connection
int retval = OK;
while (retval != GOODBYE && retval != REBOOT) {
int fd = acceptConnection(sockfd);
if (fd > 0) {
retval = decode_function(fd);
closeConnection(fd);
}
}
// waits for connection
int retval = OK;
while(retval != GOODBYE && retval != REBOOT) {
int fd = acceptConnection(sockfd);
if (fd > 0) {
retval = decode_function(fd);
closeConnection(fd);
}
}
exitServer(sockfd);
exitServer(sockfd);
if (retval == REBOOT) {
LOG(logINFORED,("Rebooting!\n"));
fflush(stdout);
if (retval == REBOOT) {
LOG(logINFORED, ("Rebooting!\n"));
fflush(stdout);
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
rebootNiosControllerAndFPGA();
rebootNiosControllerAndFPGA();
#else
system("reboot");
system("reboot");
#endif
}
LOG(logINFO,("Goodbye!\n"));
return 0;
}
LOG(logINFO, ("Goodbye!\n"));
return 0;
}

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slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c Executable file → Normal file
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