mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-05-06 12:50:02 +02:00
Jungfrau server with changed ADC phase
This commit is contained in:
parent
94a73ecd45
commit
785f025d1b
@ -9,7 +9,7 @@ CC = $(CROSS)gcc
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CFLAGS += -Wall -DMOENCHD -DMCB_FUNCS -DDACS_INT -DDEBUG #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL #-DDACS_INT_CSERVER
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PROGS= jungfrauDetectorServer
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PROGS= jungfrauDetectorServer
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INSTDIR= /tftpboot
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INSTMODE= 0777
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@ -23,12 +23,20 @@ OBJS = $(SRCS:%.c=%.o)
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all: clean $(PROGS)
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test: clean jungfrauADCTEst
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boot: $(OBJS)
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$(PROGS): $(OBJS)
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jungfrauDetectorServer: $(OBJS)
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echo $(OBJS)
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$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@)
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jungfrauADCTEst: $(OBJS)
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echo $(OBJS)
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$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@) -DTESTADC
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install: $(PROGS)
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$(INSTALL) -d $(INSTDIR)
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@ -1,3 +1,5 @@
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#define TESTADC
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#include "server_defs.h"
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#include "firmware_funcs.h"
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@ -263,42 +265,42 @@ int setPhaseShiftOnce(){
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int cleanFifo(){
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u_int32_t addr, reg, val, adc_sync;
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printf("Cleaning FIFO\n");
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addr=ADC_SYNC_REG;
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/* u_int32_t addr, reg, val, adc_sync; */
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/* printf("Cleaning FIFO\n"); */
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/* addr=ADC_SYNC_REG; */
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if(withGotthard)
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adc_sync = GOTTHARD_ADCSYNC_VAL;
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else
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adc_sync = ADCSYNC_VAL;
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/* if(withGotthard) */
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/* adc_sync = GOTTHARD_ADCSYNC_VAL; */
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/* else */
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/* adc_sync = ADCSYNC_VAL; */
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reg = bus_r(addr) & CLEAN_FIFO_MASK;
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/* reg = bus_r(addr) & CLEAN_FIFO_MASK; */
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//only for start up
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if(!reg) reg = adc_sync;
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/* //only for start up */
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/* if(!reg) reg = adc_sync; */
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// 88 3 02111
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if (ROI_flag==0) {
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val=reg | ADCSYNC_CLEAN_FIFO_BITS | TOKEN_RESTART_DELAY;
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bus_w(addr,val);
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// 88 0 02111
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val=reg | TOKEN_RESTART_DELAY;
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bus_w(addr,val);
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}
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else {
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//1b332214
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val=reg | ADCSYNC_CLEAN_FIFO_BITS | TOKEN_RESTART_DELAY_ROI;
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bus_w(addr,val);
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//1b032214
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val=reg | TOKEN_RESTART_DELAY_ROI;
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bus_w(addr,val);
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/* // 88 3 02111 */
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/* if (ROI_flag==0) { */
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/* val=reg | ADCSYNC_CLEAN_FIFO_BITS | TOKEN_RESTART_DELAY; */
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/* bus_w(addr,val); */
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/* // 88 0 02111 */
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/* val=reg | TOKEN_RESTART_DELAY; */
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/* bus_w(addr,val); */
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/* } */
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/* else { */
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/* //1b332214 */
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/* val=reg | ADCSYNC_CLEAN_FIFO_BITS | TOKEN_RESTART_DELAY_ROI; */
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/* bus_w(addr,val); */
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/* //1b032214 */
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/* val=reg | TOKEN_RESTART_DELAY_ROI; */
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/* bus_w(addr,val); */
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}
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reg=bus_r(addr);
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//#ifdef DDEBUG
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printf("ADC SYNC reg 0x19:%x\n",reg);
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//#endif
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/* } */
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/* reg=bus_r(addr); */
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/* //#ifdef DDEBUG */
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/* printf("ADC SYNC reg 0x19:%x\n",reg); */
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/* //#endif */
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return OK;
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}
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@ -1344,49 +1346,52 @@ int getTemperature(int tempSensor, int imod){
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int initHighVoltage(int val, int imod){
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#ifdef VERBOSE
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printf("Setting/Getting High Voltage of module:%d with val:%d\n",imod,val);
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#endif
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volatile u_int32_t addr=HV_REG;
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int writeVal,writeVal2;
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switch(val){
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case -1: break;
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case 0: writeVal=0x0; writeVal2=0x0; break;
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case 90: writeVal=0x0; writeVal2=0x1; break;
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case 110:writeVal=0x2; writeVal2=0x3; break;
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case 120:writeVal=0x4; writeVal2=0x5; break;
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case 150:writeVal=0x6; writeVal2=0x7; break;
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case 180:writeVal=0x8; writeVal2=0x9; break;
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case 200:writeVal=0xA; writeVal2=0xB; break;
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default :printf("Invalid voltage\n");return -2;break;
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}
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//to set value
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if(val!=-1){
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//set value to converted value
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bus_w(addr,writeVal);
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bus_w(addr,writeVal2);
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#ifdef VERBOSE
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printf("Value sent is %d and then %d\n",writeVal,writeVal2);
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#endif
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}
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//read value and return the converted value
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val=bus_r(addr);
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#ifdef VERBOSE
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printf("Value read from reg is %d\n",val);
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#endif
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switch(val){
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case 0x0:val=0;break;
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case 0x1:val=90;break;
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case 0x3:val=110;break;
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case 0x5:val=120;break;
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case 0x7:val=150;break;
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case 0x9:val=180;break;
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case 0xB:val=200;break;
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default:printf("Weird value read:%d\n",val);return -3;break;
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}
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#ifdef VERBOSE
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printf("High voltage of module:%d is %d\n",imod,val);
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#endif
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printf("*******SetHV: Doing nothing - still to be implemented!\n");
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/* #ifdef VERBOSE */
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/* printf("Setting/Getting High Voltage of module:%d with val:%d\n",imod,val); */
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/* #endif */
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/* volatile u_int32_t addr=HV_REG; */
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/* int writeVal,writeVal2; */
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/* switch(val){ */
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/* case -1: break; */
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/* case 0: writeVal=0x0; writeVal2=0x0; break; */
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/* case 90: writeVal=0x0; writeVal2=0x1; break; */
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/* case 110:writeVal=0x2; writeVal2=0x3; break; */
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/* case 120:writeVal=0x4; writeVal2=0x5; break; */
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/* case 150:writeVal=0x6; writeVal2=0x7; break; */
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/* case 180:writeVal=0x8; writeVal2=0x9; break; */
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/* case 200:writeVal=0xA; writeVal2=0xB; break; */
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/* default :printf("Invalid voltage\n");return -2;break; */
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/* } */
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/* //to set value */
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/* if(val!=-1){ */
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/* //set value to converted value */
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/* bus_w(addr,writeVal); */
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/* bus_w(addr,writeVal2); */
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/* #ifdef VERBOSE */
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/* printf("Value sent is %d and then %d\n",writeVal,writeVal2); */
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/* #endif */
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/* } */
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/* //read value and return the converted value */
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/* val=bus_r(addr); */
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/* #ifdef VERBOSE */
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/* printf("Value read from reg is %d\n",val); */
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/* #endif */
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/* switch(val){ */
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/* case 0x0:val=0;break; */
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/* case 0x1:val=90;break; */
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/* case 0x3:val=110;break; */
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/* case 0x5:val=120;break; */
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/* case 0x7:val=150;break; */
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/* case 0x9:val=180;break; */
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/* case 0xB:val=200;break; */
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/* default:printf("Weird value read:%d\n",val);return -3;break; */
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/* } */
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/* #ifdef VERBOSE */
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/* printf("High voltage of module:%d is %d\n",imod,val); */
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/* #endif */
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return val;
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}
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@ -1722,7 +1727,12 @@ int i;
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//#ifdef VERBOSE
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printf("*******Starting State Machine*******\n");
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//#endif
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cleanFifo();
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//NEEDED?
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// cleanFifo();
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// fifoReset();
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now_ptr=(char*)ram_values;
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#ifdef SHAREDMEMORY
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@ -1849,15 +1859,16 @@ u_int16_t* fifo_read_event()
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{
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int i=0;
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int i=0, j=0;
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#ifdef VIRTUAL
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return NULL;
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#endif
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#ifdef VERBOSE
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//#ifdef VERBOSE
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printf("before looping\n");
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volatile u_int32_t fs;
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#endif
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volatile u_int32_t fs;
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u_int16_t *dum;
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//#endif
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volatile u_int32_t t = bus_r16(LOOK_AT_ME_REG);
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#ifdef VERBOSE
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@ -1874,6 +1885,7 @@ u_int16_t* fifo_read_event()
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}
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*/
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bus_w(DUMMY_REG,0);
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while(t==0) {
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#ifdef VERYVERBOSE
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printf("before readout %08x %08x\n", runState(), bus_r(LOOK_AT_ME_REG));
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@ -1914,28 +1926,48 @@ u_int16_t* fifo_read_event()
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#ifdef VERYVERBOSE
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printf(" out of while loop!\n");
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#endif
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#ifdef VERYVERBOSE
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#ifdef VERYVERBOSE
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printf("before readout %08x %08x\n", runState(), bus_r(LOOK_AT_ME_REG));
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i=0;
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for (i=0; i<32; i++) {
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printf("Fifo %d (%04x) status :\n", i,FIFO_STATUS_REG | i);
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fs=bus_r16(FIFO_STATUS_REG | i);
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printf("before: %x\n",fs);
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// printf("Fifo %d (%04x) status :\n", i,FIFO_STATUS_REG | i);
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fs=bus_r16(FIFO_STATUS_REG| i);
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if (fs&0xfff0fff)
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printf("before %d: %x\n",i, fs);
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}
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#endif
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dma_memcpy(now_ptr,values ,dataBytes);
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/* dma_memcpy(now_ptr,values ,dataBytes); */
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/* #else */
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for (i=0; i<32; i++) {
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dum=((u_int16_t*)(now_ptr))+i;
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bus_w(DUMMY_REG,i<<1);
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#ifdef TESTADC
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printf("%d s:%04x ",i,bus_r16(FIFO_STATUS_REG));
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#endif
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bus_w(DUMMY_REG,(i<<1) | 1);
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bus_w(DUMMY_REG,i<<1);
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*dum=bus_r16(FIFO_DATA_REG);// | i); //values[i];
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#ifdef TESTADC
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printf("d:%04x s:%04x\n",*dum&0x3fff, bus_r16(FIFO_STATUS_REG));
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#endif
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}
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//#endif
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printf("-");
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//memcpy(now_ptr,values ,dataBytes); //this reads the fifo twice...
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#ifdef VERYVERBOSE
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#ifdef VERYVERBOSE
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printf("after readout %08x %08x\n", runState(), bus_r(LOOK_AT_ME_REG));
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i=0;
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for (i=0; i<32; i++) {
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fs=bus_r16(FIFO_STATUS_REG | i);
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printf("after %d: %x\n",i, fs);
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fs=bus_r16(FIFO_STATUS_REG| i);
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if (fs&0xfff0fff)
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printf("after %d: %x\n",i, fs);
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}
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#endif
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#endif
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#ifdef VERYVERBOSE
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int a;
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@ -2154,44 +2186,118 @@ int allocateRAM() {
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}
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int writeADC(int addr, int val) {
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u_int32_t valw,codata,csmask;
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int i,cdx,ddx,j;
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cdx=0; ddx=1;
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csmask=0xfc; // 1111100
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codata=val + (addr<< 8);
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printf("***** ADC SPI WRITE TO REGISTER %04X value %04X\n",addr,val);
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// start point
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valw=0xff;
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bus_w(ADC_WRITE_REG,(valw));
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//chip sel bar down
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valw=((0xffffffff&(~csmask)));
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bus_w(ADC_WRITE_REG,valw);
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for (i=0;i<24;i++) {
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//cldwn
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valw=valw&(~(0x1<<cdx));
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bus_w(ADC_WRITE_REG,valw);
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usleep(0);
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//write data (i)
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valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx);
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bus_w(ADC_WRITE_REG,valw);
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usleep(0);
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//clkup
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valw=valw+(0x1<<cdx);
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bus_w(ADC_WRITE_REG,valw);
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usleep(0);
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}
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// stop point =start point
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valw=valw&(~(0x1<<cdx));
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usleep(0);
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valw=0xff;
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bus_w(ADC_WRITE_REG,(valw));
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//usleep in between
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usleep(50000);
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return OK;
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}
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int prepareADC(){
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printf("Preparing ADC\n");
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u_int32_t valw,codata,csmask;
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int i,cdx,ddx;
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int i,cdx,ddx,j;
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cdx=0; ddx=1;
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csmask=0x7c; // 1111100
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codata=0;
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codata=(0x14<<8)+(0x0); //command and value;
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valw=0xff;
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bus_w(ADC_WRITE_REG,(valw)); // start point
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valw=((0xffffffff&(~csmask)));
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bus_w(ADC_WRITE_REG,valw); //chip sel bar down
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for (i=0;i<24;i++) {
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valw=valw&(~(0x1<<cdx));//cldwn
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bus_w(ADC_WRITE_REG,valw);
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usleep(0);
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#ifdef VERBOSE
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printf("DOWN 0x%x \n",valw);
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#endif
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valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx); //write data (i)
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bus_w(ADC_WRITE_REG,valw);
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usleep(0);
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#ifdef VERBOSE
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printf("LOW 0x%x \n",valw);
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#endif
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valw=valw+(0x1<<cdx);bus_w(ADC_WRITE_REG,valw); //clkup
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usleep(0);
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#ifdef VERBOSE
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printf("up 0x%x \n",valw);
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#endif
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}
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codata=0;
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writeADC(0x08,0x3);
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writeADC(0x08,0x0);
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writeADC(0x14,0x40);//lvds reduced range
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// writeADC(0x14,0x00);//lvds
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writeADC(0x16,0x01);//output clock phase
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// writeADC(0x16,0x07);//output clock phase
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// writeADC(0x16,0x4);//output clock phase
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writeADC(0xD,0x0);//no test mode
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#ifdef TESTADC
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////////////TEST ADC!!!!!!!!!!
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printf("***************************************** *******\n");
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printf("******* PUTTING ADC IN TEST MODE!!!!!!!!! *******\n");
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printf("***************************************** *******\n");
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// writeADC(0xD,0x4);//ALTERNATING CHECKERBOARD
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// writeADC(0xD,0x7);//ONE/ZERO WORD TOGGLE
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/* writeADC(0x19,0xf0);//user input */
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/* writeADC(0x1A,0xf0);//user input */
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/* writeADC(0x1B,0x0f);//user input */
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/* writeADC(0x1C,0x0f);//user input */
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/* writeADC(0xD,0x48);//user input, alternate */
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/* //writeADC(0xD,0xA);//1xsync */
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// writeADC(0xD,0xB);//1xbit high
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writeADC(0xD,0xC);//1xmixed frequqncy
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#endif
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valw=valw&(~(0x1<<cdx));usleep(0);
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valw=0xff; bus_w(ADC_WRITE_REG,(valw)); // stop point =start point */
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bus_w(ADC_LATCH_DISABLE_REG,0x0); // enable all ADCs
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bus_w(DAQ_REG,0xd);
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bus_w(DAQ_REG,0xd); //adc pipeline=13
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bus_w(ADC_OFFSET_REG,0xbbbbbbbb);
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// bus_w(ADC_INVERSION_REG,0x1f6170c6);
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return;
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}
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Binary file not shown.
Binary file not shown.
@ -116,8 +116,8 @@
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//#define ADC_SYNC_REG 66<<11//0x19<<11
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//#define HV_REG 67<<11//0x20<<11
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|
||||
#define ADCCLK_MASK_REG 66<<11
|
||||
#define ADC_INVERSION_REG 66<<11
|
||||
#define ADC_OFFSET_REG 66<<11
|
||||
#define ADC_INVERSION_REG 67<<11
|
||||
|
||||
//#define MUTIME_REG 0x1a<<11
|
||||
//temperature
|
||||
@ -351,6 +351,7 @@
|
||||
#define FIFO_RESET_BIT 0x8000
|
||||
#define SYNC_RESET 0x0400
|
||||
#define GB10_RESET_BIT 0x0800
|
||||
#define MEM_RESET_BIT 0x1000
|
||||
|
||||
/* for status register */
|
||||
#define RUN_BUSY_BIT 0x00000001
|
||||
|
||||
@ -1886,7 +1886,7 @@ int get_run_status(int file_des) {
|
||||
|
||||
printf("-----------------------------------READ MACHINE BUSY--------------------------\n");
|
||||
s=TRANSMITTING;
|
||||
} else if (retval&ALL_FIFO_EMPTY_BIT) {
|
||||
} else if (!(retval&ALL_FIFO_EMPTY_BIT)) {
|
||||
printf("-----------------------------------DATA IN FIFO--------------------------\n");
|
||||
s=TRANSMITTING;
|
||||
|
||||
|
||||
@ -4384,6 +4384,23 @@ double* slsDetector::decodeData(int *datain, double *fdata) {
|
||||
int ipos=0, ichan=0, ibyte;
|
||||
|
||||
if (thisDetector->timerValue[PROBES_NUMBER]==0) {
|
||||
if (thisDetector->myDetectorType==JUNGFRAUCTB) {
|
||||
|
||||
for (ichan=0; ichan<nch; ichan++) {
|
||||
// dataout[ichan]=0;
|
||||
ival=0;
|
||||
// for (ibyte=0; ibyte<2; ibyte++) {
|
||||
ibyte=0;
|
||||
iptr=ptr[ichan*2+ibyte];
|
||||
ival|=((iptr<<(ibyte*bytesize))&(0xff<<(ibyte*bytesize)));
|
||||
ibyte=1;
|
||||
iptr=ptr[ichan*2+ibyte];
|
||||
ival|=((iptr<<(ibyte*bytesize))&(0x3f<<(ibyte*bytesize)));
|
||||
|
||||
// }
|
||||
dataout[ichan]=ival;
|
||||
}
|
||||
} else {
|
||||
switch (nbits) {
|
||||
case 1:
|
||||
for (ibyte=0; ibyte<thisDetector->dataBytes; ibyte++) {
|
||||
@ -4430,6 +4447,7 @@ double* slsDetector::decodeData(int *datain, double *fdata) {
|
||||
dataout[ichan]=ival;
|
||||
}
|
||||
}
|
||||
}
|
||||
} else {
|
||||
for (ichan=0; ichan<nch; ichan++) {
|
||||
dataout[ichan]=datain[ichan];
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user