mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 18:17:59 +02:00
moved common files outside slsDetectorSoftware
This commit is contained in:
414
commonFiles/sls_detector_defs.h
Executable file
414
commonFiles/sls_detector_defs.h
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#ifndef SLS_DETECTOR_DEFS_H
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#define SLS_DETECTOR_DEFS_H
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#ifdef __CINT__
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#define MYROOT
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#define __cplusplus
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#endif
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//#include <stdint.h>
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#include "sls_receiver_defs.h"
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/** maximum rois */
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#define MAX_ROIS 100
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/** maximum trim en */
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#define MAX_TRIMEN 100
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/** maximum unit size of program sent to detector */
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#define MAX_FPGAPROGRAMSIZE (2 * 1024 *1024)
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typedef char mystring[MAX_STR_LENGTH];
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typedef int dacs_t;
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#define DEFAULT_DET_MAC "00:aa:bb:cc:dd:ee"
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#define DEFAULT_DET_IP "129.129.202.46"
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/**
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\file sls_detector_defs.h
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This file contains all the basic definitions common to the slsDetector class
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and to the server programs running on the detector
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* @author Anna Bergamaschi
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* @version 0.1alpha (any string)
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* @see slsDetector
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*/
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/** get flag form most functions */
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#define GET_FLAG -1
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#ifdef __cplusplus
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/** @short class containing all the structures, constants and enum definitions */
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class slsDetectorDefs: public virtual slsReceiverDefs{
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public:
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slsDetectorDefs(){};
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#endif
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/**
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@short structure for a detector module
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should not be used by unexperienced users
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\see :: moduleRegisterBit ::chipRegisterBit :channelRegisterBit
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@li reg is the module register (e.g. dynamic range? see moduleRegisterBit)
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@li dacs is the pointer to the array of dac values (in V)
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@li adcs is the pointer to the array of adc values (in V)
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@li chipregs is the pointer to the array of chip registers
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@li chanregs is the pointer to the array of channel registers
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@li gain is the module gain
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@li offset is the module offset
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*/
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typedef struct {
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int serialnumber; /**< is the module serial number */
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int nchan; /**< is the number of channels on the module*/
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int nchip; /**< is the number of chips on the module */
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int ndac; /**< is the number of dacs on the module */
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int nadc; /**< is the number of adcs on the module */
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int reg; /**< is the module register (e.g. dynamic range?)
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\see moduleRegisterBit */
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dacs_t *dacs; /**< is the pointer to the array of the dac values (in V) */
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dacs_t *adcs; /**< is the pointer to the array of the adc values (in V) FLAT_FIELD_CORRECTION*/
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int *chipregs; /**< is the pointer to the array of the chip registers
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\see ::chipRegisterBit */
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int *chanregs; /**< is the pointer to the array of the channel registers
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\see ::channelRegisterBit */
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double gain; /**< is the module gain (V/keV) */
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double offset; /**< is the module offset (V) */
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} sls_detector_module;
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/**
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network parameters
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*/
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enum networkParameter {
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DETECTOR_MAC, /**< detector MAC */
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DETECTOR_IP, /**< detector IP */
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RECEIVER_HOSTNAME, /**< receiver IP/hostname */
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RECEIVER_UDP_IP, /**< receiever UDP IP */
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RECEIVER_UDP_PORT, /**< receiever UDP Port */
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RECEIVER_UDP_MAC, /**< receiever UDP MAC */
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RECEIVER_UDP_PORT2, /**< receiever UDP Port of second half module for eiger */
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DETECTOR_TXN_DELAY_LEFT, /**< transmission delay on the (left) port for next frame */
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DETECTOR_TXN_DELAY_RIGHT, /**< transmission delay on the right port for next frame */
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DETECTOR_TXN_DELAY_FRAME, /**< transmission delay of a whole frame for all the ports */
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FLOW_CONTROL_10G, /**< flow control for 10GbE */
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FLOW_CONTROL_WR_PTR, /**< memory write pointer for flow control */
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FLOW_CONTROL_RD_PTR, /**< memory read pointer for flow control */
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RECEIVER_STREAMING_PORT, /**< receiever streaming TCP(ZMQ) port */
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CLIENT_STREAMING_PORT, /**< client streaming TCP(ZMQ) port */
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RECEIVER_STREAMING_SRC_IP,/**< receiever streaming TCP(ZMQ) ip */
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CLIENT_STREAMING_SRC_IP, /**< client streaming TCP(ZMQ) ip */
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ADDITIONAL_JSON_HEADER, /**< additional json header (ZMQ) */
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RECEIVER_UDP_SCKT_BUF_SIZE, /**< UDP socket buffer size */
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RECEIVER_REAL_UDP_SCKT_BUF_SIZE /**< real UDP socket buffer size */
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};
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/**
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type of action performed (for text client)
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*/
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enum {GET_ACTION, PUT_ACTION, READOUT_ACTION, HELP_ACTION};
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/** online flags enum \sa setOnline*/
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enum {GET_ONLINE_FLAG=-1, /**< returns wether the detector is in online or offline state */
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OFFLINE_FLAG=0, /**< detector in offline state (i.e. no communication to the detector - using only local structure - no data acquisition possible!) */
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ONLINE_FLAG =1/**< detector in online state (i.e. communication to the detector updating the local structure) */
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};
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/**
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flags to get (or set) the size of the detector
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*/
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enum numberOf {
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MAXMODX, /**<maximum number of module in X direction */
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MAXMODY, /**<maximum number of module in Y direction */
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NMODX, /**<installed number of module in X direction */
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NMODY, /**<installed number of module in Y direction */
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NCHANSX, /**<number of channels in X direction */
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NCHANSY, /**<number of channels in Y direction */
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NCHIPSX, /**<number of chips in X direction */
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NCHIPSY /**<number of chips in Y direction */
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};
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/**
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dimension indexes
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*/
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enum dimension {
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X=0, /**< X dimension */
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Y=1, /**< Y dimension */
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Z=2 /**< Z dimension */
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};
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/**
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enable/disable flags
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*/
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enum {
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DISABLED, /**<flag disabled */
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ENABLED /**<flag enabled */
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};
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/**
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use of the external signals
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*/
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enum externalSignalFlag {
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GET_EXTERNAL_SIGNAL_FLAG=-1, /**<return flag for signal */
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SIGNAL_OFF, /**<signal unused - tristate*/
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GATE_IN_ACTIVE_HIGH, /**<input gate active high*/
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GATE_IN_ACTIVE_LOW, /**<input gate active low */
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TRIGGER_IN_RISING_EDGE, /**<input exposure trigger on rising edge */
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TRIGGER_IN_FALLING_EDGE, /**<input exposure trigger on falling edge */
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RO_TRIGGER_IN_RISING_EDGE, /**<input raedout trigger on rising edge */
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RO_TRIGGER_IN_FALLING_EDGE, /**<input readout trigger on falling edge */
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GATE_OUT_ACTIVE_HIGH, /**<output active high when detector is exposing*/
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GATE_OUT_ACTIVE_LOW, /**<output active low when detector is exposing*/
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TRIGGER_OUT_RISING_EDGE, /**<output trigger rising edge at start of exposure */
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TRIGGER_OUT_FALLING_EDGE, /**<output trigger falling edge at start of exposure */
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RO_TRIGGER_OUT_RISING_EDGE, /**<output trigger rising edge at start of readout */
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RO_TRIGGER_OUT_FALLING_EDGE, /**<output trigger falling edge at start of readout */
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OUTPUT_LOW, /**< output always low */
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OUTPUT_HIGH, /**< output always high */
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MASTER_SLAVE_SYNCHRONIZATION /**< reserved for master/slave synchronization in multi detector systems */
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};
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/**
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communication mode using external signals
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*/
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enum externalCommunicationMode{
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GET_EXTERNAL_COMMUNICATION_MODE=-1,/**<return flag for communication mode */
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AUTO_TIMING, /**< internal timing */
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TRIGGER_EXPOSURE, /**< trigger mode i.e. exposure is triggered */
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TRIGGER_READOUT, /**< stop trigger mode i.e. readout is triggered by external signal */
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GATE_FIX_NUMBER, /**< gated and reads out after a fixed number of gates */
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GATE_WITH_START_TRIGGER, /**< gated with start trigger */
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BURST_TRIGGER /**< trigger a burst of frames */
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};
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/**
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detector IDs/versions
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*/
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enum idMode{
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MODULE_SERIAL_NUMBER, /**<return module serial number */
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MODULE_FIRMWARE_VERSION, /**<return module firmware */
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DETECTOR_SERIAL_NUMBER, /**<return detector system serial number */
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DETECTOR_FIRMWARE_VERSION, /**<return detector system firmware version */
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DETECTOR_SOFTWARE_VERSION, /**<return detector system software version */
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THIS_SOFTWARE_VERSION, /**<return this software version */
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RECEIVER_VERSION, /**<return receiver software version */
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SOFTWARE_FIRMWARE_API_VERSION, /** return software firmware API version **/
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CLIENT_SOFTWARE_API_VERSION, /** return detector software and client api version */
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CLIENT_RECEIVER_API_VERSION /** return client and receiver api version */
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};
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/**
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detector digital test modes
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*/
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enum digitalTestMode {
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CHIP_TEST, /**< test chips */
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MODULE_FIRMWARE_TEST, /**< test module firmware */
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DETECTOR_FIRMWARE_TEST, /**< test detector system firmware */
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DETECTOR_MEMORY_TEST, /**< test detector system memory */
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DETECTOR_SOFTWARE_TEST, /**< test detector system software */
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DIGITAL_BIT_TEST /**< gotthard digital bit test */
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};
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/**
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detector dacs indexes
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*/
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enum dacIndex {
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THRESHOLD, /**< comparator threshold level */
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CALIBRATION_PULSE, /**< calibration input pulse height */
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TRIMBIT_SIZE, /**< voltage to determine the trimbits LSB */
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PREAMP, /**< preamp feedback */
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SHAPER1, /**< shaper1 feedback */
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SHAPER2, /**< shaper2 feedback */
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TEMPERATURE_ADC, /**< temperature sensor (adc) */
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TEMPERATURE_FPGA, /**< temperature sensor (fpga) */
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HUMIDITY, /**< humidity sensor (adc) */
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DETECTOR_BIAS,/**< detector bias */
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VA_POT, /**< power supply va */
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VDD_POT, /**< chiptest board power supply vdd */
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VSH_POT, /**< chiptest board power supply vsh */
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VIO_POT, /**< chiptest board power supply va */
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HV_POT, /**< gotthard, chiptest board high voltage */
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G_VREF_DS, /**< gotthard */
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G_VCASCN_PB, /**< gotthard */
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G_VCASCP_PB, /**< gotthard */
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G_VOUT_CM, /**< gotthard */
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G_VCASC_OUT, /**< gotthard */
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G_VIN_CM, /**< gotthard */
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G_VREF_COMP, /**< gotthard */
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G_IB_TESTC, /**< gotthard */
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E_SvP, /**< eiger */
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E_SvN, /**< eiger */
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E_Vtr, /**< eiger */
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E_Vrf, /**< eiger */
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E_Vrs, /**< eiger */
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E_Vtgstv , /**< eiger */
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E_Vcmp_ll, /**< eiger */
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E_Vcmp_lr, /**< eiger */
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E_cal, /**< eiger */
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E_Vcmp_rl, /**< eiger */
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E_Vcmp_rr, /**< eiger */
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E_rxb_rb , /**< eiger */
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E_rxb_lb, /**< eiger */
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E_Vcp, /**< eiger */
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E_Vcn, /**< eiger */
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E_Vis, /**< eiger */
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IO_DELAY, /**< eiger io delay */
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ADC_VPP, /**< adc vpp for jctb */
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HV_NEW, /**< new hv index for jungfrau & c */
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TEMPERATURE_FPGAEXT, /**< temperature sensor (close to fpga) */
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TEMPERATURE_10GE, /**< temperature sensor (close to 10GE) */
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TEMPERATURE_DCDC, /**< temperature sensor (close to DCDC) */
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TEMPERATURE_SODL, /**< temperature sensor (close to SODL) */
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TEMPERATURE_SODR, /**< temperature sensor (close to SODR) */
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TEMPERATURE_FPGA2, /**< temperature sensor (fpga2 (eiger:febl) */
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TEMPERATURE_FPGA3, /**< temperature sensor (fpga3 (eiger:febr) */
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M_vIpre, /**< mythen 3 >*/
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M_vIbias, /**< mythen 3 >*/
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M_vIinSh, /**< mythen 3 >*/
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M_VdcSh, /**< mythen 3 >*/
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M_Vth2, /**< mythen 3 >*/
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M_VPL, /**< mythen 3 >*/
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M_Vth3, /**< mythen 3 >*/
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M_casSh, /**< mythen 3 >*/
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M_cas, /**< mythen 3 >*/
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M_vIbiasSh, /**< mythen 3 >*/
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M_vIcin, /**< mythen 3 >*/
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M_vIpreOut, /**< mythen 3 >*/
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V_POWER_A = 100, /**new chiptest board */
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V_POWER_B = 101, /**new chiptest board */
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V_POWER_C = 102, /**new chiptest board */
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V_POWER_D = 103, /**new chiptest board */
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V_POWER_IO =104, /**new chiptest board */
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V_POWER_CHIP=105 ,/**new chiptest board */
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I_POWER_A=106 , /**new chiptest board */
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I_POWER_B=107 , /**new chiptest board */
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I_POWER_C=108 , /**new chiptest board */
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I_POWER_D=109 , /**new chiptest board */
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I_POWER_IO=110 , /**new chiptest board */
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V_LIMIT=111 /**new chiptest board */
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};
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/**
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detector settings indexes
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*/
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enum detectorSettings{
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GET_SETTINGS=-1, /**< return current detector settings */
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STANDARD, /**< standard settings */
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FAST, /**< fast settings */
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HIGHGAIN, /**< highgain settings */
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DYNAMICGAIN, /**< dynamic gain settings */
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LOWGAIN, /**< low gain settings */
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MEDIUMGAIN, /**< medium gain settings */
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VERYHIGHGAIN, /**< very high gain settings */
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LOWNOISE, /**< low noise settings */
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DYNAMICHG0, /**< dynamic high gain 0 */
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FIXGAIN1, /**< fix gain 1 */
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FIXGAIN2, /**< fix gain 2 */
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FORCESWITCHG1, /**< force switch gain 1 */
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FORCESWITCHG2, /**< force switch gain 2 */
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VERYLOWGAIN, /**< very low gain settings */
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UNDEFINED=200, /**< undefined or custom settings */
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UNINITIALIZED /**< uninitialiazed (status at startup) */
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};
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#define TRIMBITMASK 0x3f
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/**
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important speed parameters
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*/
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enum speedVariable {
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CLOCK_DIVIDER, /**< readout clock divider */
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PHASE_SHIFT, /**< adds phase shift */
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OVERSAMPLING, /**< oversampling for analog detectors */
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ADC_CLOCK, /**< adc clock divider */
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ADC_PHASE, /**< adc clock phase */
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ADC_PIPELINE, /**< adc pipeline */
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DBIT_CLOCK, /**< adc clock divider */
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DBIT_PHASE, /**< adc clock phase */
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DBIT_PIPELINE /**< adc pipeline */
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};
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/**
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readout flags
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*/
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enum readOutFlags {
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GET_READOUT_FLAGS=-1, /**< return readout flags */
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NORMAL_READOUT=0, /**< no flag */
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STORE_IN_RAM=0x1, /**< data are stored in ram and sent only after end of acquisition for faster frame rate */
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READ_HITS=0x2, /**< return only the number of the channel which counted ate least one */
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ZERO_COMPRESSION=0x4,/**< returned data are 0-compressed */
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PUMP_PROBE_MODE=0x8,/**<pump-probe mode */
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BACKGROUND_CORRECTIONS=0x1000, /**<background corrections */
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TOT_MODE=0x2000,/**< pump-probe mode */
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CONTINOUS_RO=0x4000,/**< pump-probe mode */
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PARALLEL=0x10000,/**< eiger parallel mode */
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NONPARALLEL=0x20000,/**< eiger serial mode */
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SAFE=0x40000/**< eiger safe mode */,
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DIGITAL_ONLY=0x80000, /** chiptest board read only digital bits (not adc values)*/
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ANALOG_AND_DIGITAL=0x100000, /** chiptest board read adc values and digital bits digital bits */
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DUT_CLK=0x200000, /** chiptest board fifo clock comes from device under test */
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SHOW_OVERFLOW=0x400000, /** eiger 32 bit mode, show saturated for overflow of single subframes */
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NOOVERFLOW=0x800000 /** eiger 32 bit mode, do not show saturated for overflow of single subframes */
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};
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/** port type */
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enum portType {
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CONTROL_PORT, /**< control port */
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STOP_PORT, /**<stop port */
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DATA_PORT /**< receiver tcp port with client*/
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};
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/** hierarchy in multi-detector structure, if any */
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enum masterFlags {
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GET_MASTER=-1, /**< return master flag */
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NO_MASTER, /**< no master/slave hierarchy defined */
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IS_MASTER, /**<is master */
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IS_SLAVE /**< is slave */
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};
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enum imageType {
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DARK_IMAGE, /**< dark image */
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GAIN_IMAGE /**< gain image */
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};
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//#if defined(__cplusplus) && !defined(EIGERD)
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#ifdef __cplusplus
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protected:
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#endif
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#ifndef MYROOT
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#include "sls_detector_funcs.h"
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//#include "sls_receiver_funcs.h"
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#endif
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//#if defined(__cplusplus) && !defined(EIGERD)
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#ifdef __cplusplus
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};
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#endif
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;
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#endif
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;
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