This commit is contained in:
2021-06-22 20:50:50 +02:00
parent 1a88cbd266
commit 755738a42e
15 changed files with 378 additions and 49 deletions

View File

@ -43,6 +43,8 @@ int Beb_deactivated_transmission_flowcontrol_10g = 0;
int Beb_deactivated_transmission_delay_frame = 0;
int Beb_deactivated_transmission_delay_left = 0;
int Beb_deactivated_transmission_delay_right = 0;
int Beb_deactivated_left_datastream = 1;
int Beb_deactivated_right_datastream = 1;
void BebInfo_BebInfo(struct BebInfo *bebInfo, unsigned int beb_num) {
bebInfo->beb_number = beb_num;
@ -449,6 +451,77 @@ int Beb_GetActivate(int *retval) {
return 1;
}
int Beb_SetDataStream(int left, int enable) {
if (!Beb_activated) {
if (left) {
Beb_deactivated_left_datastream = enable;
} else {
Beb_deactivated_right_datastream = enable;
}
return 1;
}
if (left < 0) {
LOG(logERROR, ("Invalid left value\n"));
return 0;
}
if (enable < 0) {
LOG(logERROR, ("Invalid enable value\n"));
return 0;
}
u_int32_t *csp0base = 0;
int fd = Beb_open(&csp0base, XPAR_PLB_GPIO_SYS_BASEADDR);
if (fd < 0) {
LOG(logERROR, ("Activate FAIL, could not open fd\n"));
return 0;
} else {
u_int32_t reg = XPAR_GPIO_P15_STREAMING_REG;
u_int32_t mask =
(left ? XPAR_GPIO_LFT_STRM_DSBL_MSK : XPAR_GPIO_RGHT_STRM_DSBL_MSK);
u_int32_t value = Beb_Read32(csp0base, reg);
LOG(logDEBUG, ("data streaming register value before:%d\n", value));
if (enable)
value |= mask;
else
value &= ~mask;
u_int32_t retval = Beb_Write32(csp0base, reg, value);
if (retval != value) {
LOG(logERROR,
("Could not %s %s fpga datastream. Wrote 0x%x, read 0x%x\n",
(enable ? "enable" : "disable"), (left ? "left" : "right"),
value, retval));
Beb_close(fd, csp0base);
}
}
Beb_close(fd, csp0base);
return 1;
}
int Beb_GetDataStream(int left, int *retval) {
if (!Beb_activated) {
if (left) {
return Beb_deactivated_left_datastream;
} else {
return Beb_deactivated_right_datastream;
}
}
u_int32_t *csp0base = 0;
int fd = Beb_open(&csp0base, XPAR_PLB_GPIO_SYS_BASEADDR);
if (fd < 0) {
LOG(logERROR, ("Activate FAIL, could not open fd\n"));
return 0;
} else {
u_int32_t reg = XPAR_GPIO_P15_STREAMING_REG;
u_int32_t mask =
(left ? XPAR_GPIO_LFT_STRM_DSBL_MSK : XPAR_GPIO_RGHT_STRM_DSBL_MSK);
u_int32_t value = Beb_Read32(csp0base, reg);
*retval = (value & mask) ? 1 : 0;
}
Beb_close(fd, csp0base);
return 1;
}
int Beb_Set32bitOverflow(int val) {
if (!Beb_activated)
return val;

View File

@ -41,6 +41,8 @@ int Beb_SetTop(enum TOPINDEX ind);
int Beb_SetMaster(enum MASTERINDEX ind);
int Beb_SetActivate(int enable);
int Beb_GetActivate(int *retval);
int Beb_SetDataStream(int left, int enable);
int Beb_GetDataStream(int left, int *retval);
int Beb_Set32bitOverflow(int val);
int Beb_GetTenGigaFlowControl();

View File

@ -91,6 +91,8 @@ int eiger_virtual_test_mode = 0;
int eiger_virtual_quad_mode = 0;
int eiger_virtual_read_nlines = 256;
int eiger_virtual_interrupt_subframe = 0;
int eiger_virtual_left_datastream = 1;
int eiger_virtual_right_datastream = 1;
#endif
int isInitCheckDone() { return initCheckDone; }
@ -2048,6 +2050,44 @@ int getActivate(int *retval) {
return OK;
}
int setDataStream(int left, int enable) {
if (enable < 0) {
LOG(logERROR, ("Invalid setDataStream enable argument: %d\n", enable));
return FAIL;
}
if (left < 0) {
LOG(logERROR, ("Invalid setDataStream left argument: %d\n", left));
return FAIL;
}
#ifdef VIRTUAL
if (left) {
eiger_virtual_left_datastream = enable;
} else {
eiger_virtual_right_datastream = enable;
}
#else
if (!Beb_SetDataStream(left, enable)) {
return FAIL;
}
#endif
return OK;
}
int getDataStream(int left, int *retval) {
#ifdef VIRTUAL
if (left) {
*retval = eiger_virtual_left_datastream;
} else {
*retval = eiger_virtual_right_datastream;
}
#endif
if (!Beb_GetDataStream(left, retval)) {
return FAIL;
}
#endif
return OK;
}
int getTenGigaFlowControl() {
#ifdef VIRTUAL
return eiger_virtual_transmission_flowcontrol_10g;

View File

@ -35,7 +35,7 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
/* Definitions for peripheral PLB_BRAM_10G */
#define XPAR_PLB_BRAM_10G_MEM0_BASEADDR 0xD4100000
#define XPAR_PLB_BRAM_10G_MEM0_HIGHADDR 0xD410FFFF
#define XPAR_PLB_BRAM_10G_MEM0_HIGHADDR
/* Definitions for peripheral PLB_BRAM_TEMAC */
#define XPAR_PLB_BRAM_TEMAC_MEM0_BASEADDR 0xD4000000
@ -45,6 +45,18 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_PLB_GPIO_SYS_BASEADDR 0xD1000000
#define XPAR_PLB_GPIO_SYS_HIGHADDR 0xD100FFFF
// data streaming register
// clang-format off
#define XPAR_GPIO_P15_STREAMING_REG 0x01e0
#define XPAR_GPIO_FRAME_PKT_ENBL_OFST (0)
#define XPAR_GPIO_FRAME_PKT_ENBL_MSK (0x00000001 << XPAR_GPIO_FRAME_PKT_ENBL_OFST)
#define XPAR_GPIO_RGHT_STRM_DSBL_OFST (1)
#define XPAR_GPIO_RGHT_STRM_DSBL_MSK (0x00000001 << XPAR_GPIO_RGHT_STRM_DSBL_OFST)
#define XPAR_GPIO_LFT_STRM_DSBL_OFST (2)
#define XPAR_GPIO_LFT_STRM_DSBL_MSK (0x00000001 << XPAR_GPIO_LFT_STRM_DSBL_OFST)
// clang-format on
/** Command Generator */
#define XPAR_CMD_GENERATOR 0xC5000000