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rxMemsize (#479)

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* changing fifo header size to 16 to fix the rxr header (112) to be a power of 2 to make it more efficient and reduce packet loss

* release notes
This commit is contained in:
Dhanya Thattil
2022-06-08 12:03:13 +02:00
committed by GitHub
parent 1fb90ab98c
commit 728cb35c37
2 changed files with 2 additions and 1 deletions
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1
RELEASE.txt
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@ -79,6 +79,7 @@ This document describes the differences between v7.0.0 and v6.x.x
- g2 and m3 clkdiv 2 (system clock) change should affect time settings (g2: exptime, period, delayaftertrigger, burstperiod, m3: exptime, gatedelay, gateperiod, period, delayaftertrigger)
- g2 system frequency is the same irrespective of timing source
- (apparently) rxr doesnt get stuck anymore from 6.1.1
- rxr mem size changed (fifo header size from 8 to 16) due to sls rxr header = 112.. 112+ 16=128 (reduces packet losss especially for g2)
2. Resolved Issues
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