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client: removed slsDetectorutils and postprocessing. yet to compile, yet to add detpos index for every multi sls detector command and call from command interface, removed multiple threading, yet to interface with eriks single template for multiple threading

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This commit is contained in:
maliakal_d
2018-10-03 11:15:39 +02:00
parent dafbc970e3
commit 70ea4b48c3
279 changed files with 578 additions and 10937 deletions
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141
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/AD9257.h Executable file
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#ifndef AD9257_H
#define AD9257_H
#include "ansi.h"
#include "commonServerFunctions.h"
#include <stdio.h>
/* AD9257 ADC DEFINES */
#define AD9257_ADC_NUMBITS (24)
#define AD9257_DEV_IND_2_REG (0x04)
#define AD9257_CHAN_H_OFST (0)
#define AD9257_CHAN_H_MSK (0x00000001 << AD9257_CHAN_H_OFST)
#define AD9257_CHAN_G_OFST (1)
#define AD9257_CHAN_G_MSK (0x00000001 << AD9257_CHAN_G_OFST)
#define AD9257_CHAN_F_OFST (2)
#define AD9257_CHAN_F_MSK (0x00000001 << AD9257_CHAN_F_OFST)
#define AD9257_CHAN_E_OFST (3)
#define AD9257_CHAN_E_MSK (0x00000001 << AD9257_CHAN_E_OFST)
#define AD9257_DEV_IND_1_REG (0x05)
#define AD9257_CHAN_D_OFST (0)
#define AD9257_CHAN_D_MSK (0x00000001 << AD9257_CHAN_D_OFST)
#define AD9257_CHAN_C_OFST (1)
#define AD9257_CHAN_C_MSK (0x00000001 << AD9257_CHAN_C_OFST)
#define AD9257_CHAN_B_OFST (2)
#define AD9257_CHAN_B_MSK (0x00000001 << AD9257_CHAN_B_OFST)
#define AD9257_CHAN_A_OFST (3)
#define AD9257_CHAN_A_MSK (0x00000001 << AD9257_CHAN_A_OFST)
#define AD9257_CLK_CH_DCO_OFST (4)
#define AD9257_CLK_CH_DCO_MSK (0x00000001 << AD9257_CLK_CH_DCO_OFST)
#define AD9257_CLK_CH_IFCO_OFST (5)
#define AD9257_CLK_CH_IFCO_MSK (0x00000001 << AD9257_CLK_CH_IFCO_OFST)
#define AD9257_POWER_MODE_REG (0x08)
#define AD9257_POWER_INTERNAL_OFST (0)
#define AD9257_POWER_INTERNAL_MSK (0x00000003 << AD9257_POWER_INTERNAL_OFST)
#define AD9257_INT_RESET_VAL (0x3)
#define AD9257_INT_CHIP_RUN_VAL (0x0)
#define AD9257_POWER_EXTERNAL_OFST (5)
#define AD9257_POWER_EXTERNAL_MSK (0x00000001 << AD9257_POWER_EXTERNAL_OFST)
#define AD9257_EXT_FULL_POWER_VAL (0x0)
#define AD9257_EXT_STANDBY_VAL (0x1)
#define AD9257_OUT_MODE_REG (0x14)
#define AD9257_OUT_FORMAT_OFST (0)
#define AD9257_OUT_FORMAT_MSK (0x00000001 << AD9257_OUT_FORMAT_OFST)
#define AD9257_OUT_BINARY_OFST_VAL (0)
#define AD9257_OUT_TWOS_COMPL_VAL (1)
#define AD9257_OUT_LVDS_OPT_OFST (6)
#define AD9257_OUT_LVDS_OPT_MSK (0x00000001 << AD9257_OUT_LVDS_OPT_OFST)
#define AD9257_OUT_LVDS_ANSI_VAL (0)
#define AD9257_OUT_LVDS_IEEE_VAL (1)
#define AD9257_OUT_PHASE_REG (0x16)
#define AD9257_OUT_CLK_OFST (0)
#define AD9257_OUT_CLK_MSK (0x0000000F << AD9257_OUT_CLK_OFST)
#define AD9257_OUT_CLK_60_VAL (0x1)
#define AD9257_IN_CLK_OFST (4)
#define AD9257_IN_CLK_MSK (0x00000007 << AD9257_IN_CLK_OFST)
#define AD9257_IN_CLK_0_VAL (0x0)
#define AD9257_VREF_REG (0x18)
#define AD9257_VREF_OFST (0)
#define AD9257_VREF_MSK (0x00000003 << AD9257_VREF_OFST)
#define AD9257_VREF_1_33_VAL (0x2)
#define AD9257_TEST_MODE_REG (0x0D)
#define AD9257_OUT_TEST_OFST (0)
#define AD9257_OUT_TEST_MSK (0x0000000F << AD9257_OUT_TEST_OFST)
#define AD9257_NONE_VAL (0x0)
#define AD9257_MIXED_BIT_FREQ_VAL (0xC)
#define AD9257_TEST_RESET_SHORT_GEN (4)
#define AD9257_TEST_RESET_LONG_GEN (5)
#define AD9257_USER_IN_MODE_OFST (6)
#define AD9257_USER_IN_MODE_MSK (0x00000003 << AD9257_USER_IN_MODE_OFST)
void setAdc(int addr, int val) {
u_int32_t codata;
codata = val + (addr << 8);
printf(" Setting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr);
serializeToSPI(ADC_SPI_REG, codata, ADC_SERIAL_CS_OUT_MSK, AD9257_ADC_NUMBITS,
ADC_SERIAL_CLK_OUT_MSK, ADC_SERIAL_DATA_OUT_MSK, ADC_SERIAL_DATA_OUT_OFST);
}
void prepareADC(){
printf("\n\nPreparing ADC ... \n");
//power mode reset
printf("power mode reset:\n");
setAdc(AD9257_POWER_MODE_REG,
(AD9257_INT_RESET_VAL << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK);
//power mode chip run
printf("power mode chip run:\n");
setAdc(AD9257_POWER_MODE_REG,
(AD9257_INT_CHIP_RUN_VAL << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK);
//output clock phase
printf("output clock phase:\n");
setAdc(AD9257_OUT_PHASE_REG,
(AD9257_OUT_CLK_60_VAL << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK);
// lvds-iee reduced , binary offset
printf("lvds-iee reduced, binary offset:\n");
setAdc(AD9257_OUT_MODE_REG,
(AD9257_OUT_LVDS_IEEE_VAL << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK);
// all devices on chip to receive next command
printf("all devices on chip to receive next command:\n");
setAdc(AD9257_DEV_IND_2_REG,
AD9257_CHAN_H_MSK | AD9257_CHAN_G_MSK | AD9257_CHAN_F_MSK | AD9257_CHAN_E_MSK);
setAdc(AD9257_DEV_IND_1_REG,
AD9257_CHAN_D_MSK | AD9257_CHAN_C_MSK | AD9257_CHAN_B_MSK | AD9257_CHAN_A_MSK |
AD9257_CLK_CH_DCO_MSK | AD9257_CLK_CH_IFCO_MSK);
// vref 1.33
printf("vref 1.33:\n");
setAdc(AD9257_VREF_REG,
(AD9257_VREF_1_33_VAL << AD9257_VREF_OFST) & AD9257_VREF_MSK);
// no test mode
printf("no test mode:\n");
setAdc(AD9257_TEST_MODE_REG,
(AD9257_NONE_VAL << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK);
#ifdef TESTADC
printf("***************************************** *******\n");
printf("******* PUTTING ADC IN TEST MODE!!!!!!!!! *******\n");
printf("***************************************** *******\n");
// mixed bit frequency test mode
printf("mixed bit frequency test mode:\n");
setAdc(AD9257_TEST_MODE_REG,
(AD9257_MIXED_BIT_FREQ_VAL << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK);
#endif
}
#endif //AD9257_H

59
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/Makefile Normal file
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# $Id: Makefile,v 1.1.1.1 2006/02/04 03:35:01 freza Exp $
# first compile
# make cris-axis-linux-gnu
CROSS = bfin-uclinux-
CC = $(CROSS)gcc
CFLAGS += -Wall -DMOENCHD -DMCB_FUNCS -DDACS_INT -DDEBUG -DV1 -DCTB -DOLDVERSION #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL #-DDACS_INT_CSERVER
PROGS= jctbDetectorServer
INSTDIR= /tftpboot
INSTMODE= 0777
BINS = testlib_sharedlibc
SRCS = server.c server_funcs.c communication_funcs.c firmware_funcs.c slow_adc.c blackfin.c
#mcb_funcs.c sharedmemory.c
OBJS = $(SRCS:%.c=%.o)
all: clean versioning $(PROGS)
test: clean jungfrauADCTEst
boot: $(OBJS)
versioning:
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
jctbDetectorServerNew: $(OBJS)
echo $(OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@)
jctbDetectorServer: $(OBJS)
echo $(OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@) -DOLDVERSION
jungfrauADCTEst: $(OBJS)
echo $(OBJS)
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@) -DTESTADC
install: $(PROGS)
$(INSTALL) -d $(INSTDIR)
$(INSTALL) -m $(INSTMODE) $(PROGS) $(INSTDIR)
romfs:
$(ROMFSINST) /bin/$(PROGS)
clean:
rm -rf $(PROGS) *.o *.gdb

1
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/ansi.h Symbolic link
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../../slsReceiverSoftware/include/ansi.h

1
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/bf_init.sh Normal file
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export PATH=/afs/psi.ch/project/sls_det_firmware/jungfrau_software/uClinux-2010_64bit/bfin-uclinux/bin:$PATH

150
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/blackfin.c Normal file
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#include "blackfin.h"
#include <sys/ipc.h>
#include <sys/shm.h>
#include <sys/time.h>
#include <string.h>
#include <sys/utsname.h>
#include <sys/types.h>
#include <sys/socket.h>
#include <netinet/in.h>
#include <netinet/tcp.h>
#include <arpa/inet.h>
#include <netdb.h>
#include <time.h>
#include <sys/time.h>
#include <sys/mman.h>
#include <sys/socket.h>
#include <sys/stat.h>
#include <errno.h>
#include <fcntl.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h>
#include "server_defs.h"
#include "registers_m.h"
//for memory mapping
u_int32_t CSP0BASE;
u_int16_t volatile *values;
int mapCSP0(void) {
printf("Mapping memory\n");
#ifndef VIRTUAL
int fd;
fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
if (fd == -1) {
printf("\nCan't find /dev/mem!\n");
return FAIL;
}
printf("/dev/mem opened\n");
CSP0BASE = (u_int32_t)mmap(0, MEM_SIZE, PROT_READ|PROT_WRITE, MAP_FILE|MAP_SHARED, fd, CSP0);
if (CSP0BASE == (u_int32_t)MAP_FAILED) {
printf("\nCan't map memmory area!!\n");
return FAIL;
}
printf("CSP0 mapped\n");
#endif
#ifdef VIRTUAL
CSP0BASE = malloc(MEM_SIZE);
printf("memory allocated\n");
#endif
#ifdef SHAREDMEMORY
if ( (res=inism(SMSV))<0) {
printf("error attaching shared memory! %i",res);
return FAIL;
}
#endif
printf("CSPObase is 0x%08x \n",CSP0BASE);
printf("CSPOBASE=from %08x to %08x\n",CSP0BASE,CSP0BASE+MEM_SIZE);
u_int32_t address;
address = FIFO_DATA_REG;//_OFF;
//values=(u_int32_t*)(CSP0BASE+address*2);
values=(u_int16_t*)(CSP0BASE+address*2);
printf("statusreg=%08x\n",bus_r(STATUS_REG));
printf("\n\n");
return OK;
}
u_int16_t bus_r16(u_int32_t offset){
volatile u_int16_t *ptr1;
ptr1=(u_int16_t*)(CSP0BASE+offset*2);
return *ptr1;
}
u_int16_t bus_w16(u_int32_t offset, u_int16_t data) {
volatile u_int16_t *ptr1;
ptr1=(u_int16_t*)(CSP0BASE+offset*2);
*ptr1=data;
return OK;
}
u_int32_t bus_w(u_int32_t offset, u_int32_t data) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(CSP0BASE+offset*2);
*ptr1=data;
return OK;
}
u_int32_t bus_r(u_int32_t offset) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(CSP0BASE+offset*2);
return *ptr1;
}
// program dacq settings
int64_t set64BitReg(int64_t value, int aLSB, int aMSB){
int64_t v64;
u_int32_t vLSB,vMSB;
if (value!=-1) {
vLSB=value&(0xffffffff);
bus_w(aLSB,vLSB);
v64=value>> 32;
vMSB=v64&(0xffffffff);
bus_w(aMSB,vMSB);
// printf("Wreg64(%x,%x) %08x %08x %016llx\n", aLSB>>11, aMSB>>11, vLSB, vMSB, value);
}
return get64BitReg(aLSB, aMSB);
}
int64_t get64BitReg(int aLSB, int aMSB){
int64_t v64;
u_int32_t vLSB,vMSB;
vLSB=bus_r(aLSB);
vMSB=bus_r(aMSB);
v64=vMSB;
v64=(v64<<32) | vLSB;
// printf("reg64(%x,%x) %x %x %llx\n", aLSB, aMSB, vLSB, vMSB, v64);
return v64;
}
/* /\** */
/* /\** ramType is DARK_IMAGE_REG or GAIN_IMAGE_REG *\/ */
/* u_int16_t ram_w16(u_int32_t ramType, int adc, int adcCh, int Ch, u_int16_t data) { */
/* unsigned int adr = (ramType | adc << 8 | adcCh << 5 | Ch ); */
/* // printf("Writing to addr:%x\n",adr); */
/* return bus_w16(adr,data); */
/* } */
/* /\** ramType is DARK_IMAGE_REG or GAIN_IMAGE_REG *\/ */
/* u_int16_t ram_r16(u_int32_t ramType, int adc, int adcCh, int Ch){ */
/* unsigned int adr = (ramType | adc << 8 | adcCh << 5 | Ch ); */
/* // printf("Reading from addr:%x\n",adr); */
/* return bus_r16(adr); */
/* } */
/* **\/ */

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slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/blackfin.h Normal file
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#ifndef BLACKFIN_H
#define BLACKFIN_H
#define CSP0 0x20200000
#define MEM_SIZE 0x100000
#ifndef OLDVERSION
#define MEM_MAP_SHIFT 1
#endif
#ifdef OLDVERSION
#define MEM_MAP_SHIFT 11
#endif
#include <sys/types.h>
int mapCSP0(void);
u_int16_t bus_r16(u_int32_t offset);
u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
u_int32_t bus_w(u_int32_t offset, u_int32_t data);
u_int32_t bus_r(u_int32_t offset);
int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
int64_t get64BitReg(int aLSB, int aMSB);
#endif

73
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/commonServerFunctions.h Executable file
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#ifndef COMMON_SERVER_FUNCTIONS_H
#define COMMON_SERVER_FUNCTIONS_H
#ifndef GOTTHARDD //gotthard already had bus_w etc defined in its firmware_funcs.c (not yet made with common files)
#include "blackfin.h"
#endif
/* global variables */
void SPIChipSelect (u_int32_t* valw, u_int32_t addr, u_int32_t csmask) {
// start point
(*valw) = 0xffffffff; // old board compatibility (not using specific bits)
bus_w (addr, (*valw));
// chip sel bar down
(*valw) &= ~csmask; /* todo with test: done a bit different, not with previous value */
bus_w (addr, (*valw));
}
void SPIChipDeselect (u_int32_t* valw, u_int32_t addr, u_int32_t csmask, u_int32_t clkmask) {
// chip sel bar up
(*valw) |= csmask; /* todo with test: not done for spi */
bus_w (addr, (*valw));
//clk down
(*valw) &= ~clkmask;
bus_w (addr, (*valw));
// stop point = start point of course
(*valw) = 0xffffffff; // old board compatibility (not using specific bits)
bus_w (addr, (*valw));
}
void sendDataToSPI (u_int32_t* valw, u_int32_t addr, u_int32_t val, int numbitstosend, u_int32_t clkmask, u_int32_t digoutmask, int digofset) {
int i = 0;
for (i = 0; i < numbitstosend; ++i) {
// clk down
(*valw) &= ~clkmask;
bus_w (addr, (*valw));
// write data (i)
(*valw) = (((*valw) & ~digoutmask) + // unset bit
(((val >> (numbitstosend - 1 - i)) & 0x1) << digofset)); // each bit from val starting from msb
bus_w (addr, (*valw));
// clk up
(*valw) |= clkmask ;
bus_w (addr, (*valw));
}
}
void serializeToSPI(u_int32_t addr, u_int32_t val, u_int32_t csmask, int numbitstosend, u_int32_t clkmask, u_int32_t digoutmask, int digofset) {
#ifdef VERBOSE
if (numbitstosend == 16)
printf("Writing to SPI Register: 0x%04x\n",val);
else
printf("Writing to SPI Register: 0x%08x\n", val);
#endif
u_int32_t valw;
SPIChipSelect (&valw, addr, csmask);
sendDataToSPI(&valw, addr, val, numbitstosend, clkmask, digoutmask, digofset);
SPIChipDeselect(&valw, addr, csmask, clkmask);
}
#endif //COMMON_SERVER_FUNCTIONS_H

1
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/communication_funcs.c Symbolic link
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../commonFiles/communication_funcs.c

1
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/communication_funcs.h Symbolic link
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../commonFiles/communication_funcs.h

58
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/convert_pof_to_raw.c Normal file
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// Converts POF files into RAW files for flashing
#include <stdio.h>
#include <stdlib.h>
// Warning: This program is for testing only.
// It makes some assumptions regarding the pof file and the flash size that might be wrong.
// It also overwrites the destination file without any hesitation.
// Handle with care.
int main(int argc, char* argv[])
{
FILE* src;
FILE* dst;
int x;
int y;
int i;
int filepos;
if (argc < 3)
{
printf("%s Sourcefile Destinationfile\n",argv[0]);
return -1;
}
src = fopen(argv[1],"rb");
dst = fopen(argv[2],"wb");
// Remove header (0...11C)
for (filepos=0; filepos < 0x11C; filepos++)
fgetc(src);
// Write 0x80 times 0xFF (0...7F)
for (filepos=0; filepos < 0x80; filepos++)
fputc(0xFF,dst);
// Swap bits and write to file
for (filepos=0x80; filepos < 0x1000000; filepos++)
{
x = fgetc(src);
if (x < 0) break;
y=0;
for (i=0; i < 8; i++)
y=y| ( (( x & (1<<i) ) >> i) << (7-i) ); // This swaps the bits
fputc(y,dst);
}
if (filepos < 0x1000000)
printf("ERROR: EOF before end of flash\n");
printf("To flash the file in Linux do:\n");
printf(" cat /proc/mtd (to findout the right mtd)\n");
printf(" flash_eraseall /dev/mtdX\n");
printf(" cat file > /dev/mtdX\n");
return 0;
}

4072
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/firmware_funcs.c Executable file
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239
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/firmware_funcs.h Executable file
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#ifndef FIRMWARE_FUNCS_H
#define FIRMWARE_FUNCS_H
#include "sls_detector_defs.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <stdarg.h>
#include <unistd.h>
//#include <asm/page.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdarg.h>
#include <unistd.h>
int mapCSP0(void);
u_int16_t bus_r16(u_int32_t offset);
u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
u_int32_t bus_w(u_int32_t offset, u_int32_t data);
u_int32_t bus_r(u_int32_t offset);
//int setPhaseShiftOnce();
//int phaseStep(int st);
//int dbitPhaseStep(int st);
//int getDbitPhase();
int getPhase(int i);
int cleanFifo();
int setDAQRegister();
int configurePhase(int val, int i);
int configureFrequency(int val, int i);
u_int32_t putout(char *s, int modnum);
u_int32_t readin(int modnum);
//u_int32_t setClockDivider(int d, int ic);
//u_int32_t getClockDivider(int ic);
void resetPLL();
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val, int trig);
u_int32_t getPllReconfigReg(u_int32_t reg, int trig);
u_int32_t setSetLength(int d);
u_int32_t getSetLength();
u_int32_t setWaitStates(int d);
u_int32_t getWaitStates();
//u_int32_t setTotClockDivider(int d);
//u_int32_t getTotClockDivider();
//u_int32_t setTotDutyCycle(int d);
//u_int32_t getTotDutyCycle();
u_int32_t setOversampling(int d);
u_int32_t adcPipeline(int d);
u_int32_t dbitPipeline(int d);
u_int32_t setExtSignal(int d, enum externalSignalFlag mode);
int getExtSignal(int d);
u_int32_t setFPGASignal(int d, enum externalSignalFlag mode);
int getFPGASignal(int d);
int setTiming(int t);
int setConfigurationRegister(int d);
int setToT(int d);
int setContinousReadOut(int d);
int startReceiver(int d);
int setDACRegister(int idac, int val, int imod);
int getDacRegister(int dacnum);
int getTemperature(int tempSensor);
int initHighVoltage(int val,int imod);
int initConfGain(int isettings,int val,int imod);
//int setADC(int adc);
//int configureMAC(int ipad, long long int macad, long long int detectormacadd, int detipad, int ival, int udpport);
int configureMAC(uint32_t destip,uint64_t destmac,uint64_t sourcemac,int detipad,int ival,uint32_t destport);
int getAdcConfigured();
u_int64_t getDetectorNumber();
u_int32_t getFirmwareVersion();
u_int32_t getFirmwareSVNVersion();
int testFifos(void);
u_int32_t testFpga(void);
u_int32_t testRAM(void);
int testBus(void);
int setDigitalTestBit(int ival);
int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
int64_t get64BitReg(int aLSB, int aMSB);
int64_t setFrames(int64_t value);
int64_t getFrames();
int64_t setExposureTime(int64_t value);
int64_t getExposureTime();
int64_t setGates(int64_t value);
int64_t getGates();
int64_t setDelay(int64_t value);
int64_t getDelay();
int64_t setPeriod(int64_t value);
int64_t getPeriod();
int64_t setTrains(int64_t value);
int64_t getTrains();
int64_t setProbes(int64_t value);
int64_t getProbes();
int64_t getProgress();
int64_t setProgress();
int64_t getActualTime();
int64_t getMeasurementTime();
int64_t getFramesFromStart();
u_int32_t runBusy(void);
u_int32_t runState(void);
u_int32_t dataPresent(void);
int startStateMachine();
int stopStateMachine();
int startReadOut();
u_int32_t fifoReset(void);
u_int32_t fifoReadCounter(int fifonum);
u_int32_t fifoReadStatus();
u_int32_t fifo_full(void);
u_int16_t* fifo_read_event(int ns);
u_int16_t* fifo_read_frame();
u_int32_t* decode_data(int* datain);
//u_int32_t move_data(u_int64_t* datain, u_int64_t* dataout);
int setDynamicRange(int dr);
int getDynamicRange();
int getNModBoard();
int setNMod(int n);
int getNMod();
int setStoreInRAM(int b);
int allocateRAM();
int writeADC(int addr, int val);
//int prepareADC();
int clearRAM();
int setMaster(int f);
int setSynchronization(int s);
int loadImage(int index, short int ImageVals[]);
int readCounterBlock(int startACQ, short int CounterVals[]);
int resetCounterBlock(int startACQ);
int calibratePedestal(int frames);
uint64_t writePatternWord(int addr, uint64_t word);
uint64_t writePatternIOControl(uint64_t word);
uint64_t writePatternClkControl(uint64_t word);
int setPatternLoop(int level, int *start, int *stop, int *n);
int setPatternWaitAddress(int level, int addr);
uint64_t setPatternWaitTime(int level, uint64_t t);
void initDac(int dacnum);
int setDac(int dacnum,int dacvalue);
int setPower(int ind, int val);
int setROI(int nroi,ROI* arg,int *retvalsize, int *ret);
int getChannels();
int getCurrent(int idac);
int getVoltage(int idac);
void defineGPIOpins();
void resetFPGA();
void FPGAdontTouchFlash();
void FPGATouchFlash();
int startWritingFPGAprogram(FILE** filefp);
int stopWritingFPGAprogram(FILE* filefp);
int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp);
void eraseFlash();
/*
u_int32_t setNBits(u_int32_t);
u_int32_t getNBits();
*/
/*
//move to mcb_funcs?
int readOutChan(int *val);
u_int32_t getModuleNumber(int modnum);
int testShiftIn(int imod);
int testShiftOut(int imod);
int testShiftStSel(int imod);
int testDataInOut(int num, int imod);
int testExtPulse(int imod);
int testExtPulseMux(int imod, int ow);
int testDataInOutMux(int imod, int ow, int num);
int testOutMux(int imod);
int testFpgaMux(int imod);
int calibration_sensor(int num, int *values, int *dacs) ;
int calibration_chip(int num, int *values, int *dacs);
*/
int64_t setSamples(int64_t value);
//int setOutputMode(int d);
int setReadOutMode(int arg);
int vLimitCompliant(int val_mV)
#endif

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slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/get_server.sh Executable file
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#!/bin/sh
serv="pc8498"
f="jungfrauDetectorServerTest"
if [ "$#" -gt 0 ]; then
f=$1
fi
if [ "$#" -gt 1 ]; then
serv=$2
fi
tftp $serv -r $f -g
chmod a+xrw $f

9
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/gitInfo.txt Normal file
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Path: slsDetectorsPackage/slsDetectorSoftware/jctbDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: 9ae128961675230ad322ff2867f1862dbe8566a7
Revision: 25
Branch: developer
Last Changed Author: Anna_Bergamaschi
Last Changed Rev: 3764
Last Changed Date: 2018-05-07 14:30:14.000000002 +0200 ./Makefile

6
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/gitInfoMoench.h Normal file
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#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "9ae128961675230ad322ff2867f1862dbe8566a7"
#define GITAUTH "Anna_Bergamaschi"
#define GITREV 0x3764
#define GITDATE 0x20180507
#define GITBRANCH "developer"

6
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/gitInfoMoenchTmp.h Normal file
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#define GITURL ""
#define GITREPUUID ""
#define GITAUTH ""
#define GITREV ""
#define GITDATE ""
#define GITBRANCH ""

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slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/jctbDetectorServer_developer Executable file
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slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/mcb_funcs.c Executable file
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slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/mcb_funcs.h Executable file
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#ifdef MCB_FUNCS
#ifndef MCB_FUNCS_H
#define MCB_FUNCS_H
#include "sls_detector_defs.h"
#define RGPRVALS {100,50,200}
#define RGSH1VALS {300,200,400}
#define RGSH2VALS {260,300,260}
#define DEFAULTGAIN {11.66,9.32,14.99}
#define DEFAULTOFFSET {817.5,828.6,804.2}
// DAC definitions
enum dacsVal{VDAC0, VDAC1, VDAC2, VDAC3, VDAC4, VDAC5, VDAC6, VDAC7, HIGH_VOLTAGE, CONFGAIN};
/* DAC adresses */
#define DACCS {0,0,1,1,2,2,3,3,4,4,5,5,6,6}
#define DACADDR {0,1,0,1,0,1,0,1,0,1,0,1,0,1}
//Register Definitions for temp,hv,dac gain
enum adcVals{TEMP_FPGA, TEMP_ADC};
//dynamic range
/*
#define MAX5523 commented out by dhanya
#ifndef MAX5523
#define MAX5533
#endif
#ifdef MAX5533
#define DAC_DR 4096
#endif
#ifdef MAX5523
*/
#define DAC_DR 1024
//#endif
//reference voltage
#define DAC_REFOUT1
#ifdef DAC_REFOUT2
#define DAC_MAX 2.425
#define DAC_REFOUT 2
#define DAC_REFOUT1
#endif
#ifdef DAC_REFOUT3
#define DAC_MAX 3.885
#define DAC_REFOUT 3
#define DAC_REFOUT1
#endif
#ifdef DAC_REFOUT0
#define DAC_MAX 1.214
#define DAC_REFOUT 0
#endif
#ifdef DAC_REFOUT1
#define DAC_MAX 1.940
#define DAC_REFOUT 1
#endif
/* dac calibration constants */
#define VA 1.11
#define CVTRIM 52.430851
#define BVTRIM -0.102022
#define AVTRIM 0.000050
#define PARTREF {100,1.55,-2.5,-2.5,0,-2.5}
#define PARTR1 {78,10,10,10,10,10}
#define PARTR2 {0,4.7,27,47,22,47}
//chip shiftin register meaning
#define OUTMUX_OFFSET 20
#define PROBES_OFFSET 4
#define OUTBUF_OFFSET 0
void showbits(int h);
int initDetector();
int copyChannel(sls_detector_channel *destChan, sls_detector_channel *srcChan);
int copyChip(sls_detector_chip *destChip, sls_detector_chip *srcChip);
int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod);
/* Register commands */
/* int clearDACSregister(int imod ); */
/* int nextDAC(int imod ); */
int clearCSregister(int imod );
int setCSregister(int imod );
int nextChip(int imod );
int firstChip(int imod );
int clearSSregister(int imod );
int setSSregister(int imod );
int nextStrip(int imod );
int selChannel(int strip,int imod );
int selChip(int chip,int imod );
int selMod(int mod,int imod );
/* DACs routines */
/* int program_one_dac(int addr, int value,int imod ); */
/* int set_one_dac(int imod); */
/* int initDAC(int dac_addr, int value,int imod ); */
/* int initDACs(int* v,int imod ); */
/* int initDACbyIndex(int ind,int val, int imod); */
/* int initDACbyIndexDACU(int ind,int val, int imod); */
/* int getDACbyIndexDACU(int ind, int imod); */
/* int getThresholdEnergy(); */
/* int setThresholdEnergy(int ethr); */
int setSettings(int i,int imod);
/* Other DAC index routines*/
int getTemperatureByModule(int tempSensor, int imod);
int initHighVoltageByModule(int val, int imod);
int initConfGainByModule(int isettings,int val,int imod);
/* Initialization*/
int initChannel(int ft,int cae, int ae, int coe, int ocoe, int counts,int imod );
int initChannelbyNumber(sls_detector_channel myChan);
int getChannelbyNumber(sls_detector_channel*);
int getTrimbit(int imod, int ichip, int ichan);
int initChip(int obe, int ow,int imod );
int initChipWithProbes(int obe, int ow,int nprobes, int imod);
//int getNProbes();
int initChipbyNumber(sls_detector_chip myChip);
int getChipbyNumber(sls_detector_chip*);
int initMCBregisters(int cm,int imod );
int initModulebyNumber(sls_detector_module);
int getModulebyNumber(sls_detector_module*);
/* To chips */
int clearCounter(int imod );
int clearOutReg(int imod);
int setOutReg(int imod );
int extPulse(int ncal,int imod );
int calPulse(int ncal,int imod );
int counterClear(int imod );
int countEnable(int imod );
int counterSet(int imod );
/* moved from firmware_funcs */
int readOutChan(int *val);
int getModuleNumber(int modnum);
int testShiftIn(int imod);
int testShiftOut(int imod);
int testShiftStSel(int imod);
int testDataInOut(int num, int imod);
int testExtPulse(int imod);
int testExtPulseMux(int imod, int ow);
int testDataInOutMux(int imod, int ow, int num);
int testOutMux(int imod);
int testFpgaMux(int imod);
int calibration_sensor(int num, int *values, int *dacs) ;
int calibration_chip(int num, int *values, int *dacs);
//ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret);
#endif
#endif

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slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/program_fpga.sh Executable file
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#!/bin/sh
serv="pc8498"
f="Jungfrau_CTB.rawbin"
if [ "$#" -gt 0 ]; then
f=$1
fi
if [ "$#" -gt 1 ]; then
serv=$2
fi
echo "File is $f server is $serv"
mount -t tmpfs none /mnt/
cd /mnt/
tftp -r $f -g $serv
echo 7 > /sys/class/gpio/export
echo 9 > /sys/class/gpio/export
echo in > /sys/class/gpio/gpio7/direction
echo out > /sys/class/gpio/gpio9/direction
echo 0 > /sys/class/gpio/gpio9/value
flash_eraseall /dev/mtd3
cat /mnt/$f > /dev/mtd3
echo 1 > /sys/class/gpio/gpio9/value
cat /sys/class/gpio/gpio7/value

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slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/registers_m.h Normal file
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#ifndef REGISTERS_G_H
#define REGISTERS_G_H
#include "sls_detector_defs.h"
/* Definitions for FPGA*/
#define CSP0 0x20200000
#define MEM_SIZE 0x100000
/* values defined for FPGA */
#define MCSNUM 0x0
#define FIXED_PATT_VAL 0xacdc1980
#define FPGA_INIT_PAT 0x60008
#define FPGA_INIT_ADDR 0xb0000000
//#ifdef JUNGFRAU_DHANYA
#define POWER_ON_REG 0x5e << MEM_MAP_SHIFT
// Pwr_I2C_SDA <= PowerReg_s(1) when PowerReg_s(3)='1' else 'Z';
// Pwr_I2C_SCL <= PowerReg_s(0) when PowerReg_s(2)='1' else 'Z';
#define PWR_I2C_SCL_BIT 0
#define PWR_I2C_SDA_BIT 1
#define PWR_I2C_SCL_EN_BIT 2
#define PWR_I2C_SDA_EN_BIT 3
#define POWER_STATUS_REG 41 << MEM_MAP_SHIFT
#define ADCREG1 0x08
#define ADCREG2 0x14//20
#define ADCREG3 0x4
#define ADCREG4 0x5
#define ADCREG_VREFS 24
#define DBIT_PIPELINE_REG 89 << MEM_MAP_SHIFT //0x59 same PATTERN_N_LOOP2_REG
#define MEM_MACHINE_FIFOS_REG 79 << MEM_MAP_SHIFT //from gotthard
#define CONFGAIN_REG 93 << MEM_MAP_SHIFT //from gotthard
#define ADC_PIPELINE_REG 66 << MEM_MAP_SHIFT //0x42 same as ADC_OFFSET_REG
//#endif
//#define ADC_OFFSET_REG 93 << MEM_MAP_SHIFT //same as DAQ_REG
#define ADC_INVERSION_REG 67 << MEM_MAP_SHIFT
#define DAC_REG 64 << MEM_MAP_SHIFT//0x17 << MEM_MAP_SHIFT// control the dacs
//ADC
#define ADC_WRITE_REG 65 << MEM_MAP_SHIFT//0x18 << MEM_MAP_SHIFT
//#define ADC_SYNC_REG 66 << MEM_MAP_SHIFT//0x19 << MEM_MAP_SHIFT
//#define HV_REG 67 << MEM_MAP_SHIFT//0x20 << MEM_MAP_SHIFT
//#define MUTIME_REG 0x1a << MEM_MAP_SHIFT
//temperature
#define TEMP_IN_REG 0x1b << MEM_MAP_SHIFT
#define TEMP_OUT_REG 0x1c << MEM_MAP_SHIFT
//configure MAC
#define TSE_CONF_REG 0x1d << MEM_MAP_SHIFT
#define ENET_CONF_REG 0x1e << MEM_MAP_SHIFT
//#define WRTSE_SHAD_REG 0x1f << MEM_MAP_SHIFT
//HV
#define DUMMY_REG 68 << MEM_MAP_SHIFT//0x21 << MEM_MAP_SHIFT
#define FPGA_VERSION_REG 0 << MEM_MAP_SHIFT //0x22 << MEM_MAP_SHIFT
#define PCB_REV_REG 0 << MEM_MAP_SHIFT
#define FIX_PATT_REG 1 << MEM_MAP_SHIFT //0x23 << MEM_MAP_SHIFT
#define CONTROL_REG 79 << MEM_MAP_SHIFT//0x24 << MEM_MAP_SHIFT
#define STATUS_REG 2 << MEM_MAP_SHIFT //0x25 << MEM_MAP_SHIFT
#define CONFIG_REG 77 << MEM_MAP_SHIFT//0x26 << MEM_MAP_SHIFT
#define EXT_SIGNAL_REG 78 << MEM_MAP_SHIFT// 0x27 << MEM_MAP_SHIFT
//#define FPGA_SVN_REG 0x29 << MEM_MAP_SHIFT
#define CHIP_OF_INTRST_REG 0x2A << MEM_MAP_SHIFT
//FIFO
#define LOOK_AT_ME_REG 3 << MEM_MAP_SHIFT //0x28 << MEM_MAP_SHIFT
#define SYSTEM_STATUS_REG 4 << MEM_MAP_SHIFT
#define FIFO_DATA_REG 6 << MEM_MAP_SHIFT
#define FIFO_STATUS_REG 7 << MEM_MAP_SHIFT
// constant FifoDigitalInReg_c : integer := 60;
#define FIFO_DIGITAL_DATA_LSB_REG 60 << MEM_MAP_SHIFT
#define FIFO_DIGITAL_DATA_MSB_REG 61 << MEM_MAP_SHIFT
#define FIFO_DATA_REG_OFF 0x50 << MEM_MAP_SHIFT ///////
//to read back dac registers
//#define MOD_DACS1_REG 0x65 << MEM_MAP_SHIFT
//#define MOD_DACS2_REG 0x66 << MEM_MAP_SHIFT
//#define MOD_DACS3_REG 0x67 << MEM_MAP_SHIFT
//user entered
#define GET_ACTUAL_TIME_LSB_REG 16 << MEM_MAP_SHIFT
#define GET_ACTUAL_TIME_MSB_REG 17 << MEM_MAP_SHIFT
#define GET_MEASUREMENT_TIME_LSB_REG 38 << MEM_MAP_SHIFT
#define GET_MEASUREMENT_TIME_MSB_REG 39 << MEM_MAP_SHIFT
#define SET_DELAY_LSB_REG 96 << MEM_MAP_SHIFT //0x68 << MEM_MAP_SHIFT
#define SET_DELAY_MSB_REG 97 << MEM_MAP_SHIFT //0x69 << MEM_MAP_SHIFT
#define GET_DELAY_LSB_REG 18 << MEM_MAP_SHIFT//0x6a << MEM_MAP_SHIFT
#define GET_DELAY_MSB_REG 19 << MEM_MAP_SHIFT//0x6b << MEM_MAP_SHIFT
#define SET_CYCLES_LSB_REG 98 << MEM_MAP_SHIFT//0x6c << MEM_MAP_SHIFT
#define SET_CYCLES_MSB_REG 99 << MEM_MAP_SHIFT//0x6d << MEM_MAP_SHIFT
#define GET_CYCLES_LSB_REG 20 << MEM_MAP_SHIFT//0x6e << MEM_MAP_SHIFT
#define GET_CYCLES_MSB_REG 21 << MEM_MAP_SHIFT//0x6f << MEM_MAP_SHIFT
#define SET_FRAMES_LSB_REG 100 << MEM_MAP_SHIFT//0x70 << MEM_MAP_SHIFT
#define SET_FRAMES_MSB_REG 101 << MEM_MAP_SHIFT//0x71 << MEM_MAP_SHIFT
#define GET_FRAMES_LSB_REG 22 << MEM_MAP_SHIFT//0x72 << MEM_MAP_SHIFT
#define GET_FRAMES_MSB_REG 23 << MEM_MAP_SHIFT//0x73 << MEM_MAP_SHIFT
#define SET_PERIOD_LSB_REG 102 << MEM_MAP_SHIFT//0x74 << MEM_MAP_SHIFT
#define SET_PERIOD_MSB_REG 103 << MEM_MAP_SHIFT//0x75 << MEM_MAP_SHIFT
#define GET_PERIOD_LSB_REG 24 << MEM_MAP_SHIFT//0x76 << MEM_MAP_SHIFT
#define GET_PERIOD_MSB_REG 25 << MEM_MAP_SHIFT//0x77 << MEM_MAP_SHIFT
//#define PATTERN_WAIT0_TIME_REG_LSB 114 << MEM_MAP_SHIFT
//#define PATTERN_WAIT0_TIME_REG_MSB 115 << MEM_MAP_SHIFT
#define SET_EXPTIME_LSB_REG 114 << MEM_MAP_SHIFT//0x78 << MEM_MAP_SHIFT
#define SET_EXPTIME_MSB_REG 115 << MEM_MAP_SHIFT//0x79 << MEM_MAP_SHIFT
#define GET_EXPTIME_LSB_REG 26 << MEM_MAP_SHIFT//0x7a << MEM_MAP_SHIFT
#define GET_EXPTIME_MSB_REG 27 << MEM_MAP_SHIFT//0x7b << MEM_MAP_SHIFT
#define SET_GATES_LSB_REG 106 << MEM_MAP_SHIFT//0x7c << MEM_MAP_SHIFT
#define SET_GATES_MSB_REG 107 << MEM_MAP_SHIFT//0x7d << MEM_MAP_SHIFT
#define GET_GATES_LSB_REG 28 << MEM_MAP_SHIFT//0x7e << MEM_MAP_SHIFT
#define GET_GATES_MSB_REG 29 << MEM_MAP_SHIFT//0x7f << MEM_MAP_SHIFT
#define DATA_IN_LSB_REG 30 << MEM_MAP_SHIFT
#define DATA_IN_MSB_REG 31 << MEM_MAP_SHIFT
#define PATTERN_OUT_LSB_REG 32 << MEM_MAP_SHIFT
#define PATTERN_OUT_MSB_REG 33 << MEM_MAP_SHIFT
#define FRAMES_FROM_START_LSB_REG 34 << MEM_MAP_SHIFT
#define FRAMES_FROM_START_MSB_REG 35 << MEM_MAP_SHIFT
#define FRAMES_FROM_START_PG_LSB_REG 36 << MEM_MAP_SHIFT
#define FRAMES_FROM_START_PG_MSB_REG 37 << MEM_MAP_SHIFT
#define SLOW_ADC_REG 43 << MEM_MAP_SHIFT
#define PLL_PARAM_REG 80 << MEM_MAP_SHIFT//0x37 << MEM_MAP_SHIFT
#define PLL_PARAM_OUT_REG 5 << MEM_MAP_SHIFT //0x38 << MEM_MAP_SHIFT
#define PLL_CNTRL_REG 81 << MEM_MAP_SHIFT//0x34 << MEM_MAP_SHIFT
#ifdef NEW_GBE_INTERFACE
#define GBE_PARAM_OUT_REG 40 << MEM_MAP_SHIFT
#define GBE_PARAM_REG 69 << MEM_MAP_SHIFT
#define GBE_CNTRL_REG 70 << MEM_MAP_SHIFT
#else
#define RX_UDP_AREG 69 << MEM_MAP_SHIFT //rx_udpip_AReg_c : integer:= 69; *\/
#define UDPPORTS_AREG 70 << MEM_MAP_SHIFT// udpports_AReg_c : integer:= 70; *\/
#define RX_UDPMACL_AREG 71 << MEM_MAP_SHIFT//rx_udpmacL_AReg_c : integer:= 71; *\/
#define RX_UDPMACH_AREG 72 << MEM_MAP_SHIFT//rx_udpmacH_AReg_c : integer:= 72; *\/
#define DETECTORMACL_AREG 73 << MEM_MAP_SHIFT//detectormacL_AReg_c : integer:= 73; *\/
#define DETECTORMACH_AREG 74 << MEM_MAP_SHIFT//detectormacH_AReg_c : integer:= 74; *\/
#define DETECTORIP_AREG 75 << MEM_MAP_SHIFT//detectorip_AReg_c : integer:= 75; *\/
#define IPCHKSUM_AREG 76 << MEM_MAP_SHIFT//ipchksum_AReg_c : integer:= 76; *\/ */
#endif
#define PATTERN_CNTRL_REG 82 << MEM_MAP_SHIFT
#define PATTERN_LIMITS_AREG 83 << MEM_MAP_SHIFT
#define PATTERN_LOOP0_AREG 84 << MEM_MAP_SHIFT
#define PATTERN_N_LOOP0_REG 85 << MEM_MAP_SHIFT
#define PATTERN_LOOP1_AREG 86 << MEM_MAP_SHIFT
#define PATTERN_N_LOOP1_REG 87 << MEM_MAP_SHIFT
#define PATTERN_LOOP2_AREG 88 << MEM_MAP_SHIFT
#define PATTERN_N_LOOP2_REG 89 << MEM_MAP_SHIFT
#define PATTERN_WAIT0_AREG 90 << MEM_MAP_SHIFT
#define PATTERN_WAIT1_AREG 91 << MEM_MAP_SHIFT
#define PATTERN_WAIT2_AREG 92 << MEM_MAP_SHIFT
//#define DAQ_REG 93 << MEM_MAP_SHIFT //unused
#define NSAMPLES_REG 93 << MEM_MAP_SHIFT
#define HV_REG 95 << MEM_MAP_SHIFT
#define PATTERN_IOCTRL_REG_LSB 108 << MEM_MAP_SHIFT
#define PATTERN_IOCTRL_REG_MSB 109 << MEM_MAP_SHIFT
#define PATTERN_IOCLKCTRL_REG_LSB 110 << MEM_MAP_SHIFT
#define PATTERN_IOCLKCTRL_REG_MSB 111 << MEM_MAP_SHIFT
#define PATTERN_IN_REG_LSB 112 << MEM_MAP_SHIFT
#define PATTERN_IN_REG_MSB 113 << MEM_MAP_SHIFT
#define PATTERN_WAIT0_TIME_REG_LSB 114 << MEM_MAP_SHIFT
#define PATTERN_WAIT0_TIME_REG_MSB 115 << MEM_MAP_SHIFT
#define PATTERN_WAIT1_TIME_REG_LSB 116 << MEM_MAP_SHIFT
#define PATTERN_WAIT1_TIME_REG_MSB 117 << MEM_MAP_SHIFT
#define PATTERN_WAIT2_TIME_REG_LSB 118 << MEM_MAP_SHIFT
#define PATTERN_WAIT2_TIME_REG_MSB 119 << MEM_MAP_SHIFT
//#define DAC_REG_OFF 120
//#define DAC_0_1_VAL_REG 120 << MEM_MAP_SHIFT
//#define DAC_2_3_VAL_REG 121 << MEM_MAP_SHIFT
//#define DAC_4_5_VAL_REG 122 << MEM_MAP_SHIFT
//#define DAC_6_7_VAL_REG 123 << MEM_MAP_SHIFT
//#define DAC_8_9_VAL_REG 124 << MEM_MAP_SHIFT
//#define DAC_10_11_VAL_REG 125 << MEM_MAP_SHIFT
//#define DAC_12_13_VAL_REG 126 << MEM_MAP_SHIFT
//#define DAC_14_15_VAL_REG 127 << MEM_MAP_SHIFT
#define DAC_VAL_REG 121 << MEM_MAP_SHIFT
#define DAC_NUM_REG 122 << MEM_MAP_SHIFT
#define DAC_VAL_OUT_REG 42 << MEM_MAP_SHIFT
#define ADC_LATCH_DISABLE_REG 120 << MEM_MAP_SHIFT
/* registers defined in FPGA */
#define GAIN_REG 0
//#define FLOW_CONTROL_REG 0x11 << MEM_MAP_SHIFT
//#define FLOW_STATUS_REG 0x12 << MEM_MAP_SHIFT
//#define FRAME_REG 0x13 << MEM_MAP_SHIFT
#define MULTI_PURPOSE_REG 0
//#define TIME_FROM_START_REG 0x16 << MEM_MAP_SHIFT
#define ROI_REG 0 // 0x35 << MEM_MAP_SHIFT
#define OVERSAMPLING_REG 0 // 0x36 << MEM_MAP_SHIFT
#define MOENCH_CNTR_REG 0 // 0x31 << MEM_MAP_SHIFT
#define MOENCH_CNTR_OUT_REG 0 // 0x33 << MEM_MAP_SHIFT
#define MOENCH_CNTR_CONF_REG 0 // 0x32 << MEM_MAP_SHIFT
//image
#define DARK_IMAGE_REG 0 // 0x81 << MEM_MAP_SHIFT
#define GAIN_IMAGE_REG 0 // 0x82 << MEM_MAP_SHIFT
//counter block memory
#define COUNTER_MEMORY_REG 0 // 0x85 << MEM_MAP_SHIFT
//not used
//#define MCB_DOUT_REG_OFF 0 // 0x200000
//#define FIFO_CNTRL_REG_OFF 0 // 0x300000
//#define FIFO_COUNTR_REG_OFF 0 // 0x400000
//not used so far
//#define SPEED_REG 0 // 0x006000
//#define SET_NBITS_REG 0 // 0x008000
//not used
//#define GET_SHIFT_IN_REG 0 // 0x022000
#define SHIFTMOD 2
#define SHIFTFIFO 9
/** for PCB_REV_REG */
#define DETECTOR_TYPE_MASK 0xFF000000
#define DETECTOR_TYPE_OFFSET 24
#define BOARD_REVISION_MASK 0xFFFFFF
#define MOENCH03_MODULE_ID 2
#define JUNGFRAU_MODULE_ID 1
#define JUNGFRAU_CTB_ID 3
/* for control register (16bit only)*/
#define START_ACQ_BIT 0x0001
#define STOP_ACQ_BIT 0x0002
#define START_FIFOTEST_BIT 0x0004 // ?????
#define STOP_FIFOTEST_BIT 0x0008 // ??????
#define START_READOUT_BIT 0x0010
#define STOP_READOUT_BIT 0x0020
#define START_EXPOSURE_BIT 0x0040
#define STOP_EXPOSURE_BIT 0x0080
#define START_TRAIN_BIT 0x0100
#define STOP_TRAIN_BIT 0x0200
#define FIFO_RESET_BIT 0x8000
#define SYNC_RESET 0x0400
#define GB10_RESET_BIT 0x0800
#define MEM_RESET_BIT 0x1000
/* for status register */
#define RUN_BUSY_BIT 0x00000001
#define READOUT_BUSY_BIT 0x00000002
#define FIFOTEST_BUSY_BIT 0x00000004 //????
#define WAITING_FOR_TRIGGER_BIT 0x00000008
#define DELAYBEFORE_BIT 0x00000010
#define DELAYAFTER_BIT 0x00000020
#define EXPOSING_BIT 0x00000040
#define COUNT_ENABLE_BIT 0x00000080
#define READSTATE_0_BIT 0x00000100
#define READSTATE_1_BIT 0x00000200
#define READSTATE_2_BIT 0x00000400
#define LAM_BIT 0x00000400 // error!
#define SOME_FIFO_FULL_BIT 0x00000800 // error!
#define RUNSTATE_0_BIT 0x00001000
#define RUNSTATE_1_BIT 0x00002000
#define RUNSTATE_2_BIT 0x00004000
#define STOPPED_BIT 0x00008000 // stopped!
#define ALL_FIFO_EMPTY_BIT 0x00010000 // data ready
#define RUNMACHINE_BUSY_BIT 0x00020000
#define READMACHINE_BUSY_BIT 0x00040000
#define PLL_RECONFIG_BUSY 0x00100000
/* for fifo status register */
#define FIFO_ENABLED_BIT 0x80000000
#define FIFO_DISABLED_BIT 0x01000000
#define FIFO_ERROR_BIT 0x08000000
#define FIFO_EMPTY_BIT 0x04000000
#define FIFO_DATA_READY_BIT 0x02000000
#define FIFO_COUNTER_MASK 0x000001ff
#define FIFO_NM_MASK 0x00e00000
#define FIFO_NM_OFF 21
#define FIFO_NC_MASK 0x001ffe00
#define FIFO_NC_OFF 9
/* for config register *///not really used yet
#define TOT_ENABLE_BIT 0x00000002
#define TIMED_GATE_BIT 0x00000004
#define CONT_RO_ENABLE_BIT 0x00080000
#define GB10_NOT_CPU_BIT 0x00001000
#define ADC_OUTPUT_DISABLE_BIT 0x00100
#define DIGITAL_OUTPUT_ENABLE_BIT 0x00200
/* for speed register */
#define CLK_DIVIDER_MASK 0x000000ff
#define CLK_DIVIDER_OFFSET 0
#define SET_LENGTH_MASK 0x00000f00
#define SET_LENGTH_OFFSET 8
#define WAIT_STATES_MASK 0x0000f000
#define WAIT_STATES_OFFSET 12
#define TOTCLK_DIVIDER_MASK 0xff000000
#define TOTCLK_DIVIDER_OFFSET 24
#define TOTCLK_DUTYCYCLE_MASK 0x00ff0000
#define TOTCLK_DUTYCYCLE_OFFSET 16
/* for external signal register */
#define SIGNAL_OFFSET 4
#define SIGNAL_MASK 0xF
#define EXT_SIG_OFF 0x0
#define EXT_GATE_IN_ACTIVEHIGH 0x1
#define EXT_GATE_IN_ACTIVELOW 0x2
#define EXT_TRIG_IN_RISING 0x3
#define EXT_TRIG_IN_FALLING 0x4
#define EXT_RO_TRIG_IN_RISING 0x5
#define EXT_RO_TRIG_IN_FALLING 0x6
#define EXT_GATE_OUT_ACTIVEHIGH 0x7
#define EXT_GATE_OUT_ACTIVELOW 0x8
#define EXT_TRIG_OUT_RISING 0x9
#define EXT_TRIG_OUT_FALLING 0xA
#define EXT_RO_TRIG_OUT_RISING 0xB
#define EXT_RO_TRIG_OUT_FALLING 0xC
/* for temperature register */
#define T1_CLK_BIT 0x00000001
#define T1_CS_BIT 0x00000002
#define T2_CLK_BIT 0x00000004
#define T2_CS_BIT 0x00000008
/* fifo control register */
//#define FIFO_RESET_BIT 0x00000001
//#define FIFO_DISABLE_TOGGLE_BIT 0x00000002
//chip shiftin register meaning
#define OUTMUX_OFF 20
#define OUTMUX_MASK 0x1f
#define PROBES_OFF 4
#define PROBES_MASK 0x7f
#define OUTBUF_OFF 0
#define OUTBUF_MASK 1
/* multi purpose register */
#define PHASE_STEP_BIT 0x00000001
#define PHASE_STEP_OFFSET 0
// #define xxx_BIT 0x00000002
#define RESET_COUNTER_BIT 0x00000004
#define RESET_COUNTER_OFFSET 2
//#define xxx_BIT 0x00000008
//#define xxx_BIT 0x00000010
#define SW1_BIT 0x00000020
#define SW1_OFFSET 5
#define WRITE_BACK_BIT 0x00000040
#define WRITE_BACK_OFFSET 6
#define RESET_BIT 0x00000080
#define RESET_OFFSET 7
#define ENET_RESETN_BIT 0x00000800
#define ENET_RESETN_OFFSET 11
#define INT_RSTN_BIT 0x00002000
#define INT_RSTN_OFFSET 13
#define DIGITAL_TEST_BIT 0x00004000
#define DIGITAL_TEST_OFFSET 14
//#define CHANGE_AT_POWER_ON_BIT 0x00008000
//#define CHANGE_AT_POWER_ON_OFFSET 15
/* settings/conf gain register */
#define GAIN_MASK 0x0000000f
#define GAIN_OFFSET 0
#define SETTINGS_MASK 0x000000f0
#define SETTINGS_OFFSET 4
/* CHIP_OF_INTRST_REG */
#define CHANNEL_MASK 0xffff0000
#define CHANNEL_OFFSET 16
#define ACTIVE_ADC_MASK 0x0000001f
/**ADC SYNC CLEAN FIFO*/
#define ADCSYNC_CLEAN_FIFO_BITS 0x300000
#define CLEAN_FIFO_MASK 0x0fffff
enum {run_clk_c, adc_clk_c, sync_clk_c, dbit_clk_c};
#define PLL_CNTR_ADDR_OFF 16 //PLL_CNTR_REG bits 21 downto 16 represent the counter address
#define PLL_CNTR_RECONFIG_RESET_BIT 0
#define PLL_CNTR_READ_BIT 1
#define PLL_CNTR_WRITE_BIT 2
#define PLL_CNTR_PLL_RESET_BIT 3
#define PLL_CNTR_PHASE_EN_BIT 8
#define PLL_CNTR_UPDN_BIT 9
#define PLL_CNTR_CNTSEL_OFF 10
#define PLL_MODE_REG 0x0
#define PLL_STATUS_REG 0x1
#define PLL_START_REG 0x2
#define PLL_N_COUNTER_REG 0x3
#define PLL_M_COUNTER_REG 0x4
#define PLL_C_COUNTER_REG 0x5 //which ccounter stands in param 22:18; 7:0 lowcount 15:8 highcount; 16 bypassenable; 17 oddivision
#define PLL_PHASE_SHIFT_REG 0x6 // which ccounter stands in param 16:20; 21 updown (1 up, 0 down)
#define PLL_K_COUNTER_REG 0x7
#define PLL_BANDWIDTH_REG 0x8
#define PLL_CHARGEPUMP_REG 0x9
#define PLL_VCO_DIV_REG 0x1c
#define PLL_MIF_REG 0x1f
#define PPL_M_CNT_PARAM_DEFAULT 0x4040
#define PPL_N_CNT_PARAM_DEFAULT 0x20D0C
#define PPL_C0_CNT_PARAM_DEFAULT 0x20D0C
#define PPL_C1_CNT_PARAM_DEFAULT 0xA0A0
#define PPL_C2_CNT_PARAM_DEFAULT 0x20D0C
#define PPL_C3_CNT_PARAM_DEFAULT 0x0808
#define PPL_BW_PARAM_DEFAULT 0x2EE0
#define PPL_VCO_PARAM_DEFAULT 0x1
#define NEW_PLL_RECONFIG
#ifdef NEW_PLL_RECONFIG
#define PLL_VCO_FREQ_MHZ 400//480//800
#else
#define PLL_VCO_FREQ_MHZ 480//800
#endif
/*
GBE parameter and control registers definitions
*/
#define GBE_CTRL_WSTROBE 0
#define GBE_CTRL_VAR_OFFSET 16
#define GBE_CTRL_VAR_MASK 0XF
#define GBE_CTRL_RAMADDR_OFFSET 24
#define GBE_CTRL_RAMADDR_MASK 0X3F
#define GBE_CTRL_INTERFACE 23
#define RX_UDP_IP_ADDR 0
#define RX_UDP_PORTS_ADDR 1
#define RX_UDP_MAC_L_ADDR 2
#define RX_UDP_MAC_H_ADDR 3
#define IPCHECKSUM_ADDR 4
#define GBE_DELAY_ADDR 5
#define GBE_RESERVED1_ADDR 6
#define GBE_RESERVED2_ADDR 7
#define DETECTOR_MAC_L_ADDR 8
#define DETECTOR_MAC_H_ADDR 9
#define DETECTOR_IP_ADDR 10
/**------------------
-- pattern registers definitions
--------------------------------------------- */
#define IOSIGNALS_MASK 0xfffffffffffff
#define ADC_ENABLE_BIT 63
#define APATTERN_MASK 0xffff
#define ASTART_OFFSET 0
#define ASTOP_OFFSET 16
#define PATTERN_CTRL_WRITE_BIT 0
#define PATTERN_CTRL_READ_BIT 1
#define PATTERN_CTRL_ADDR_OFFSET 16
#define MAX_PATTERN_LENGTH 1024
#endif

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slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/server.c Executable file
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/* A simple server in the internet domain using TCP
The port number is passed as an argument */
#include "sls_detector_defs.h"
#include <stdlib.h>
#include "communication_funcs.h"
#include "server_funcs.h"
#include <string.h>
extern int sockfd;
extern int phase_shift;
void error(char *msg)
{
perror(msg);
}
int main(int argc, char *argv[])
{
int portno, b;
char cmd[500];
int retval=OK;
int sd, fd;
int iarg;
int checkType = 1;
for(iarg=1; iarg<argc; iarg++){
if(!strcasecmp(argv[iarg],"-phaseshift")){
if(argc==iarg+1){
printf("No phaseshift given. Exiting.\n");
return 1;
}
if ( sscanf(argv[iarg+1],"%d",&phase_shift)==0) {
printf("could not decode phase shift\n");
return 1;
}
}
else if(!strcasecmp(argv[iarg],"-test")){
if(argc==iarg+1){
printf("No test condition given. Exiting.\n");
return 1;
}
if(!strcasecmp(argv[iarg+1],"with_gotthard")){
checkType = 0;
}else{
printf("could not decode test condition. Possible arguments: with_gotthard. Exiting\n");
return 1;
}
}
}
//stop server
if ((argc > 2) && (!strcasecmp(argv[2],"stopserver"))){
portno = DEFAULT_PORTNO+1;
if ( sscanf(argv[1],"%d",&portno) ==0) {
printf("could not open stop server: unknown port\n");
return 1;
}
b=0;
printf("\n\nStop Server\nOpening stop server on port %d\n",portno);
checkType=0;
}
//control server
else {
portno = DEFAULT_PORTNO;
if(checkType)
sprintf(cmd,"%s %d stopserver &",argv[0],DEFAULT_PORTNO+1);
else
sprintf(cmd,"%s %d stopserver -test with_gotthard &",argv[0],DEFAULT_PORTNO+1);
printf("\n\nControl Server\nOpening control server on port %d\n",portno );
//printf("\n\ncmd:%s\n",cmd);
system(cmd);
b=1;
checkType=1;
}
init_detector(b, checkType);
sd=bindSocket(portno);
sockfd=sd;
if (getServerError(sd)) {
printf("server error!\n");
return -1;
}
/* assign function table */
function_table();
#ifdef VERBOSE
printf("function table assigned \n");
#endif
/* waits for connection */
while(retval!=GOODBYE) {
#ifdef VERBOSE
printf("\n");
#endif
#ifdef VERY_VERBOSE
printf("Waiting for client call\n");
#endif
fd=acceptConnection(sockfd);
#ifdef VERY_VERBOSE
printf("Conenction accepted\n");
#endif
retval=decode_function(fd);
#ifdef VERY_VERBOSE
printf("function executed\n");
#endif
closeConnection(fd);
#ifdef VERY_VERBOSE
printf("connection closed\n");
#endif
}
exitServer(sockfd);
printf("Goodbye!\n");
return 0;
}

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slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/server_defs.h Executable file
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#ifndef SERVER_DEFS_H
#define SERVER_DEFS_H
#include "sls_detector_defs.h"
#include <stdint.h>
// Hardware definitions
#define NCHAN 36
#define NCHIP 1
#define NADC 9 //
/* #ifdef CTB */
/* #define NDAC 24 */
/* #define NPWR 5 */
/* #else */
/* #define NDAC 16 */
/* #define NPWR 0 */
/* #endif */
#define DAC_CMD_OFF 20
#define NMAXMODX 1
#define NMAXMODY 1
#define NMAXMOD (NMAXMODX*NMAXMODY)
#define NCHANS (NCHAN*NCHIP*NMAXMOD)
#define NDACS (NDAC*NMAXMOD)
/**when moench readout tested with gotthard module*/
#define TRIM_DR (((int)pow(2,NTRIMBITS))-1)
#define COUNT_DR (((int)pow(2,NCOUNTBITS))-1)
#define ALLMOD 0xffff
#define ALLFIFO 0xffff
#define GOTTHARD_ADCSYNC_VAL 0x32214
#define ADCSYNC_VAL 0x02111
#define TOKEN_RESTART_DELAY 0x88000000
#define TOKEN_RESTART_DELAY_ROI 0x1b000000
#define TOKEN_TIMING_REV1 0x1f16
#define TOKEN_TIMING_REV2 0x1f0f
#define DEFAULT_PHASE_SHIFT 0 // 120
#define DEFAULT_IP_PACKETSIZE 0x0522
#define DEFAULT_UDP_PACKETSIZE 0x050E
#define ADC1_IP_PACKETSIZE 256*2+14+20
#define ADC1_UDP_PACKETSIZE 256*2+4+8+2
#ifdef VIRTUAL
#define DEBUGOUT
#endif
#define CLK_FREQ 156.25E+6
#define ADC_CLK_FREQ 32E+6
#endif

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slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/server_funcs.c Normal file
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slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/server_funcs.h Executable file
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#ifndef SERVER_FUNCS_H
#define SERVER_FUNCS_H
#include "sls_detector_defs.h"
#include <stdio.h>
/*
#include <sys/types.h>
#include <sys/socket.h>
#include <netinet/in.h>
*/
#include "communication_funcs.h"
#define GOODBYE -200
int sockfd;
int function_table();
int decode_function(int);
const char* getFunctionName(enum detFuncs func);
int init_detector(int,int);
int M_nofunc(int);
int exit_server(int);
// General purpose functions
int get_detector_type(int);
int set_number_of_modules(int);
int get_max_number_of_modules(int);
int exec_command(int);
int set_external_signal_flag(int);
int set_external_communication_mode(int);
int get_id(int);
int digital_test(int);
int write_register(int);
int read_register(int);
int set_dac(int);
int get_adc(int);
int set_channel(int);
int set_chip(int);
int set_module(int);
int get_channel(int);
int get_chip(int);
int get_module(int);
int get_threshold_energy(int);
int set_threshold_energy(int);
int set_settings(int);
int start_acquisition(int);
int stop_acquisition(int);
int start_readout(int);
int get_run_status(int);
int read_frame(int);
int read_all(int);
int start_and_read_all(int);
int set_timer(int);
int get_time_left(int);
int set_dynamic_range(int);
int set_roi(int);
int get_roi(int);
int set_speed(int);
int set_readout_flags(int);
int execute_trimming(int);
int lock_server(int);
int set_port(int);
int get_last_client_ip(int);
int set_master(int);
int set_synchronization(int);
int update_client(int);
int send_update(int);
int configure_mac(int);
int load_image(int);
int read_counter_block(int);
int reset_counter_block(int);
int calibrate_pedestal(int);
int set_roi(int);
int set_ctb_pattern(int);
int write_adc_register(int);
int power_chip(int);
int reset_fpga(int);
int program_fpga(int);
int activate(int);
int prepare_acquisition(int);
int cleanup_acquisition(int);
#endif

39
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/sharedmemory.c Executable file
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#include "sharedmemory.h"
struct statusdata *stdata;
int inism(int clsv) {
static int scansmid;
if (clsv==SMSV) {
if ( (scansmid=shmget(SMKEY,1024,IPC_CREAT | 0666 ))==-1 ) {
return -1;
}
if ( (stdata=shmat(scansmid,NULL,0))==(void*)-1) {
return -2;
}
}
if (clsv==SMCL) {
if ( (scansmid=shmget(SMKEY,0,0) )==-1 ) {
return -3;
}
if ( (stdata=shmat(scansmid,NULL,0))==(void*)-1) {
return -4;
}
}
return 1;
}
void write_status_sm(char *status) {
strcpy(stdata->status,status);
}
void write_stop_sm(int v) {
stdata->stop=v;
}
void write_runnumber_sm(int v) {
stdata->runnumber=v;
}

48
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/sharedmemory.h Executable file
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#ifndef SM
#define SM
#include "sls_detector_defs.h"
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <sys/mman.h>
#include <fcntl.h>
#include <stdarg.h>
#include <unistd.h>
//#include <asm/page.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <stdarg.h>
#include <unistd.h>
#include <sys/shm.h>
#include <sys/ipc.h>
#include <sys/stat.h>
/* key for shared memory */
#define SMKEY 10001
#define SMSV 1
#define SMCL 2
struct statusdata {
int runnumber;
int stop;
char status[20];
} ;
/* for shared memory */
int inism(int clsv);
void write_status_sm(char *status);
void write_stop_sm(int v);
void write_runnumber_sm(int v);
#endif

245
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/slow_adc.c Normal file
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#include "firmware_funcs.h"
#include "registers_m.h"
#include "server_defs.h"
#include "blackfin.h"
int prepareSlowADCSeq() {
// u_int16_t vv=0x3c40;
u_int16_t codata=( 1<<13) | (7<<10) | (7<<7) | (1<<6) | (0<<3) | (2<<1) | 1;
u_int32_t valw;
int obit, ibit;
// int cnv_bit=16, sdi_bit=17, sck_bit=18;
int cnv_bit=10, sdi_bit=8, sck_bit=9;
// int oval=0;
printf("Codata is %04x\n",codata);
/* //convert */
valw=(1<<cnv_bit);
bus_w(ADC_WRITE_REG,valw);
usleep(20);
valw=0;
bus_w(ADC_WRITE_REG,(valw));
usleep(20);
for (ibit=0; ibit<14; ibit++) {
obit=((codata >> (13-ibit)) & 1);
// printf("%d",obit);
valw = obit << sdi_bit;
bus_w(ADC_WRITE_REG,valw);
usleep(20);
bus_w(ADC_WRITE_REG,valw|(1<<sck_bit));
usleep(20);
bus_w(ADC_WRITE_REG,valw);
}
// printf("\n");
bus_w(ADC_WRITE_REG,0);
/* //convert */
valw=(1<<cnv_bit);
bus_w(ADC_WRITE_REG,valw);
usleep(20);
valw=0;
bus_w(ADC_WRITE_REG,(valw));
usleep(20);
return 0;
}
int prepareSlowADC(int ichan) {
// u_int16_t vv=0x3c40;
// u_int16_t codata=( 1<<13) | (7<<10) | (7<<7) | (1<<6) | (0<<3) | (2<<1) | 1;
u_int16_t codata=(1<<13) | (7<<10) | (ichan<<7) | (1<<6) | (0<<3) | (0<<1) | 1; //read single channel
if (ichan<0) codata=( 1<<13) | (3<<10) | (7<7) | (1<<6) | (0<<3) | (0<<1) | 1;
u_int32_t valw;
int obit, ibit;
// int cnv_bit=16, sdi_bit=17, sck_bit=18;
int cnv_bit=10, sdi_bit=8, sck_bit=9;
// int oval=0;
printf("Codata is %04x\n",codata);
/* //convert */
valw=(1<<cnv_bit);
bus_w(ADC_WRITE_REG,valw);
usleep(20);
valw=0;
bus_w(ADC_WRITE_REG,(valw));
usleep(20);
for (ibit=0; ibit<14; ibit++) {
obit=((codata >> (13-ibit)) & 1);
// printf("%d",obit);
valw = obit << sdi_bit;
bus_w(ADC_WRITE_REG,valw);
usleep(20);
bus_w(ADC_WRITE_REG,valw|(1<<sck_bit));
usleep(20);
bus_w(ADC_WRITE_REG,valw);
}
// printf("\n");
bus_w(ADC_WRITE_REG,0);
/* //convert */
valw=(1<<cnv_bit);
bus_w(ADC_WRITE_REG,valw);
usleep(20);
valw=0;
bus_w(ADC_WRITE_REG,(valw));
usleep(20);
return 0;
}
int readSlowADC(int ichan) {
// u_int16_t vv=0x3c40;
// u_int16_t codata=( 1<<13) | (7<<10) | (ichan<<7) | (1<<6) | (0<<3) | (0<<1) | 1; //read single channel
u_int32_t valw;
int i, obit;
// int cnv_bit=16, sdi_bit=17, sck_bit=18;
int cnv_bit=10, sdi_bit=8, sck_bit=9;
int oval=0;
printf("DAC index is %d\n",ichan);
if (ichan<-1 || ichan>7)
return -1;
prepareSlowADC(ichan);
/* printf("Codata is %04x\n",codata); */
/* /\* //convert *\/ */
/* valw=(1<<cnv_bit); */
/* bus_w(ADC_WRITE_REG,valw); */
/* usleep(20); */
/* valw=0; */
/* bus_w(ADC_WRITE_REG,(valw)); */
/* usleep(20); */
/* for (ibit=0; ibit<14; ibit++) { */
/* obit=((codata >> (13-ibit)) & 1); */
/* // printf("%d",obit); */
/* valw = obit << sdi_bit; */
/* bus_w(ADC_WRITE_REG,valw); */
/* usleep(20); */
/* bus_w(ADC_WRITE_REG,valw|(1<<sck_bit)); */
/* usleep(20); */
/* bus_w(ADC_WRITE_REG,valw); */
/* } */
/* // printf("\n"); */
/* bus_w(ADC_WRITE_REG,0); */
for (ichan=0; ichan<9; ichan++) {
/* //convert */
valw=(1<<cnv_bit);
bus_w(ADC_WRITE_REG,valw);
usleep(20);
valw=0;
bus_w(ADC_WRITE_REG,(valw));
usleep(20);
// printf("Channel %d ",ichan);
//read
oval=0;
for (i=0;i<16;i++) {
obit=bus_r16(SLOW_ADC_REG)&0x1;
// printf("%d",obit);
//write data (i)
// usleep(0);
oval|=obit<<(15-i);
//cldwn
valw=0;
bus_w(ADC_WRITE_REG,valw);
bus_w(ADC_WRITE_REG,valw|(1<<sck_bit));
usleep(20);
bus_w(ADC_WRITE_REG,valw);
usleep(20);
}
printf("\t");
printf("Value %d is %d (%d mV)\n",ichan, oval,2500*oval/65535);
}
printf("Value %d is %d\n",ichan, oval);
return 2500*oval/65535;
}

10
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/slow_adc.h Normal file
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#ifndef SLOW_ADC_H
#define SLOW_ADC_H
int prepareSlowADCSeq();
int prepareSlowADC(int ichan);
int readSlowADC(int ichan);
#endif

1
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/sls_detector_defs.h Symbolic link
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../commonFiles/sls_detector_defs.h

1
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/sls_detector_funcs.h Symbolic link
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../commonFiles/sls_detector_funcs.h

1
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/sls_receiver_defs.h Symbolic link
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../../slsReceiverSoftware/include/sls_receiver_defs.h

1
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/sls_receiver_funcs.h Symbolic link
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../../slsReceiverSoftware/include/sls_receiver_funcs.h

46
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/stop_server.c Executable file
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/* A simple server in the internet domain using TCP
The port number is passed as an argument */
#include "sls_detector_defs.h"
#include "communication_funcs.h"
#include "firmware_funcs.h"
int sockfd;
int main(int argc, char *argv[])
{
int portno;
int retval=0;
portno = DEFAULT_PORTNO;
bindSocket(portno);
if (getServerError())
return -1;
/* waits for connection */
while(retval!=GOODBYE) {
#ifdef VERBOSE
printf("\n");
#endif
#ifdef VERY_VERBOSE
printf("Stop server: waiting for client call\n");
#endif
acceptConnection();
retval=stopStateMachine();
closeConnection();
}
exitServer();
printf("Goodbye!\n");
return 0;
}

31
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/updateGitVersion.sh Executable file
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SERVER=jctbDetectorServer
MAINDIR=slsDetectorsPackage
SPECDIR=slsDetectorSoftware/$SERVER
TMPFILE=gitInfoMoenchTmp.h
INCLFILE=gitInfoMoench.h
#evaluate the variables
EVALFILE=../../evalVersionVariables.sh
source $EVALFILE
#get modified date
#RDATE1='git log --pretty=format:"%ci" -1'
RDATE1="find . -type f -exec stat --format '%Y :%y %n' '{}' \; | sort -nr | cut -d: -f2- | egrep -v 'gitInfo|.git|updateGitVersion|.o' | head -n 1"
RDATE=`eval $RDATE1`
NEWDATE=$(sed "s/-//g" <<< $RDATE | awk '{print $1;}')
NEWDATE=${NEWDATE/#/0x}
#get old date from INCLFILE
OLDDATE=$(more $INCLFILE | grep '#define GITDATE' | awk '{print $3}')
#update INCLFILE if changes
if [ "$OLDDATE" != "$NEWDATE" ]; then
echo Path: ${MAINDIR}/${SPECDIR} $'\n'URL: ${GITREPO} $'\n'Repository Root: ${GITREPO} $'\n'Repsitory UUID: ${REPUID} $'\n'Revision: ${FOLDERREV} $'\n'Branch: ${BRANCH} $'\n'Last Changed Author: ${AUTH1}_${AUTH2} $'\n'Last Changed Rev: ${REV} $'\n'Last Changed Date: ${RDATE} > gitInfo.txt
cd ../../
./genVersionHeader.sh $SPECDIR/gitInfo.txt $SPECDIR/$TMPFILE $SPECDIR/$INCLFILE
cd $WD
fi