mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-21 00:58:01 +02:00
client: removed slsDetectorutils and postprocessing. yet to compile, yet to add detpos index for every multi sls detector command and call from command interface, removed multiple threading, yet to interface with eriks single template for multiple threading
This commit is contained in:
@ -0,0 +1,210 @@
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#include "ansi.h"
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#include <termios.h> /* POSIX terminal control definitions */
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#include <stdio.h>
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#include <stdlib.h> // atoi
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#include <fcntl.h> // File control definitions
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#include <sys/ioctl.h> // ioctl
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#include <unistd.h> // read, close
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#include <string.h> // memset
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#include <linux/i2c-dev.h> // I2C_SLAVE, __u8 reg
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#include <errno.h>
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#define PORTNAME "/dev/ttyBF1"
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#define GOODBYE 200
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#define BUFFERSIZE 16
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#define I2C_DEVICE_FILE "/dev/i2c-0"
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#define I2C_DEVICE_ADDRESS 0x4C
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//#define I2C_DEVICE_ADDRESS 0x48
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#define I2C_REGISTER_ADDRESS 0x40
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int i2c_open(const char* file,unsigned int addr){
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//device file
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int fd = open( file, O_RDWR );
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if (fd < 0) {
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cprintf(RED,"Warning: Unable to open file %s\n",file);
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return -1;
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}
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//device address
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if( ioctl( fd, I2C_SLAVE, addr&0x7F ) < 0 ) {
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cprintf(RED,"Warning: Unable to set slave address:0x%x \n",addr);
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return -2;
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}
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return fd;
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}
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int i2c_read(){
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int fd = i2c_open(I2C_DEVICE_FILE, I2C_DEVICE_ADDRESS);
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__u8 reg = I2C_REGISTER_ADDRESS & 0xff;
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unsigned char buf = reg;
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if (write(fd, &buf, 1)!= 1){
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cprintf(RED,"Warning: Unable to write read request to register %d\n", reg);
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return -1;
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}
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//read and update value (but old value read out)
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if(read(fd, &buf, 1) != 1){
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cprintf(RED,"Warning: Unable to read register %d\n", reg);
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return -2;
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}
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//read again to read the updated value
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if(read(fd, &buf, 1) != 1){
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cprintf(RED,"Warning: Unable to read register %d\n", reg);
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return -2;
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}
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close(fd);
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return buf;
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}
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int i2c_write(unsigned int value){
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__u8 val = value & 0xff;
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int fd = i2c_open(I2C_DEVICE_FILE, I2C_DEVICE_ADDRESS);
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if(fd < 0)
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return fd;
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__u8 reg = I2C_REGISTER_ADDRESS & 0xff;
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char buf[3];
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buf[0] = reg;
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buf[1] = val;
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if (write(fd, buf, 2) != 2) {
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cprintf(RED,"Warning: Unable to write %d to register %d\n",val, reg);
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return -1;
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}
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close(fd);
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return 0;
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}
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int main(int argc, char* argv[]) {
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int fd = open(PORTNAME, O_RDWR | O_NOCTTY | O_SYNC);
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if(fd < 0){
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cprintf(RED,"Warning: Unable to open port %s\n", PORTNAME);
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return -1;
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}
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cprintf(GREEN,"opened port at %s\n",PORTNAME);
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struct termios serial_conf;
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// reset structure
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memset(&serial_conf,0,sizeof(serial_conf));
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// control options
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serial_conf.c_cflag = B2400 | CS8 | CREAD | CLOCAL;
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// input options
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serial_conf.c_iflag = IGNPAR;
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// output options
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serial_conf.c_oflag = 0;
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// line options
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serial_conf.c_lflag = ICANON;
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// flush input
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if(tcflush(fd, TCIOFLUSH) < 0){
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cprintf(RED,"Warning: error form tcflush %d\n", errno);
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return 0;
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}
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// set new options for the port, TCSANOW:changes occur immediately without waiting for data to complete
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if(tcsetattr(fd, TCSANOW, &serial_conf) < 0){
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cprintf(RED,"Warning: error form tcsetattr %d\n", errno);
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return 0;
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}
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if(tcsetattr(fd, TCSAFLUSH, &serial_conf) < 0){
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cprintf(RED,"Warning: error form tcsetattr %d\n", errno);
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return 0;
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}
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int ret = 0;
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int n = 0;
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int ival= 0;
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char buffer[BUFFERSIZE];
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memset(buffer,0,BUFFERSIZE);
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buffer[BUFFERSIZE-1] = '\n';
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cprintf(GREEN,"Ready...\n");
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while(ret != GOODBYE){
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memset(buffer,0,BUFFERSIZE);
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n = read(fd,buffer,BUFFERSIZE);
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#ifdef VERBOSE
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cprintf(BLUE,"Received %d Bytes\n", n);
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#endif
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cprintf(BLUE,"Got message: '%s'\n",buffer);
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switch(buffer[0]){
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case '\0':
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cprintf(GREEN,"Got Start (Detector restart)\n");
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break;
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case 's':
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cprintf(GREEN,"Got Start \n");
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break;
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case 'p':
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if (!sscanf(&buffer[1],"%d",&ival)){
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cprintf(RED,"Warning: cannot scan voltage value\n");
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break;
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}
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// ok/ fail
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memset(buffer,0,BUFFERSIZE);
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buffer[BUFFERSIZE-1] = '\n';
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if(i2c_write(ival)<0)
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strcpy(buffer,"fail ");
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else
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strcpy(buffer,"success ");
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cprintf(GREEN,"Sending: '%s'\n",buffer);
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n = write(fd, buffer, BUFFERSIZE);
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#ifdef VERBOSE
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cprintf(GREEN,"Sent %d Bytes\n", n);
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#endif
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break;
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case 'g':
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ival = i2c_read();
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//ok/ fail
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memset(buffer,0,BUFFERSIZE);
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buffer[BUFFERSIZE-1] = '\n';
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if(ival < 0)
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strcpy(buffer,"fail ");
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else
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strcpy(buffer,"success ");
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n = write(fd, buffer, BUFFERSIZE);
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cprintf(GREEN,"Sending: '%s'\n",buffer);
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#ifdef VERBOSE
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cprintf(GREEN,"Sent %d Bytes\n", n);
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#endif
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//value
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memset(buffer,0,BUFFERSIZE);
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buffer[BUFFERSIZE-1] = '\n';
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if(ival >= 0){
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cprintf(GREEN,"Sending: '%d'\n",ival);
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sprintf(buffer,"%d ",ival);
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n = write(fd, buffer, BUFFERSIZE);
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#ifdef VERBOSE
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cprintf(GREEN,"Sent %d Bytes\n", n);
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#endif
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}else cprintf(RED,"%s\n",buffer);
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break;
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case 'e':
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printf("Exiting Program\n");
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ret = GOODBYE;
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break;
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default:
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cprintf(RED,"Unknown Command. buffer:'%s'\n",buffer);
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break;
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}
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}
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close(fd);
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printf("Goodbye Serial Communication for HV(9M)\n");
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return 0;
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}
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1346
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Beb.c
Normal file
1346
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Beb.c
Normal file
File diff suppressed because it is too large
Load Diff
103
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Beb.h
Normal file
103
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Beb.h
Normal file
@ -0,0 +1,103 @@
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/**
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* @author Ian Johnson
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* @version 1.0
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*/
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#ifndef BEB_H
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#define BEB_H
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#include "LocalLinkInterface.h"
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#include "slsDetectorServer_defs.h"
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struct BebInfo{
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unsigned int beb_number;
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unsigned int serial_address;
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char src_mac_1GbE[50];
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char src_mac_10GbE[50];
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char src_ip_1GbE[50];
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char src_ip_10GbE[50];
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unsigned int src_port_1GbE;
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unsigned int src_port_10GbE;
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};
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void BebInfo_BebInfo(struct BebInfo* bebInfo, unsigned int beb_num);
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void BebInfo_BebDstInfo(struct BebInfo* bebInfo, unsigned int beb_num);
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int BebInfo_SetSerialAddress(struct BebInfo* bebInfo, unsigned int add);
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int BebInfo_SetHeaderInfo(struct BebInfo* bebInfo, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);//src_port fixed 42000+beb_number or 52000 + beb_number);
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unsigned int BebInfo_GetBebNumber(struct BebInfo* bebInfo);
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unsigned int BebInfo_GetSerialAddress(struct BebInfo* bebInfo);
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char* BebInfo_GetSrcMAC(struct BebInfo* bebInfo, int ten_gig);
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char* BebInfo_GetSrcIP(struct BebInfo* bebInfo, int ten_gig);
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unsigned int BebInfo_GetSrcPort(struct BebInfo* bebInfo, int ten_gig);
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void BebInfo_Print(struct BebInfo* bebInfo);
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void Beb_ClearBebInfos();
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int Beb_InitBebInfos();
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int Beb_CheckSourceStuffBebInfo();
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unsigned int Beb_GetBebInfoIndex(unsigned int beb_numb);
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void Beb_GetModuleConfiguration(int* master, int* top, int* normal);
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void Beb_EndofDataSend(int tengiga);
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int Beb_SetMasterViaSoftware();
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int Beb_SetSlaveViaSoftware();
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int Beb_Activate(int enable);
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int Beb_Set32bitOverflow(int val);
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int Beb_SetNetworkParameter(enum NETWORKINDEX mode, int val);
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int Beb_ResetToHardwareSettings();
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u_int32_t Beb_GetFirmwareRevision();
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u_int32_t Beb_GetFirmwareSoftwareAPIVersion();
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void Beb_ResetFrameNumber();
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int Beb_WriteTo(unsigned int index);
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int Beb_SetMAC(char* mac, uint8_t* dst_ptr);
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int Beb_SetIP(char* ip, uint8_t* dst_ptr);
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int Beb_SetPortNumber(unsigned int port_number, uint8_t* dst_ptr);
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void Beb_AdjustIPChecksum(struct udp_header_type *ip);
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int Beb_SetHeaderData(unsigned int beb_number, int ten_gig, char* dst_mac, char* dst_ip, unsigned int dst_port);
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int Beb_SetHeaderData1(char* src_mac, char* src_ip, unsigned int src_port, char* dst_mac, char* dst_ip, unsigned int dst_port);
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void Beb_SwapDataFun(int little_endian, unsigned int n, unsigned int *d);
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int Beb_SetByteOrder();
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void Beb_Beb();
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int Beb_SetBebSrcHeaderInfos(unsigned int beb_number, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);
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int Beb_SetUpUDPHeader(unsigned int beb_number, int ten_gig, unsigned int header_number, char* dst_mac, char* dst_ip, unsigned int dst_port);
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/*int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty=1);*/
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int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty);
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int Beb_StopAcquisition();
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int Beb_SetUpTransferParameters(short the_bit_mode);
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/*int Beb_RequestNImages(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait=0); //all images go to the same destination!*/
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int Beb_RequestNImages(unsigned int beb_number, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait);
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int Beb_Test(unsigned int beb_number);
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int Beb_GetBebFPGATemp();
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void Beb_SetDetectorNumber(uint32_t detid);
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int Beb_SetDetectorPosition(int pos[]);
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uint16_t Beb_swap_uint16( uint16_t val);
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int Beb_open(u_int32_t** csp0base, u_int32_t offset);
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u_int32_t Beb_Read32 (u_int32_t* baseaddr, u_int32_t offset);
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u_int32_t Beb_Write32 (u_int32_t* baseaddr, u_int32_t offset, u_int32_t data);
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void Beb_close(int fd,u_int32_t* csp0base);
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#endif
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335
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Feb.c
Normal file
335
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Feb.c
Normal file
@ -0,0 +1,335 @@
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/**
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* @author Ian Johnson
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* @version 1.0
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*/
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|
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|
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/*#include <iostream>
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#include <iomanip>*/
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#include <stdio.h>
|
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#include <stdlib.h>
|
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#include <unistd.h>
|
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|
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#include "xparameters.h"
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#include "Feb.h"
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void Feb_Feb(){
|
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Feb_nfebs = 0;
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Feb_feb_numb = 0;
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Feb_send_ndata = 0;
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Feb_send_buffer_size = 1026;
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Feb_send_data_raw = malloc((Feb_send_buffer_size+1)*sizeof(int));
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Feb_send_data = &Feb_send_data_raw[1];
|
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|
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Feb_recv_ndata = 0;
|
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Feb_recv_buffer_size = 1026;
|
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Feb_recv_data_raw = malloc((Feb_recv_buffer_size+1)*sizeof(int));
|
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Feb_recv_data = &Feb_recv_data_raw[1];
|
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|
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Local_LocalLinkInterface1(ll,XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR);
|
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|
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}
|
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/*
|
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~Feb(){
|
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delete ll;
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if(feb_numb) delete [] feb_numb;
|
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delete [] send_data_raw;
|
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delete [] recv_data_raw;
|
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}
|
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*/
|
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|
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void Feb_SendCompleteFebList(unsigned int n,unsigned int* list){
|
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unsigned int i;
|
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if(Feb_feb_numb) free(Feb_feb_numb);
|
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Feb_nfebs = n;
|
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Feb_feb_numb = malloc(n*sizeof(unsigned int));
|
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for(i=0;i<n;i++) Feb_feb_numb[i] = list[i];
|
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}
|
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|
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int Feb_WriteTo(unsigned int ch){
|
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if(ch>0xfff) return 0;
|
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|
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Feb_send_data_raw[0] = 0x90000000 | (ch<<16); //we
|
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if(Local_Write(ll,4,Feb_send_data_raw)!=4) return 0;
|
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|
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Feb_send_data_raw[0] = 0xc0000000; //data
|
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return 1;//((Feb_send_ndata+1)*4==Local_Write(ll,(Feb_send_ndata+1)*4,Feb_send_data_raw));
|
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}
|
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|
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int Feb_ReadFrom(unsigned int ch, unsigned int ntrys){
|
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unsigned int t;
|
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if(ch>=0xfff) return 0;
|
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|
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Feb_recv_data_raw[0] = 0xa0000000 | (ch<<16); //read data
|
||||
Local_Write(ll,4,Feb_recv_data_raw);
|
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usleep(20);
|
||||
|
||||
Feb_recv_ndata=-1;
|
||||
for(t=0;t<ntrys;t++){
|
||||
if((Feb_recv_ndata=Local_Read(ll,Feb_recv_buffer_size*4,Feb_recv_data_raw)/4)>0){
|
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Feb_recv_ndata--;
|
||||
break;
|
||||
}
|
||||
printf("\t Read try number: %d\n",t);
|
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usleep(1000);
|
||||
}
|
||||
|
||||
|
||||
return (Feb_recv_ndata>=0);
|
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}
|
||||
|
||||
void Feb_PrintData(){
|
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int i;
|
||||
printf("Sent data: %d\n",Feb_send_ndata);
|
||||
for(i=0;i<Feb_send_ndata;i++) printf("\t%d)%d (0x%x)\n",i,Feb_send_data[i],Feb_send_data[i]);
|
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printf("Receive data: %d\n",Feb_recv_ndata);
|
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for(i=0;i<Feb_recv_ndata;i++) printf("\t%d)%d (0x%x)\n",i,Feb_recv_data[i],Feb_recv_data[i]);
|
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printf("\n\n");
|
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}
|
||||
|
||||
|
||||
int Feb_CheckHeader(unsigned int valid_bit_mask, int print_error_info){
|
||||
|
||||
int header_returned_is_ok = (Feb_send_data[0] & valid_bit_mask)==(Feb_recv_data[0] & valid_bit_mask);
|
||||
|
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if(print_error_info && !header_returned_is_ok){
|
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printf("Error: Command received not the same as command recieved.\n");
|
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printf("\t\t Header sent: %d (0x%x) received: %d (0x%x)\n",Feb_send_data[0], Feb_send_data[0], Feb_recv_data[0], Feb_recv_data[0]);
|
||||
if(Feb_send_ndata>1&&Feb_recv_ndata>1){
|
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printf("\t\t Tail sent: %d (0x%x) receiver: %d (0x%x)\n",Feb_send_data[Feb_send_ndata-1],Feb_send_data[Feb_send_ndata-1],Feb_recv_data[Feb_recv_ndata-1],Feb_recv_data[Feb_recv_ndata-1]);
|
||||
}else{
|
||||
printf("Error printing tail, too little data nsent = 0x%x, nrecv = 0x%x.\n",Feb_send_ndata, Feb_recv_ndata);
|
||||
}
|
||||
Feb_PrintData();
|
||||
}
|
||||
return header_returned_is_ok;
|
||||
}
|
||||
|
||||
|
||||
int Feb_CheckTail(unsigned int valid_bit_mask){
|
||||
if(Feb_send_ndata<=1&&Feb_recv_ndata<=1){
|
||||
printf("Error checking tail, too little data nsent = %d, nrecv = %d.\n",Feb_send_ndata, Feb_recv_ndata);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int the_tail = Feb_recv_data[Feb_recv_ndata-1]&valid_bit_mask;
|
||||
if(the_tail!=0){
|
||||
printf("Error returned in tail: 0x%x (%d)\n",the_tail,the_tail);
|
||||
if(the_tail&0x10000000) printf("\t\tBusy flag address error.\n");
|
||||
if(the_tail&0x20000000) printf("\t\tRead register address error.\n");
|
||||
if(the_tail&0x40000000) printf("\t\tWrite register address error.\n");
|
||||
if(the_tail&0x80000000) printf("\t\tBram number error.\n");
|
||||
if(the_tail&0x08000000) printf("\t\tFifo to read from error.\n");
|
||||
if(the_tail&0x3ff) printf("\t\tNumber of data send error.\n");
|
||||
return 0; //error
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int Feb_CheckCommunication(){
|
||||
Feb_send_data_raw[0] = 0x8fff0000; //rst-all serial coms and lls
|
||||
if(Local_Write(ll,4,Feb_send_data_raw)!=4) return 0;
|
||||
|
||||
printf("CheckingCommunication ....\n");
|
||||
while((Local_Read(ll,Feb_recv_buffer_size*4,Feb_recv_data_raw)/4)>0) printf("\t) Cleanning buffer ...\n");
|
||||
|
||||
return Feb_SetByteOrder();
|
||||
}
|
||||
|
||||
|
||||
int Feb_SetByteOrder(){
|
||||
|
||||
unsigned int i;
|
||||
Feb_send_ndata = 2;
|
||||
Feb_send_data[0] = 0; //header
|
||||
Feb_send_data[1] = 0; //tail
|
||||
|
||||
unsigned int dst = 0xff;
|
||||
for( i=0;i<Feb_nfebs;i++) dst = (dst | Feb_feb_numb[i]); //get sub dst bits (left right in this case)
|
||||
int passed = Feb_WriteTo(dst);
|
||||
|
||||
for(i=0;i<Feb_nfebs;i++){
|
||||
printf("\t%d) Set Byte Order .............. ",i);
|
||||
unsigned int current_passed = Feb_ReadFrom(Feb_feb_numb[i],20)&&(Feb_recv_ndata==2)&&Feb_CheckHeader(0xffffffff,1);
|
||||
if(current_passed) printf("passed.\n");
|
||||
else printf("failed.\n");
|
||||
passed&=current_passed;
|
||||
}
|
||||
printf("\n");
|
||||
|
||||
return passed;
|
||||
}
|
||||
|
||||
/* feb_ needed
|
||||
int Feb_CheckSubNumber(unsigned int Feb_sub_num){
|
||||
if(sub_num>=nfebs){
|
||||
cout<<"Error invalid sub number "<<sub_num<<" must be less than "<<nfebs<<"."<<endl;
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
int Feb_SetStartOnEndOnFebs(int sub_num_s, unsigned int& start_on, unsigned int& end_on){
|
||||
// -1 means write to all
|
||||
|
||||
if(sub_num_s<=-2){
|
||||
cout<<"Error bad subnumber "<<sub_num_s<<"."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
start_on = sub_num_s!=-1 ? sub_num_s : 0;
|
||||
end_on = sub_num_s!=-1 ? sub_num_s : nfebs - 1;
|
||||
|
||||
return Feb_CheckSubNumber(start_on);
|
||||
}
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
int Feb_ReadRegister(unsigned int Feb_sub_num, unsigned int Feb_reg_num,unsigned int& Feb_value_read){
|
||||
return Feb_ReadRegisters(Feb_sub_num,1,&Feb_reg_num,&Feb_value_read);
|
||||
}
|
||||
*/
|
||||
int Feb_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read){
|
||||
return Feb_ReadRegisters(sub_num,1,®_num,value_read);
|
||||
}
|
||||
|
||||
int Feb_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read){
|
||||
//here cout<<"Reading Register ...."<<endl;
|
||||
unsigned int i;
|
||||
nreads &= 0x3ff; //10 bits
|
||||
if(!nreads||nreads>Feb_send_buffer_size-2) return 0;
|
||||
|
||||
Feb_send_ndata = nreads+2;
|
||||
Feb_send_data[0] = 0x20000000 | nreads << 14; //cmd -> read "00" , nreads
|
||||
|
||||
for(i=0;i<nreads;i++) Feb_send_data[i+1]=reg_nums[i];
|
||||
Feb_send_data[nreads+1] = 0; //tail
|
||||
|
||||
if(!Feb_WriteTo(sub_num)||!Feb_ReadFrom(sub_num,20)||Feb_recv_ndata!=(int)(nreads+2)||!Feb_CheckHeader(0xffffffff,1)||!Feb_CheckTail(0xffffffff)){
|
||||
Feb_PrintData();
|
||||
printf("Error reading register.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
for(i=0;i<nreads;i++) values_read[i] = Feb_recv_data[i+1];
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int Feb_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address){
|
||||
return Feb_WriteRegisters(sub_num,1,®_num,&value,&wait_on,&wait_on_address);
|
||||
}
|
||||
|
||||
int Feb_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses){
|
||||
unsigned int i;
|
||||
// sub_num == 0xfff means write to all
|
||||
|
||||
nwrites &= 0x3ff; //10 bits
|
||||
if(!nwrites||nwrites>Feb_send_buffer_size-2) return 0;
|
||||
|
||||
//cout<<"Write register : "<<this<<" "<<s_num<<" "<<nwrites<<" "<<reg_nums<<" "<<values<<" "<<wait_ons<<" "<<wait_on_addresses<<endl;
|
||||
Feb_send_ndata = 2*nwrites+2;
|
||||
Feb_send_data[0] = 0x80000000 | nwrites << 14; //cmd -> write nwrites and how many
|
||||
Feb_send_data[2*nwrites+1] = 0; //tail
|
||||
|
||||
for(i=0;i<nwrites;i++) Feb_send_data[2*i+1] = 0x3fff®_nums[i]; // register address data_in(13 downto 0)
|
||||
for(i=0;i<nwrites;i++) Feb_send_data[2*i+2] = values[i]; // value is data_in(31 downto 0)
|
||||
// wait on busy data(28), address of busy flag data(27 downto 14)
|
||||
if(wait_ons&&wait_on_addresses) for(i=0;i<nwrites;i++) Feb_send_data[2*i+1] |= (wait_ons[i]<<28 | (0x3fff&wait_on_addresses[i])<<14);
|
||||
|
||||
if(!Feb_WriteTo(sub_num)){
|
||||
printf("%d) Error writing register(s).\n",sub_num);
|
||||
Feb_PrintData();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int passed = 1;
|
||||
unsigned int n = (sub_num&0xff)==0xff ? Feb_nfebs : 1;
|
||||
unsigned int* nums = (sub_num&0xff)==0xff ? Feb_feb_numb : &sub_num;
|
||||
for(i=0;i<n;i++){
|
||||
if((sub_num&0xf00&(nums[i]))==0) continue;
|
||||
if(!Feb_ReadFrom(nums[i],20)||Feb_recv_ndata!=2||!Feb_CheckHeader(0xffffffff,1)){
|
||||
printf("%d) Error writing register(s) response.\n",nums[i]);
|
||||
Feb_PrintData();
|
||||
passed = 0;
|
||||
}else{
|
||||
passed = passed && Feb_CheckTail(0xffffffff);
|
||||
}
|
||||
}
|
||||
|
||||
return passed;
|
||||
}
|
||||
|
||||
|
||||
int Feb_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values){
|
||||
// -1 means write to all
|
||||
unsigned int i;
|
||||
mem_num &= 0x3f; //6 bits
|
||||
start_address &= 0x3fff; //14 bits
|
||||
nwrites &= 0x3ff; //10 bits
|
||||
if(!nwrites||nwrites>Feb_send_buffer_size-2) return 0;
|
||||
|
||||
Feb_send_ndata = nwrites+2;
|
||||
Feb_send_data[0] = 0xc0000000 | mem_num << 24 | nwrites << 14 | start_address; //cmd -> write to memory, nwrites, mem number, start address
|
||||
Feb_send_data[nwrites+1] = 0; //tail
|
||||
for(i=0;i<nwrites;i++) Feb_send_data[i+1] = values[i];
|
||||
|
||||
|
||||
if(!Feb_WriteTo(sub_num)){
|
||||
printf("%d) Error writing memory.\n",sub_num);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int passed = 1;
|
||||
unsigned int n = (sub_num&0xff)==0xff ? Feb_nfebs : 1;
|
||||
unsigned int* nums = (sub_num&0xff)==0xff ? Feb_feb_numb : &sub_num;
|
||||
for(i=0;i<n;i++){
|
||||
if((sub_num&0xf00&(nums[i]))==0) continue;
|
||||
if(!Feb_ReadFrom(nums[i],20)||Feb_recv_ndata!=2||!Feb_CheckHeader(0xffffffff,1)){
|
||||
printf("%d) Error writing memory response. \n",nums[i]);
|
||||
Feb_PrintData();
|
||||
passed = 0;
|
||||
}else{
|
||||
passed = passed && Feb_CheckTail(0xffffffff);
|
||||
}
|
||||
}
|
||||
// unsigned int n = sub_num==0xfff ? nfebs : 1;
|
||||
// unsigned int* nums = sub_num==0xfff ? feb_numb : &sub_num;
|
||||
// for(unsigned int i=0;i<n;i++){
|
||||
|
||||
return passed;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int Feb_Test(){//int sub_num_s, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values){
|
||||
// -1 means write to all
|
||||
unsigned int i;
|
||||
unsigned int reg_nums[10]={0,1,2,3,1,2,3,1,2,3};
|
||||
|
||||
printf("Test\n\n\n\n");
|
||||
|
||||
unsigned int value = 0;
|
||||
for(i=0;i<10;i++){
|
||||
Feb_WriteRegister(0xfff,reg_nums[i%10],i,0,0);
|
||||
Feb_ReadRegister(256,reg_nums[i%10],&value);
|
||||
printf("%d %d\n",i,value);
|
||||
Feb_ReadRegister(512,reg_nums[i%10],&value);
|
||||
printf("%d %d\n",i,value);
|
||||
Feb_WriteMemory(0xfff,0,0,10,reg_nums);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -0,0 +1,59 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FEB_H
|
||||
#define FEB_H
|
||||
|
||||
#include "LocalLinkInterface.h"
|
||||
|
||||
|
||||
struct LocalLinkInterface* ll;
|
||||
|
||||
unsigned int Feb_nfebs;
|
||||
unsigned int* Feb_feb_numb;
|
||||
|
||||
int Feb_send_ndata;
|
||||
unsigned int Feb_send_buffer_size;
|
||||
unsigned int* Feb_send_data_raw;
|
||||
unsigned int* Feb_send_data;
|
||||
|
||||
int Feb_recv_ndata;
|
||||
unsigned int Feb_recv_buffer_size;
|
||||
unsigned int* Feb_recv_data_raw;
|
||||
unsigned int* Feb_recv_data;
|
||||
|
||||
int Feb_WriteTo(unsigned int ch);
|
||||
/*int Feb_ReadFrom(unsigned int Feb_ch, unsigned int Feb_ntrys=20);*/
|
||||
int Feb_ReadFrom(unsigned int ch, unsigned int ntrys);
|
||||
/* int Feb_CheckHeader(unsigned int Feb_valid_bit_mask=0xffffffff, int Feb_print_error_info=1);*/
|
||||
int Feb_CheckHeader(unsigned int valid_bit_mask, int print_error_info);
|
||||
/*int Feb_CheckTail(unsigned int Feb_valid_bit_mask=0xffffffff);*/
|
||||
int Feb_CheckTail(unsigned int valid_bit_mask);
|
||||
|
||||
int Feb_SetByteOrder();
|
||||
//int Feb_CheckSubNumber(unsigned int Feb_sub_num);
|
||||
//int Feb_SetStartOnEndOnFebs(int Feb_sub_num_s, unsigned int& Feb_start_on, unsigned int& Feb_end_on);
|
||||
void Feb_PrintData();
|
||||
|
||||
|
||||
void Feb_Feb();
|
||||
/*virtual ~Feb();*/
|
||||
void Feb_SendCompleteFebList(unsigned int n,unsigned int* list);
|
||||
int Feb_CheckCommunication();
|
||||
/*int Feb_ReadRegister(unsigned int Feb_sub_num, unsigned int Feb_reg_num,unsigned int& Feb_value_read);*/
|
||||
int Feb_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read);
|
||||
int Feb_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read);
|
||||
/*int WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on=0, unsigned int wait_on_address=0);*/
|
||||
int Feb_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address);
|
||||
/*int WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons=0, unsigned int* wait_on_addresses=0);*/
|
||||
int Feb_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses);
|
||||
int Feb_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
|
||||
int Feb_Test();
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,210 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FEBCONTROL_H
|
||||
#define FEBCONTROL_H
|
||||
|
||||
#include <netinet/in.h>
|
||||
#include <stdlib.h>
|
||||
//#include <string>
|
||||
//#include <vector>
|
||||
|
||||
|
||||
#include "FebInterface.h"
|
||||
|
||||
|
||||
struct Module{
|
||||
unsigned int module_number;
|
||||
int top_address_valid;
|
||||
unsigned int top_left_address;
|
||||
unsigned int top_right_address;
|
||||
int bottom_address_valid;
|
||||
unsigned int bottom_left_address;
|
||||
unsigned int bottom_right_address;
|
||||
|
||||
unsigned int idelay_top[4]; //ll,lr,rl,ll
|
||||
unsigned int idelay_bottom[4]; //ll,lr,rl,ll
|
||||
float high_voltage;
|
||||
int* top_dac;
|
||||
int* bottom_dac;
|
||||
};
|
||||
|
||||
|
||||
void Module_Module(struct Module* mod,unsigned int number, unsigned int address_top);
|
||||
void Module_ModuleBottom(struct Module* mod,unsigned int number, unsigned int address_bottom);
|
||||
void Module_Module1(struct Module* mod,unsigned int number, unsigned int address_top, unsigned int address_bottom);
|
||||
unsigned int Module_GetModuleNumber(struct Module* mod);
|
||||
int Module_TopAddressIsValid(struct Module* mod);
|
||||
unsigned int Module_GetTopBaseAddress(struct Module* mod);
|
||||
unsigned int Module_GetTopLeftAddress(struct Module* mod) ;
|
||||
unsigned int Module_GetTopRightAddress(struct Module* mod);
|
||||
unsigned int Module_GetBottomBaseAddress(struct Module* mod);
|
||||
int Module_BottomAddressIsValid(struct Module* mod);
|
||||
unsigned int Module_GetBottomLeftAddress(struct Module* mod);
|
||||
unsigned int Module_GetBottomRightAddress(struct Module* mod);
|
||||
unsigned int Module_SetTopIDelay(struct Module* mod,unsigned int chip,unsigned int value);
|
||||
unsigned int Module_GetTopIDelay(struct Module* mod,unsigned int chip) ;
|
||||
unsigned int Module_SetBottomIDelay(struct Module* mod,unsigned int chip,unsigned int value);
|
||||
unsigned int Module_GetBottomIDelay(struct Module* mod,unsigned int chip);
|
||||
|
||||
float Module_SetHighVoltage(struct Module* mod,float value);
|
||||
float Module_GetHighVoltage(struct Module* mod);
|
||||
|
||||
int Module_SetTopDACValue(struct Module* mod,unsigned int i, int value);
|
||||
int Module_GetTopDACValue(struct Module* mod,unsigned int i);
|
||||
int Module_SetBottomDACValue(struct Module* mod,unsigned int i, int value);
|
||||
int Module_GetBottomDACValue(struct Module* mod,unsigned int i);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void Feb_Control_activate(int activate);
|
||||
|
||||
int Feb_Control_IsBottomModule();
|
||||
int Feb_Control_GetModuleNumber();
|
||||
|
||||
|
||||
|
||||
|
||||
void Feb_Control_PrintModuleList();
|
||||
int Feb_Control_GetModuleIndex(unsigned int module_number, unsigned int* module_index);
|
||||
int Feb_Control_CheckModuleAddresses(struct Module* m);
|
||||
int Feb_Control_AddModule(unsigned int module_number, unsigned int top_address);
|
||||
/*int Feb_Control_AddModule(unsigned int module_number, unsigned int top_address, unsigned int bottom_address, int half_module=0);*/
|
||||
int Feb_Control_AddModule1(unsigned int module_number, int top_enable, unsigned int top_address, unsigned int bottom_address, int half_module);
|
||||
|
||||
int Feb_Control_GetDACNumber(char* s, unsigned int* n);
|
||||
int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch, unsigned int* value);
|
||||
int Feb_Control_VoltageToDAC(float value, unsigned int* digital, unsigned int nsteps, float vmin, float vmax);
|
||||
float Feb_Control_DACToVoltage(unsigned int digital,unsigned int nsteps,float vmin,float vmax);
|
||||
|
||||
|
||||
int Feb_Control_SendIDelays(unsigned int dst_num, int chip_lr, unsigned int channels, unsigned int ndelay_units);
|
||||
|
||||
int Feb_Control_SetStaticBits();
|
||||
int Feb_Control_SetStaticBits1(unsigned int the_static_bits);
|
||||
|
||||
int Feb_Control_SendBitModeToBebServer();
|
||||
|
||||
unsigned int Feb_Control_ConvertTimeToRegister(float time_in_sec);
|
||||
|
||||
unsigned int Feb_Control_AddressToAll();
|
||||
int Feb_Control_SetCommandRegister(unsigned int cmd);
|
||||
int Feb_Control_GetDAQStatusRegister(unsigned int dst_address, unsigned int* ret_status);
|
||||
/*int Feb_Control_StartDAQOnlyNWaitForFinish(int sleep_time_us=5000);*/
|
||||
int Feb_Control_StartDAQOnlyNWaitForFinish(int sleep_time_us);
|
||||
|
||||
int Feb_Control_ResetChipCompletely();
|
||||
int Feb_Control_ResetChipPartially();
|
||||
|
||||
//struct sockaddr_in Feb_Control_serv_addr;
|
||||
/*
|
||||
int Feb_Control_SetupSendToSocket(const char* ip_address_hostname, unsigned short int port);
|
||||
int Feb_Control_WriteNRead(char* message, int length, int max_length);
|
||||
*/
|
||||
|
||||
|
||||
void Feb_Control_FebControl();
|
||||
int Feb_Control_Init(int master, int top, int normal, int module_num);
|
||||
int Feb_Control_OpenSerialCommunication();
|
||||
void Feb_Control_CloseSerialCommunication();
|
||||
int Feb_Control_CheckSetup();
|
||||
|
||||
unsigned int Feb_Control_GetNModules();
|
||||
unsigned int Feb_Control_GetNHalfModules();
|
||||
|
||||
int Feb_Control_SetHighVoltage(int value);
|
||||
int Feb_Control_GetHighVoltage(int* value);
|
||||
|
||||
int Feb_Control_SendHighVoltage(int dacvalue);
|
||||
int Feb_Control_ReceiveHighVoltage(unsigned int* value);
|
||||
|
||||
int Feb_Control_SetIDelays(unsigned int module_num, unsigned int ndelay_units);
|
||||
int Feb_Control_SetIDelays1(unsigned int module_num, unsigned int chip_pos, unsigned int ndelay_units);
|
||||
|
||||
int Feb_Control_DecodeDACString(char* dac_str, unsigned int* module_index, int* top, int* bottom, unsigned int* dac_ch);
|
||||
/*int Feb_Control_SetDAC(string s, int value, int is_a_voltage_mv=0);*/
|
||||
int Feb_Control_SetDAC(char* s, int value, int is_a_voltage_mv);
|
||||
/* int Feb_Control_GetDAC(string s, int* ret_value, int voltage_mv=0);*/
|
||||
int Feb_Control_GetDAC(char* s, int* ret_value, int voltage_mv);
|
||||
int Feb_Control_GetDACName(unsigned int dac_num,char* s);
|
||||
|
||||
int Feb_Control_SetTrimbits(unsigned int module_num, unsigned int* trimbits);
|
||||
unsigned int* Feb_Control_GetTrimbits();
|
||||
|
||||
|
||||
/**Added by Dhanya */
|
||||
int Feb_Control_SaveAllTrimbitsTo(int value);
|
||||
|
||||
|
||||
|
||||
int Feb_Control_Reset();
|
||||
int Feb_Control_PrepareForAcquisition();
|
||||
|
||||
int Feb_Control_StartAcquisition();
|
||||
int Feb_Control_StopAcquisition();
|
||||
int Feb_Control_AcquisitionInProgress();
|
||||
int Feb_Control_AcquisitionStartedBit();
|
||||
/*int Feb_Control_WaitForFinishedFlag(int sleep_time_us=5000);*/
|
||||
int Feb_Control_WaitForFinishedFlag(int sleep_time_us);
|
||||
int Feb_Control_WaitForStartedFlag(int sleep_time_us, int prev_flag);
|
||||
|
||||
//functions for setting up exposure
|
||||
void Feb_Control_PrintAcquisitionSetup();
|
||||
int Feb_Control_SetNExposures(unsigned int n_images);
|
||||
unsigned int Feb_Control_GetNExposures();
|
||||
int Feb_Control_SetExposureTime(double the_exposure_time_in_sec);
|
||||
double Feb_Control_GetExposureTime();
|
||||
int64_t Feb_Control_GetExposureTime_in_nsec();
|
||||
int Feb_Control_SetSubFrameExposureTime(int64_t the_subframe_exposure_time_in_10nsec);
|
||||
int64_t Feb_Control_GetSubFrameExposureTime();
|
||||
int Feb_Control_SetSubFramePeriod(int64_t the_subframe_period_in_10nsec);
|
||||
int64_t Feb_Control_GetSubFramePeriod();
|
||||
int Feb_Control_SetExposurePeriod(double the_exposure_period_in_sec);
|
||||
double Feb_Control_GetExposurePeriod();
|
||||
int Feb_Control_SetDynamicRange(unsigned int four_eight_sixteen_or_thirtytwo);
|
||||
unsigned int Feb_Control_GetDynamicRange();
|
||||
int Feb_Control_SetReadoutSpeed(unsigned int readout_speed); //0 was default, 0->full,1->half,2->quarter or 3->super_slow
|
||||
int Feb_Control_SetReadoutMode(unsigned int readout_mode); ///0 was default,0->parallel,1->non-parallel,2-> safe_mode
|
||||
int Feb_Control_SetTriggerMode(unsigned int trigger_mode, int polarity);//0 and 1 was default,
|
||||
int Feb_Control_SetExternalEnableMode(int use_external_enable, int polarity);//0 and 1 was default,
|
||||
|
||||
//functions for testing
|
||||
/*int Feb_Control_SetTestModeVariable(int on=1);*/
|
||||
int Feb_Control_SetInTestModeVariable(int on);
|
||||
int Feb_Control_GetTestModeVariable();
|
||||
|
||||
void Feb_Control_Set_Counter_Bit(int value);
|
||||
int Feb_Control_Get_Counter_Bit();
|
||||
int Feb_Control_Pulse_Pixel(int npulses,int x, int y);
|
||||
int Feb_Control_PulsePixelNMove(int npulses, int inc_x_pos, int inc_y_pos);
|
||||
int Feb_Control_Shift32InSerialIn(unsigned int value_to_shift_in);
|
||||
int Feb_Control_SendTokenIn();
|
||||
int Feb_Control_ClockRowClock(unsigned int ntimes);
|
||||
int Feb_Control_PulseChip(int npulses);
|
||||
|
||||
int64_t Feb_Control_Get_RateTable_Tau_in_nsec();
|
||||
int64_t Feb_Control_Get_RateTable_Period_in_nsec();
|
||||
int Feb_Control_SetRateCorrectionTau(int64_t tau_in_Nsec);
|
||||
int Feb_Control_SetRateCorrectionTable(unsigned int *table);
|
||||
int Feb_Control_GetRateCorrectionVariable();
|
||||
void Feb_Control_SetRateCorrectionVariable(int activate_rate_correction);
|
||||
int Feb_Control_PrintCorrectedValues();
|
||||
|
||||
int Feb_Control_GetLeftFPGATemp();
|
||||
int Feb_Control_GetRightFPGATemp();
|
||||
|
||||
int64_t Feb_Control_GetMeasuredPeriod();
|
||||
int64_t Feb_Control_GetSubMeasuredPeriod();
|
||||
|
||||
int Feb_Control_SoftwareTrigger();
|
||||
|
||||
uint32_t Feb_Control_WriteRegister(uint32_t offset, uint32_t data);
|
||||
uint32_t Feb_Control_ReadRegister(uint32_t offset);
|
||||
#endif
|
||||
@ -0,0 +1,210 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
|
||||
//#include <iostream>
|
||||
//#include <iomanip>
|
||||
//#include <unistd.h>
|
||||
//#include <string.h>
|
||||
//#include <sys/mman.h>
|
||||
//#include <fcntl.h>
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "xparameters.h"
|
||||
|
||||
#include "FebInterface.h"
|
||||
|
||||
|
||||
|
||||
struct LocalLinkInterface ll_local,* ll;
|
||||
|
||||
unsigned int Feb_Interface_nfebs;
|
||||
unsigned int* Feb_Interface_feb_numb;
|
||||
|
||||
int Feb_Interface_send_ndata;
|
||||
unsigned int Feb_Interface_send_buffer_size;
|
||||
unsigned int* Feb_Interface_send_data_raw;
|
||||
unsigned int* Feb_Interface_send_data;
|
||||
|
||||
int Feb_Interface_recv_ndata;
|
||||
unsigned int Feb_Interface_recv_buffer_size;
|
||||
unsigned int* Feb_Interface_recv_data_raw;
|
||||
unsigned int* Feb_Interface_recv_data;
|
||||
|
||||
|
||||
void Feb_Interface_FebInterface(){
|
||||
ll = &ll_local;
|
||||
Feb_Interface_nfebs = 0;
|
||||
Feb_Interface_feb_numb = 0;
|
||||
|
||||
Feb_Interface_send_ndata = 0;
|
||||
Feb_Interface_send_buffer_size = 1026;
|
||||
Feb_Interface_send_data_raw = malloc((Feb_Interface_send_buffer_size+1) * sizeof(unsigned int));
|
||||
Feb_Interface_send_data = &Feb_Interface_send_data_raw[1];
|
||||
|
||||
Feb_Interface_recv_ndata = 0;
|
||||
Feb_Interface_recv_buffer_size = 1026;
|
||||
Feb_Interface_recv_data_raw = malloc((Feb_Interface_recv_buffer_size+1) * sizeof(unsigned int));
|
||||
Feb_Interface_recv_data = &Feb_Interface_recv_data_raw[1];
|
||||
|
||||
Local_LocalLinkInterface1(ll,XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
void Feb_Interface_SendCompleteList(unsigned int n,unsigned int* list){
|
||||
unsigned int i;
|
||||
if(Feb_Interface_feb_numb) free(Feb_Interface_feb_numb);
|
||||
Feb_Interface_nfebs = n;
|
||||
Feb_Interface_feb_numb = malloc(n * sizeof(unsigned int));
|
||||
for(i=0;i<n;i++) Feb_Interface_feb_numb[i] = list[i];
|
||||
}
|
||||
|
||||
int Feb_Interface_WriteTo(unsigned int ch){
|
||||
if(ch>0xfff) return 0;
|
||||
|
||||
#ifdef MARTIN
|
||||
cprintf(YELLOW, "FIW ch %d\n", ch);
|
||||
#endif
|
||||
|
||||
Feb_Interface_send_data_raw[0] = 0x8fff0000;
|
||||
if(Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
|
||||
|
||||
Feb_Interface_send_data_raw[0] = 0x90000000 | (ch<<16);
|
||||
if(Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
|
||||
|
||||
Feb_Interface_send_data_raw[0] = 0xc0000000;
|
||||
return ((Feb_Interface_send_ndata+1)*4==Local_Write(ll,(Feb_Interface_send_ndata+1)*4,Feb_Interface_send_data_raw));
|
||||
}
|
||||
|
||||
int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys){
|
||||
unsigned int t;
|
||||
if(ch>=0xfff) return 0;
|
||||
|
||||
Feb_Interface_recv_data_raw[0] = 0xa0000000 | (ch<<16);
|
||||
Local_Write(ll,4,Feb_Interface_recv_data_raw);
|
||||
usleep(20);
|
||||
|
||||
Feb_Interface_recv_ndata=-1;
|
||||
for(t=0;t<ntrys;t++){
|
||||
if((Feb_Interface_recv_ndata=Local_Read(ll,Feb_Interface_recv_buffer_size*4,Feb_Interface_recv_data_raw)/4)>0){
|
||||
Feb_Interface_recv_ndata--;
|
||||
break;
|
||||
}
|
||||
usleep(1000);
|
||||
}
|
||||
|
||||
return (Feb_Interface_recv_ndata>=0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
int Feb_Interface_SetByteOrder(){
|
||||
Feb_Interface_send_data_raw[0] = 0x8fff0000;
|
||||
if(Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
|
||||
Feb_Interface_send_ndata = 2;
|
||||
Feb_Interface_send_data[0] = 0;
|
||||
Feb_Interface_send_data[1] = 0;
|
||||
unsigned int i;
|
||||
unsigned int dst = 0xff;
|
||||
for(i=0;i<Feb_Interface_nfebs;i++) dst = (dst | Feb_Interface_feb_numb[i]);
|
||||
int passed = Feb_Interface_WriteTo(dst);
|
||||
|
||||
return passed;
|
||||
}
|
||||
|
||||
|
||||
int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read){
|
||||
return Feb_Interface_ReadRegisters(sub_num,1,®_num,value_read);
|
||||
}
|
||||
|
||||
|
||||
int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read){
|
||||
//here cout<<"Reading Register ...."<<endl;
|
||||
unsigned int i;
|
||||
nreads &= 0x3ff;
|
||||
if(!nreads||nreads>Feb_Interface_send_buffer_size-2) return 0;
|
||||
|
||||
Feb_Interface_send_ndata = nreads+2;
|
||||
Feb_Interface_send_data[0] = 0x20000000 | nreads << 14;
|
||||
|
||||
for(i=0;i<nreads;i++) Feb_Interface_send_data[i+1]=reg_nums[i];
|
||||
Feb_Interface_send_data[nreads+1] = 0;
|
||||
|
||||
if(!Feb_Interface_WriteTo(sub_num)||!Feb_Interface_ReadFrom(sub_num,20)||Feb_Interface_recv_ndata!=(int)(nreads+2)) return 0;
|
||||
|
||||
for(i=0;i<nreads;i++) values_read[i] = Feb_Interface_recv_data[i+1];
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address){
|
||||
return Feb_Interface_WriteRegisters(sub_num,1,®_num,&value,&wait_on,&wait_on_address);
|
||||
}
|
||||
|
||||
int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses){
|
||||
unsigned int i;
|
||||
nwrites &= 0x3ff; //10 bits
|
||||
if(!nwrites||2*nwrites>Feb_Interface_send_buffer_size-2) return 0;
|
||||
|
||||
//cout<<"Write register : "<<this<<" "<<s_num<<" "<<nwrites<<" "<<reg_nums<<" "<<values<<" "<<wait_ons<<" "<<wait_on_addresses<<endl;
|
||||
Feb_Interface_send_ndata = 2*nwrites+2;
|
||||
Feb_Interface_send_data[0] = 0x80000000 | nwrites << 14;
|
||||
Feb_Interface_send_data[2*nwrites+1] = 0;
|
||||
|
||||
for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+1] = 0x3fff®_nums[i];
|
||||
for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+2] = values[i];
|
||||
// wait on busy data(28), address of busy flag data(27 downto 14)
|
||||
if(wait_ons&&wait_on_addresses) for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+1] |= (wait_ons[i]<<28 | (0x3fff&wait_on_addresses[i])<<14);
|
||||
|
||||
if(!Feb_Interface_WriteTo(sub_num)) return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values){
|
||||
unsigned int max_single_packet_size = 352;
|
||||
int passed=1;
|
||||
unsigned int n_to_send = max_single_packet_size;
|
||||
unsigned int ndata_sent = 0;
|
||||
unsigned int ndata_countdown = nwrites;
|
||||
while(ndata_countdown>0){
|
||||
n_to_send = ndata_countdown<max_single_packet_size ? ndata_countdown:max_single_packet_size;
|
||||
if(!Feb_Interface_WriteMemory(sub_num,mem_num,start_address,n_to_send,&(values[ndata_sent]))){passed=0; break;}
|
||||
ndata_countdown-=n_to_send;
|
||||
ndata_sent +=n_to_send;
|
||||
start_address +=n_to_send;
|
||||
usleep(500);//500 works
|
||||
}
|
||||
return passed;
|
||||
}
|
||||
|
||||
int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values){
|
||||
// -1 means write to all
|
||||
unsigned int i;
|
||||
mem_num &= 0x3f;
|
||||
start_address &= 0x3fff;
|
||||
nwrites &= 0x3ff;
|
||||
if(!nwrites||nwrites>Feb_Interface_send_buffer_size-2) {printf("error herer: nwrites:%d\n",nwrites);return 0;}//*d-1026
|
||||
|
||||
Feb_Interface_send_ndata = nwrites+2;//*d-1026
|
||||
Feb_Interface_send_data[0] = 0xc0000000 | mem_num << 24 | nwrites << 14 | start_address; //cmd -> write to memory, nwrites, mem number, start address
|
||||
Feb_Interface_send_data[nwrites+1] = 0;
|
||||
for(i=0;i<nwrites;i++) Feb_Interface_send_data[i+1] = values[i];
|
||||
|
||||
|
||||
if(!Feb_Interface_WriteTo(sub_num)) return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,43 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FEBINTERFACE_H
|
||||
#define FEBINTERFACE_H
|
||||
|
||||
#include "LocalLinkInterface.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int Feb_Interface_WriteTo(unsigned int ch);
|
||||
/*int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys=20);*/
|
||||
int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys);
|
||||
|
||||
void Feb_Interface_FebInterface();
|
||||
|
||||
|
||||
void Feb_Interface_SendCompleteList(unsigned int n,unsigned int* list);
|
||||
int Feb_Interface_SetByteOrder();
|
||||
|
||||
int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read);
|
||||
int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read);
|
||||
/*int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on=0, unsigned int wait_on_address=0);*/
|
||||
int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address);
|
||||
/*int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons=0, unsigned int* wait_on_addresses=0);*/
|
||||
int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses);
|
||||
|
||||
//mem_num is 0 for trimbit BRAM and 1 for rate correction BRAM
|
||||
int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
|
||||
|
||||
int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,227 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
//daq register definitions
|
||||
#define DAQ_REG_CTRL 1
|
||||
#define DAQ_REG_CHIP_CMDS 2
|
||||
#define DAQ_REG_STATIC_BITS 3
|
||||
#define DAQ_REG_CLK_ROW_CLK_NTIMES 3
|
||||
#define DAQ_REG_SHIFT_IN_32 3
|
||||
#define DAQ_REG_READOUT_NROWS 3
|
||||
#define DAQ_REG_SEND_N_TESTPULSES 3
|
||||
|
||||
#define DAQ_REG_NEXPOSURES 3
|
||||
#define DAQ_REG_EXPOSURE_TIMER 4 // == (31 downto 3) * 10^(2 downto 0)
|
||||
#define DAQ_REG_EXPOSURE_REPEAT_TIMER 5 // == (31 downto 3) * 10^(2 downto 0)
|
||||
#define DAQ_REG_SUBFRAME_EXPOSURES 6
|
||||
#define DAQ_REG_SUBFRAME_PERIOD 7 //also pg and fifo status register
|
||||
|
||||
|
||||
#define DAQ_REG_RO_OFFSET 12
|
||||
#define DAQ_REG_STATUS (DAQ_REG_RO_OFFSET + 0) //also pg and fifo status register
|
||||
#define FEB_REG_STATUS (DAQ_REG_RO_OFFSET + 3)
|
||||
#define MEAS_SUBPERIOD_REG (DAQ_REG_RO_OFFSET + 4)
|
||||
#define MEAS_PERIOD_REG (DAQ_REG_RO_OFFSET + 5)
|
||||
|
||||
|
||||
|
||||
#define DAQ_CTRL_RESET 0x80000000
|
||||
#define DAQ_CTRL_START 0x40000000
|
||||
#define ACQ_CTRL_START 0x50000000 //this is 0x10000000 (acq) | 0x40000000 (daq)
|
||||
#define DAQ_CTRL_STOP 0x00000000
|
||||
|
||||
//direct chip commands to the DAQ_REG_CHIP_CMDS register
|
||||
#define DAQ_SET_STATIC_BIT 0x00000001
|
||||
#define DAQ_RESET_COMPLETELY 0x0000000E
|
||||
#define DAQ_RESET_PERIPHERY 0x00000002
|
||||
#define DAQ_RESET_PIXEL_COUNTERS 0x00000004
|
||||
#define DAQ_RESET_COLUMN_SELECT 0x00000008
|
||||
|
||||
#define DAQ_STORE_IMAGE 0x00000010
|
||||
#define DAQ_RELEASE_IMAGE_STORE 0x00000020
|
||||
|
||||
#define DAQ_SEND_A_TOKEN_IN 0x00000040
|
||||
#define DAQ_CLK_ROW_CLK_NTIMES 0x00000080
|
||||
#define DAQ_SERIALIN_SHIFT_IN_32 0x00000100
|
||||
#define DAQ_LOAD_16ROWS_OF_TRIMBITS 0x00000200
|
||||
|
||||
#define DAQ_IGNORE_INITIAL_CRAP 0x00000400 //crap before readout
|
||||
#define DAQ_READOUT_NROWS 0x00000800
|
||||
#define DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START 0x00001000 //last 4 bit of data in the last frame
|
||||
|
||||
#define DAQ_RELEASE_IMAGE_STORE_AFTER_READOUT 0x00002000
|
||||
#define DAQ_RESET_PIXEL_COUNTERS_AFTER_READOUT 0x00004000
|
||||
|
||||
#define DAQ_CLK_ROW_CLK_TO_SELECT_NEXT_ROW 0x00008000
|
||||
#define DAQ_CLK_MAIN_CLK_TO_SELECT_NEXT_PIXEL 0x00010000
|
||||
#define DAQ_SEND_N_TEST_PULSES 0x00020000
|
||||
|
||||
#define DAQ_CHIP_CONTROLLER_HALF_SPEED 0x00040000 //everything at 100 MHz (50MHz ddr readout)
|
||||
#define DAQ_CHIP_CONTROLLER_QUARTER_SPEED 0x00080000 //everything at 50 MHz (25MHz ddr readout)
|
||||
#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED 0x000c0000 //everything at ~200 kHz (200 kHz MHz ddr readout)
|
||||
|
||||
//#define DAQ_FIFO_ENABLE 0x00100000 commented out as it is not used anywhere
|
||||
#define DAQ_REG_CHIP_CMDS_INT_TRIGGER 0x00100000
|
||||
|
||||
//direct chip commands to the DAQ_REG_CHIP_CMDS register
|
||||
#define DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE 0x00200000 //row clk is before main clk readout sequence
|
||||
#define DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE 0x00400000 //expose ->readout ->expose -> ..., with store is always closed
|
||||
#define DAQ_NEXPOSURERS_PARALLEL_MODE 0x00600000 //parallel acquire/read mode
|
||||
|
||||
//DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES is old now hard-wired in the firmware that every image comes with a header
|
||||
//#define DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES 0x00800000 //DAQ_IGNORE_INITIAL_CRAP and DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START
|
||||
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING 0x01000000
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING_POLARITY 0x02000000
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_TRIGGER_POLARITY 0x04000000
|
||||
|
||||
#define DAQ_NEXPOSURERS_INTERNAL_ACQUISITION 0x00000000 //internally controlled
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START 0x08000000 //external acquisition start
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START 0x10000000 //external image start
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP 0x18000000 //externally controlly, external image start and stop
|
||||
|
||||
#define DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING 0x20000000
|
||||
#define DAQ_NEXPOSURERS_ACTIVATE_RATE_CORRECTION 0x40000000
|
||||
|
||||
//#define DAQ_MASTER_HALF_MODULE 0x80000000 currently not used
|
||||
|
||||
|
||||
//chips static bits
|
||||
#define DAQ_STATIC_BIT_PROGRAM 0x00000001
|
||||
#define DAQ_STATIC_BIT_M4 0x00000002 //these are the status bits, not bit mode
|
||||
#define DAQ_STATIC_BIT_M8 0x00000004 //these are the status bits, not bit mode
|
||||
#define DAQ_STATIC_BIT_M12 0x00000000 //these are the status bits, not bit mode, ie. "00" is 12 bit mode
|
||||
#define DAQ_STATIC_BIT_CHIP_TEST 0x00000008
|
||||
#define DAQ_STATIC_BIT_ROTEST 0x00000010
|
||||
#define DAQ_CS_BAR_LEFT 0x00000020
|
||||
#define DAQ_CS_BAR_RIGHT 0x00000040
|
||||
|
||||
|
||||
//status flags
|
||||
#define DAQ_STATUS_DAQ_RUNNING 0x01
|
||||
#define DAQ_DATA_COLLISION_ERROR 0x02
|
||||
|
||||
|
||||
#define DAQ_STATUS_CURRENT_M4 0x04
|
||||
#define DAQ_STATUS_CURRENT_M8 0x08
|
||||
#define DAQ_STATUS_CURRENT_M12 0x00 //in 12 bit mode both are cleared
|
||||
#define DAQ_STATUS_CURRENT_TESTMODE 0x10
|
||||
#define DAQ_STATUS_TOKEN_OUT 0x20
|
||||
#define DAQ_STATUS_SERIAL_OUT 0x40
|
||||
#define DAQ_STATUS_PIXELS_ARE_ENABLED 0x80
|
||||
#define DAQ_STATUS_DAQ_RUN_TOGGLE 0x200
|
||||
|
||||
//data delay registers
|
||||
#define CHIP_DATA_OUT_DELAY_REG_CTRL 1
|
||||
#define CHIP_DATA_OUT_DELAY_REG2 2
|
||||
#define CHIP_DATA_OUT_DELAY_REG3 3
|
||||
#define CHIP_DATA_OUT_DELAY_REG4 4
|
||||
#define CHIP_DATA_OUT_DELAY_SET 0x20000000
|
||||
|
||||
//module configuration
|
||||
#define TOP_BIT_MASK 0x00f
|
||||
#define MASTER_BIT_MASK 0x200
|
||||
#define NORMAL_MODULE_BIT_MASK 0x400
|
||||
|
||||
// Master Slave Top Bottom Definition
|
||||
#define MODULE_CONFIGURATION_MASK 0x84
|
||||
//Software Configuration
|
||||
#define MASTERCONFIG_OFFSET 0x160 //0x20 * 11 (P11)
|
||||
#define MASTER_BIT 0x1
|
||||
#define OVERWRITE_HARDWARE_BIT 0x2
|
||||
#define DEACTIVATE_BIT 0x4
|
||||
|
||||
#define FPGA_TEMP_OFFSET 0x200
|
||||
|
||||
#define TXM_DELAY_LEFT_OFFSET 0x180
|
||||
#define TXM_DELAY_RIGHT_OFFSET 0x1A0
|
||||
#define TXM_DELAY_FRAME_OFFSET 0x1C0
|
||||
#define FLOW_REG_OFFSET 0x140
|
||||
|
||||
#define FLOW_REG_TXM_FLOW_CNTRL_10G_OFST (0)
|
||||
#define FLOW_REG_TXM_FLOW_CNTRL_10G_MSK (0x1 << FLOW_REG_TXM_FLOW_CNTRL_10G_OFST)
|
||||
#define FLOW_REG_OVERFLOW_32_BIT_OFST (2)
|
||||
#define FLOW_REG_OVERFLOW_32_BIT_MSK (0x1 << FLOW_REG_OVERFLOW_32_BIT_OFST)
|
||||
|
||||
//command memory
|
||||
#define LEFT_OFFSET 0x0
|
||||
#define RIGHT_OFFSET 0x100
|
||||
|
||||
#define FIRST_CMD_PART1_OFFSET 0x8
|
||||
#define FIRST_CMD_PART2_OFFSET 0xc
|
||||
#define SECOND_CMD_PART1_OFFSET 0x10
|
||||
#define SECOND_CMD_PART2_OFFSET 0x14
|
||||
#define COMMAND_COUNTER_OFFSET 0x18
|
||||
#define STOP_ACQ_OFFSET 0x1c
|
||||
#define STOP_ACQ_BIT 0x40000000
|
||||
#define TWO_REQUESTS_OFFSET 0x1c
|
||||
#define TWO_REQUESTS_BIT 0x80000000
|
||||
|
||||
//version
|
||||
#define FIRMWARE_VERSION_OFFSET 0x4
|
||||
#define FIRMWARESOFTWARE_API_OFFSET 0x0
|
||||
|
||||
#define FRAME_NUM_RESET_OFFSET 0xA0
|
||||
|
||||
//1g counters
|
||||
#define ONE_GIGA_LEFT_INDEX_LSB_COUNTER 0x04
|
||||
#define ONE_GIGA_LEFT_INDEX_MSB_COUNTER 0x24
|
||||
|
||||
#define ONE_GIGA_LEFT_TXN_DELAY_COUNTER 0x104
|
||||
#define ONE_GIGA_LEFT_FRAME_DELAY_COUNTER 0x124
|
||||
|
||||
#define ONE_GIGA_RIGHT_INDEX_LSB_COUNTER 0x44
|
||||
#define ONE_GIGA_RIGHT_INDEX_MSB_COUNTER 0x64
|
||||
|
||||
#define ONE_GIGA_RIGHT_TXN_DELAY_COUNTER 0x144
|
||||
#define ONE_GIGA_RIGHT_FRAME_DELAY_COUNTER 0x164
|
||||
|
||||
//10g counters
|
||||
#define TEN_GIGA_LEFT_INDEX_LSB_COUNTER 0x84
|
||||
#define TEN_GIGA_LEFT_INDEX_MSB_COUNTER 0xa4
|
||||
|
||||
#define TEN_GIGA_LEFT_TXN_DELAY_COUNTER 0x184
|
||||
#define TEN_GIGA_LEFT_FRAME_DELAY_COUNTER 0x1a4
|
||||
|
||||
#define TEN_GIGA_RIGHT_INDEX_LSB_COUNTER 0xc4
|
||||
#define TEN_GIGA_RIGHT_INDEX_MSB_COUNTER 0xe4
|
||||
|
||||
#define TEN_GIGA_RIGHT_TXN_DELAY_COUNTER 0x1c4
|
||||
#define TEN_GIGA_RIGHT_FRAME_DELAY_COUNTER 0x1e4
|
||||
|
||||
// udp header (position, id)
|
||||
#define UDP_HEADER_A_LEFT_OFST 0x00C0
|
||||
#define UDP_HEADER_B_LEFT_OFST 0x00E0
|
||||
#define UDP_HEADER_A_RIGHT_OFST 0x0100
|
||||
#define UDP_HEADER_B_RIGHT_OFST 0x0120
|
||||
|
||||
#define UDP_HEADER_X_OFST (0)
|
||||
#define UDP_HEADER_X_MSK (0xFFFF << UDP_HEADER_X_OFST)
|
||||
#define UDP_HEADER_ID_OFST (16)
|
||||
#define UDP_HEADER_ID_MSK (0xFFFF << UDP_HEADER_ID_OFST)
|
||||
#define UDP_HEADER_Z_OFST (0)
|
||||
#define UDP_HEADER_Z_MSK (0xFFFF << UDP_HEADER_Z_OFST)
|
||||
#define UDP_HEADER_Y_OFST (16)
|
||||
#define UDP_HEADER_Y_MSK (0xFFFF << UDP_HEADER_Y_OFST)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,87 @@
|
||||
|
||||
//Class initially from Gerd and was called mmap_test.c
|
||||
//return reversed 1 means good, 0 means failed
|
||||
|
||||
|
||||
//#include <stdio.h>
|
||||
//#include <unistd.h>
|
||||
//#include <string.h>
|
||||
//#include <sys/mman.h>
|
||||
//#include <fcntl.h>
|
||||
|
||||
#include "HardwareIO.h"
|
||||
|
||||
xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress)
|
||||
{
|
||||
/* read the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
xfs_u8 IoContents;
|
||||
__asm__ volatile ("eieio; lbz %0,0(%1)":"=r" (IoContents):"b"
|
||||
(InAddress));
|
||||
return IoContents;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress)
|
||||
{
|
||||
/* read the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
xfs_u16 IoContents;
|
||||
__asm__ volatile ("eieio; lhz %0,0(%1)":"=r" (IoContents):"b"
|
||||
(InAddress));
|
||||
return IoContents;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress)
|
||||
{
|
||||
/* read the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
xfs_u32 IoContents;
|
||||
__asm__ volatile ("eieio; lwz %0,0(%1)":"=r" (IoContents):"b"
|
||||
(InAddress));
|
||||
return IoContents;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value)
|
||||
{
|
||||
/* write the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
__asm__ volatile ("stb %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value)
|
||||
{
|
||||
/* write the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
__asm__ volatile ("sth %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value)
|
||||
{
|
||||
/* write the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
__asm__ volatile ("stw %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,26 @@
|
||||
|
||||
|
||||
//Class initially from Gerd and was called mmap_test.c
|
||||
|
||||
#ifndef HARDWAREIO_H
|
||||
#define HARDWAREIO_H
|
||||
|
||||
#include "xfs_types.h"
|
||||
|
||||
|
||||
|
||||
xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress);
|
||||
xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress);
|
||||
xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress);
|
||||
|
||||
void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value);
|
||||
void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value);
|
||||
void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,62 @@
|
||||
|
||||
|
||||
//from Gerd and was called mmap_test.h
|
||||
|
||||
#ifndef __PLB_LL_FIFO_H__
|
||||
#define __PLB_LL_FIFO_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* definitions */
|
||||
/******************************************************************************/
|
||||
|
||||
#define PLB_LL_FIFO_REG_CTRL 0
|
||||
#define PLB_LL_FIFO_REG_STATUS 1
|
||||
#define PLB_LL_FIFO_REG_FIFO 2
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_LL_REM_SHIFT 30
|
||||
#define PLB_LL_FIFO_CTRL_LL_REM 0xC0000000
|
||||
#define PLB_LL_FIFO_CTRL_LL_EOF 0x20000000
|
||||
#define PLB_LL_FIFO_CTRL_LL_SOF 0x10000000
|
||||
#define PLB_LL_FIFO_CTRL_LL_MASK 0xF0000000
|
||||
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_TX_RESET 0x08000000
|
||||
#define PLB_LL_FIFO_CTRL_RX_RESET 0x04000000
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_RESET_STATUS 0x00800000
|
||||
#define PLB_LL_FIFO_CTRL_RESET_USER 0x00400000
|
||||
#define PLB_LL_FIFO_CTRL_RESET_LINK 0x00200000
|
||||
#define PLB_LL_FIFO_CTRL_RESET_GT 0x00100000
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_RESET_ALL 0x0CF00000
|
||||
|
||||
// do not reset complete gtx dual in std. case
|
||||
// cause this would reset PLL and stop LL clk
|
||||
#define PLB_LL_FIFO_CTRL_RESET_STD 0x0CE00000
|
||||
|
||||
// reset Rx and Tx Fifo and set User Reset
|
||||
#define PLB_LL_FIFO_CTRL_RESET_FIFO 0x0C400000
|
||||
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_CONFIG_VECTOR 0x000FFFFF
|
||||
|
||||
|
||||
#define PLB_LL_FIFO_STATUS_LL_REM_SHIFT 30
|
||||
#define PLB_LL_FIFO_STATUS_LL_REM 0xC0000000
|
||||
#define PLB_LL_FIFO_STATUS_LL_EOF 0x20000000
|
||||
#define PLB_LL_FIFO_STATUS_LL_SOF 0x10000000
|
||||
|
||||
#define PLB_LL_FIFO_STATUS_EMPTY 0x08000000
|
||||
#define PLB_LL_FIFO_STATUS_ALMOSTEMPTY 0x04000000
|
||||
#define PLB_LL_FIFO_STATUS_FULL 0x02000000
|
||||
#define PLB_LL_FIFO_STATUS_ALMOSTFULL 0x01000000
|
||||
|
||||
#define PLB_LL_FIFO_STATUS_VECTOR 0x000FFFFF
|
||||
|
||||
#define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
|
||||
|
||||
|
||||
#endif // __PLB_LL_FIFO_H__
|
||||
|
||||
|
||||
@ -0,0 +1,260 @@
|
||||
|
||||
//Class initially from Gerd and was called mmap_test.c
|
||||
//return reversed 1 means good, 0 means failed
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
//#include <string.h>
|
||||
|
||||
|
||||
#include "HardwareMMappingDefs.h"
|
||||
|
||||
#include "LocalLinkInterface.h"
|
||||
|
||||
|
||||
|
||||
void Local_LocalLinkInterface1(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr){
|
||||
// printf("\n v 1 \n");
|
||||
printf("Initialize PLB LL FIFOs\n");
|
||||
ll->ll_fifo_base=0;
|
||||
ll->ll_fifo_ctrl_reg=0;
|
||||
if(Local_Init(ll,ll_fifo_badr)){
|
||||
Local_Reset(ll);
|
||||
printf("\tFIFO Status : 0x%08x\n",Local_StatusVector(ll));
|
||||
}else printf("\tError LocalLink Mappping : 0x%08x\n",ll_fifo_badr);
|
||||
printf("\n\n");
|
||||
}
|
||||
|
||||
/*~LocalLinkInterface(){};*/
|
||||
|
||||
void Local_LocalLinkInterface(struct LocalLinkInterface* ll){
|
||||
printf("Initializing new memory\n");
|
||||
}
|
||||
|
||||
|
||||
|
||||
int Local_Init(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr){
|
||||
int fd;
|
||||
void *plb_ll_fifo_ptr;
|
||||
|
||||
if ((fd=open("/dev/mem", O_RDWR)) < 0){
|
||||
fprintf(stderr, "Could not open /dev/mem\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
plb_ll_fifo_ptr = mmap(0, getpagesize(), PROT_READ | PROT_WRITE, MAP_FILE | MAP_SHARED, fd, ll_fifo_badr);
|
||||
close(fd);
|
||||
|
||||
if (plb_ll_fifo_ptr == MAP_FAILED){
|
||||
perror ("mmap");
|
||||
return 0;
|
||||
}
|
||||
|
||||
ll->ll_fifo_base = (xfs_u32) plb_ll_fifo_ptr;
|
||||
ll->ll_fifo_ctrl_reg = 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int Local_Reset(struct LocalLinkInterface* ll){
|
||||
return Local_Reset1(ll,PLB_LL_FIFO_CTRL_RESET_STD);
|
||||
}
|
||||
|
||||
int Local_Reset1(struct LocalLinkInterface* ll,unsigned int rst_mask){
|
||||
ll->ll_fifo_ctrl_reg |= rst_mask;
|
||||
printf("\tCTRL Register bits: 0x%08x\n",ll->ll_fifo_ctrl_reg);
|
||||
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
|
||||
|
||||
ll->ll_fifo_ctrl_reg &= (~rst_mask);
|
||||
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
|
||||
// printf("FIFO CTRL Address: 0x%08x\n FIFO CTRL Register: 0x%08x\n",PLB_LL_FIFO_REG_CTRL,plb_ll_fifo[PLB_LL_FIFO_REG_CTRL]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
unsigned int Local_StatusVector(struct LocalLinkInterface* ll){
|
||||
return HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
|
||||
}
|
||||
|
||||
int Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer){
|
||||
// note: buffer must be word (4 byte) aligned
|
||||
// frame_len in byte
|
||||
int vacancy=0;
|
||||
int i;
|
||||
int words_send = 0;
|
||||
int last_word;
|
||||
unsigned int *word_ptr;
|
||||
unsigned int fifo_ctrl;
|
||||
xfs_u32 status;
|
||||
|
||||
if (buffer_len < 1) return -1;
|
||||
|
||||
last_word = (buffer_len-1)/4;
|
||||
word_ptr = (unsigned int *)buffer;
|
||||
|
||||
#ifdef MARTIN
|
||||
cprintf(BLUE, "LL Write - Len: %2d - If: %X - Data: ",buffer_len, ll->ll_fifo_base);
|
||||
for (i=0; i < buffer_len/4; i++)
|
||||
cprintf(BLUE, "%.8X ",*(((unsigned *) buffer)+i));
|
||||
printf("\n");
|
||||
#endif
|
||||
|
||||
while (words_send <= last_word)
|
||||
{
|
||||
while (!vacancy)//wait for Fifo to be empty again
|
||||
{
|
||||
status = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
|
||||
if((status & PLB_LL_FIFO_STATUS_ALMOSTFULL) == 0) vacancy = 1;
|
||||
#ifdef MARTIN
|
||||
if (vacancy == 0) cprintf(RED, "Fifo full!\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
//Just to know: #define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
|
||||
for (i=0; ((i<PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS) && (words_send <= last_word)); i++)
|
||||
{
|
||||
fifo_ctrl = 0;
|
||||
if (words_send == 0)
|
||||
{
|
||||
fifo_ctrl = PLB_LL_FIFO_CTRL_LL_SOF;//announce the start of file
|
||||
}
|
||||
|
||||
if (words_send == last_word)
|
||||
{
|
||||
fifo_ctrl |= (PLB_LL_FIFO_CTRL_LL_EOF | (( (buffer_len-1)<<PLB_LL_FIFO_CTRL_LL_REM_SHIFT) & PLB_LL_FIFO_CTRL_LL_REM) );
|
||||
}
|
||||
Local_ctrl_reg_write_mask(ll,PLB_LL_FIFO_CTRL_LL_MASK,fifo_ctrl);
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_FIFO,word_ptr[words_send++]);
|
||||
}
|
||||
}
|
||||
return buffer_len;
|
||||
}
|
||||
|
||||
|
||||
int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer){
|
||||
static unsigned int buffer_ptr = 0;
|
||||
// note: buffer must be word (4 byte) aligned
|
||||
// frame_len in byte
|
||||
int len;
|
||||
unsigned int *word_ptr;
|
||||
unsigned int status;
|
||||
volatile unsigned int fifo_val;
|
||||
int sof = 0;
|
||||
|
||||
#ifdef MARTIN
|
||||
cprintf(CYAN, "LL Read - If: %X - Data: ",ll->ll_fifo_base);
|
||||
#endif
|
||||
|
||||
word_ptr = (unsigned int *)buffer;
|
||||
do
|
||||
{
|
||||
status = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
|
||||
|
||||
if (!(status & PLB_LL_FIFO_STATUS_EMPTY))
|
||||
{
|
||||
if (status & PLB_LL_FIFO_STATUS_LL_SOF)
|
||||
{
|
||||
if (buffer_ptr)
|
||||
{
|
||||
buffer_ptr = 0;
|
||||
return -1; // buffer overflow
|
||||
}
|
||||
// printf(">>>> SOF\n\r");
|
||||
buffer_ptr = 0;
|
||||
sof = 1;
|
||||
}
|
||||
|
||||
fifo_val = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_FIFO); //read from fifo
|
||||
|
||||
if ((buffer_ptr > 0) || sof)
|
||||
{
|
||||
if ( (buffer_len >> 2) > buffer_ptr)
|
||||
{
|
||||
#ifdef MARTIN
|
||||
cprintf(CYAN, "%.8X ", fifo_val);
|
||||
#endif
|
||||
word_ptr[buffer_ptr++] = fifo_val; //write to buffer
|
||||
}
|
||||
else
|
||||
{
|
||||
buffer_ptr = 0;
|
||||
return -2; // buffer overflow
|
||||
}
|
||||
|
||||
if (status & PLB_LL_FIFO_STATUS_LL_EOF)
|
||||
{
|
||||
len = (buffer_ptr << 2) -3 + ( (status & PLB_LL_FIFO_STATUS_LL_REM)>>PLB_LL_FIFO_STATUS_LL_REM_SHIFT );
|
||||
#ifdef MARTIN
|
||||
cprintf(CYAN, "Len: %d\n",len);
|
||||
#endif
|
||||
// printf(">>>>status=0x%08x EOF len = %d \n\r\n\r",status, len);
|
||||
buffer_ptr = 0;
|
||||
return len;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
while(!(status & PLB_LL_FIFO_STATUS_EMPTY));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int Local_ctrl_reg_write_mask(struct LocalLinkInterface* ll,unsigned int mask, unsigned int val){
|
||||
// printf("Fifo CTRL Reg(1): 0x%08x\n",plb_ll_fifo_ctrl_reg);
|
||||
ll->ll_fifo_ctrl_reg &= (~mask);
|
||||
//printf("Fifo CTRL Reg(2): 0x%08x\n",plb_ll_fifo_ctrl_reg);
|
||||
ll->ll_fifo_ctrl_reg |= ( mask & val);
|
||||
// printf("Fifo CTRL Reg: 0x%08x\n",plb_ll_fifo_ctrl_reg);
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
|
||||
// printf("Fifo STAT Reg: 0x%08x\n", plb_ll_fifo[PLB_LL_FIFO_REG_STATUS]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer){
|
||||
|
||||
int len;
|
||||
unsigned int rec_buff_len = 4096;
|
||||
unsigned int rec_buffer[4097];
|
||||
|
||||
|
||||
Local_Write(ll,buffer_len,buffer);
|
||||
usleep(10000);
|
||||
|
||||
do{
|
||||
len = Local_Read(ll,rec_buff_len,rec_buffer);
|
||||
printf("receive length: %i\n",len);
|
||||
|
||||
if (len > 0){
|
||||
rec_buffer[len]=0;
|
||||
printf((char*) rec_buffer);
|
||||
printf("\n");
|
||||
}
|
||||
} while(len > 0);
|
||||
|
||||
printf("\n\n\n\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
void Local_llfifo_print_frame(struct LocalLinkInterface* ll,unsigned char* fbuff, int len){
|
||||
int i;
|
||||
printf("\n\r----Frame of len : %d Byte\n\r",len);
|
||||
for(i=0;i<len;i++){
|
||||
printf("0x%02x ",fbuff[i] );
|
||||
if ((i&0xf) == 0x7) printf(" ");
|
||||
if ((i&0xf) == 0xf) printf("\n\r");
|
||||
}
|
||||
printf("\n\r");
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,54 @@
|
||||
|
||||
//Class initially from Gerd and was called mmap_test.c
|
||||
|
||||
#ifndef LOCALLINKINTERFACE_H
|
||||
#define LOCALLINKINTERFACE_H
|
||||
|
||||
#include "xfs_types.h"
|
||||
#include "HardwareIO.h"
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "ansi.h"
|
||||
#include <sys/mman.h>
|
||||
#include <fcntl.h>
|
||||
|
||||
/*class LocalLinkInterface: public HardwareIO{ //*/
|
||||
|
||||
|
||||
struct LocalLinkInterface{
|
||||
xfs_u32 ll_fifo_base;
|
||||
unsigned int ll_fifo_ctrl_reg;
|
||||
};
|
||||
|
||||
|
||||
|
||||
int Local_Init(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr);
|
||||
int Local_Reset1(struct LocalLinkInterface* ll,unsigned int rst_mask);
|
||||
|
||||
int Local_ctrl_reg_write_mask(struct LocalLinkInterface* ll,unsigned int mask, unsigned int val);
|
||||
void Local_llfifo_print_frame(struct LocalLinkInterface* ll,unsigned char* fbuff, int len);
|
||||
|
||||
|
||||
void Local_LocalLinkInterface1(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr);
|
||||
/* virtual ~LocalLinkInterface();*/
|
||||
|
||||
unsigned int Local_StatusVector(struct LocalLinkInterface* ll);
|
||||
int Local_Reset(struct LocalLinkInterface* ll);
|
||||
int Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
|
||||
int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
|
||||
|
||||
int Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
|
||||
|
||||
void Local_LocalLinkInterface(struct LocalLinkInterface* ll);
|
||||
|
||||
/*
|
||||
int FiFoReset(unsigned int numb);
|
||||
int FifoSend(unsigned int numb, unsigned int frame_len, void *buffer);
|
||||
int FifoReceive(unsigned int numb, unsigned int frame_len, void *buffer);
|
||||
int FifoTest(unsigned int numb,unsigned int send_len, char *send_str);
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
38
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Makefile
Executable file
38
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Makefile
Executable file
@ -0,0 +1,38 @@
|
||||
CC = powerpc-4xx-softfloat-gcc
|
||||
BLACKFIN_CC = bfin-uclinux-gcc
|
||||
CFLAGS += -Wall -DDACS_INT -DEIGERD -DSLS_DETECTOR_FUNCTION_LIST -DDACS_INT -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE #-DVIRTUAL -DPCCOMPILE -DMARTIN
|
||||
LDLIBS += -lm -lstdc++
|
||||
|
||||
PROGS = eigerDetectorServer
|
||||
DESTDIR ?= bin
|
||||
INSTMODE = 0777
|
||||
|
||||
|
||||
SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c FebControl.c Beb.c HardwareIO.c LocalLinkInterface.c Feb.c FebInterface.c
|
||||
OBJS = $(SRC_CLNT:.c=.o)
|
||||
|
||||
|
||||
all: clean versioning $(PROGS) #hv9m_blackfin_server
|
||||
|
||||
|
||||
boot: $(OBJS)
|
||||
|
||||
versioning:
|
||||
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
|
||||
|
||||
$(PROGS): $(OBJS)
|
||||
# echo $(OBJS)
|
||||
mkdir -p $(DESTDIR)
|
||||
$(CC) -o $@ $(SRC_CLNT) $(CFLAGS) $(LDLIBS)
|
||||
mv $(PROGS) $(DESTDIR)
|
||||
|
||||
|
||||
hv9m_blackfin_server:9mhvserial_bf.c
|
||||
$(BLACKFIN_CC) -o hv9m_blackfin_server 9mhvserial_bf.c -Wall #-DVERBOSE
|
||||
mv hv9m_blackfin_server $(DESTDIR)
|
||||
rm hv9m_blackfin_server.gdb
|
||||
|
||||
clean:
|
||||
rm -rf $(DESTDIR)/$(PROGS) *.o $(DESTDIR)/hv9m_blackfin_server
|
||||
|
||||
|
||||
@ -0,0 +1,28 @@
|
||||
CC = gcc
|
||||
CFLAGS += -Wall -DDACS_INT -DEIGERD -DSLS_DETECTOR_FUNCTION_LIST -DDACS_INT -DPCCOMPILE -DSTOP_SERVER #-DVERBOSE
|
||||
CFLAGS += -DVIRTUAL -DVIRTUAL_9M
|
||||
MASTERFLAG += -DVIRTUAL_MASTER
|
||||
LDLIBS += -lm -lstdc++ -pthread
|
||||
|
||||
DESTDIR ?= bin
|
||||
|
||||
SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
|
||||
|
||||
|
||||
|
||||
all: clean master slave
|
||||
|
||||
|
||||
master: $(SRC_CLNT)
|
||||
mkdir -p $(DESTDIR)
|
||||
$(CC) -o eigerDetectorServer_virtualMaster $(SRC_CLNT) $(CFLAGS) $(MASTERFLAG) $(LDLIBS)
|
||||
mv eigerDetectorServer_virtualMaster $(DESTDIR)
|
||||
|
||||
slave: $(SRC_CLNT)
|
||||
mkdir -p $(DESTDIR)
|
||||
$(CC) -o eigerDetectorServer_virtualSlave $(SRC_CLNT) $(CFLAGS) $(LDLIBS)
|
||||
mv eigerDetectorServer_virtualSlave $(DESTDIR)
|
||||
|
||||
clean:
|
||||
rm -rf $(DESTDIR)/eigerDetectorServer_virtualMaster $(DESTDIR)/eigerDetectorServer_virtualSlave *.o
|
||||
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/ansi.h
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -0,0 +1 @@
|
||||
../commonFiles/communication_funcs.c
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/communication_funcs.h
|
||||
@ -0,0 +1,9 @@
|
||||
Path: slsDetectorsPackage/slsDetectorSoftware/eigerDetectorServer
|
||||
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
|
||||
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
|
||||
Repsitory UUID: c52025dd7c4b44b93e64353a22997d971996ab18
|
||||
Revision: 350
|
||||
Branch: developer
|
||||
Last Changed Author: Gemma_Tinti
|
||||
Last Changed Rev: 3999
|
||||
Last Changed Date: 2018-09-28 14:11:53.000000002 +0200 ./Makefile.virtual
|
||||
@ -0,0 +1,6 @@
|
||||
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
|
||||
#define GITREPUUID "c52025dd7c4b44b93e64353a22997d971996ab18"
|
||||
#define GITAUTH "Gemma_Tinti"
|
||||
#define GITREV 0x3999
|
||||
#define GITDATE 0x20180928
|
||||
#define GITBRANCH "developer"
|
||||
@ -0,0 +1,6 @@
|
||||
#define GITURL ""
|
||||
#define GITREPUUID ""
|
||||
#define GITAUTH ""
|
||||
#define GITREV ""
|
||||
#define GITDATE ""
|
||||
#define GITBRANCH ""
|
||||
@ -0,0 +1,4 @@
|
||||
mv bin/eigerDetectorServer bin/$2
|
||||
cp bin/$2 /tftpboot
|
||||
git rm -f bin/$1
|
||||
git add bin/$2
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorFunctionList.h
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorServer.c
|
||||
@ -0,0 +1,100 @@
|
||||
/*
|
||||
* slsDetectorServer_defs.h
|
||||
*
|
||||
* Created on: Jan 24, 2013
|
||||
* Author: l_maliakal_d
|
||||
*/
|
||||
|
||||
#ifndef SLSDETECTORSERVER_DEFS_H_
|
||||
#define SLSDETECTORSERVER_DEFS_H_
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#define GOODBYE (-200)
|
||||
#define REQUIRED_FIRMWARE_VERSION (22)
|
||||
#define IDFILECOMMAND "more /home/root/executables/detid.txt"
|
||||
|
||||
#define STATUS_IDLE 0
|
||||
#define STATUS_RUNNING 1
|
||||
#define STATUS_ERROR 2
|
||||
|
||||
/* Enums */
|
||||
enum CLK_SPEED_INDEX {FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
|
||||
enum DACINDEX {SVP,VTR,VRF,VRS,SVN,VTGSTV,VCMP_LL,VCMP_LR,CAL,VCMP_RL,RXB_RB,RXB_LB,VCMP_RR,VCP,VCN,VIS,VTHRESHOLD};
|
||||
#define DEFAULT_DAC_VALS { \
|
||||
0, /* SvP */ \
|
||||
2480, /* Vtr */ \
|
||||
3300, /* Vrf */ \
|
||||
1400, /* Vrs */ \
|
||||
4000, /* SvN */ \
|
||||
2556, /* Vtgstv */ \
|
||||
1000, /* Vcmp_ll */ \
|
||||
1000, /* Vcmp_lr */ \
|
||||
4000, /* cal */ \
|
||||
1000, /* Vcmp_rl */ \
|
||||
1100, /* rxb_rb */ \
|
||||
1100, /* rxb_lb */ \
|
||||
1000, /* Vcmp_rr */ \
|
||||
1000, /* Vcp */ \
|
||||
2000, /* Vcn */ \
|
||||
1550 /* Vis */ \
|
||||
};
|
||||
enum ADCINDEX {TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
|
||||
enum NETWORKINDEX {TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
|
||||
|
||||
|
||||
/* Hardware Definitions */
|
||||
#define NMAXMOD (1)
|
||||
#define NMOD (1)
|
||||
#define NCHAN (256 * 256)
|
||||
#define NCHIP (4)
|
||||
#define NADC (0)
|
||||
#define NDAC (16)
|
||||
#define NGAIN (0)
|
||||
#define NOFFSET (0)
|
||||
|
||||
|
||||
#define TEN_GIGA_BUFFER_SIZE (4112)
|
||||
#define ONE_GIGA_BUFFER_SIZE (1040)
|
||||
#define TEN_GIGA_CONSTANT (4)
|
||||
#define ONE_GIGA_CONSTANT (16)
|
||||
#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
|
||||
#define NORMAL_HIGHVOLTAGE_OUTPUTPORT "/sys/class/hwmon/hwmon5/device/out0_output"
|
||||
#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
|
||||
#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE (16)
|
||||
|
||||
/** Default Parameters */
|
||||
#define DEFAULT_MOD_INDEX (0)
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DEFAULT_EXPTIME (1E9) //ns
|
||||
#define DEFAULT_PERIOD (1E9) //ns
|
||||
#define DEFAULT_DELAY (0)
|
||||
#define DEFAULT_HIGH_VOLTAGE (0)
|
||||
#define DEFAULT_SETTINGS (DYNAMICGAIN)
|
||||
#define DEFAULT_SUBFRAME_EXPOSURE (2621440) // 2.6ms
|
||||
#define DEFAULT_SUBFRAME_DEADTIME (0)
|
||||
#define DEFAULT_DYNAMIC_RANGE (16)
|
||||
|
||||
#define DEFAULT_READOUT_MODE (NONPARALLEL)
|
||||
#define DEFAULT_READOUT_STOREINRAM_MODE (CONTINOUS_RO)
|
||||
#define DEFAULT_READOUT_OVERFLOW32_MODE (NOOVERFLOW)
|
||||
#define DEFAULT_CLK_SPEED (HALF_SPEED)
|
||||
#define DEFAULT_IO_DELAY (650)
|
||||
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
|
||||
#define DEFAULT_PHOTON_ENERGY (-1)
|
||||
#define DEFAULT_RATE_CORRECTION (0)
|
||||
#define DEFAULT_EXT_GATING_ENABLE (0)
|
||||
#define DEFAULT_EXT_GATING_POLARITY (1) //positive
|
||||
#define DEFAULT_TEST_MODE (0)
|
||||
#define DEFAULT_HIGH_VOLTAGE (0)
|
||||
|
||||
|
||||
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS (0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
|
||||
|
||||
#define SLAVE_HIGH_VOLTAGE_READ_VAL (-999)
|
||||
#define HIGH_VOLTAGE_TOLERANCE (5)
|
||||
|
||||
|
||||
#endif /* SLSDETECTORSERVER_DEFS_H_ */
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorServer_funcs.c
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorServer_funcs.h
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/sls_detector_defs.h
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/sls_detector_funcs.h
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/sls_receiver_defs.h
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/sls_receiver_funcs.h
|
||||
@ -0,0 +1,7 @@
|
||||
SRCFILE=gitInfoEiger.h
|
||||
DSTFILE=versionAPI.h
|
||||
|
||||
SRCPATTERN=GITDATE
|
||||
DSTPATTERN=APIEIGER
|
||||
|
||||
awk -v a="$SRCFILE" -v b="$DSTFILE" -v c="$SRCPATTERN" -v d="$DSTPATTERN" 'FNR==NR&&$2==c{x=$3} NR!=FNR{if($2==d){$3="0x"substr(x,5)}print > b}' $SRCFILE $DSTFILE
|
||||
@ -0,0 +1,32 @@
|
||||
SERVER=eigerDetectorServer
|
||||
MAINDIR=slsDetectorsPackage
|
||||
SPECDIR=slsDetectorSoftware/$SERVER
|
||||
TMPFILE=gitInfoEigerTmp.h
|
||||
INCLFILE=gitInfoEiger.h
|
||||
|
||||
#evaluate the variables
|
||||
EVALFILE=../../evalVersionVariables.sh
|
||||
source $EVALFILE
|
||||
|
||||
|
||||
#get modified date
|
||||
#RDATE1='git log --pretty=format:"%ci" -1'
|
||||
RDATE1="find ../slsDetectorServer . -type f -exec stat --format '%Y :%y %n' '{}' \; | sort -nr | cut -d: -f2- | egrep -v 'gitInfo|bin|.git|updateGitVersion|.o' | head -n 1"
|
||||
RDATE=`eval $RDATE1`
|
||||
NEWDATE=$(sed "s/-//g" <<< $RDATE | awk '{print $1;}')
|
||||
NEWDATE=${NEWDATE/#/0x}
|
||||
|
||||
|
||||
#get old date from INCLFILE
|
||||
OLDDATE=$(more $INCLFILE | grep '#define GITDATE' | awk '{print $3}')
|
||||
|
||||
|
||||
#update INCLFILE if changes
|
||||
if [ "$OLDDATE" != "$NEWDATE" ]; then
|
||||
echo Path: ${MAINDIR}/${SPECDIR} $'\n'URL: ${GITREPO} $'\n'Repository Root: ${GITREPO} $'\n'Repsitory UUID: ${REPUID} $'\n'Revision: ${FOLDERREV} $'\n'Branch: ${BRANCH} $'\n'Last Changed Author: ${AUTH1}_${AUTH2} $'\n'Last Changed Rev: ${REV} $'\n'Last Changed Date: ${RDATE} > gitInfo.txt
|
||||
cd ../../
|
||||
./genVersionHeader.sh $SPECDIR/gitInfo.txt $SPECDIR/$TMPFILE $SPECDIR/$INCLFILE
|
||||
cd $WD
|
||||
fi
|
||||
|
||||
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/versionAPI.h
|
||||
@ -0,0 +1,52 @@
|
||||
#ifndef __XFS_TYPES_H__
|
||||
#define __XFS_TYPES_H__
|
||||
|
||||
//#include "types.h"
|
||||
#include <stdint.h>
|
||||
/******************************************************************************/
|
||||
/* types */
|
||||
/******************************************************************************/
|
||||
|
||||
typedef unsigned int xfs_u32;
|
||||
typedef unsigned short xfs_u16;
|
||||
typedef unsigned char xfs_u8;
|
||||
|
||||
typedef signed int xfs_i32;
|
||||
typedef signed short xfs_i16;
|
||||
typedef signed char xfs_i8;
|
||||
|
||||
|
||||
// UDP Header
|
||||
struct udp_header_type
|
||||
{
|
||||
// ethternet frame (14 byte)
|
||||
uint8_t dst_mac[6];
|
||||
uint8_t src_mac[6];
|
||||
uint8_t len_type[2];
|
||||
|
||||
// ip header (20 byte)
|
||||
uint8_t ver_headerlen[1];
|
||||
uint8_t service_type[1];
|
||||
uint8_t total_length[2];
|
||||
uint8_t identification[2];
|
||||
uint8_t flags[1];
|
||||
uint8_t frag_offset[1];
|
||||
uint8_t time_to_live[1];
|
||||
uint8_t protocol[1];
|
||||
uint8_t ip_header_checksum[2];
|
||||
uint8_t src_ip[4];
|
||||
uint8_t dst_ip[4];
|
||||
|
||||
// udp header (8 byte)
|
||||
uint8_t src_port[2];
|
||||
uint8_t dst_port[2];
|
||||
uint8_t udp_message_len[2];
|
||||
uint8_t udp_checksum[2];
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
#endif // __XFS_TYPES_H__
|
||||
|
||||
|
||||
@ -0,0 +1,538 @@
|
||||
/* ONLY THOSE ARE USED IN THIS SOFTWARE. If one of those is modified in xilinx compilation, this file should be replaced with updated values
|
||||
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR
|
||||
XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR
|
||||
XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR
|
||||
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
|
||||
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR
|
||||
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
|
||||
*/
|
||||
/*******************************************************************
|
||||
*
|
||||
* CAUTION: This file is automatically generated by libgen.
|
||||
* Version: Xilinx EDK 12.4 EDK_MS4.81d
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
*
|
||||
* Description: Driver parameters
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
#define STDIN_BASEADDRESS 0xC0000000
|
||||
#define STDOUT_BASEADDRESS 0xC0000000
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral BB_IO_SHIFT_REG_PPC440 */
|
||||
#define XPAR_BB_IO_SHIFT_REG_PPC440_BASEADDR 0xD3000000
|
||||
#define XPAR_BB_IO_SHIFT_REG_PPC440_HIGHADDR 0xD300FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral EIGER_BEB_SYNCH_IO_PPC440 */
|
||||
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_BASEADDR 0xD3100000
|
||||
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_HIGHADDR 0xD310FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_BRAM_10G */
|
||||
#define XPAR_PLB_BRAM_10G_MEM0_BASEADDR 0xD4100000
|
||||
#define XPAR_PLB_BRAM_10G_MEM0_HIGHADDR 0xD410FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_BRAM_TEMAC */
|
||||
#define XPAR_PLB_BRAM_TEMAC_MEM0_BASEADDR 0xD4000000
|
||||
#define XPAR_PLB_BRAM_TEMAC_MEM0_HIGHADDR 0xD400FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_GPIO_SYS */
|
||||
#define XPAR_PLB_GPIO_SYS_BASEADDR 0xD1000000
|
||||
#define XPAR_PLB_GPIO_SYS_HIGHADDR 0xD100FFFF
|
||||
|
||||
/** Command Generator */
|
||||
#define XPAR_CMD_GENERATOR 0xC5000000
|
||||
|
||||
|
||||
/** Version Numbers */
|
||||
#define XPAR_VERSION 0xc6000000
|
||||
|
||||
/* Definitions for peripheral PLB_GPIO_TEST */
|
||||
#define XPAR_PLB_GPIO_TEST_BASEADDR 0xD1010000
|
||||
#define XPAR_PLB_GPIO_TEST_HIGHADDR 0xD101FFFF
|
||||
|
||||
|
||||
|
||||
/* Definitions for packet, frame and delay down counters */
|
||||
#define XPAR_COUNTER_BASEADDR 0xD1020000
|
||||
#define XPAR_COUNTER_HIGHADDR 0xD102FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT */
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR 0xC4100000
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_HIGHADDR 0xC410FFFF
|
||||
|
||||
/* Definitions for a new memory */
|
||||
//#define XPAR_PLB_LL_NEW_MEMORY 0xD1000000//0xD1000084//0xC4200000
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT */
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR 0xC4110000
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_HIGHADDR 0xC411FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_LEFT */
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR 0xC4120000
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_HIGHADDR 0xC412FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT */
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR 0xC4130000
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_HIGHADDR 0xC413FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_XAUI_10G */
|
||||
#define XPAR_PLB_LL_FIFO_XAUI_10G_BASEADDR 0xC4140000
|
||||
#define XPAR_PLB_LL_FIFO_XAUI_10G_HIGHADDR 0xC414FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_V46_CPU_TO_PLB_V46_BRIDGED */
|
||||
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_BASEADDR 0xCFFF0000
|
||||
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_HIGHADDR 0xCFFFFFFF
|
||||
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_BASEADDR 0xD0000000
|
||||
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_HIGHADDR 0xDFFFFFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PPC_SRAM */
|
||||
#define XPAR_PPC_SRAM_BASEADDR 0x00000000
|
||||
#define XPAR_PPC_SRAM_HIGHADDR 0x01FFFFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral PFLASH */
|
||||
#define XPAR_PFLASH_NUM_BANKS_MEM 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for peripheral PFLASH */
|
||||
#define XPAR_PFLASH_MEM0_BASEADDR 0xE0000000
|
||||
#define XPAR_PFLASH_MEM0_HIGHADDR 0xE3FFFFFF
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PFLASH */
|
||||
#define XPAR_EMC_0_NUM_BANKS_MEM 1
|
||||
#define XPAR_EMC_0_MEM0_BASEADDR 0xE0000000
|
||||
#define XPAR_EMC_0_MEM0_HIGHADDR 0xE3FFFFFF
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver PLB_SHT1X_IF */
|
||||
#define XPAR_PLB_SHT1X_IF_NUM_INSTANCES 2
|
||||
|
||||
/* Definitions for peripheral PLB_SHT1X_IF_CH1 */
|
||||
#define XPAR_PLB_SHT1X_IF_CH1_DEVICE_ID 0
|
||||
#define XPAR_PLB_SHT1X_IF_CH1_BASEADDR 0xD2200000
|
||||
#define XPAR_PLB_SHT1X_IF_CH1_HIGHADDR 0xD220FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_SHT1X_IF_CH2 */
|
||||
#define XPAR_PLB_SHT1X_IF_CH2_DEVICE_ID 1
|
||||
#define XPAR_PLB_SHT1X_IF_CH2_BASEADDR 0xD2210000
|
||||
#define XPAR_PLB_SHT1X_IF_CH2_HIGHADDR 0xD221FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver UARTLITE */
|
||||
#define XPAR_XUARTLITE_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral RS232 */
|
||||
#define XPAR_RS232_BASEADDR 0xC0000000
|
||||
#define XPAR_RS232_HIGHADDR 0xC000FFFF
|
||||
#define XPAR_RS232_DEVICE_ID 0
|
||||
#define XPAR_RS232_BAUDRATE 115200
|
||||
#define XPAR_RS232_USE_PARITY 0
|
||||
#define XPAR_RS232_ODD_PARITY 0
|
||||
#define XPAR_RS232_DATA_BITS 8
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral RS232 */
|
||||
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_DEVICE_ID
|
||||
#define XPAR_UARTLITE_0_BASEADDR 0xC0000000
|
||||
#define XPAR_UARTLITE_0_HIGHADDR 0xC000FFFF
|
||||
#define XPAR_UARTLITE_0_BAUDRATE 115200
|
||||
#define XPAR_UARTLITE_0_USE_PARITY 0
|
||||
#define XPAR_UARTLITE_0_ODD_PARITY 0
|
||||
#define XPAR_UARTLITE_0_DATA_BITS 8
|
||||
#define XPAR_UARTLITE_0_SIO_CHAN 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SPI */
|
||||
#define XPAR_XSPI_NUM_INSTANCES 2
|
||||
|
||||
/* Definitions for peripheral SPI_FLASH */
|
||||
#define XPAR_SPI_FLASH_DEVICE_ID 0
|
||||
#define XPAR_SPI_FLASH_BASEADDR 0xD2000000
|
||||
#define XPAR_SPI_FLASH_HIGHADDR 0xD200FFFF
|
||||
#define XPAR_SPI_FLASH_FIFO_EXIST 1
|
||||
#define XPAR_SPI_FLASH_SPI_SLAVE_ONLY 0
|
||||
#define XPAR_SPI_FLASH_NUM_SS_BITS 1
|
||||
#define XPAR_SPI_FLASH_NUM_TRANSFER_BITS 8
|
||||
|
||||
|
||||
/* Definitions for peripheral XPS_SPI_FEB_CFG */
|
||||
#define XPAR_XPS_SPI_FEB_CFG_DEVICE_ID 1
|
||||
#define XPAR_XPS_SPI_FEB_CFG_BASEADDR 0xD2010000
|
||||
#define XPAR_XPS_SPI_FEB_CFG_HIGHADDR 0xD201FFFF
|
||||
#define XPAR_XPS_SPI_FEB_CFG_FIFO_EXIST 1
|
||||
#define XPAR_XPS_SPI_FEB_CFG_SPI_SLAVE_ONLY 0
|
||||
#define XPAR_XPS_SPI_FEB_CFG_NUM_SS_BITS 2
|
||||
#define XPAR_XPS_SPI_FEB_CFG_NUM_TRANSFER_BITS 8
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral SPI_FLASH */
|
||||
#define XPAR_SPI_0_DEVICE_ID XPAR_SPI_FLASH_DEVICE_ID
|
||||
#define XPAR_SPI_0_BASEADDR 0xD2000000
|
||||
#define XPAR_SPI_0_HIGHADDR 0xD200FFFF
|
||||
#define XPAR_SPI_0_FIFO_EXIST 1
|
||||
#define XPAR_SPI_0_SPI_SLAVE_ONLY 0
|
||||
#define XPAR_SPI_0_NUM_SS_BITS 1
|
||||
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral XPS_SPI_FEB_CFG */
|
||||
#define XPAR_SPI_1_DEVICE_ID XPAR_XPS_SPI_FEB_CFG_DEVICE_ID
|
||||
#define XPAR_SPI_1_BASEADDR 0xD2010000
|
||||
#define XPAR_SPI_1_HIGHADDR 0xD201FFFF
|
||||
#define XPAR_SPI_1_FIFO_EXIST 1
|
||||
#define XPAR_SPI_1_SPI_SLAVE_ONLY 0
|
||||
#define XPAR_SPI_1_NUM_SS_BITS 2
|
||||
#define XPAR_SPI_1_NUM_TRANSFER_BITS 8
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver LLTEMAC */
|
||||
#define XPAR_XLLTEMAC_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral TEMAC_INST Channel 0 */
|
||||
#define XPAR_TEMAC_INST_CHAN_0_DEVICE_ID 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_BASEADDR 0xC3000000
|
||||
#define XPAR_TEMAC_INST_CHAN_0_HIGHADDR 0xC30FFFFF
|
||||
#define XPAR_TEMAC_INST_CHAN_0_TXCSUM 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_RXCSUM 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_PHY_TYPE 4
|
||||
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TRAN 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TRAN 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TAG 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TAG 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_STRP 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_STRP 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_MCAST_EXTEND 0
|
||||
|
||||
/* Canonical definitions for peripheral TEMAC_INST Channel 0 */
|
||||
#define XPAR_LLTEMAC_0_DEVICE_ID 0
|
||||
#define XPAR_LLTEMAC_0_BASEADDR 0xC3000000
|
||||
#define XPAR_LLTEMAC_0_HIGHADDR 0xC30FFFFF
|
||||
#define XPAR_LLTEMAC_0_TXCSUM 0
|
||||
#define XPAR_LLTEMAC_0_RXCSUM 0
|
||||
#define XPAR_LLTEMAC_0_PHY_TYPE 4
|
||||
#define XPAR_LLTEMAC_0_TXVLAN_TRAN 0
|
||||
#define XPAR_LLTEMAC_0_RXVLAN_TRAN 0
|
||||
#define XPAR_LLTEMAC_0_TXVLAN_TAG 0
|
||||
#define XPAR_LLTEMAC_0_RXVLAN_TAG 0
|
||||
#define XPAR_LLTEMAC_0_TXVLAN_STRP 0
|
||||
#define XPAR_LLTEMAC_0_RXVLAN_STRP 0
|
||||
#define XPAR_LLTEMAC_0_MCAST_EXTEND 0
|
||||
#define XPAR_LLTEMAC_0_INTR 1
|
||||
|
||||
|
||||
/* LocalLink TYPE Enumerations */
|
||||
#define XPAR_LL_FIFO 1
|
||||
#define XPAR_LL_DMA 2
|
||||
|
||||
|
||||
/* Canonical LocalLink parameters for TEMAC_INST */
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral XPS_BRAM_IF_CNTLR_PPC440 */
|
||||
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_BASEADDR 0xFFFC0000
|
||||
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_HIGHADDR 0xFFFFFFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 5
|
||||
#define XPAR_XINTC_HAS_IPR 1
|
||||
#define XPAR_XINTC_USE_DCR 0
|
||||
/* Definitions for driver INTC */
|
||||
#define XPAR_XINTC_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral XPS_INTC_PPC440 */
|
||||
#define XPAR_XPS_INTC_PPC440_DEVICE_ID 0
|
||||
#define XPAR_XPS_INTC_PPC440_BASEADDR 0xC1000000
|
||||
#define XPAR_XPS_INTC_PPC440_HIGHADDR 0xC100FFFF
|
||||
#define XPAR_XPS_INTC_PPC440_KIND_OF_INTR 0xFFFFFFF4
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
#define XPAR_INTC_SINGLE_BASEADDR 0xC1000000
|
||||
#define XPAR_INTC_SINGLE_HIGHADDR 0xC100FFFF
|
||||
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
|
||||
#define XPAR_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_MASK 0X000001
|
||||
#define XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR 0
|
||||
#define XPAR_TEMAC_INST_TEMACINTC0_IRPT_MASK 0X000002
|
||||
#define XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR 1
|
||||
#define XPAR_XPS_TIMER_PPC440_INTERRUPT_MASK 0X000004
|
||||
#define XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR 2
|
||||
#define XPAR_SPI_FLASH_IP2INTC_IRPT_MASK 0X000008
|
||||
#define XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR 3
|
||||
#define XPAR_RS232_INTERRUPT_MASK 0X000010
|
||||
#define XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR 4
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral XPS_INTC_PPC440 */
|
||||
#define XPAR_INTC_0_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
|
||||
#define XPAR_INTC_0_BASEADDR 0xC1000000
|
||||
#define XPAR_INTC_0_HIGHADDR 0xC100FFFF
|
||||
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFF4
|
||||
|
||||
#define XPAR_INTC_0_LLFIFO_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
|
||||
#define XPAR_INTC_0_LLTEMAC_0_VEC_ID XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
|
||||
#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
|
||||
#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
|
||||
#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver LLFIFO */
|
||||
#define XPAR_XLLFIFO_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral XPS_LL_FIFO_TEMAC */
|
||||
#define XPAR_XPS_LL_FIFO_TEMAC_DEVICE_ID 0
|
||||
#define XPAR_XPS_LL_FIFO_TEMAC_BASEADDR 0xC4000000
|
||||
#define XPAR_XPS_LL_FIFO_TEMAC_HIGHADDR 0xC400FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral XPS_LL_FIFO_TEMAC */
|
||||
#define XPAR_LLFIFO_0_DEVICE_ID XPAR_XPS_LL_FIFO_TEMAC_DEVICE_ID
|
||||
#define XPAR_LLFIFO_0_BASEADDR 0xC4000000
|
||||
#define XPAR_LLFIFO_0_HIGHADDR 0xC400FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SYSMON */
|
||||
#define XPAR_XSYSMON_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral XPS_SYSMON_ADC_PPC440 */
|
||||
#define XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID 0
|
||||
#define XPAR_XPS_SYSMON_ADC_PPC440_BASEADDR 0xD0010000
|
||||
#define XPAR_XPS_SYSMON_ADC_PPC440_HIGHADDR 0xD001FFFF
|
||||
#define XPAR_XPS_SYSMON_ADC_PPC440_INCLUDE_INTR 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral XPS_SYSMON_ADC_PPC440 */
|
||||
#define XPAR_SYSMON_0_DEVICE_ID XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID
|
||||
#define XPAR_SYSMON_0_BASEADDR 0xD0010000
|
||||
#define XPAR_SYSMON_0_HIGHADDR 0xD001FFFF
|
||||
#define XPAR_SYSMON_0_INCLUDE_INTR 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver TMRCTR */
|
||||
#define XPAR_XTMRCTR_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral XPS_TIMER_PPC440 */
|
||||
#define XPAR_XPS_TIMER_PPC440_DEVICE_ID 0
|
||||
#define XPAR_XPS_TIMER_PPC440_BASEADDR 0xC2000000
|
||||
#define XPAR_XPS_TIMER_PPC440_HIGHADDR 0xC200FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral XPS_TIMER_PPC440 */
|
||||
#define XPAR_TMRCTR_0_DEVICE_ID XPAR_XPS_TIMER_PPC440_DEVICE_ID
|
||||
#define XPAR_TMRCTR_0_BASEADDR 0xC2000000
|
||||
#define XPAR_TMRCTR_0_HIGHADDR 0xC200FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for bus frequencies */
|
||||
#define XPAR_CPU_PPC440_MPLB_FREQ_HZ 100000000
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for bus frequencies */
|
||||
#define XPAR_PROC_BUS_0_FREQ_HZ 100000000
|
||||
/******************************************************************/
|
||||
|
||||
#define XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ 400000000
|
||||
#define XPAR_PPC440_VIRTEX5_CORE_CLOCK_FREQ_HZ 400000000
|
||||
#define XPAR_CPU_PPC440_IDCR_BASEADDR 0x00000000
|
||||
/******************************************************************/
|
||||
#define XPAR_CPU_ID 0
|
||||
#define XPAR_PPC440_VIRTEX5_ID 0
|
||||
#define XPAR_PPC440_VIRTEX5_PIR 0b1111
|
||||
#define XPAR_PPC440_VIRTEX5_ENDIAN_RESET 0
|
||||
#define XPAR_PPC440_VIRTEX5_USER_RESET 0b0000
|
||||
#define XPAR_PPC440_VIRTEX5_INTERCONNECT_IMASK 0xffffffff
|
||||
#define XPAR_PPC440_VIRTEX5_ICU_RD_FETCH_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_ICU_RD_SPEC_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_ICU_RD_TOUCH_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_RD_LD_CACHE_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_RD_NONCACHE_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_RD_TOUCH_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_RD_URGENT_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_WR_FLUSH_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_WR_STORE_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_WR_URGENT_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_IDCR_BASEADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_IDCR_HIGHADDR 0x000000FF
|
||||
#define XPAR_PPC440_VIRTEX5_APU_CONTROL 0b00010000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_0 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_1 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_2 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_3 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_4 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_5 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_6 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_7 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_8 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_9 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_10 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_11 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_12 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_13 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_14 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_15 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_BASE 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_HIGH 0X01FFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_ROW_CONFLICT_MASK 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_BANK_CONFLICT_MASK 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_CONTROL 0X8140008F
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_ICU 4
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUW 3
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUR 2
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB1 0
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB0 1
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_ARB_MODE 0
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_MAX_BURST 8
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_AWIDTH 32
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_NATIVE_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_COUNTER 0x00000500
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_ICU 4
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUW 3
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUR 2
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB1 0
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB0 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_ARB_MODE 0
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_SYNC_TATTRIBUTE 0
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_MAX_BURST 8
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_ALLOW_LOCK_XFER 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_READ_PIPE_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_PIPE_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_POST_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_P2P 0
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_WDOG_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_AWIDTH 32
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_NATIVE_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_SUPPORT_BURSTS 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_USE_MPLB_ADDR 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MPLB_ADDR_RNG 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MASTERS 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_MID_WIDTH 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_ALLOW_LOCK_XFER 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_READ_PIPE_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_PROPAGATE_MIRQ 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_P2P -1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_AWIDTH 32
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_NATIVE_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_SUPPORT_BURSTS 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_USE_MPLB_ADDR 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MPLB_ADDR_RNG 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MASTERS 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_MID_WIDTH 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_ALLOW_LOCK_XFER 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_READ_PIPE_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_PROPAGATE_MIRQ 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_P2P -1
|
||||
#define XPAR_PPC440_VIRTEX5_NUM_DMA 0
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_TXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_RXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_CONTROL 0b00000000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_TXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_RXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_TXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_RXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_CONTROL 0b00000000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_TXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_RXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_TXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_RXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_CONTROL 0b00000000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_TXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_RXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_TXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_RXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_CONTROL 0b00000000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_TXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_RXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DCR_AUTOLOCK_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_PPCDM_ASYNCMODE 0
|
||||
#define XPAR_PPC440_VIRTEX5_PPCDS_ASYNCMODE 0
|
||||
#define XPAR_PPC440_VIRTEX5_GENERATE_PLB_TIMESPECS 1
|
||||
#define XPAR_PPC440_VIRTEX5_HW_VER "1.01.a"
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
Reference in New Issue
Block a user