mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 01:58:00 +02:00
client: removed slsDetectorutils and postprocessing. yet to compile, yet to add detpos index for every multi sls detector command and call from command interface, removed multiple threading, yet to interface with eriks single template for multiple threading
This commit is contained in:
@ -0,0 +1,210 @@
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#include "ansi.h"
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#include <termios.h> /* POSIX terminal control definitions */
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#include <stdio.h>
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#include <stdlib.h> // atoi
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#include <fcntl.h> // File control definitions
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#include <sys/ioctl.h> // ioctl
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#include <unistd.h> // read, close
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#include <string.h> // memset
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#include <linux/i2c-dev.h> // I2C_SLAVE, __u8 reg
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#include <errno.h>
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#define PORTNAME "/dev/ttyBF1"
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#define GOODBYE 200
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#define BUFFERSIZE 16
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#define I2C_DEVICE_FILE "/dev/i2c-0"
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#define I2C_DEVICE_ADDRESS 0x4C
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//#define I2C_DEVICE_ADDRESS 0x48
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#define I2C_REGISTER_ADDRESS 0x40
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int i2c_open(const char* file,unsigned int addr){
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//device file
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int fd = open( file, O_RDWR );
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if (fd < 0) {
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cprintf(RED,"Warning: Unable to open file %s\n",file);
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return -1;
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}
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//device address
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if( ioctl( fd, I2C_SLAVE, addr&0x7F ) < 0 ) {
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cprintf(RED,"Warning: Unable to set slave address:0x%x \n",addr);
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return -2;
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}
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return fd;
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}
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int i2c_read(){
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int fd = i2c_open(I2C_DEVICE_FILE, I2C_DEVICE_ADDRESS);
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__u8 reg = I2C_REGISTER_ADDRESS & 0xff;
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unsigned char buf = reg;
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if (write(fd, &buf, 1)!= 1){
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cprintf(RED,"Warning: Unable to write read request to register %d\n", reg);
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return -1;
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}
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//read and update value (but old value read out)
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if(read(fd, &buf, 1) != 1){
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cprintf(RED,"Warning: Unable to read register %d\n", reg);
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return -2;
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}
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//read again to read the updated value
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if(read(fd, &buf, 1) != 1){
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cprintf(RED,"Warning: Unable to read register %d\n", reg);
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return -2;
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}
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close(fd);
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return buf;
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}
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int i2c_write(unsigned int value){
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__u8 val = value & 0xff;
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int fd = i2c_open(I2C_DEVICE_FILE, I2C_DEVICE_ADDRESS);
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if(fd < 0)
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return fd;
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__u8 reg = I2C_REGISTER_ADDRESS & 0xff;
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char buf[3];
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buf[0] = reg;
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buf[1] = val;
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if (write(fd, buf, 2) != 2) {
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cprintf(RED,"Warning: Unable to write %d to register %d\n",val, reg);
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return -1;
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}
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close(fd);
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return 0;
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}
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int main(int argc, char* argv[]) {
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int fd = open(PORTNAME, O_RDWR | O_NOCTTY | O_SYNC);
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if(fd < 0){
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cprintf(RED,"Warning: Unable to open port %s\n", PORTNAME);
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return -1;
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}
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cprintf(GREEN,"opened port at %s\n",PORTNAME);
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struct termios serial_conf;
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// reset structure
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memset(&serial_conf,0,sizeof(serial_conf));
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// control options
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serial_conf.c_cflag = B2400 | CS8 | CREAD | CLOCAL;
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// input options
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serial_conf.c_iflag = IGNPAR;
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// output options
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serial_conf.c_oflag = 0;
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// line options
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serial_conf.c_lflag = ICANON;
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// flush input
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if(tcflush(fd, TCIOFLUSH) < 0){
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cprintf(RED,"Warning: error form tcflush %d\n", errno);
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return 0;
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}
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// set new options for the port, TCSANOW:changes occur immediately without waiting for data to complete
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if(tcsetattr(fd, TCSANOW, &serial_conf) < 0){
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cprintf(RED,"Warning: error form tcsetattr %d\n", errno);
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return 0;
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}
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if(tcsetattr(fd, TCSAFLUSH, &serial_conf) < 0){
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cprintf(RED,"Warning: error form tcsetattr %d\n", errno);
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return 0;
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}
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int ret = 0;
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int n = 0;
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int ival= 0;
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char buffer[BUFFERSIZE];
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memset(buffer,0,BUFFERSIZE);
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buffer[BUFFERSIZE-1] = '\n';
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cprintf(GREEN,"Ready...\n");
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while(ret != GOODBYE){
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memset(buffer,0,BUFFERSIZE);
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n = read(fd,buffer,BUFFERSIZE);
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#ifdef VERBOSE
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cprintf(BLUE,"Received %d Bytes\n", n);
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#endif
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cprintf(BLUE,"Got message: '%s'\n",buffer);
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switch(buffer[0]){
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case '\0':
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cprintf(GREEN,"Got Start (Detector restart)\n");
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break;
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case 's':
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cprintf(GREEN,"Got Start \n");
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break;
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case 'p':
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if (!sscanf(&buffer[1],"%d",&ival)){
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cprintf(RED,"Warning: cannot scan voltage value\n");
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break;
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}
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// ok/ fail
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memset(buffer,0,BUFFERSIZE);
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buffer[BUFFERSIZE-1] = '\n';
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if(i2c_write(ival)<0)
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strcpy(buffer,"fail ");
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else
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strcpy(buffer,"success ");
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cprintf(GREEN,"Sending: '%s'\n",buffer);
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n = write(fd, buffer, BUFFERSIZE);
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#ifdef VERBOSE
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cprintf(GREEN,"Sent %d Bytes\n", n);
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#endif
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break;
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case 'g':
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ival = i2c_read();
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//ok/ fail
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memset(buffer,0,BUFFERSIZE);
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buffer[BUFFERSIZE-1] = '\n';
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if(ival < 0)
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strcpy(buffer,"fail ");
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else
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strcpy(buffer,"success ");
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n = write(fd, buffer, BUFFERSIZE);
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cprintf(GREEN,"Sending: '%s'\n",buffer);
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#ifdef VERBOSE
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cprintf(GREEN,"Sent %d Bytes\n", n);
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#endif
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//value
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memset(buffer,0,BUFFERSIZE);
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buffer[BUFFERSIZE-1] = '\n';
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if(ival >= 0){
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cprintf(GREEN,"Sending: '%d'\n",ival);
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sprintf(buffer,"%d ",ival);
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n = write(fd, buffer, BUFFERSIZE);
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#ifdef VERBOSE
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cprintf(GREEN,"Sent %d Bytes\n", n);
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#endif
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}else cprintf(RED,"%s\n",buffer);
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break;
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case 'e':
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printf("Exiting Program\n");
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ret = GOODBYE;
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break;
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default:
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cprintf(RED,"Unknown Command. buffer:'%s'\n",buffer);
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break;
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}
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}
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close(fd);
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printf("Goodbye Serial Communication for HV(9M)\n");
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return 0;
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}
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1346
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Beb.c
Normal file
1346
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Beb.c
Normal file
File diff suppressed because it is too large
Load Diff
103
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Beb.h
Normal file
103
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Beb.h
Normal file
@ -0,0 +1,103 @@
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/**
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* @author Ian Johnson
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* @version 1.0
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*/
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#ifndef BEB_H
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#define BEB_H
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#include "LocalLinkInterface.h"
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#include "slsDetectorServer_defs.h"
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struct BebInfo{
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unsigned int beb_number;
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unsigned int serial_address;
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char src_mac_1GbE[50];
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char src_mac_10GbE[50];
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char src_ip_1GbE[50];
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char src_ip_10GbE[50];
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unsigned int src_port_1GbE;
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unsigned int src_port_10GbE;
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};
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void BebInfo_BebInfo(struct BebInfo* bebInfo, unsigned int beb_num);
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void BebInfo_BebDstInfo(struct BebInfo* bebInfo, unsigned int beb_num);
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int BebInfo_SetSerialAddress(struct BebInfo* bebInfo, unsigned int add);
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int BebInfo_SetHeaderInfo(struct BebInfo* bebInfo, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);//src_port fixed 42000+beb_number or 52000 + beb_number);
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unsigned int BebInfo_GetBebNumber(struct BebInfo* bebInfo);
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unsigned int BebInfo_GetSerialAddress(struct BebInfo* bebInfo);
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char* BebInfo_GetSrcMAC(struct BebInfo* bebInfo, int ten_gig);
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char* BebInfo_GetSrcIP(struct BebInfo* bebInfo, int ten_gig);
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unsigned int BebInfo_GetSrcPort(struct BebInfo* bebInfo, int ten_gig);
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void BebInfo_Print(struct BebInfo* bebInfo);
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void Beb_ClearBebInfos();
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int Beb_InitBebInfos();
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int Beb_CheckSourceStuffBebInfo();
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unsigned int Beb_GetBebInfoIndex(unsigned int beb_numb);
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void Beb_GetModuleConfiguration(int* master, int* top, int* normal);
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void Beb_EndofDataSend(int tengiga);
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int Beb_SetMasterViaSoftware();
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int Beb_SetSlaveViaSoftware();
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int Beb_Activate(int enable);
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int Beb_Set32bitOverflow(int val);
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int Beb_SetNetworkParameter(enum NETWORKINDEX mode, int val);
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int Beb_ResetToHardwareSettings();
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u_int32_t Beb_GetFirmwareRevision();
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u_int32_t Beb_GetFirmwareSoftwareAPIVersion();
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void Beb_ResetFrameNumber();
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int Beb_WriteTo(unsigned int index);
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int Beb_SetMAC(char* mac, uint8_t* dst_ptr);
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int Beb_SetIP(char* ip, uint8_t* dst_ptr);
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int Beb_SetPortNumber(unsigned int port_number, uint8_t* dst_ptr);
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void Beb_AdjustIPChecksum(struct udp_header_type *ip);
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int Beb_SetHeaderData(unsigned int beb_number, int ten_gig, char* dst_mac, char* dst_ip, unsigned int dst_port);
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int Beb_SetHeaderData1(char* src_mac, char* src_ip, unsigned int src_port, char* dst_mac, char* dst_ip, unsigned int dst_port);
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void Beb_SwapDataFun(int little_endian, unsigned int n, unsigned int *d);
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int Beb_SetByteOrder();
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void Beb_Beb();
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int Beb_SetBebSrcHeaderInfos(unsigned int beb_number, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);
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int Beb_SetUpUDPHeader(unsigned int beb_number, int ten_gig, unsigned int header_number, char* dst_mac, char* dst_ip, unsigned int dst_port);
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/*int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty=1);*/
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int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty);
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int Beb_StopAcquisition();
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int Beb_SetUpTransferParameters(short the_bit_mode);
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/*int Beb_RequestNImages(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait=0); //all images go to the same destination!*/
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int Beb_RequestNImages(unsigned int beb_number, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait);
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int Beb_Test(unsigned int beb_number);
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int Beb_GetBebFPGATemp();
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void Beb_SetDetectorNumber(uint32_t detid);
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int Beb_SetDetectorPosition(int pos[]);
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uint16_t Beb_swap_uint16( uint16_t val);
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int Beb_open(u_int32_t** csp0base, u_int32_t offset);
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u_int32_t Beb_Read32 (u_int32_t* baseaddr, u_int32_t offset);
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u_int32_t Beb_Write32 (u_int32_t* baseaddr, u_int32_t offset, u_int32_t data);
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void Beb_close(int fd,u_int32_t* csp0base);
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#endif
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335
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Feb.c
Normal file
335
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Feb.c
Normal file
@ -0,0 +1,335 @@
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/**
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* @author Ian Johnson
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* @version 1.0
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*/
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|
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/*#include <iostream>
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#include <iomanip>*/
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#include <stdio.h>
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#include <stdlib.h>
|
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#include <unistd.h>
|
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#include "xparameters.h"
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#include "Feb.h"
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void Feb_Feb(){
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Feb_nfebs = 0;
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Feb_feb_numb = 0;
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Feb_send_ndata = 0;
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Feb_send_buffer_size = 1026;
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Feb_send_data_raw = malloc((Feb_send_buffer_size+1)*sizeof(int));
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Feb_send_data = &Feb_send_data_raw[1];
|
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|
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Feb_recv_ndata = 0;
|
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Feb_recv_buffer_size = 1026;
|
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Feb_recv_data_raw = malloc((Feb_recv_buffer_size+1)*sizeof(int));
|
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Feb_recv_data = &Feb_recv_data_raw[1];
|
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|
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Local_LocalLinkInterface1(ll,XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR);
|
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|
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}
|
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/*
|
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~Feb(){
|
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delete ll;
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if(feb_numb) delete [] feb_numb;
|
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delete [] send_data_raw;
|
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delete [] recv_data_raw;
|
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}
|
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*/
|
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|
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void Feb_SendCompleteFebList(unsigned int n,unsigned int* list){
|
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unsigned int i;
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if(Feb_feb_numb) free(Feb_feb_numb);
|
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Feb_nfebs = n;
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Feb_feb_numb = malloc(n*sizeof(unsigned int));
|
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for(i=0;i<n;i++) Feb_feb_numb[i] = list[i];
|
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}
|
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|
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int Feb_WriteTo(unsigned int ch){
|
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if(ch>0xfff) return 0;
|
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|
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Feb_send_data_raw[0] = 0x90000000 | (ch<<16); //we
|
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if(Local_Write(ll,4,Feb_send_data_raw)!=4) return 0;
|
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|
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Feb_send_data_raw[0] = 0xc0000000; //data
|
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return 1;//((Feb_send_ndata+1)*4==Local_Write(ll,(Feb_send_ndata+1)*4,Feb_send_data_raw));
|
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}
|
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|
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int Feb_ReadFrom(unsigned int ch, unsigned int ntrys){
|
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unsigned int t;
|
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if(ch>=0xfff) return 0;
|
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|
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Feb_recv_data_raw[0] = 0xa0000000 | (ch<<16); //read data
|
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Local_Write(ll,4,Feb_recv_data_raw);
|
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usleep(20);
|
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|
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Feb_recv_ndata=-1;
|
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for(t=0;t<ntrys;t++){
|
||||
if((Feb_recv_ndata=Local_Read(ll,Feb_recv_buffer_size*4,Feb_recv_data_raw)/4)>0){
|
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Feb_recv_ndata--;
|
||||
break;
|
||||
}
|
||||
printf("\t Read try number: %d\n",t);
|
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usleep(1000);
|
||||
}
|
||||
|
||||
|
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return (Feb_recv_ndata>=0);
|
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}
|
||||
|
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void Feb_PrintData(){
|
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int i;
|
||||
printf("Sent data: %d\n",Feb_send_ndata);
|
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for(i=0;i<Feb_send_ndata;i++) printf("\t%d)%d (0x%x)\n",i,Feb_send_data[i],Feb_send_data[i]);
|
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printf("Receive data: %d\n",Feb_recv_ndata);
|
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for(i=0;i<Feb_recv_ndata;i++) printf("\t%d)%d (0x%x)\n",i,Feb_recv_data[i],Feb_recv_data[i]);
|
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printf("\n\n");
|
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}
|
||||
|
||||
|
||||
int Feb_CheckHeader(unsigned int valid_bit_mask, int print_error_info){
|
||||
|
||||
int header_returned_is_ok = (Feb_send_data[0] & valid_bit_mask)==(Feb_recv_data[0] & valid_bit_mask);
|
||||
|
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if(print_error_info && !header_returned_is_ok){
|
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printf("Error: Command received not the same as command recieved.\n");
|
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printf("\t\t Header sent: %d (0x%x) received: %d (0x%x)\n",Feb_send_data[0], Feb_send_data[0], Feb_recv_data[0], Feb_recv_data[0]);
|
||||
if(Feb_send_ndata>1&&Feb_recv_ndata>1){
|
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printf("\t\t Tail sent: %d (0x%x) receiver: %d (0x%x)\n",Feb_send_data[Feb_send_ndata-1],Feb_send_data[Feb_send_ndata-1],Feb_recv_data[Feb_recv_ndata-1],Feb_recv_data[Feb_recv_ndata-1]);
|
||||
}else{
|
||||
printf("Error printing tail, too little data nsent = 0x%x, nrecv = 0x%x.\n",Feb_send_ndata, Feb_recv_ndata);
|
||||
}
|
||||
Feb_PrintData();
|
||||
}
|
||||
return header_returned_is_ok;
|
||||
}
|
||||
|
||||
|
||||
int Feb_CheckTail(unsigned int valid_bit_mask){
|
||||
if(Feb_send_ndata<=1&&Feb_recv_ndata<=1){
|
||||
printf("Error checking tail, too little data nsent = %d, nrecv = %d.\n",Feb_send_ndata, Feb_recv_ndata);
|
||||
return 0;
|
||||
}
|
||||
|
||||
unsigned int the_tail = Feb_recv_data[Feb_recv_ndata-1]&valid_bit_mask;
|
||||
if(the_tail!=0){
|
||||
printf("Error returned in tail: 0x%x (%d)\n",the_tail,the_tail);
|
||||
if(the_tail&0x10000000) printf("\t\tBusy flag address error.\n");
|
||||
if(the_tail&0x20000000) printf("\t\tRead register address error.\n");
|
||||
if(the_tail&0x40000000) printf("\t\tWrite register address error.\n");
|
||||
if(the_tail&0x80000000) printf("\t\tBram number error.\n");
|
||||
if(the_tail&0x08000000) printf("\t\tFifo to read from error.\n");
|
||||
if(the_tail&0x3ff) printf("\t\tNumber of data send error.\n");
|
||||
return 0; //error
|
||||
}
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int Feb_CheckCommunication(){
|
||||
Feb_send_data_raw[0] = 0x8fff0000; //rst-all serial coms and lls
|
||||
if(Local_Write(ll,4,Feb_send_data_raw)!=4) return 0;
|
||||
|
||||
printf("CheckingCommunication ....\n");
|
||||
while((Local_Read(ll,Feb_recv_buffer_size*4,Feb_recv_data_raw)/4)>0) printf("\t) Cleanning buffer ...\n");
|
||||
|
||||
return Feb_SetByteOrder();
|
||||
}
|
||||
|
||||
|
||||
int Feb_SetByteOrder(){
|
||||
|
||||
unsigned int i;
|
||||
Feb_send_ndata = 2;
|
||||
Feb_send_data[0] = 0; //header
|
||||
Feb_send_data[1] = 0; //tail
|
||||
|
||||
unsigned int dst = 0xff;
|
||||
for( i=0;i<Feb_nfebs;i++) dst = (dst | Feb_feb_numb[i]); //get sub dst bits (left right in this case)
|
||||
int passed = Feb_WriteTo(dst);
|
||||
|
||||
for(i=0;i<Feb_nfebs;i++){
|
||||
printf("\t%d) Set Byte Order .............. ",i);
|
||||
unsigned int current_passed = Feb_ReadFrom(Feb_feb_numb[i],20)&&(Feb_recv_ndata==2)&&Feb_CheckHeader(0xffffffff,1);
|
||||
if(current_passed) printf("passed.\n");
|
||||
else printf("failed.\n");
|
||||
passed&=current_passed;
|
||||
}
|
||||
printf("\n");
|
||||
|
||||
return passed;
|
||||
}
|
||||
|
||||
/* feb_ needed
|
||||
int Feb_CheckSubNumber(unsigned int Feb_sub_num){
|
||||
if(sub_num>=nfebs){
|
||||
cout<<"Error invalid sub number "<<sub_num<<" must be less than "<<nfebs<<"."<<endl;
|
||||
return 0;
|
||||
}
|
||||
return 1;
|
||||
}
|
||||
|
||||
int Feb_SetStartOnEndOnFebs(int sub_num_s, unsigned int& start_on, unsigned int& end_on){
|
||||
// -1 means write to all
|
||||
|
||||
if(sub_num_s<=-2){
|
||||
cout<<"Error bad subnumber "<<sub_num_s<<"."<<endl;
|
||||
return 0;
|
||||
}
|
||||
|
||||
start_on = sub_num_s!=-1 ? sub_num_s : 0;
|
||||
end_on = sub_num_s!=-1 ? sub_num_s : nfebs - 1;
|
||||
|
||||
return Feb_CheckSubNumber(start_on);
|
||||
}
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
int Feb_ReadRegister(unsigned int Feb_sub_num, unsigned int Feb_reg_num,unsigned int& Feb_value_read){
|
||||
return Feb_ReadRegisters(Feb_sub_num,1,&Feb_reg_num,&Feb_value_read);
|
||||
}
|
||||
*/
|
||||
int Feb_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read){
|
||||
return Feb_ReadRegisters(sub_num,1,®_num,value_read);
|
||||
}
|
||||
|
||||
int Feb_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read){
|
||||
//here cout<<"Reading Register ...."<<endl;
|
||||
unsigned int i;
|
||||
nreads &= 0x3ff; //10 bits
|
||||
if(!nreads||nreads>Feb_send_buffer_size-2) return 0;
|
||||
|
||||
Feb_send_ndata = nreads+2;
|
||||
Feb_send_data[0] = 0x20000000 | nreads << 14; //cmd -> read "00" , nreads
|
||||
|
||||
for(i=0;i<nreads;i++) Feb_send_data[i+1]=reg_nums[i];
|
||||
Feb_send_data[nreads+1] = 0; //tail
|
||||
|
||||
if(!Feb_WriteTo(sub_num)||!Feb_ReadFrom(sub_num,20)||Feb_recv_ndata!=(int)(nreads+2)||!Feb_CheckHeader(0xffffffff,1)||!Feb_CheckTail(0xffffffff)){
|
||||
Feb_PrintData();
|
||||
printf("Error reading register.\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
for(i=0;i<nreads;i++) values_read[i] = Feb_recv_data[i+1];
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int Feb_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address){
|
||||
return Feb_WriteRegisters(sub_num,1,®_num,&value,&wait_on,&wait_on_address);
|
||||
}
|
||||
|
||||
int Feb_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses){
|
||||
unsigned int i;
|
||||
// sub_num == 0xfff means write to all
|
||||
|
||||
nwrites &= 0x3ff; //10 bits
|
||||
if(!nwrites||nwrites>Feb_send_buffer_size-2) return 0;
|
||||
|
||||
//cout<<"Write register : "<<this<<" "<<s_num<<" "<<nwrites<<" "<<reg_nums<<" "<<values<<" "<<wait_ons<<" "<<wait_on_addresses<<endl;
|
||||
Feb_send_ndata = 2*nwrites+2;
|
||||
Feb_send_data[0] = 0x80000000 | nwrites << 14; //cmd -> write nwrites and how many
|
||||
Feb_send_data[2*nwrites+1] = 0; //tail
|
||||
|
||||
for(i=0;i<nwrites;i++) Feb_send_data[2*i+1] = 0x3fff®_nums[i]; // register address data_in(13 downto 0)
|
||||
for(i=0;i<nwrites;i++) Feb_send_data[2*i+2] = values[i]; // value is data_in(31 downto 0)
|
||||
// wait on busy data(28), address of busy flag data(27 downto 14)
|
||||
if(wait_ons&&wait_on_addresses) for(i=0;i<nwrites;i++) Feb_send_data[2*i+1] |= (wait_ons[i]<<28 | (0x3fff&wait_on_addresses[i])<<14);
|
||||
|
||||
if(!Feb_WriteTo(sub_num)){
|
||||
printf("%d) Error writing register(s).\n",sub_num);
|
||||
Feb_PrintData();
|
||||
return 0;
|
||||
}
|
||||
|
||||
int passed = 1;
|
||||
unsigned int n = (sub_num&0xff)==0xff ? Feb_nfebs : 1;
|
||||
unsigned int* nums = (sub_num&0xff)==0xff ? Feb_feb_numb : &sub_num;
|
||||
for(i=0;i<n;i++){
|
||||
if((sub_num&0xf00&(nums[i]))==0) continue;
|
||||
if(!Feb_ReadFrom(nums[i],20)||Feb_recv_ndata!=2||!Feb_CheckHeader(0xffffffff,1)){
|
||||
printf("%d) Error writing register(s) response.\n",nums[i]);
|
||||
Feb_PrintData();
|
||||
passed = 0;
|
||||
}else{
|
||||
passed = passed && Feb_CheckTail(0xffffffff);
|
||||
}
|
||||
}
|
||||
|
||||
return passed;
|
||||
}
|
||||
|
||||
|
||||
int Feb_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values){
|
||||
// -1 means write to all
|
||||
unsigned int i;
|
||||
mem_num &= 0x3f; //6 bits
|
||||
start_address &= 0x3fff; //14 bits
|
||||
nwrites &= 0x3ff; //10 bits
|
||||
if(!nwrites||nwrites>Feb_send_buffer_size-2) return 0;
|
||||
|
||||
Feb_send_ndata = nwrites+2;
|
||||
Feb_send_data[0] = 0xc0000000 | mem_num << 24 | nwrites << 14 | start_address; //cmd -> write to memory, nwrites, mem number, start address
|
||||
Feb_send_data[nwrites+1] = 0; //tail
|
||||
for(i=0;i<nwrites;i++) Feb_send_data[i+1] = values[i];
|
||||
|
||||
|
||||
if(!Feb_WriteTo(sub_num)){
|
||||
printf("%d) Error writing memory.\n",sub_num);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int passed = 1;
|
||||
unsigned int n = (sub_num&0xff)==0xff ? Feb_nfebs : 1;
|
||||
unsigned int* nums = (sub_num&0xff)==0xff ? Feb_feb_numb : &sub_num;
|
||||
for(i=0;i<n;i++){
|
||||
if((sub_num&0xf00&(nums[i]))==0) continue;
|
||||
if(!Feb_ReadFrom(nums[i],20)||Feb_recv_ndata!=2||!Feb_CheckHeader(0xffffffff,1)){
|
||||
printf("%d) Error writing memory response. \n",nums[i]);
|
||||
Feb_PrintData();
|
||||
passed = 0;
|
||||
}else{
|
||||
passed = passed && Feb_CheckTail(0xffffffff);
|
||||
}
|
||||
}
|
||||
// unsigned int n = sub_num==0xfff ? nfebs : 1;
|
||||
// unsigned int* nums = sub_num==0xfff ? feb_numb : &sub_num;
|
||||
// for(unsigned int i=0;i<n;i++){
|
||||
|
||||
return passed;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int Feb_Test(){//int sub_num_s, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values){
|
||||
// -1 means write to all
|
||||
unsigned int i;
|
||||
unsigned int reg_nums[10]={0,1,2,3,1,2,3,1,2,3};
|
||||
|
||||
printf("Test\n\n\n\n");
|
||||
|
||||
unsigned int value = 0;
|
||||
for(i=0;i<10;i++){
|
||||
Feb_WriteRegister(0xfff,reg_nums[i%10],i,0,0);
|
||||
Feb_ReadRegister(256,reg_nums[i%10],&value);
|
||||
printf("%d %d\n",i,value);
|
||||
Feb_ReadRegister(512,reg_nums[i%10],&value);
|
||||
printf("%d %d\n",i,value);
|
||||
Feb_WriteMemory(0xfff,0,0,10,reg_nums);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -0,0 +1,59 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FEB_H
|
||||
#define FEB_H
|
||||
|
||||
#include "LocalLinkInterface.h"
|
||||
|
||||
|
||||
struct LocalLinkInterface* ll;
|
||||
|
||||
unsigned int Feb_nfebs;
|
||||
unsigned int* Feb_feb_numb;
|
||||
|
||||
int Feb_send_ndata;
|
||||
unsigned int Feb_send_buffer_size;
|
||||
unsigned int* Feb_send_data_raw;
|
||||
unsigned int* Feb_send_data;
|
||||
|
||||
int Feb_recv_ndata;
|
||||
unsigned int Feb_recv_buffer_size;
|
||||
unsigned int* Feb_recv_data_raw;
|
||||
unsigned int* Feb_recv_data;
|
||||
|
||||
int Feb_WriteTo(unsigned int ch);
|
||||
/*int Feb_ReadFrom(unsigned int Feb_ch, unsigned int Feb_ntrys=20);*/
|
||||
int Feb_ReadFrom(unsigned int ch, unsigned int ntrys);
|
||||
/* int Feb_CheckHeader(unsigned int Feb_valid_bit_mask=0xffffffff, int Feb_print_error_info=1);*/
|
||||
int Feb_CheckHeader(unsigned int valid_bit_mask, int print_error_info);
|
||||
/*int Feb_CheckTail(unsigned int Feb_valid_bit_mask=0xffffffff);*/
|
||||
int Feb_CheckTail(unsigned int valid_bit_mask);
|
||||
|
||||
int Feb_SetByteOrder();
|
||||
//int Feb_CheckSubNumber(unsigned int Feb_sub_num);
|
||||
//int Feb_SetStartOnEndOnFebs(int Feb_sub_num_s, unsigned int& Feb_start_on, unsigned int& Feb_end_on);
|
||||
void Feb_PrintData();
|
||||
|
||||
|
||||
void Feb_Feb();
|
||||
/*virtual ~Feb();*/
|
||||
void Feb_SendCompleteFebList(unsigned int n,unsigned int* list);
|
||||
int Feb_CheckCommunication();
|
||||
/*int Feb_ReadRegister(unsigned int Feb_sub_num, unsigned int Feb_reg_num,unsigned int& Feb_value_read);*/
|
||||
int Feb_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read);
|
||||
int Feb_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read);
|
||||
/*int WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on=0, unsigned int wait_on_address=0);*/
|
||||
int Feb_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address);
|
||||
/*int WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons=0, unsigned int* wait_on_addresses=0);*/
|
||||
int Feb_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses);
|
||||
int Feb_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
|
||||
int Feb_Test();
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,210 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FEBCONTROL_H
|
||||
#define FEBCONTROL_H
|
||||
|
||||
#include <netinet/in.h>
|
||||
#include <stdlib.h>
|
||||
//#include <string>
|
||||
//#include <vector>
|
||||
|
||||
|
||||
#include "FebInterface.h"
|
||||
|
||||
|
||||
struct Module{
|
||||
unsigned int module_number;
|
||||
int top_address_valid;
|
||||
unsigned int top_left_address;
|
||||
unsigned int top_right_address;
|
||||
int bottom_address_valid;
|
||||
unsigned int bottom_left_address;
|
||||
unsigned int bottom_right_address;
|
||||
|
||||
unsigned int idelay_top[4]; //ll,lr,rl,ll
|
||||
unsigned int idelay_bottom[4]; //ll,lr,rl,ll
|
||||
float high_voltage;
|
||||
int* top_dac;
|
||||
int* bottom_dac;
|
||||
};
|
||||
|
||||
|
||||
void Module_Module(struct Module* mod,unsigned int number, unsigned int address_top);
|
||||
void Module_ModuleBottom(struct Module* mod,unsigned int number, unsigned int address_bottom);
|
||||
void Module_Module1(struct Module* mod,unsigned int number, unsigned int address_top, unsigned int address_bottom);
|
||||
unsigned int Module_GetModuleNumber(struct Module* mod);
|
||||
int Module_TopAddressIsValid(struct Module* mod);
|
||||
unsigned int Module_GetTopBaseAddress(struct Module* mod);
|
||||
unsigned int Module_GetTopLeftAddress(struct Module* mod) ;
|
||||
unsigned int Module_GetTopRightAddress(struct Module* mod);
|
||||
unsigned int Module_GetBottomBaseAddress(struct Module* mod);
|
||||
int Module_BottomAddressIsValid(struct Module* mod);
|
||||
unsigned int Module_GetBottomLeftAddress(struct Module* mod);
|
||||
unsigned int Module_GetBottomRightAddress(struct Module* mod);
|
||||
unsigned int Module_SetTopIDelay(struct Module* mod,unsigned int chip,unsigned int value);
|
||||
unsigned int Module_GetTopIDelay(struct Module* mod,unsigned int chip) ;
|
||||
unsigned int Module_SetBottomIDelay(struct Module* mod,unsigned int chip,unsigned int value);
|
||||
unsigned int Module_GetBottomIDelay(struct Module* mod,unsigned int chip);
|
||||
|
||||
float Module_SetHighVoltage(struct Module* mod,float value);
|
||||
float Module_GetHighVoltage(struct Module* mod);
|
||||
|
||||
int Module_SetTopDACValue(struct Module* mod,unsigned int i, int value);
|
||||
int Module_GetTopDACValue(struct Module* mod,unsigned int i);
|
||||
int Module_SetBottomDACValue(struct Module* mod,unsigned int i, int value);
|
||||
int Module_GetBottomDACValue(struct Module* mod,unsigned int i);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
void Feb_Control_activate(int activate);
|
||||
|
||||
int Feb_Control_IsBottomModule();
|
||||
int Feb_Control_GetModuleNumber();
|
||||
|
||||
|
||||
|
||||
|
||||
void Feb_Control_PrintModuleList();
|
||||
int Feb_Control_GetModuleIndex(unsigned int module_number, unsigned int* module_index);
|
||||
int Feb_Control_CheckModuleAddresses(struct Module* m);
|
||||
int Feb_Control_AddModule(unsigned int module_number, unsigned int top_address);
|
||||
/*int Feb_Control_AddModule(unsigned int module_number, unsigned int top_address, unsigned int bottom_address, int half_module=0);*/
|
||||
int Feb_Control_AddModule1(unsigned int module_number, int top_enable, unsigned int top_address, unsigned int bottom_address, int half_module);
|
||||
|
||||
int Feb_Control_GetDACNumber(char* s, unsigned int* n);
|
||||
int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch, unsigned int* value);
|
||||
int Feb_Control_VoltageToDAC(float value, unsigned int* digital, unsigned int nsteps, float vmin, float vmax);
|
||||
float Feb_Control_DACToVoltage(unsigned int digital,unsigned int nsteps,float vmin,float vmax);
|
||||
|
||||
|
||||
int Feb_Control_SendIDelays(unsigned int dst_num, int chip_lr, unsigned int channels, unsigned int ndelay_units);
|
||||
|
||||
int Feb_Control_SetStaticBits();
|
||||
int Feb_Control_SetStaticBits1(unsigned int the_static_bits);
|
||||
|
||||
int Feb_Control_SendBitModeToBebServer();
|
||||
|
||||
unsigned int Feb_Control_ConvertTimeToRegister(float time_in_sec);
|
||||
|
||||
unsigned int Feb_Control_AddressToAll();
|
||||
int Feb_Control_SetCommandRegister(unsigned int cmd);
|
||||
int Feb_Control_GetDAQStatusRegister(unsigned int dst_address, unsigned int* ret_status);
|
||||
/*int Feb_Control_StartDAQOnlyNWaitForFinish(int sleep_time_us=5000);*/
|
||||
int Feb_Control_StartDAQOnlyNWaitForFinish(int sleep_time_us);
|
||||
|
||||
int Feb_Control_ResetChipCompletely();
|
||||
int Feb_Control_ResetChipPartially();
|
||||
|
||||
//struct sockaddr_in Feb_Control_serv_addr;
|
||||
/*
|
||||
int Feb_Control_SetupSendToSocket(const char* ip_address_hostname, unsigned short int port);
|
||||
int Feb_Control_WriteNRead(char* message, int length, int max_length);
|
||||
*/
|
||||
|
||||
|
||||
void Feb_Control_FebControl();
|
||||
int Feb_Control_Init(int master, int top, int normal, int module_num);
|
||||
int Feb_Control_OpenSerialCommunication();
|
||||
void Feb_Control_CloseSerialCommunication();
|
||||
int Feb_Control_CheckSetup();
|
||||
|
||||
unsigned int Feb_Control_GetNModules();
|
||||
unsigned int Feb_Control_GetNHalfModules();
|
||||
|
||||
int Feb_Control_SetHighVoltage(int value);
|
||||
int Feb_Control_GetHighVoltage(int* value);
|
||||
|
||||
int Feb_Control_SendHighVoltage(int dacvalue);
|
||||
int Feb_Control_ReceiveHighVoltage(unsigned int* value);
|
||||
|
||||
int Feb_Control_SetIDelays(unsigned int module_num, unsigned int ndelay_units);
|
||||
int Feb_Control_SetIDelays1(unsigned int module_num, unsigned int chip_pos, unsigned int ndelay_units);
|
||||
|
||||
int Feb_Control_DecodeDACString(char* dac_str, unsigned int* module_index, int* top, int* bottom, unsigned int* dac_ch);
|
||||
/*int Feb_Control_SetDAC(string s, int value, int is_a_voltage_mv=0);*/
|
||||
int Feb_Control_SetDAC(char* s, int value, int is_a_voltage_mv);
|
||||
/* int Feb_Control_GetDAC(string s, int* ret_value, int voltage_mv=0);*/
|
||||
int Feb_Control_GetDAC(char* s, int* ret_value, int voltage_mv);
|
||||
int Feb_Control_GetDACName(unsigned int dac_num,char* s);
|
||||
|
||||
int Feb_Control_SetTrimbits(unsigned int module_num, unsigned int* trimbits);
|
||||
unsigned int* Feb_Control_GetTrimbits();
|
||||
|
||||
|
||||
/**Added by Dhanya */
|
||||
int Feb_Control_SaveAllTrimbitsTo(int value);
|
||||
|
||||
|
||||
|
||||
int Feb_Control_Reset();
|
||||
int Feb_Control_PrepareForAcquisition();
|
||||
|
||||
int Feb_Control_StartAcquisition();
|
||||
int Feb_Control_StopAcquisition();
|
||||
int Feb_Control_AcquisitionInProgress();
|
||||
int Feb_Control_AcquisitionStartedBit();
|
||||
/*int Feb_Control_WaitForFinishedFlag(int sleep_time_us=5000);*/
|
||||
int Feb_Control_WaitForFinishedFlag(int sleep_time_us);
|
||||
int Feb_Control_WaitForStartedFlag(int sleep_time_us, int prev_flag);
|
||||
|
||||
//functions for setting up exposure
|
||||
void Feb_Control_PrintAcquisitionSetup();
|
||||
int Feb_Control_SetNExposures(unsigned int n_images);
|
||||
unsigned int Feb_Control_GetNExposures();
|
||||
int Feb_Control_SetExposureTime(double the_exposure_time_in_sec);
|
||||
double Feb_Control_GetExposureTime();
|
||||
int64_t Feb_Control_GetExposureTime_in_nsec();
|
||||
int Feb_Control_SetSubFrameExposureTime(int64_t the_subframe_exposure_time_in_10nsec);
|
||||
int64_t Feb_Control_GetSubFrameExposureTime();
|
||||
int Feb_Control_SetSubFramePeriod(int64_t the_subframe_period_in_10nsec);
|
||||
int64_t Feb_Control_GetSubFramePeriod();
|
||||
int Feb_Control_SetExposurePeriod(double the_exposure_period_in_sec);
|
||||
double Feb_Control_GetExposurePeriod();
|
||||
int Feb_Control_SetDynamicRange(unsigned int four_eight_sixteen_or_thirtytwo);
|
||||
unsigned int Feb_Control_GetDynamicRange();
|
||||
int Feb_Control_SetReadoutSpeed(unsigned int readout_speed); //0 was default, 0->full,1->half,2->quarter or 3->super_slow
|
||||
int Feb_Control_SetReadoutMode(unsigned int readout_mode); ///0 was default,0->parallel,1->non-parallel,2-> safe_mode
|
||||
int Feb_Control_SetTriggerMode(unsigned int trigger_mode, int polarity);//0 and 1 was default,
|
||||
int Feb_Control_SetExternalEnableMode(int use_external_enable, int polarity);//0 and 1 was default,
|
||||
|
||||
//functions for testing
|
||||
/*int Feb_Control_SetTestModeVariable(int on=1);*/
|
||||
int Feb_Control_SetInTestModeVariable(int on);
|
||||
int Feb_Control_GetTestModeVariable();
|
||||
|
||||
void Feb_Control_Set_Counter_Bit(int value);
|
||||
int Feb_Control_Get_Counter_Bit();
|
||||
int Feb_Control_Pulse_Pixel(int npulses,int x, int y);
|
||||
int Feb_Control_PulsePixelNMove(int npulses, int inc_x_pos, int inc_y_pos);
|
||||
int Feb_Control_Shift32InSerialIn(unsigned int value_to_shift_in);
|
||||
int Feb_Control_SendTokenIn();
|
||||
int Feb_Control_ClockRowClock(unsigned int ntimes);
|
||||
int Feb_Control_PulseChip(int npulses);
|
||||
|
||||
int64_t Feb_Control_Get_RateTable_Tau_in_nsec();
|
||||
int64_t Feb_Control_Get_RateTable_Period_in_nsec();
|
||||
int Feb_Control_SetRateCorrectionTau(int64_t tau_in_Nsec);
|
||||
int Feb_Control_SetRateCorrectionTable(unsigned int *table);
|
||||
int Feb_Control_GetRateCorrectionVariable();
|
||||
void Feb_Control_SetRateCorrectionVariable(int activate_rate_correction);
|
||||
int Feb_Control_PrintCorrectedValues();
|
||||
|
||||
int Feb_Control_GetLeftFPGATemp();
|
||||
int Feb_Control_GetRightFPGATemp();
|
||||
|
||||
int64_t Feb_Control_GetMeasuredPeriod();
|
||||
int64_t Feb_Control_GetSubMeasuredPeriod();
|
||||
|
||||
int Feb_Control_SoftwareTrigger();
|
||||
|
||||
uint32_t Feb_Control_WriteRegister(uint32_t offset, uint32_t data);
|
||||
uint32_t Feb_Control_ReadRegister(uint32_t offset);
|
||||
#endif
|
||||
@ -0,0 +1,210 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
|
||||
//#include <iostream>
|
||||
//#include <iomanip>
|
||||
//#include <unistd.h>
|
||||
//#include <string.h>
|
||||
//#include <sys/mman.h>
|
||||
//#include <fcntl.h>
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <unistd.h>
|
||||
|
||||
#include "xparameters.h"
|
||||
|
||||
#include "FebInterface.h"
|
||||
|
||||
|
||||
|
||||
struct LocalLinkInterface ll_local,* ll;
|
||||
|
||||
unsigned int Feb_Interface_nfebs;
|
||||
unsigned int* Feb_Interface_feb_numb;
|
||||
|
||||
int Feb_Interface_send_ndata;
|
||||
unsigned int Feb_Interface_send_buffer_size;
|
||||
unsigned int* Feb_Interface_send_data_raw;
|
||||
unsigned int* Feb_Interface_send_data;
|
||||
|
||||
int Feb_Interface_recv_ndata;
|
||||
unsigned int Feb_Interface_recv_buffer_size;
|
||||
unsigned int* Feb_Interface_recv_data_raw;
|
||||
unsigned int* Feb_Interface_recv_data;
|
||||
|
||||
|
||||
void Feb_Interface_FebInterface(){
|
||||
ll = &ll_local;
|
||||
Feb_Interface_nfebs = 0;
|
||||
Feb_Interface_feb_numb = 0;
|
||||
|
||||
Feb_Interface_send_ndata = 0;
|
||||
Feb_Interface_send_buffer_size = 1026;
|
||||
Feb_Interface_send_data_raw = malloc((Feb_Interface_send_buffer_size+1) * sizeof(unsigned int));
|
||||
Feb_Interface_send_data = &Feb_Interface_send_data_raw[1];
|
||||
|
||||
Feb_Interface_recv_ndata = 0;
|
||||
Feb_Interface_recv_buffer_size = 1026;
|
||||
Feb_Interface_recv_data_raw = malloc((Feb_Interface_recv_buffer_size+1) * sizeof(unsigned int));
|
||||
Feb_Interface_recv_data = &Feb_Interface_recv_data_raw[1];
|
||||
|
||||
Local_LocalLinkInterface1(ll,XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR);
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
void Feb_Interface_SendCompleteList(unsigned int n,unsigned int* list){
|
||||
unsigned int i;
|
||||
if(Feb_Interface_feb_numb) free(Feb_Interface_feb_numb);
|
||||
Feb_Interface_nfebs = n;
|
||||
Feb_Interface_feb_numb = malloc(n * sizeof(unsigned int));
|
||||
for(i=0;i<n;i++) Feb_Interface_feb_numb[i] = list[i];
|
||||
}
|
||||
|
||||
int Feb_Interface_WriteTo(unsigned int ch){
|
||||
if(ch>0xfff) return 0;
|
||||
|
||||
#ifdef MARTIN
|
||||
cprintf(YELLOW, "FIW ch %d\n", ch);
|
||||
#endif
|
||||
|
||||
Feb_Interface_send_data_raw[0] = 0x8fff0000;
|
||||
if(Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
|
||||
|
||||
Feb_Interface_send_data_raw[0] = 0x90000000 | (ch<<16);
|
||||
if(Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
|
||||
|
||||
Feb_Interface_send_data_raw[0] = 0xc0000000;
|
||||
return ((Feb_Interface_send_ndata+1)*4==Local_Write(ll,(Feb_Interface_send_ndata+1)*4,Feb_Interface_send_data_raw));
|
||||
}
|
||||
|
||||
int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys){
|
||||
unsigned int t;
|
||||
if(ch>=0xfff) return 0;
|
||||
|
||||
Feb_Interface_recv_data_raw[0] = 0xa0000000 | (ch<<16);
|
||||
Local_Write(ll,4,Feb_Interface_recv_data_raw);
|
||||
usleep(20);
|
||||
|
||||
Feb_Interface_recv_ndata=-1;
|
||||
for(t=0;t<ntrys;t++){
|
||||
if((Feb_Interface_recv_ndata=Local_Read(ll,Feb_Interface_recv_buffer_size*4,Feb_Interface_recv_data_raw)/4)>0){
|
||||
Feb_Interface_recv_ndata--;
|
||||
break;
|
||||
}
|
||||
usleep(1000);
|
||||
}
|
||||
|
||||
return (Feb_Interface_recv_ndata>=0);
|
||||
}
|
||||
|
||||
|
||||
|
||||
int Feb_Interface_SetByteOrder(){
|
||||
Feb_Interface_send_data_raw[0] = 0x8fff0000;
|
||||
if(Local_Write(ll,4,Feb_Interface_send_data_raw)!=4) return 0;
|
||||
Feb_Interface_send_ndata = 2;
|
||||
Feb_Interface_send_data[0] = 0;
|
||||
Feb_Interface_send_data[1] = 0;
|
||||
unsigned int i;
|
||||
unsigned int dst = 0xff;
|
||||
for(i=0;i<Feb_Interface_nfebs;i++) dst = (dst | Feb_Interface_feb_numb[i]);
|
||||
int passed = Feb_Interface_WriteTo(dst);
|
||||
|
||||
return passed;
|
||||
}
|
||||
|
||||
|
||||
int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read){
|
||||
return Feb_Interface_ReadRegisters(sub_num,1,®_num,value_read);
|
||||
}
|
||||
|
||||
|
||||
int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read){
|
||||
//here cout<<"Reading Register ...."<<endl;
|
||||
unsigned int i;
|
||||
nreads &= 0x3ff;
|
||||
if(!nreads||nreads>Feb_Interface_send_buffer_size-2) return 0;
|
||||
|
||||
Feb_Interface_send_ndata = nreads+2;
|
||||
Feb_Interface_send_data[0] = 0x20000000 | nreads << 14;
|
||||
|
||||
for(i=0;i<nreads;i++) Feb_Interface_send_data[i+1]=reg_nums[i];
|
||||
Feb_Interface_send_data[nreads+1] = 0;
|
||||
|
||||
if(!Feb_Interface_WriteTo(sub_num)||!Feb_Interface_ReadFrom(sub_num,20)||Feb_Interface_recv_ndata!=(int)(nreads+2)) return 0;
|
||||
|
||||
for(i=0;i<nreads;i++) values_read[i] = Feb_Interface_recv_data[i+1];
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address){
|
||||
return Feb_Interface_WriteRegisters(sub_num,1,®_num,&value,&wait_on,&wait_on_address);
|
||||
}
|
||||
|
||||
int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses){
|
||||
unsigned int i;
|
||||
nwrites &= 0x3ff; //10 bits
|
||||
if(!nwrites||2*nwrites>Feb_Interface_send_buffer_size-2) return 0;
|
||||
|
||||
//cout<<"Write register : "<<this<<" "<<s_num<<" "<<nwrites<<" "<<reg_nums<<" "<<values<<" "<<wait_ons<<" "<<wait_on_addresses<<endl;
|
||||
Feb_Interface_send_ndata = 2*nwrites+2;
|
||||
Feb_Interface_send_data[0] = 0x80000000 | nwrites << 14;
|
||||
Feb_Interface_send_data[2*nwrites+1] = 0;
|
||||
|
||||
for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+1] = 0x3fff®_nums[i];
|
||||
for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+2] = values[i];
|
||||
// wait on busy data(28), address of busy flag data(27 downto 14)
|
||||
if(wait_ons&&wait_on_addresses) for(i=0;i<nwrites;i++) Feb_Interface_send_data[2*i+1] |= (wait_ons[i]<<28 | (0x3fff&wait_on_addresses[i])<<14);
|
||||
|
||||
if(!Feb_Interface_WriteTo(sub_num)) return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values){
|
||||
unsigned int max_single_packet_size = 352;
|
||||
int passed=1;
|
||||
unsigned int n_to_send = max_single_packet_size;
|
||||
unsigned int ndata_sent = 0;
|
||||
unsigned int ndata_countdown = nwrites;
|
||||
while(ndata_countdown>0){
|
||||
n_to_send = ndata_countdown<max_single_packet_size ? ndata_countdown:max_single_packet_size;
|
||||
if(!Feb_Interface_WriteMemory(sub_num,mem_num,start_address,n_to_send,&(values[ndata_sent]))){passed=0; break;}
|
||||
ndata_countdown-=n_to_send;
|
||||
ndata_sent +=n_to_send;
|
||||
start_address +=n_to_send;
|
||||
usleep(500);//500 works
|
||||
}
|
||||
return passed;
|
||||
}
|
||||
|
||||
int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values){
|
||||
// -1 means write to all
|
||||
unsigned int i;
|
||||
mem_num &= 0x3f;
|
||||
start_address &= 0x3fff;
|
||||
nwrites &= 0x3ff;
|
||||
if(!nwrites||nwrites>Feb_Interface_send_buffer_size-2) {printf("error herer: nwrites:%d\n",nwrites);return 0;}//*d-1026
|
||||
|
||||
Feb_Interface_send_ndata = nwrites+2;//*d-1026
|
||||
Feb_Interface_send_data[0] = 0xc0000000 | mem_num << 24 | nwrites << 14 | start_address; //cmd -> write to memory, nwrites, mem number, start address
|
||||
Feb_Interface_send_data[nwrites+1] = 0;
|
||||
for(i=0;i<nwrites;i++) Feb_Interface_send_data[i+1] = values[i];
|
||||
|
||||
|
||||
if(!Feb_Interface_WriteTo(sub_num)) return 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,43 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
#ifndef FEBINTERFACE_H
|
||||
#define FEBINTERFACE_H
|
||||
|
||||
#include "LocalLinkInterface.h"
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
int Feb_Interface_WriteTo(unsigned int ch);
|
||||
/*int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys=20);*/
|
||||
int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys);
|
||||
|
||||
void Feb_Interface_FebInterface();
|
||||
|
||||
|
||||
void Feb_Interface_SendCompleteList(unsigned int n,unsigned int* list);
|
||||
int Feb_Interface_SetByteOrder();
|
||||
|
||||
int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read);
|
||||
int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read);
|
||||
/*int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on=0, unsigned int wait_on_address=0);*/
|
||||
int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address);
|
||||
/*int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons=0, unsigned int* wait_on_addresses=0);*/
|
||||
int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses);
|
||||
|
||||
//mem_num is 0 for trimbit BRAM and 1 for rate correction BRAM
|
||||
int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
|
||||
|
||||
int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,227 @@
|
||||
|
||||
/**
|
||||
* @author Ian Johnson
|
||||
* @version 1.0
|
||||
*/
|
||||
|
||||
|
||||
//daq register definitions
|
||||
#define DAQ_REG_CTRL 1
|
||||
#define DAQ_REG_CHIP_CMDS 2
|
||||
#define DAQ_REG_STATIC_BITS 3
|
||||
#define DAQ_REG_CLK_ROW_CLK_NTIMES 3
|
||||
#define DAQ_REG_SHIFT_IN_32 3
|
||||
#define DAQ_REG_READOUT_NROWS 3
|
||||
#define DAQ_REG_SEND_N_TESTPULSES 3
|
||||
|
||||
#define DAQ_REG_NEXPOSURES 3
|
||||
#define DAQ_REG_EXPOSURE_TIMER 4 // == (31 downto 3) * 10^(2 downto 0)
|
||||
#define DAQ_REG_EXPOSURE_REPEAT_TIMER 5 // == (31 downto 3) * 10^(2 downto 0)
|
||||
#define DAQ_REG_SUBFRAME_EXPOSURES 6
|
||||
#define DAQ_REG_SUBFRAME_PERIOD 7 //also pg and fifo status register
|
||||
|
||||
|
||||
#define DAQ_REG_RO_OFFSET 12
|
||||
#define DAQ_REG_STATUS (DAQ_REG_RO_OFFSET + 0) //also pg and fifo status register
|
||||
#define FEB_REG_STATUS (DAQ_REG_RO_OFFSET + 3)
|
||||
#define MEAS_SUBPERIOD_REG (DAQ_REG_RO_OFFSET + 4)
|
||||
#define MEAS_PERIOD_REG (DAQ_REG_RO_OFFSET + 5)
|
||||
|
||||
|
||||
|
||||
#define DAQ_CTRL_RESET 0x80000000
|
||||
#define DAQ_CTRL_START 0x40000000
|
||||
#define ACQ_CTRL_START 0x50000000 //this is 0x10000000 (acq) | 0x40000000 (daq)
|
||||
#define DAQ_CTRL_STOP 0x00000000
|
||||
|
||||
//direct chip commands to the DAQ_REG_CHIP_CMDS register
|
||||
#define DAQ_SET_STATIC_BIT 0x00000001
|
||||
#define DAQ_RESET_COMPLETELY 0x0000000E
|
||||
#define DAQ_RESET_PERIPHERY 0x00000002
|
||||
#define DAQ_RESET_PIXEL_COUNTERS 0x00000004
|
||||
#define DAQ_RESET_COLUMN_SELECT 0x00000008
|
||||
|
||||
#define DAQ_STORE_IMAGE 0x00000010
|
||||
#define DAQ_RELEASE_IMAGE_STORE 0x00000020
|
||||
|
||||
#define DAQ_SEND_A_TOKEN_IN 0x00000040
|
||||
#define DAQ_CLK_ROW_CLK_NTIMES 0x00000080
|
||||
#define DAQ_SERIALIN_SHIFT_IN_32 0x00000100
|
||||
#define DAQ_LOAD_16ROWS_OF_TRIMBITS 0x00000200
|
||||
|
||||
#define DAQ_IGNORE_INITIAL_CRAP 0x00000400 //crap before readout
|
||||
#define DAQ_READOUT_NROWS 0x00000800
|
||||
#define DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START 0x00001000 //last 4 bit of data in the last frame
|
||||
|
||||
#define DAQ_RELEASE_IMAGE_STORE_AFTER_READOUT 0x00002000
|
||||
#define DAQ_RESET_PIXEL_COUNTERS_AFTER_READOUT 0x00004000
|
||||
|
||||
#define DAQ_CLK_ROW_CLK_TO_SELECT_NEXT_ROW 0x00008000
|
||||
#define DAQ_CLK_MAIN_CLK_TO_SELECT_NEXT_PIXEL 0x00010000
|
||||
#define DAQ_SEND_N_TEST_PULSES 0x00020000
|
||||
|
||||
#define DAQ_CHIP_CONTROLLER_HALF_SPEED 0x00040000 //everything at 100 MHz (50MHz ddr readout)
|
||||
#define DAQ_CHIP_CONTROLLER_QUARTER_SPEED 0x00080000 //everything at 50 MHz (25MHz ddr readout)
|
||||
#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED 0x000c0000 //everything at ~200 kHz (200 kHz MHz ddr readout)
|
||||
|
||||
//#define DAQ_FIFO_ENABLE 0x00100000 commented out as it is not used anywhere
|
||||
#define DAQ_REG_CHIP_CMDS_INT_TRIGGER 0x00100000
|
||||
|
||||
//direct chip commands to the DAQ_REG_CHIP_CMDS register
|
||||
#define DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE 0x00200000 //row clk is before main clk readout sequence
|
||||
#define DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE 0x00400000 //expose ->readout ->expose -> ..., with store is always closed
|
||||
#define DAQ_NEXPOSURERS_PARALLEL_MODE 0x00600000 //parallel acquire/read mode
|
||||
|
||||
//DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES is old now hard-wired in the firmware that every image comes with a header
|
||||
//#define DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES 0x00800000 //DAQ_IGNORE_INITIAL_CRAP and DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START
|
||||
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING 0x01000000
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING_POLARITY 0x02000000
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_TRIGGER_POLARITY 0x04000000
|
||||
|
||||
#define DAQ_NEXPOSURERS_INTERNAL_ACQUISITION 0x00000000 //internally controlled
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START 0x08000000 //external acquisition start
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START 0x10000000 //external image start
|
||||
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP 0x18000000 //externally controlly, external image start and stop
|
||||
|
||||
#define DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING 0x20000000
|
||||
#define DAQ_NEXPOSURERS_ACTIVATE_RATE_CORRECTION 0x40000000
|
||||
|
||||
//#define DAQ_MASTER_HALF_MODULE 0x80000000 currently not used
|
||||
|
||||
|
||||
//chips static bits
|
||||
#define DAQ_STATIC_BIT_PROGRAM 0x00000001
|
||||
#define DAQ_STATIC_BIT_M4 0x00000002 //these are the status bits, not bit mode
|
||||
#define DAQ_STATIC_BIT_M8 0x00000004 //these are the status bits, not bit mode
|
||||
#define DAQ_STATIC_BIT_M12 0x00000000 //these are the status bits, not bit mode, ie. "00" is 12 bit mode
|
||||
#define DAQ_STATIC_BIT_CHIP_TEST 0x00000008
|
||||
#define DAQ_STATIC_BIT_ROTEST 0x00000010
|
||||
#define DAQ_CS_BAR_LEFT 0x00000020
|
||||
#define DAQ_CS_BAR_RIGHT 0x00000040
|
||||
|
||||
|
||||
//status flags
|
||||
#define DAQ_STATUS_DAQ_RUNNING 0x01
|
||||
#define DAQ_DATA_COLLISION_ERROR 0x02
|
||||
|
||||
|
||||
#define DAQ_STATUS_CURRENT_M4 0x04
|
||||
#define DAQ_STATUS_CURRENT_M8 0x08
|
||||
#define DAQ_STATUS_CURRENT_M12 0x00 //in 12 bit mode both are cleared
|
||||
#define DAQ_STATUS_CURRENT_TESTMODE 0x10
|
||||
#define DAQ_STATUS_TOKEN_OUT 0x20
|
||||
#define DAQ_STATUS_SERIAL_OUT 0x40
|
||||
#define DAQ_STATUS_PIXELS_ARE_ENABLED 0x80
|
||||
#define DAQ_STATUS_DAQ_RUN_TOGGLE 0x200
|
||||
|
||||
//data delay registers
|
||||
#define CHIP_DATA_OUT_DELAY_REG_CTRL 1
|
||||
#define CHIP_DATA_OUT_DELAY_REG2 2
|
||||
#define CHIP_DATA_OUT_DELAY_REG3 3
|
||||
#define CHIP_DATA_OUT_DELAY_REG4 4
|
||||
#define CHIP_DATA_OUT_DELAY_SET 0x20000000
|
||||
|
||||
//module configuration
|
||||
#define TOP_BIT_MASK 0x00f
|
||||
#define MASTER_BIT_MASK 0x200
|
||||
#define NORMAL_MODULE_BIT_MASK 0x400
|
||||
|
||||
// Master Slave Top Bottom Definition
|
||||
#define MODULE_CONFIGURATION_MASK 0x84
|
||||
//Software Configuration
|
||||
#define MASTERCONFIG_OFFSET 0x160 //0x20 * 11 (P11)
|
||||
#define MASTER_BIT 0x1
|
||||
#define OVERWRITE_HARDWARE_BIT 0x2
|
||||
#define DEACTIVATE_BIT 0x4
|
||||
|
||||
#define FPGA_TEMP_OFFSET 0x200
|
||||
|
||||
#define TXM_DELAY_LEFT_OFFSET 0x180
|
||||
#define TXM_DELAY_RIGHT_OFFSET 0x1A0
|
||||
#define TXM_DELAY_FRAME_OFFSET 0x1C0
|
||||
#define FLOW_REG_OFFSET 0x140
|
||||
|
||||
#define FLOW_REG_TXM_FLOW_CNTRL_10G_OFST (0)
|
||||
#define FLOW_REG_TXM_FLOW_CNTRL_10G_MSK (0x1 << FLOW_REG_TXM_FLOW_CNTRL_10G_OFST)
|
||||
#define FLOW_REG_OVERFLOW_32_BIT_OFST (2)
|
||||
#define FLOW_REG_OVERFLOW_32_BIT_MSK (0x1 << FLOW_REG_OVERFLOW_32_BIT_OFST)
|
||||
|
||||
//command memory
|
||||
#define LEFT_OFFSET 0x0
|
||||
#define RIGHT_OFFSET 0x100
|
||||
|
||||
#define FIRST_CMD_PART1_OFFSET 0x8
|
||||
#define FIRST_CMD_PART2_OFFSET 0xc
|
||||
#define SECOND_CMD_PART1_OFFSET 0x10
|
||||
#define SECOND_CMD_PART2_OFFSET 0x14
|
||||
#define COMMAND_COUNTER_OFFSET 0x18
|
||||
#define STOP_ACQ_OFFSET 0x1c
|
||||
#define STOP_ACQ_BIT 0x40000000
|
||||
#define TWO_REQUESTS_OFFSET 0x1c
|
||||
#define TWO_REQUESTS_BIT 0x80000000
|
||||
|
||||
//version
|
||||
#define FIRMWARE_VERSION_OFFSET 0x4
|
||||
#define FIRMWARESOFTWARE_API_OFFSET 0x0
|
||||
|
||||
#define FRAME_NUM_RESET_OFFSET 0xA0
|
||||
|
||||
//1g counters
|
||||
#define ONE_GIGA_LEFT_INDEX_LSB_COUNTER 0x04
|
||||
#define ONE_GIGA_LEFT_INDEX_MSB_COUNTER 0x24
|
||||
|
||||
#define ONE_GIGA_LEFT_TXN_DELAY_COUNTER 0x104
|
||||
#define ONE_GIGA_LEFT_FRAME_DELAY_COUNTER 0x124
|
||||
|
||||
#define ONE_GIGA_RIGHT_INDEX_LSB_COUNTER 0x44
|
||||
#define ONE_GIGA_RIGHT_INDEX_MSB_COUNTER 0x64
|
||||
|
||||
#define ONE_GIGA_RIGHT_TXN_DELAY_COUNTER 0x144
|
||||
#define ONE_GIGA_RIGHT_FRAME_DELAY_COUNTER 0x164
|
||||
|
||||
//10g counters
|
||||
#define TEN_GIGA_LEFT_INDEX_LSB_COUNTER 0x84
|
||||
#define TEN_GIGA_LEFT_INDEX_MSB_COUNTER 0xa4
|
||||
|
||||
#define TEN_GIGA_LEFT_TXN_DELAY_COUNTER 0x184
|
||||
#define TEN_GIGA_LEFT_FRAME_DELAY_COUNTER 0x1a4
|
||||
|
||||
#define TEN_GIGA_RIGHT_INDEX_LSB_COUNTER 0xc4
|
||||
#define TEN_GIGA_RIGHT_INDEX_MSB_COUNTER 0xe4
|
||||
|
||||
#define TEN_GIGA_RIGHT_TXN_DELAY_COUNTER 0x1c4
|
||||
#define TEN_GIGA_RIGHT_FRAME_DELAY_COUNTER 0x1e4
|
||||
|
||||
// udp header (position, id)
|
||||
#define UDP_HEADER_A_LEFT_OFST 0x00C0
|
||||
#define UDP_HEADER_B_LEFT_OFST 0x00E0
|
||||
#define UDP_HEADER_A_RIGHT_OFST 0x0100
|
||||
#define UDP_HEADER_B_RIGHT_OFST 0x0120
|
||||
|
||||
#define UDP_HEADER_X_OFST (0)
|
||||
#define UDP_HEADER_X_MSK (0xFFFF << UDP_HEADER_X_OFST)
|
||||
#define UDP_HEADER_ID_OFST (16)
|
||||
#define UDP_HEADER_ID_MSK (0xFFFF << UDP_HEADER_ID_OFST)
|
||||
#define UDP_HEADER_Z_OFST (0)
|
||||
#define UDP_HEADER_Z_MSK (0xFFFF << UDP_HEADER_Z_OFST)
|
||||
#define UDP_HEADER_Y_OFST (16)
|
||||
#define UDP_HEADER_Y_MSK (0xFFFF << UDP_HEADER_Y_OFST)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,87 @@
|
||||
|
||||
//Class initially from Gerd and was called mmap_test.c
|
||||
//return reversed 1 means good, 0 means failed
|
||||
|
||||
|
||||
//#include <stdio.h>
|
||||
//#include <unistd.h>
|
||||
//#include <string.h>
|
||||
//#include <sys/mman.h>
|
||||
//#include <fcntl.h>
|
||||
|
||||
#include "HardwareIO.h"
|
||||
|
||||
xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress)
|
||||
{
|
||||
/* read the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
xfs_u8 IoContents;
|
||||
__asm__ volatile ("eieio; lbz %0,0(%1)":"=r" (IoContents):"b"
|
||||
(InAddress));
|
||||
return IoContents;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress)
|
||||
{
|
||||
/* read the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
xfs_u16 IoContents;
|
||||
__asm__ volatile ("eieio; lhz %0,0(%1)":"=r" (IoContents):"b"
|
||||
(InAddress));
|
||||
return IoContents;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress)
|
||||
{
|
||||
/* read the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
xfs_u32 IoContents;
|
||||
__asm__ volatile ("eieio; lwz %0,0(%1)":"=r" (IoContents):"b"
|
||||
(InAddress));
|
||||
return IoContents;
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value)
|
||||
{
|
||||
/* write the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
__asm__ volatile ("stb %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value)
|
||||
{
|
||||
/* write the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
__asm__ volatile ("sth %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
|
||||
}
|
||||
|
||||
/*****************************************************************************/
|
||||
|
||||
void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value)
|
||||
{
|
||||
/* write the contents of the I/O location and then synchronize the I/O
|
||||
* such that the I/O operation completes before proceeding on
|
||||
*/
|
||||
|
||||
__asm__ volatile ("stw %0,0(%1); eieio"::"r" (Value), "b"(OutAddress));
|
||||
}
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,26 @@
|
||||
|
||||
|
||||
//Class initially from Gerd and was called mmap_test.c
|
||||
|
||||
#ifndef HARDWAREIO_H
|
||||
#define HARDWAREIO_H
|
||||
|
||||
#include "xfs_types.h"
|
||||
|
||||
|
||||
|
||||
xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress);
|
||||
xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress);
|
||||
xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress);
|
||||
|
||||
void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value);
|
||||
void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value);
|
||||
void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value);
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,62 @@
|
||||
|
||||
|
||||
//from Gerd and was called mmap_test.h
|
||||
|
||||
#ifndef __PLB_LL_FIFO_H__
|
||||
#define __PLB_LL_FIFO_H__
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* definitions */
|
||||
/******************************************************************************/
|
||||
|
||||
#define PLB_LL_FIFO_REG_CTRL 0
|
||||
#define PLB_LL_FIFO_REG_STATUS 1
|
||||
#define PLB_LL_FIFO_REG_FIFO 2
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_LL_REM_SHIFT 30
|
||||
#define PLB_LL_FIFO_CTRL_LL_REM 0xC0000000
|
||||
#define PLB_LL_FIFO_CTRL_LL_EOF 0x20000000
|
||||
#define PLB_LL_FIFO_CTRL_LL_SOF 0x10000000
|
||||
#define PLB_LL_FIFO_CTRL_LL_MASK 0xF0000000
|
||||
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_TX_RESET 0x08000000
|
||||
#define PLB_LL_FIFO_CTRL_RX_RESET 0x04000000
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_RESET_STATUS 0x00800000
|
||||
#define PLB_LL_FIFO_CTRL_RESET_USER 0x00400000
|
||||
#define PLB_LL_FIFO_CTRL_RESET_LINK 0x00200000
|
||||
#define PLB_LL_FIFO_CTRL_RESET_GT 0x00100000
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_RESET_ALL 0x0CF00000
|
||||
|
||||
// do not reset complete gtx dual in std. case
|
||||
// cause this would reset PLL and stop LL clk
|
||||
#define PLB_LL_FIFO_CTRL_RESET_STD 0x0CE00000
|
||||
|
||||
// reset Rx and Tx Fifo and set User Reset
|
||||
#define PLB_LL_FIFO_CTRL_RESET_FIFO 0x0C400000
|
||||
|
||||
|
||||
#define PLB_LL_FIFO_CTRL_CONFIG_VECTOR 0x000FFFFF
|
||||
|
||||
|
||||
#define PLB_LL_FIFO_STATUS_LL_REM_SHIFT 30
|
||||
#define PLB_LL_FIFO_STATUS_LL_REM 0xC0000000
|
||||
#define PLB_LL_FIFO_STATUS_LL_EOF 0x20000000
|
||||
#define PLB_LL_FIFO_STATUS_LL_SOF 0x10000000
|
||||
|
||||
#define PLB_LL_FIFO_STATUS_EMPTY 0x08000000
|
||||
#define PLB_LL_FIFO_STATUS_ALMOSTEMPTY 0x04000000
|
||||
#define PLB_LL_FIFO_STATUS_FULL 0x02000000
|
||||
#define PLB_LL_FIFO_STATUS_ALMOSTFULL 0x01000000
|
||||
|
||||
#define PLB_LL_FIFO_STATUS_VECTOR 0x000FFFFF
|
||||
|
||||
#define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
|
||||
|
||||
|
||||
#endif // __PLB_LL_FIFO_H__
|
||||
|
||||
|
||||
@ -0,0 +1,260 @@
|
||||
|
||||
//Class initially from Gerd and was called mmap_test.c
|
||||
//return reversed 1 means good, 0 means failed
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
#include <unistd.h>
|
||||
//#include <string.h>
|
||||
|
||||
|
||||
#include "HardwareMMappingDefs.h"
|
||||
|
||||
#include "LocalLinkInterface.h"
|
||||
|
||||
|
||||
|
||||
void Local_LocalLinkInterface1(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr){
|
||||
// printf("\n v 1 \n");
|
||||
printf("Initialize PLB LL FIFOs\n");
|
||||
ll->ll_fifo_base=0;
|
||||
ll->ll_fifo_ctrl_reg=0;
|
||||
if(Local_Init(ll,ll_fifo_badr)){
|
||||
Local_Reset(ll);
|
||||
printf("\tFIFO Status : 0x%08x\n",Local_StatusVector(ll));
|
||||
}else printf("\tError LocalLink Mappping : 0x%08x\n",ll_fifo_badr);
|
||||
printf("\n\n");
|
||||
}
|
||||
|
||||
/*~LocalLinkInterface(){};*/
|
||||
|
||||
void Local_LocalLinkInterface(struct LocalLinkInterface* ll){
|
||||
printf("Initializing new memory\n");
|
||||
}
|
||||
|
||||
|
||||
|
||||
int Local_Init(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr){
|
||||
int fd;
|
||||
void *plb_ll_fifo_ptr;
|
||||
|
||||
if ((fd=open("/dev/mem", O_RDWR)) < 0){
|
||||
fprintf(stderr, "Could not open /dev/mem\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
plb_ll_fifo_ptr = mmap(0, getpagesize(), PROT_READ | PROT_WRITE, MAP_FILE | MAP_SHARED, fd, ll_fifo_badr);
|
||||
close(fd);
|
||||
|
||||
if (plb_ll_fifo_ptr == MAP_FAILED){
|
||||
perror ("mmap");
|
||||
return 0;
|
||||
}
|
||||
|
||||
ll->ll_fifo_base = (xfs_u32) plb_ll_fifo_ptr;
|
||||
ll->ll_fifo_ctrl_reg = 0;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
int Local_Reset(struct LocalLinkInterface* ll){
|
||||
return Local_Reset1(ll,PLB_LL_FIFO_CTRL_RESET_STD);
|
||||
}
|
||||
|
||||
int Local_Reset1(struct LocalLinkInterface* ll,unsigned int rst_mask){
|
||||
ll->ll_fifo_ctrl_reg |= rst_mask;
|
||||
printf("\tCTRL Register bits: 0x%08x\n",ll->ll_fifo_ctrl_reg);
|
||||
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
|
||||
|
||||
ll->ll_fifo_ctrl_reg &= (~rst_mask);
|
||||
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
|
||||
// printf("FIFO CTRL Address: 0x%08x\n FIFO CTRL Register: 0x%08x\n",PLB_LL_FIFO_REG_CTRL,plb_ll_fifo[PLB_LL_FIFO_REG_CTRL]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
|
||||
unsigned int Local_StatusVector(struct LocalLinkInterface* ll){
|
||||
return HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
|
||||
}
|
||||
|
||||
int Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer){
|
||||
// note: buffer must be word (4 byte) aligned
|
||||
// frame_len in byte
|
||||
int vacancy=0;
|
||||
int i;
|
||||
int words_send = 0;
|
||||
int last_word;
|
||||
unsigned int *word_ptr;
|
||||
unsigned int fifo_ctrl;
|
||||
xfs_u32 status;
|
||||
|
||||
if (buffer_len < 1) return -1;
|
||||
|
||||
last_word = (buffer_len-1)/4;
|
||||
word_ptr = (unsigned int *)buffer;
|
||||
|
||||
#ifdef MARTIN
|
||||
cprintf(BLUE, "LL Write - Len: %2d - If: %X - Data: ",buffer_len, ll->ll_fifo_base);
|
||||
for (i=0; i < buffer_len/4; i++)
|
||||
cprintf(BLUE, "%.8X ",*(((unsigned *) buffer)+i));
|
||||
printf("\n");
|
||||
#endif
|
||||
|
||||
while (words_send <= last_word)
|
||||
{
|
||||
while (!vacancy)//wait for Fifo to be empty again
|
||||
{
|
||||
status = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
|
||||
if((status & PLB_LL_FIFO_STATUS_ALMOSTFULL) == 0) vacancy = 1;
|
||||
#ifdef MARTIN
|
||||
if (vacancy == 0) cprintf(RED, "Fifo full!\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
//Just to know: #define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
|
||||
for (i=0; ((i<PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS) && (words_send <= last_word)); i++)
|
||||
{
|
||||
fifo_ctrl = 0;
|
||||
if (words_send == 0)
|
||||
{
|
||||
fifo_ctrl = PLB_LL_FIFO_CTRL_LL_SOF;//announce the start of file
|
||||
}
|
||||
|
||||
if (words_send == last_word)
|
||||
{
|
||||
fifo_ctrl |= (PLB_LL_FIFO_CTRL_LL_EOF | (( (buffer_len-1)<<PLB_LL_FIFO_CTRL_LL_REM_SHIFT) & PLB_LL_FIFO_CTRL_LL_REM) );
|
||||
}
|
||||
Local_ctrl_reg_write_mask(ll,PLB_LL_FIFO_CTRL_LL_MASK,fifo_ctrl);
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_FIFO,word_ptr[words_send++]);
|
||||
}
|
||||
}
|
||||
return buffer_len;
|
||||
}
|
||||
|
||||
|
||||
int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer){
|
||||
static unsigned int buffer_ptr = 0;
|
||||
// note: buffer must be word (4 byte) aligned
|
||||
// frame_len in byte
|
||||
int len;
|
||||
unsigned int *word_ptr;
|
||||
unsigned int status;
|
||||
volatile unsigned int fifo_val;
|
||||
int sof = 0;
|
||||
|
||||
#ifdef MARTIN
|
||||
cprintf(CYAN, "LL Read - If: %X - Data: ",ll->ll_fifo_base);
|
||||
#endif
|
||||
|
||||
word_ptr = (unsigned int *)buffer;
|
||||
do
|
||||
{
|
||||
status = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_STATUS);
|
||||
|
||||
if (!(status & PLB_LL_FIFO_STATUS_EMPTY))
|
||||
{
|
||||
if (status & PLB_LL_FIFO_STATUS_LL_SOF)
|
||||
{
|
||||
if (buffer_ptr)
|
||||
{
|
||||
buffer_ptr = 0;
|
||||
return -1; // buffer overflow
|
||||
}
|
||||
// printf(">>>> SOF\n\r");
|
||||
buffer_ptr = 0;
|
||||
sof = 1;
|
||||
}
|
||||
|
||||
fifo_val = HWIO_xfs_in32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_FIFO); //read from fifo
|
||||
|
||||
if ((buffer_ptr > 0) || sof)
|
||||
{
|
||||
if ( (buffer_len >> 2) > buffer_ptr)
|
||||
{
|
||||
#ifdef MARTIN
|
||||
cprintf(CYAN, "%.8X ", fifo_val);
|
||||
#endif
|
||||
word_ptr[buffer_ptr++] = fifo_val; //write to buffer
|
||||
}
|
||||
else
|
||||
{
|
||||
buffer_ptr = 0;
|
||||
return -2; // buffer overflow
|
||||
}
|
||||
|
||||
if (status & PLB_LL_FIFO_STATUS_LL_EOF)
|
||||
{
|
||||
len = (buffer_ptr << 2) -3 + ( (status & PLB_LL_FIFO_STATUS_LL_REM)>>PLB_LL_FIFO_STATUS_LL_REM_SHIFT );
|
||||
#ifdef MARTIN
|
||||
cprintf(CYAN, "Len: %d\n",len);
|
||||
#endif
|
||||
// printf(">>>>status=0x%08x EOF len = %d \n\r\n\r",status, len);
|
||||
buffer_ptr = 0;
|
||||
return len;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
}
|
||||
while(!(status & PLB_LL_FIFO_STATUS_EMPTY));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int Local_ctrl_reg_write_mask(struct LocalLinkInterface* ll,unsigned int mask, unsigned int val){
|
||||
// printf("Fifo CTRL Reg(1): 0x%08x\n",plb_ll_fifo_ctrl_reg);
|
||||
ll->ll_fifo_ctrl_reg &= (~mask);
|
||||
//printf("Fifo CTRL Reg(2): 0x%08x\n",plb_ll_fifo_ctrl_reg);
|
||||
ll->ll_fifo_ctrl_reg |= ( mask & val);
|
||||
// printf("Fifo CTRL Reg: 0x%08x\n",plb_ll_fifo_ctrl_reg);
|
||||
HWIO_xfs_out32(ll->ll_fifo_base+4*PLB_LL_FIFO_REG_CTRL,ll->ll_fifo_ctrl_reg);
|
||||
// printf("Fifo STAT Reg: 0x%08x\n", plb_ll_fifo[PLB_LL_FIFO_REG_STATUS]);
|
||||
return 1;
|
||||
}
|
||||
|
||||
|
||||
int Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer){
|
||||
|
||||
int len;
|
||||
unsigned int rec_buff_len = 4096;
|
||||
unsigned int rec_buffer[4097];
|
||||
|
||||
|
||||
Local_Write(ll,buffer_len,buffer);
|
||||
usleep(10000);
|
||||
|
||||
do{
|
||||
len = Local_Read(ll,rec_buff_len,rec_buffer);
|
||||
printf("receive length: %i\n",len);
|
||||
|
||||
if (len > 0){
|
||||
rec_buffer[len]=0;
|
||||
printf((char*) rec_buffer);
|
||||
printf("\n");
|
||||
}
|
||||
} while(len > 0);
|
||||
|
||||
printf("\n\n\n\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
void Local_llfifo_print_frame(struct LocalLinkInterface* ll,unsigned char* fbuff, int len){
|
||||
int i;
|
||||
printf("\n\r----Frame of len : %d Byte\n\r",len);
|
||||
for(i=0;i<len;i++){
|
||||
printf("0x%02x ",fbuff[i] );
|
||||
if ((i&0xf) == 0x7) printf(" ");
|
||||
if ((i&0xf) == 0xf) printf("\n\r");
|
||||
}
|
||||
printf("\n\r");
|
||||
}
|
||||
|
||||
|
||||
@ -0,0 +1,54 @@
|
||||
|
||||
//Class initially from Gerd and was called mmap_test.c
|
||||
|
||||
#ifndef LOCALLINKINTERFACE_H
|
||||
#define LOCALLINKINTERFACE_H
|
||||
|
||||
#include "xfs_types.h"
|
||||
#include "HardwareIO.h"
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "ansi.h"
|
||||
#include <sys/mman.h>
|
||||
#include <fcntl.h>
|
||||
|
||||
/*class LocalLinkInterface: public HardwareIO{ //*/
|
||||
|
||||
|
||||
struct LocalLinkInterface{
|
||||
xfs_u32 ll_fifo_base;
|
||||
unsigned int ll_fifo_ctrl_reg;
|
||||
};
|
||||
|
||||
|
||||
|
||||
int Local_Init(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr);
|
||||
int Local_Reset1(struct LocalLinkInterface* ll,unsigned int rst_mask);
|
||||
|
||||
int Local_ctrl_reg_write_mask(struct LocalLinkInterface* ll,unsigned int mask, unsigned int val);
|
||||
void Local_llfifo_print_frame(struct LocalLinkInterface* ll,unsigned char* fbuff, int len);
|
||||
|
||||
|
||||
void Local_LocalLinkInterface1(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr);
|
||||
/* virtual ~LocalLinkInterface();*/
|
||||
|
||||
unsigned int Local_StatusVector(struct LocalLinkInterface* ll);
|
||||
int Local_Reset(struct LocalLinkInterface* ll);
|
||||
int Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
|
||||
int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
|
||||
|
||||
int Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
|
||||
|
||||
void Local_LocalLinkInterface(struct LocalLinkInterface* ll);
|
||||
|
||||
/*
|
||||
int FiFoReset(unsigned int numb);
|
||||
int FifoSend(unsigned int numb, unsigned int frame_len, void *buffer);
|
||||
int FifoReceive(unsigned int numb, unsigned int frame_len, void *buffer);
|
||||
int FifoTest(unsigned int numb,unsigned int send_len, char *send_str);
|
||||
*/
|
||||
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
38
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Makefile
Executable file
38
slsDetectorSoftware/slsDetectorServers/eigerDetectorServer/Makefile
Executable file
@ -0,0 +1,38 @@
|
||||
CC = powerpc-4xx-softfloat-gcc
|
||||
BLACKFIN_CC = bfin-uclinux-gcc
|
||||
CFLAGS += -Wall -DDACS_INT -DEIGERD -DSLS_DETECTOR_FUNCTION_LIST -DDACS_INT -DSTOP_SERVER #-DVERBOSEI #-DVERBOSE #-DVIRTUAL -DPCCOMPILE -DMARTIN
|
||||
LDLIBS += -lm -lstdc++
|
||||
|
||||
PROGS = eigerDetectorServer
|
||||
DESTDIR ?= bin
|
||||
INSTMODE = 0777
|
||||
|
||||
|
||||
SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c FebControl.c Beb.c HardwareIO.c LocalLinkInterface.c Feb.c FebInterface.c
|
||||
OBJS = $(SRC_CLNT:.c=.o)
|
||||
|
||||
|
||||
all: clean versioning $(PROGS) #hv9m_blackfin_server
|
||||
|
||||
|
||||
boot: $(OBJS)
|
||||
|
||||
versioning:
|
||||
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
|
||||
|
||||
$(PROGS): $(OBJS)
|
||||
# echo $(OBJS)
|
||||
mkdir -p $(DESTDIR)
|
||||
$(CC) -o $@ $(SRC_CLNT) $(CFLAGS) $(LDLIBS)
|
||||
mv $(PROGS) $(DESTDIR)
|
||||
|
||||
|
||||
hv9m_blackfin_server:9mhvserial_bf.c
|
||||
$(BLACKFIN_CC) -o hv9m_blackfin_server 9mhvserial_bf.c -Wall #-DVERBOSE
|
||||
mv hv9m_blackfin_server $(DESTDIR)
|
||||
rm hv9m_blackfin_server.gdb
|
||||
|
||||
clean:
|
||||
rm -rf $(DESTDIR)/$(PROGS) *.o $(DESTDIR)/hv9m_blackfin_server
|
||||
|
||||
|
||||
@ -0,0 +1,28 @@
|
||||
CC = gcc
|
||||
CFLAGS += -Wall -DDACS_INT -DEIGERD -DSLS_DETECTOR_FUNCTION_LIST -DDACS_INT -DPCCOMPILE -DSTOP_SERVER #-DVERBOSE
|
||||
CFLAGS += -DVIRTUAL -DVIRTUAL_9M
|
||||
MASTERFLAG += -DVIRTUAL_MASTER
|
||||
LDLIBS += -lm -lstdc++ -pthread
|
||||
|
||||
DESTDIR ?= bin
|
||||
|
||||
SRC_CLNT = communication_funcs.c slsDetectorServer.c slsDetectorServer_funcs.c slsDetectorFunctionList.c
|
||||
|
||||
|
||||
|
||||
all: clean master slave
|
||||
|
||||
|
||||
master: $(SRC_CLNT)
|
||||
mkdir -p $(DESTDIR)
|
||||
$(CC) -o eigerDetectorServer_virtualMaster $(SRC_CLNT) $(CFLAGS) $(MASTERFLAG) $(LDLIBS)
|
||||
mv eigerDetectorServer_virtualMaster $(DESTDIR)
|
||||
|
||||
slave: $(SRC_CLNT)
|
||||
mkdir -p $(DESTDIR)
|
||||
$(CC) -o eigerDetectorServer_virtualSlave $(SRC_CLNT) $(CFLAGS) $(LDLIBS)
|
||||
mv eigerDetectorServer_virtualSlave $(DESTDIR)
|
||||
|
||||
clean:
|
||||
rm -rf $(DESTDIR)/eigerDetectorServer_virtualMaster $(DESTDIR)/eigerDetectorServer_virtualSlave *.o
|
||||
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/ansi.h
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
Binary file not shown.
@ -0,0 +1 @@
|
||||
../commonFiles/communication_funcs.c
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/communication_funcs.h
|
||||
@ -0,0 +1,9 @@
|
||||
Path: slsDetectorsPackage/slsDetectorSoftware/eigerDetectorServer
|
||||
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
|
||||
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
|
||||
Repsitory UUID: c52025dd7c4b44b93e64353a22997d971996ab18
|
||||
Revision: 350
|
||||
Branch: developer
|
||||
Last Changed Author: Gemma_Tinti
|
||||
Last Changed Rev: 3999
|
||||
Last Changed Date: 2018-09-28 14:11:53.000000002 +0200 ./Makefile.virtual
|
||||
@ -0,0 +1,6 @@
|
||||
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
|
||||
#define GITREPUUID "c52025dd7c4b44b93e64353a22997d971996ab18"
|
||||
#define GITAUTH "Gemma_Tinti"
|
||||
#define GITREV 0x3999
|
||||
#define GITDATE 0x20180928
|
||||
#define GITBRANCH "developer"
|
||||
@ -0,0 +1,6 @@
|
||||
#define GITURL ""
|
||||
#define GITREPUUID ""
|
||||
#define GITAUTH ""
|
||||
#define GITREV ""
|
||||
#define GITDATE ""
|
||||
#define GITBRANCH ""
|
||||
@ -0,0 +1,4 @@
|
||||
mv bin/eigerDetectorServer bin/$2
|
||||
cp bin/$2 /tftpboot
|
||||
git rm -f bin/$1
|
||||
git add bin/$2
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorFunctionList.h
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorServer.c
|
||||
@ -0,0 +1,100 @@
|
||||
/*
|
||||
* slsDetectorServer_defs.h
|
||||
*
|
||||
* Created on: Jan 24, 2013
|
||||
* Author: l_maliakal_d
|
||||
*/
|
||||
|
||||
#ifndef SLSDETECTORSERVER_DEFS_H_
|
||||
#define SLSDETECTORSERVER_DEFS_H_
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#define GOODBYE (-200)
|
||||
#define REQUIRED_FIRMWARE_VERSION (22)
|
||||
#define IDFILECOMMAND "more /home/root/executables/detid.txt"
|
||||
|
||||
#define STATUS_IDLE 0
|
||||
#define STATUS_RUNNING 1
|
||||
#define STATUS_ERROR 2
|
||||
|
||||
/* Enums */
|
||||
enum CLK_SPEED_INDEX {FULL_SPEED, HALF_SPEED, QUARTER_SPEED};
|
||||
enum DACINDEX {SVP,VTR,VRF,VRS,SVN,VTGSTV,VCMP_LL,VCMP_LR,CAL,VCMP_RL,RXB_RB,RXB_LB,VCMP_RR,VCP,VCN,VIS,VTHRESHOLD};
|
||||
#define DEFAULT_DAC_VALS { \
|
||||
0, /* SvP */ \
|
||||
2480, /* Vtr */ \
|
||||
3300, /* Vrf */ \
|
||||
1400, /* Vrs */ \
|
||||
4000, /* SvN */ \
|
||||
2556, /* Vtgstv */ \
|
||||
1000, /* Vcmp_ll */ \
|
||||
1000, /* Vcmp_lr */ \
|
||||
4000, /* cal */ \
|
||||
1000, /* Vcmp_rl */ \
|
||||
1100, /* rxb_rb */ \
|
||||
1100, /* rxb_lb */ \
|
||||
1000, /* Vcmp_rr */ \
|
||||
1000, /* Vcp */ \
|
||||
2000, /* Vcn */ \
|
||||
1550 /* Vis */ \
|
||||
};
|
||||
enum ADCINDEX {TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
|
||||
enum NETWORKINDEX {TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
|
||||
|
||||
|
||||
/* Hardware Definitions */
|
||||
#define NMAXMOD (1)
|
||||
#define NMOD (1)
|
||||
#define NCHAN (256 * 256)
|
||||
#define NCHIP (4)
|
||||
#define NADC (0)
|
||||
#define NDAC (16)
|
||||
#define NGAIN (0)
|
||||
#define NOFFSET (0)
|
||||
|
||||
|
||||
#define TEN_GIGA_BUFFER_SIZE (4112)
|
||||
#define ONE_GIGA_BUFFER_SIZE (1040)
|
||||
#define TEN_GIGA_CONSTANT (4)
|
||||
#define ONE_GIGA_CONSTANT (16)
|
||||
#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
|
||||
#define NORMAL_HIGHVOLTAGE_OUTPUTPORT "/sys/class/hwmon/hwmon5/device/out0_output"
|
||||
#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
|
||||
#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE (16)
|
||||
|
||||
/** Default Parameters */
|
||||
#define DEFAULT_MOD_INDEX (0)
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DEFAULT_EXPTIME (1E9) //ns
|
||||
#define DEFAULT_PERIOD (1E9) //ns
|
||||
#define DEFAULT_DELAY (0)
|
||||
#define DEFAULT_HIGH_VOLTAGE (0)
|
||||
#define DEFAULT_SETTINGS (DYNAMICGAIN)
|
||||
#define DEFAULT_SUBFRAME_EXPOSURE (2621440) // 2.6ms
|
||||
#define DEFAULT_SUBFRAME_DEADTIME (0)
|
||||
#define DEFAULT_DYNAMIC_RANGE (16)
|
||||
|
||||
#define DEFAULT_READOUT_MODE (NONPARALLEL)
|
||||
#define DEFAULT_READOUT_STOREINRAM_MODE (CONTINOUS_RO)
|
||||
#define DEFAULT_READOUT_OVERFLOW32_MODE (NOOVERFLOW)
|
||||
#define DEFAULT_CLK_SPEED (HALF_SPEED)
|
||||
#define DEFAULT_IO_DELAY (650)
|
||||
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
|
||||
#define DEFAULT_PHOTON_ENERGY (-1)
|
||||
#define DEFAULT_RATE_CORRECTION (0)
|
||||
#define DEFAULT_EXT_GATING_ENABLE (0)
|
||||
#define DEFAULT_EXT_GATING_POLARITY (1) //positive
|
||||
#define DEFAULT_TEST_MODE (0)
|
||||
#define DEFAULT_HIGH_VOLTAGE (0)
|
||||
|
||||
|
||||
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS (0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
|
||||
|
||||
#define SLAVE_HIGH_VOLTAGE_READ_VAL (-999)
|
||||
#define HIGH_VOLTAGE_TOLERANCE (5)
|
||||
|
||||
|
||||
#endif /* SLSDETECTORSERVER_DEFS_H_ */
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorServer_funcs.c
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/slsDetectorServer_funcs.h
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/sls_detector_defs.h
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/sls_detector_funcs.h
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/sls_receiver_defs.h
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/sls_receiver_funcs.h
|
||||
@ -0,0 +1,7 @@
|
||||
SRCFILE=gitInfoEiger.h
|
||||
DSTFILE=versionAPI.h
|
||||
|
||||
SRCPATTERN=GITDATE
|
||||
DSTPATTERN=APIEIGER
|
||||
|
||||
awk -v a="$SRCFILE" -v b="$DSTFILE" -v c="$SRCPATTERN" -v d="$DSTPATTERN" 'FNR==NR&&$2==c{x=$3} NR!=FNR{if($2==d){$3="0x"substr(x,5)}print > b}' $SRCFILE $DSTFILE
|
||||
@ -0,0 +1,32 @@
|
||||
SERVER=eigerDetectorServer
|
||||
MAINDIR=slsDetectorsPackage
|
||||
SPECDIR=slsDetectorSoftware/$SERVER
|
||||
TMPFILE=gitInfoEigerTmp.h
|
||||
INCLFILE=gitInfoEiger.h
|
||||
|
||||
#evaluate the variables
|
||||
EVALFILE=../../evalVersionVariables.sh
|
||||
source $EVALFILE
|
||||
|
||||
|
||||
#get modified date
|
||||
#RDATE1='git log --pretty=format:"%ci" -1'
|
||||
RDATE1="find ../slsDetectorServer . -type f -exec stat --format '%Y :%y %n' '{}' \; | sort -nr | cut -d: -f2- | egrep -v 'gitInfo|bin|.git|updateGitVersion|.o' | head -n 1"
|
||||
RDATE=`eval $RDATE1`
|
||||
NEWDATE=$(sed "s/-//g" <<< $RDATE | awk '{print $1;}')
|
||||
NEWDATE=${NEWDATE/#/0x}
|
||||
|
||||
|
||||
#get old date from INCLFILE
|
||||
OLDDATE=$(more $INCLFILE | grep '#define GITDATE' | awk '{print $3}')
|
||||
|
||||
|
||||
#update INCLFILE if changes
|
||||
if [ "$OLDDATE" != "$NEWDATE" ]; then
|
||||
echo Path: ${MAINDIR}/${SPECDIR} $'\n'URL: ${GITREPO} $'\n'Repository Root: ${GITREPO} $'\n'Repsitory UUID: ${REPUID} $'\n'Revision: ${FOLDERREV} $'\n'Branch: ${BRANCH} $'\n'Last Changed Author: ${AUTH1}_${AUTH2} $'\n'Last Changed Rev: ${REV} $'\n'Last Changed Date: ${RDATE} > gitInfo.txt
|
||||
cd ../../
|
||||
./genVersionHeader.sh $SPECDIR/gitInfo.txt $SPECDIR/$TMPFILE $SPECDIR/$INCLFILE
|
||||
cd $WD
|
||||
fi
|
||||
|
||||
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/versionAPI.h
|
||||
@ -0,0 +1,52 @@
|
||||
#ifndef __XFS_TYPES_H__
|
||||
#define __XFS_TYPES_H__
|
||||
|
||||
//#include "types.h"
|
||||
#include <stdint.h>
|
||||
/******************************************************************************/
|
||||
/* types */
|
||||
/******************************************************************************/
|
||||
|
||||
typedef unsigned int xfs_u32;
|
||||
typedef unsigned short xfs_u16;
|
||||
typedef unsigned char xfs_u8;
|
||||
|
||||
typedef signed int xfs_i32;
|
||||
typedef signed short xfs_i16;
|
||||
typedef signed char xfs_i8;
|
||||
|
||||
|
||||
// UDP Header
|
||||
struct udp_header_type
|
||||
{
|
||||
// ethternet frame (14 byte)
|
||||
uint8_t dst_mac[6];
|
||||
uint8_t src_mac[6];
|
||||
uint8_t len_type[2];
|
||||
|
||||
// ip header (20 byte)
|
||||
uint8_t ver_headerlen[1];
|
||||
uint8_t service_type[1];
|
||||
uint8_t total_length[2];
|
||||
uint8_t identification[2];
|
||||
uint8_t flags[1];
|
||||
uint8_t frag_offset[1];
|
||||
uint8_t time_to_live[1];
|
||||
uint8_t protocol[1];
|
||||
uint8_t ip_header_checksum[2];
|
||||
uint8_t src_ip[4];
|
||||
uint8_t dst_ip[4];
|
||||
|
||||
// udp header (8 byte)
|
||||
uint8_t src_port[2];
|
||||
uint8_t dst_port[2];
|
||||
uint8_t udp_message_len[2];
|
||||
uint8_t udp_checksum[2];
|
||||
|
||||
};
|
||||
|
||||
|
||||
|
||||
#endif // __XFS_TYPES_H__
|
||||
|
||||
|
||||
@ -0,0 +1,538 @@
|
||||
/* ONLY THOSE ARE USED IN THIS SOFTWARE. If one of those is modified in xilinx compilation, this file should be replaced with updated values
|
||||
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR
|
||||
XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR
|
||||
XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR
|
||||
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
|
||||
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR
|
||||
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
|
||||
*/
|
||||
/*******************************************************************
|
||||
*
|
||||
* CAUTION: This file is automatically generated by libgen.
|
||||
* Version: Xilinx EDK 12.4 EDK_MS4.81d
|
||||
* DO NOT EDIT.
|
||||
*
|
||||
* Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
|
||||
|
||||
*
|
||||
* Description: Driver parameters
|
||||
*
|
||||
*******************************************************************/
|
||||
|
||||
#define STDIN_BASEADDRESS 0xC0000000
|
||||
#define STDOUT_BASEADDRESS 0xC0000000
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral BB_IO_SHIFT_REG_PPC440 */
|
||||
#define XPAR_BB_IO_SHIFT_REG_PPC440_BASEADDR 0xD3000000
|
||||
#define XPAR_BB_IO_SHIFT_REG_PPC440_HIGHADDR 0xD300FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral EIGER_BEB_SYNCH_IO_PPC440 */
|
||||
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_BASEADDR 0xD3100000
|
||||
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_HIGHADDR 0xD310FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_BRAM_10G */
|
||||
#define XPAR_PLB_BRAM_10G_MEM0_BASEADDR 0xD4100000
|
||||
#define XPAR_PLB_BRAM_10G_MEM0_HIGHADDR 0xD410FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_BRAM_TEMAC */
|
||||
#define XPAR_PLB_BRAM_TEMAC_MEM0_BASEADDR 0xD4000000
|
||||
#define XPAR_PLB_BRAM_TEMAC_MEM0_HIGHADDR 0xD400FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_GPIO_SYS */
|
||||
#define XPAR_PLB_GPIO_SYS_BASEADDR 0xD1000000
|
||||
#define XPAR_PLB_GPIO_SYS_HIGHADDR 0xD100FFFF
|
||||
|
||||
/** Command Generator */
|
||||
#define XPAR_CMD_GENERATOR 0xC5000000
|
||||
|
||||
|
||||
/** Version Numbers */
|
||||
#define XPAR_VERSION 0xc6000000
|
||||
|
||||
/* Definitions for peripheral PLB_GPIO_TEST */
|
||||
#define XPAR_PLB_GPIO_TEST_BASEADDR 0xD1010000
|
||||
#define XPAR_PLB_GPIO_TEST_HIGHADDR 0xD101FFFF
|
||||
|
||||
|
||||
|
||||
/* Definitions for packet, frame and delay down counters */
|
||||
#define XPAR_COUNTER_BASEADDR 0xD1020000
|
||||
#define XPAR_COUNTER_HIGHADDR 0xD102FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT */
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR 0xC4100000
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_HIGHADDR 0xC410FFFF
|
||||
|
||||
/* Definitions for a new memory */
|
||||
//#define XPAR_PLB_LL_NEW_MEMORY 0xD1000000//0xD1000084//0xC4200000
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT */
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR 0xC4110000
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_HIGHADDR 0xC411FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_LEFT */
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR 0xC4120000
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_HIGHADDR 0xC412FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT */
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR 0xC4130000
|
||||
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_HIGHADDR 0xC413FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_LL_FIFO_XAUI_10G */
|
||||
#define XPAR_PLB_LL_FIFO_XAUI_10G_BASEADDR 0xC4140000
|
||||
#define XPAR_PLB_LL_FIFO_XAUI_10G_HIGHADDR 0xC414FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_V46_CPU_TO_PLB_V46_BRIDGED */
|
||||
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_BASEADDR 0xCFFF0000
|
||||
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_HIGHADDR 0xCFFFFFFF
|
||||
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_BASEADDR 0xD0000000
|
||||
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_HIGHADDR 0xDFFFFFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PPC_SRAM */
|
||||
#define XPAR_PPC_SRAM_BASEADDR 0x00000000
|
||||
#define XPAR_PPC_SRAM_HIGHADDR 0x01FFFFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral PFLASH */
|
||||
#define XPAR_PFLASH_NUM_BANKS_MEM 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for peripheral PFLASH */
|
||||
#define XPAR_PFLASH_MEM0_BASEADDR 0xE0000000
|
||||
#define XPAR_PFLASH_MEM0_HIGHADDR 0xE3FFFFFF
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral PFLASH */
|
||||
#define XPAR_EMC_0_NUM_BANKS_MEM 1
|
||||
#define XPAR_EMC_0_MEM0_BASEADDR 0xE0000000
|
||||
#define XPAR_EMC_0_MEM0_HIGHADDR 0xE3FFFFFF
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver PLB_SHT1X_IF */
|
||||
#define XPAR_PLB_SHT1X_IF_NUM_INSTANCES 2
|
||||
|
||||
/* Definitions for peripheral PLB_SHT1X_IF_CH1 */
|
||||
#define XPAR_PLB_SHT1X_IF_CH1_DEVICE_ID 0
|
||||
#define XPAR_PLB_SHT1X_IF_CH1_BASEADDR 0xD2200000
|
||||
#define XPAR_PLB_SHT1X_IF_CH1_HIGHADDR 0xD220FFFF
|
||||
|
||||
|
||||
/* Definitions for peripheral PLB_SHT1X_IF_CH2 */
|
||||
#define XPAR_PLB_SHT1X_IF_CH2_DEVICE_ID 1
|
||||
#define XPAR_PLB_SHT1X_IF_CH2_BASEADDR 0xD2210000
|
||||
#define XPAR_PLB_SHT1X_IF_CH2_HIGHADDR 0xD221FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver UARTLITE */
|
||||
#define XPAR_XUARTLITE_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral RS232 */
|
||||
#define XPAR_RS232_BASEADDR 0xC0000000
|
||||
#define XPAR_RS232_HIGHADDR 0xC000FFFF
|
||||
#define XPAR_RS232_DEVICE_ID 0
|
||||
#define XPAR_RS232_BAUDRATE 115200
|
||||
#define XPAR_RS232_USE_PARITY 0
|
||||
#define XPAR_RS232_ODD_PARITY 0
|
||||
#define XPAR_RS232_DATA_BITS 8
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral RS232 */
|
||||
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_DEVICE_ID
|
||||
#define XPAR_UARTLITE_0_BASEADDR 0xC0000000
|
||||
#define XPAR_UARTLITE_0_HIGHADDR 0xC000FFFF
|
||||
#define XPAR_UARTLITE_0_BAUDRATE 115200
|
||||
#define XPAR_UARTLITE_0_USE_PARITY 0
|
||||
#define XPAR_UARTLITE_0_ODD_PARITY 0
|
||||
#define XPAR_UARTLITE_0_DATA_BITS 8
|
||||
#define XPAR_UARTLITE_0_SIO_CHAN 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SPI */
|
||||
#define XPAR_XSPI_NUM_INSTANCES 2
|
||||
|
||||
/* Definitions for peripheral SPI_FLASH */
|
||||
#define XPAR_SPI_FLASH_DEVICE_ID 0
|
||||
#define XPAR_SPI_FLASH_BASEADDR 0xD2000000
|
||||
#define XPAR_SPI_FLASH_HIGHADDR 0xD200FFFF
|
||||
#define XPAR_SPI_FLASH_FIFO_EXIST 1
|
||||
#define XPAR_SPI_FLASH_SPI_SLAVE_ONLY 0
|
||||
#define XPAR_SPI_FLASH_NUM_SS_BITS 1
|
||||
#define XPAR_SPI_FLASH_NUM_TRANSFER_BITS 8
|
||||
|
||||
|
||||
/* Definitions for peripheral XPS_SPI_FEB_CFG */
|
||||
#define XPAR_XPS_SPI_FEB_CFG_DEVICE_ID 1
|
||||
#define XPAR_XPS_SPI_FEB_CFG_BASEADDR 0xD2010000
|
||||
#define XPAR_XPS_SPI_FEB_CFG_HIGHADDR 0xD201FFFF
|
||||
#define XPAR_XPS_SPI_FEB_CFG_FIFO_EXIST 1
|
||||
#define XPAR_XPS_SPI_FEB_CFG_SPI_SLAVE_ONLY 0
|
||||
#define XPAR_XPS_SPI_FEB_CFG_NUM_SS_BITS 2
|
||||
#define XPAR_XPS_SPI_FEB_CFG_NUM_TRANSFER_BITS 8
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral SPI_FLASH */
|
||||
#define XPAR_SPI_0_DEVICE_ID XPAR_SPI_FLASH_DEVICE_ID
|
||||
#define XPAR_SPI_0_BASEADDR 0xD2000000
|
||||
#define XPAR_SPI_0_HIGHADDR 0xD200FFFF
|
||||
#define XPAR_SPI_0_FIFO_EXIST 1
|
||||
#define XPAR_SPI_0_SPI_SLAVE_ONLY 0
|
||||
#define XPAR_SPI_0_NUM_SS_BITS 1
|
||||
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral XPS_SPI_FEB_CFG */
|
||||
#define XPAR_SPI_1_DEVICE_ID XPAR_XPS_SPI_FEB_CFG_DEVICE_ID
|
||||
#define XPAR_SPI_1_BASEADDR 0xD2010000
|
||||
#define XPAR_SPI_1_HIGHADDR 0xD201FFFF
|
||||
#define XPAR_SPI_1_FIFO_EXIST 1
|
||||
#define XPAR_SPI_1_SPI_SLAVE_ONLY 0
|
||||
#define XPAR_SPI_1_NUM_SS_BITS 2
|
||||
#define XPAR_SPI_1_NUM_TRANSFER_BITS 8
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver LLTEMAC */
|
||||
#define XPAR_XLLTEMAC_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral TEMAC_INST Channel 0 */
|
||||
#define XPAR_TEMAC_INST_CHAN_0_DEVICE_ID 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_BASEADDR 0xC3000000
|
||||
#define XPAR_TEMAC_INST_CHAN_0_HIGHADDR 0xC30FFFFF
|
||||
#define XPAR_TEMAC_INST_CHAN_0_TXCSUM 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_RXCSUM 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_PHY_TYPE 4
|
||||
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TRAN 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TRAN 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TAG 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TAG 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_STRP 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_STRP 0
|
||||
#define XPAR_TEMAC_INST_CHAN_0_MCAST_EXTEND 0
|
||||
|
||||
/* Canonical definitions for peripheral TEMAC_INST Channel 0 */
|
||||
#define XPAR_LLTEMAC_0_DEVICE_ID 0
|
||||
#define XPAR_LLTEMAC_0_BASEADDR 0xC3000000
|
||||
#define XPAR_LLTEMAC_0_HIGHADDR 0xC30FFFFF
|
||||
#define XPAR_LLTEMAC_0_TXCSUM 0
|
||||
#define XPAR_LLTEMAC_0_RXCSUM 0
|
||||
#define XPAR_LLTEMAC_0_PHY_TYPE 4
|
||||
#define XPAR_LLTEMAC_0_TXVLAN_TRAN 0
|
||||
#define XPAR_LLTEMAC_0_RXVLAN_TRAN 0
|
||||
#define XPAR_LLTEMAC_0_TXVLAN_TAG 0
|
||||
#define XPAR_LLTEMAC_0_RXVLAN_TAG 0
|
||||
#define XPAR_LLTEMAC_0_TXVLAN_STRP 0
|
||||
#define XPAR_LLTEMAC_0_RXVLAN_STRP 0
|
||||
#define XPAR_LLTEMAC_0_MCAST_EXTEND 0
|
||||
#define XPAR_LLTEMAC_0_INTR 1
|
||||
|
||||
|
||||
/* LocalLink TYPE Enumerations */
|
||||
#define XPAR_LL_FIFO 1
|
||||
#define XPAR_LL_DMA 2
|
||||
|
||||
|
||||
/* Canonical LocalLink parameters for TEMAC_INST */
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Definitions for peripheral XPS_BRAM_IF_CNTLR_PPC440 */
|
||||
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_BASEADDR 0xFFFC0000
|
||||
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_HIGHADDR 0xFFFFFFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 5
|
||||
#define XPAR_XINTC_HAS_IPR 1
|
||||
#define XPAR_XINTC_USE_DCR 0
|
||||
/* Definitions for driver INTC */
|
||||
#define XPAR_XINTC_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral XPS_INTC_PPC440 */
|
||||
#define XPAR_XPS_INTC_PPC440_DEVICE_ID 0
|
||||
#define XPAR_XPS_INTC_PPC440_BASEADDR 0xC1000000
|
||||
#define XPAR_XPS_INTC_PPC440_HIGHADDR 0xC100FFFF
|
||||
#define XPAR_XPS_INTC_PPC440_KIND_OF_INTR 0xFFFFFFF4
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
#define XPAR_INTC_SINGLE_BASEADDR 0xC1000000
|
||||
#define XPAR_INTC_SINGLE_HIGHADDR 0xC100FFFF
|
||||
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
|
||||
#define XPAR_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_MASK 0X000001
|
||||
#define XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR 0
|
||||
#define XPAR_TEMAC_INST_TEMACINTC0_IRPT_MASK 0X000002
|
||||
#define XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR 1
|
||||
#define XPAR_XPS_TIMER_PPC440_INTERRUPT_MASK 0X000004
|
||||
#define XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR 2
|
||||
#define XPAR_SPI_FLASH_IP2INTC_IRPT_MASK 0X000008
|
||||
#define XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR 3
|
||||
#define XPAR_RS232_INTERRUPT_MASK 0X000010
|
||||
#define XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR 4
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral XPS_INTC_PPC440 */
|
||||
#define XPAR_INTC_0_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
|
||||
#define XPAR_INTC_0_BASEADDR 0xC1000000
|
||||
#define XPAR_INTC_0_HIGHADDR 0xC100FFFF
|
||||
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFF4
|
||||
|
||||
#define XPAR_INTC_0_LLFIFO_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
|
||||
#define XPAR_INTC_0_LLTEMAC_0_VEC_ID XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
|
||||
#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
|
||||
#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
|
||||
#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver LLFIFO */
|
||||
#define XPAR_XLLFIFO_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral XPS_LL_FIFO_TEMAC */
|
||||
#define XPAR_XPS_LL_FIFO_TEMAC_DEVICE_ID 0
|
||||
#define XPAR_XPS_LL_FIFO_TEMAC_BASEADDR 0xC4000000
|
||||
#define XPAR_XPS_LL_FIFO_TEMAC_HIGHADDR 0xC400FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for peripheral XPS_LL_FIFO_TEMAC */
|
||||
#define XPAR_LLFIFO_0_DEVICE_ID XPAR_XPS_LL_FIFO_TEMAC_DEVICE_ID
|
||||
#define XPAR_LLFIFO_0_BASEADDR 0xC4000000
|
||||
#define XPAR_LLFIFO_0_HIGHADDR 0xC400FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver SYSMON */
|
||||
#define XPAR_XSYSMON_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral XPS_SYSMON_ADC_PPC440 */
|
||||
#define XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID 0
|
||||
#define XPAR_XPS_SYSMON_ADC_PPC440_BASEADDR 0xD0010000
|
||||
#define XPAR_XPS_SYSMON_ADC_PPC440_HIGHADDR 0xD001FFFF
|
||||
#define XPAR_XPS_SYSMON_ADC_PPC440_INCLUDE_INTR 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral XPS_SYSMON_ADC_PPC440 */
|
||||
#define XPAR_SYSMON_0_DEVICE_ID XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID
|
||||
#define XPAR_SYSMON_0_BASEADDR 0xD0010000
|
||||
#define XPAR_SYSMON_0_HIGHADDR 0xD001FFFF
|
||||
#define XPAR_SYSMON_0_INCLUDE_INTR 1
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for driver TMRCTR */
|
||||
#define XPAR_XTMRCTR_NUM_INSTANCES 1
|
||||
|
||||
/* Definitions for peripheral XPS_TIMER_PPC440 */
|
||||
#define XPAR_XPS_TIMER_PPC440_DEVICE_ID 0
|
||||
#define XPAR_XPS_TIMER_PPC440_BASEADDR 0xC2000000
|
||||
#define XPAR_XPS_TIMER_PPC440_HIGHADDR 0xC200FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
|
||||
/* Canonical definitions for peripheral XPS_TIMER_PPC440 */
|
||||
#define XPAR_TMRCTR_0_DEVICE_ID XPAR_XPS_TIMER_PPC440_DEVICE_ID
|
||||
#define XPAR_TMRCTR_0_BASEADDR 0xC2000000
|
||||
#define XPAR_TMRCTR_0_HIGHADDR 0xC200FFFF
|
||||
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
/* Definitions for bus frequencies */
|
||||
#define XPAR_CPU_PPC440_MPLB_FREQ_HZ 100000000
|
||||
/******************************************************************/
|
||||
|
||||
/* Canonical definitions for bus frequencies */
|
||||
#define XPAR_PROC_BUS_0_FREQ_HZ 100000000
|
||||
/******************************************************************/
|
||||
|
||||
#define XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ 400000000
|
||||
#define XPAR_PPC440_VIRTEX5_CORE_CLOCK_FREQ_HZ 400000000
|
||||
#define XPAR_CPU_PPC440_IDCR_BASEADDR 0x00000000
|
||||
/******************************************************************/
|
||||
#define XPAR_CPU_ID 0
|
||||
#define XPAR_PPC440_VIRTEX5_ID 0
|
||||
#define XPAR_PPC440_VIRTEX5_PIR 0b1111
|
||||
#define XPAR_PPC440_VIRTEX5_ENDIAN_RESET 0
|
||||
#define XPAR_PPC440_VIRTEX5_USER_RESET 0b0000
|
||||
#define XPAR_PPC440_VIRTEX5_INTERCONNECT_IMASK 0xffffffff
|
||||
#define XPAR_PPC440_VIRTEX5_ICU_RD_FETCH_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_ICU_RD_SPEC_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_ICU_RD_TOUCH_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_RD_LD_CACHE_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_RD_NONCACHE_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_RD_TOUCH_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_RD_URGENT_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_WR_FLUSH_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_WR_STORE_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DCU_WR_URGENT_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_PLB_PRIO 0b00
|
||||
#define XPAR_PPC440_VIRTEX5_IDCR_BASEADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_IDCR_HIGHADDR 0x000000FF
|
||||
#define XPAR_PPC440_VIRTEX5_APU_CONTROL 0b00010000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_0 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_1 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_2 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_3 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_4 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_5 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_6 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_7 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_8 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_9 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_10 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_11 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_12 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_13 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_14 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_APU_UDI_15 0b000000000000000000000000
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_BASE 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_HIGH 0X01FFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_ROW_CONFLICT_MASK 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_BANK_CONFLICT_MASK 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_CONTROL 0X8140008F
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_ICU 4
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUW 3
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUR 2
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB1 0
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB0 1
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_ARB_MODE 0
|
||||
#define XPAR_PPC440_VIRTEX5_PPC440MC_MAX_BURST 8
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_AWIDTH 32
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_NATIVE_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_COUNTER 0x00000500
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_ICU 4
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUW 3
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUR 2
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB1 0
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB0 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_ARB_MODE 0
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_SYNC_TATTRIBUTE 0
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_MAX_BURST 8
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_ALLOW_LOCK_XFER 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_READ_PIPE_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_PIPE_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_POST_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_P2P 0
|
||||
#define XPAR_PPC440_VIRTEX5_MPLB_WDOG_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_AWIDTH 32
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_NATIVE_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_SUPPORT_BURSTS 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_USE_MPLB_ADDR 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MPLB_ADDR_RNG 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MASTERS 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_MID_WIDTH 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_ALLOW_LOCK_XFER 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_READ_PIPE_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_PROPAGATE_MIRQ 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB0_P2P -1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_AWIDTH 32
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_NATIVE_DWIDTH 128
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_SUPPORT_BURSTS 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_USE_MPLB_ADDR 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MPLB_ADDR_RNG 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_BASEADDR 0xFFFFFFFF
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_HIGHADDR 0x00000000
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MASTERS 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_MID_WIDTH 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_ALLOW_LOCK_XFER 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_READ_PIPE_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_PROPAGATE_MIRQ 0
|
||||
#define XPAR_PPC440_VIRTEX5_SPLB1_P2P -1
|
||||
#define XPAR_PPC440_VIRTEX5_NUM_DMA 0
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_TXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_RXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_CONTROL 0b00000000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_TXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA0_RXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_TXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_RXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_CONTROL 0b00000000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_TXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA1_RXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_TXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_RXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_CONTROL 0b00000000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_TXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA2_RXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_TXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_RXCHANNELCTRL 0x01010000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_CONTROL 0b00000000
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_TXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DMA3_RXIRQTIMER 0b1111111111
|
||||
#define XPAR_PPC440_VIRTEX5_DCR_AUTOLOCK_ENABLE 1
|
||||
#define XPAR_PPC440_VIRTEX5_PPCDM_ASYNCMODE 0
|
||||
#define XPAR_PPC440_VIRTEX5_PPCDS_ASYNCMODE 0
|
||||
#define XPAR_PPC440_VIRTEX5_GENERATE_PLB_TIMESPECS 1
|
||||
#define XPAR_PPC440_VIRTEX5_HW_VER "1.01.a"
|
||||
|
||||
/******************************************************************/
|
||||
|
||||
@ -0,0 +1 @@
|
||||
AXIS_BUILDTYPE ?= cris-axis-linux-gnu
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/AD9257.h
|
||||
51
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/Makefile
Executable file
51
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/Makefile
Executable file
@ -0,0 +1,51 @@
|
||||
# $Id: Makefile,v 1.1.1.1 2006/02/04 03:35:01 freza Exp $
|
||||
# first compile
|
||||
# make cris-axis-linux-gnu
|
||||
|
||||
|
||||
CROSS = bfin-uclinux-
|
||||
CC = $(CROSS)gcc
|
||||
|
||||
CFLAGS += -Wall -DGOTTHARDD -DMCB_FUNCS -DDACS_INT -DDEBUG # -DVERBOSE #-DVERYVERBOSE #-DVIRTUAL #-DDACS_INT_CSERVER
|
||||
|
||||
|
||||
PROGS= gotthardDetectorServer
|
||||
INSTDIR= /tftpboot
|
||||
INSTMODE= 0777
|
||||
|
||||
|
||||
|
||||
BINS = testlib_sharedlibc
|
||||
SRCS = server.c firmware_funcs.c server_funcs.c communication_funcs.c mcb_funcs.c
|
||||
OBJS = $(SRCS:%.c=%.o)
|
||||
|
||||
|
||||
|
||||
all: clean versioning $(PROGS)
|
||||
|
||||
boot: $(OBJS)
|
||||
|
||||
versioning:
|
||||
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
|
||||
|
||||
$(PROGS): $(OBJS)
|
||||
# echo $(OBJS)
|
||||
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@)
|
||||
rm gotthardDetectorServer.gdb
|
||||
|
||||
|
||||
install: $(PROGS)
|
||||
$(INSTALL) -d $(INSTDIR)
|
||||
$(INSTALL) -m $(INSTMODE) $(PROGS) $(INSTDIR)
|
||||
|
||||
|
||||
romfs:
|
||||
$(ROMFSINST) /bin/$(PROGS)
|
||||
|
||||
clean:
|
||||
rm -rf $(PROGS) *.o *.gdb
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,49 @@
|
||||
# $Id: Makefile,v 1.1.1.1 2006/02/04 03:35:01 freza Exp $
|
||||
# first compile
|
||||
# make cris-axis-linux-gnu
|
||||
|
||||
|
||||
CROSS = bfin-uclinux-
|
||||
CC = $(CROSS)gcc
|
||||
|
||||
CFLAGS += -Wall -DGOTTHARDD -DPROPIXD -DMCB_FUNCS -DDACS_INT -DDEBUG # -DVERBOSE #-DVERYVERBOSE #-DVIRTUAL #-DDACS_INT_CSERVER
|
||||
|
||||
|
||||
PROGS= propixDetectorServer
|
||||
INSTDIR= /tftpboot
|
||||
INSTMODE= 0777
|
||||
|
||||
|
||||
|
||||
BINS = testlib_sharedlibc
|
||||
SRCS = server.c server_funcs.c communication_funcs.c firmware_funcs.c mcb_funcs.c
|
||||
OBJS = $(SRCS:%.c=%.o)
|
||||
|
||||
|
||||
|
||||
all: clean $(PROGS)
|
||||
|
||||
boot: $(OBJS)
|
||||
|
||||
$(PROGS): $(OBJS)
|
||||
echo $(OBJS)
|
||||
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
|
||||
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@)
|
||||
|
||||
|
||||
install: $(PROGS)
|
||||
$(INSTALL) -d $(INSTDIR)
|
||||
$(INSTALL) -m $(INSTMODE) $(PROGS) $(INSTDIR)
|
||||
|
||||
|
||||
romfs:
|
||||
$(ROMFSINST) /bin/$(PROGS)
|
||||
|
||||
clean:
|
||||
rm -rf $(PROGS) *.o *.gdb
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1,30 @@
|
||||
|
||||
DESTDIR ?= ./
|
||||
|
||||
CC = gcc
|
||||
CFLAGS += -Wall -DGOTTHARDD -DMCB_FUNCS -DDACS_INT -DDEBUG -DVIRTUAL
|
||||
|
||||
|
||||
PROGS= $(DESTDIR)/gotthardDetectorServer_virtual
|
||||
|
||||
|
||||
SRCS = server.c server_funcs.c communication_funcs.c firmware_funcs.c mcb_funcs.c
|
||||
OBJS = $(SRCS:%.c=%.o)
|
||||
|
||||
gotthardVirtualServer = $(PROGS)
|
||||
|
||||
all: clean $(PROGS)
|
||||
|
||||
|
||||
$(PROGS): $(OBJS)
|
||||
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@)
|
||||
|
||||
|
||||
clean:
|
||||
rm -rf $(PROGS) *.o *.gdb
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/ansi.h
|
||||
@ -0,0 +1 @@
|
||||
../slsDetectorServer/commonServerFunctions.h
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/communication_funcs.c
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/communication_funcs.h
|
||||
@ -0,0 +1,23 @@
|
||||
#masterflags (no_master, is_master, is_slave)
|
||||
masterflags no_master
|
||||
|
||||
#master default delay
|
||||
masterdefaultdelay 70
|
||||
|
||||
#patternphase
|
||||
patternphase 0
|
||||
|
||||
#adcphase
|
||||
adcphase 0
|
||||
|
||||
#slave pattern phase
|
||||
slavepatternphase 0
|
||||
|
||||
#slave adc phase
|
||||
slaveadcphase 0
|
||||
|
||||
#rst to sw1 delay
|
||||
rsttosw1delay 2
|
||||
|
||||
#start acquisition delay
|
||||
startacqdelay 1
|
||||
1922
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/firmware_funcs.c
Executable file
1922
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/firmware_funcs.c
Executable file
File diff suppressed because it is too large
Load Diff
179
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/firmware_funcs.h
Executable file
179
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/firmware_funcs.h
Executable file
@ -0,0 +1,179 @@
|
||||
#ifndef FIRMWARE_FUNCS_H
|
||||
#define FIRMWARE_FUNCS_H
|
||||
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <sys/mman.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdarg.h>
|
||||
#include <unistd.h>
|
||||
//#include <asm/page.h>
|
||||
#include <sys/mman.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdarg.h>
|
||||
#include <unistd.h>
|
||||
|
||||
|
||||
int mapCSP0(void);
|
||||
|
||||
u_int16_t bus_r16(u_int32_t offset);
|
||||
u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
|
||||
u_int32_t bus_w(u_int32_t offset, u_int32_t data);
|
||||
u_int32_t bus_r(u_int32_t offset);
|
||||
|
||||
void setMasterSlaveConfiguration();
|
||||
int setPhaseShiftOnce();
|
||||
int setPhaseShift(int numphaseshift);
|
||||
int cleanFifo();
|
||||
int setDAQRegister();
|
||||
|
||||
u_int32_t putout(char *s, int modnum);
|
||||
u_int32_t readin(int modnum);
|
||||
u_int32_t setClockDivider(int d);
|
||||
u_int32_t getClockDivider();
|
||||
u_int32_t setSetLength(int d);
|
||||
u_int32_t getSetLength();
|
||||
u_int32_t setWaitStates(int d);
|
||||
u_int32_t getWaitStates();
|
||||
u_int32_t setTotClockDivider(int d);
|
||||
u_int32_t getTotClockDivider();
|
||||
u_int32_t setTotDutyCycle(int d);
|
||||
u_int32_t getTotDutyCycle();
|
||||
|
||||
u_int32_t setExtSignal(enum externalSignalFlag mode);
|
||||
int getExtSignal();
|
||||
|
||||
u_int32_t setFPGASignal(enum externalSignalFlag mode);
|
||||
int getFPGASignal();
|
||||
|
||||
int setTiming(int t);
|
||||
|
||||
|
||||
int setConfigurationRegister(int d);
|
||||
int setToT(int d);
|
||||
int setContinousReadOut(int d);
|
||||
int startReceiver(int d);
|
||||
|
||||
int setDACRegister(int idac, int val, int imod);
|
||||
|
||||
int getTemperature(int tempSensor,int imod);
|
||||
int initHighVoltage(int val,int imod);
|
||||
int initConfGain(int isettings,int val,int imod);
|
||||
|
||||
int setADC(int adc);
|
||||
int configureMAC(int ipad, long long int macad, long long int detectormacadd, int detipad, int ival, int udpport);
|
||||
int getAdcConfigured();
|
||||
|
||||
|
||||
u_int64_t getDetectorNumber();
|
||||
u_int32_t getFirmwareVersion();
|
||||
u_int32_t getFirmwareSVNVersion();
|
||||
int testFifos(void);
|
||||
u_int32_t testFpga(void);
|
||||
int testBus(void);
|
||||
int setDigitalTestBit(int ival);
|
||||
|
||||
int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
|
||||
int64_t get64BitReg(int aLSB, int aMSB);
|
||||
|
||||
int64_t setFrames(int64_t value);
|
||||
int64_t getFrames();
|
||||
|
||||
int64_t setExposureTime(int64_t value);
|
||||
int64_t getExposureTime();
|
||||
|
||||
int64_t setGates(int64_t value);
|
||||
int64_t getGates();
|
||||
|
||||
int64_t setDelay(int64_t value);
|
||||
int64_t getDelay();
|
||||
|
||||
int64_t setPeriod(int64_t value);
|
||||
int64_t getPeriod();
|
||||
|
||||
int64_t setTrains(int64_t value);
|
||||
int64_t getTrains();
|
||||
|
||||
int64_t setProbes(int64_t value);
|
||||
int64_t getProbes();
|
||||
|
||||
int64_t getProgress();
|
||||
int64_t setProgress();
|
||||
|
||||
int64_t getActualTime();
|
||||
int64_t getMeasurementTime();
|
||||
|
||||
|
||||
u_int32_t runBusy(void);
|
||||
u_int32_t runState(void);
|
||||
u_int32_t dataPresent(void);
|
||||
|
||||
|
||||
int startStateMachine();
|
||||
int stopStateMachine();
|
||||
int startReadOut();
|
||||
u_int32_t fifoReset(void);
|
||||
u_int32_t fifoReadCounter(int fifonum);
|
||||
u_int32_t fifoReadStatus();
|
||||
|
||||
|
||||
u_int32_t fifo_full(void);
|
||||
|
||||
|
||||
void waitForAcquisitionFinish();
|
||||
|
||||
u_int32_t* decode_data(int* datain);
|
||||
//u_int32_t move_data(u_int64_t* datain, u_int64_t* dataout);
|
||||
int setDynamicRange(int dr);
|
||||
int getDynamicRange();
|
||||
int getNModBoard();
|
||||
int setNMod(int n);
|
||||
int setStoreInRAM(int b);
|
||||
|
||||
|
||||
|
||||
|
||||
int setMaster(int f);
|
||||
int setSynchronization(int s);
|
||||
|
||||
int loadImage(int index, short int ImageVals[]);
|
||||
int readCounterBlock(int startACQ, short int CounterVals[]);
|
||||
int resetCounterBlock(int startACQ);
|
||||
|
||||
int calibratePedestal(int frames);
|
||||
|
||||
|
||||
|
||||
/*
|
||||
|
||||
u_int32_t setNBits(u_int32_t);
|
||||
u_int32_t getNBits();
|
||||
*/
|
||||
|
||||
/*
|
||||
//move to mcb_funcs?
|
||||
|
||||
int readOutChan(int *val);
|
||||
u_int32_t getModuleNumber(int modnum);
|
||||
int testShiftIn(int imod);
|
||||
int testShiftOut(int imod);
|
||||
int testShiftStSel(int imod);
|
||||
int testDataInOut(int num, int imod);
|
||||
int testExtPulse(int imod);
|
||||
int testExtPulseMux(int imod, int ow);
|
||||
int testDataInOutMux(int imod, int ow, int num);
|
||||
int testOutMux(int imod);
|
||||
int testFpgaMux(int imod);
|
||||
int calibration_sensor(int num, int *values, int *dacs) ;
|
||||
int calibration_chip(int num, int *values, int *dacs);
|
||||
*/
|
||||
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,9 @@
|
||||
Path: slsDetectorsPackage/slsDetectorSoftware/gotthardDetectorServer
|
||||
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
|
||||
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
|
||||
Repsitory UUID: c52025dd7c4b44b93e64353a22997d971996ab18
|
||||
Revision: 237
|
||||
Branch: developer
|
||||
Last Changed Author: Gemma_Tinti
|
||||
Last Changed Rev: 3999
|
||||
Last Changed Date: 2018-09-28 16:10:41.000000002 +0200 ./server_funcs.c
|
||||
@ -0,0 +1,6 @@
|
||||
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
|
||||
#define GITREPUUID "c52025dd7c4b44b93e64353a22997d971996ab18"
|
||||
#define GITAUTH "Gemma_Tinti"
|
||||
#define GITREV 0x3999
|
||||
#define GITDATE 0x20180928
|
||||
#define GITBRANCH "developer"
|
||||
@ -0,0 +1,6 @@
|
||||
#define GITURL ""
|
||||
#define GITREPUUID ""
|
||||
#define GITAUTH ""
|
||||
#define GITREV ""
|
||||
#define GITDATE ""
|
||||
#define GITBRANCH ""
|
||||
Binary file not shown.
Binary file not shown.
Binary file not shown.
2340
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/mcb_funcs.c
Executable file
2340
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/mcb_funcs.c
Executable file
File diff suppressed because it is too large
Load Diff
183
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/mcb_funcs.h
Executable file
183
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/mcb_funcs.h
Executable file
@ -0,0 +1,183 @@
|
||||
#ifdef MCB_FUNCS
|
||||
|
||||
#ifndef MCB_FUNCS_H
|
||||
#define MCB_FUNCS_H
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#define RGPRVALS {100,50,200}
|
||||
#define RGSH1VALS {300,200,400}
|
||||
#define RGSH2VALS {260,300,260}
|
||||
|
||||
// high,dynamic,low,medium,very high
|
||||
#define CONF_GAIN {0,0, 0, 8, 6, 2, 1}//dynamic gain confgain yet to be figured out-probably 8 or 16
|
||||
|
||||
|
||||
#define DEFAULTGAIN {11.66,9.32,14.99}
|
||||
#define DEFAULTOFFSET {817.5,828.6,804.2}
|
||||
|
||||
// DAC definitions
|
||||
enum dacsVal{VREF_DS, VCASCN_PB, VCASCP_PB, VOUT_CM, VCASC_OUT, VIN_CM, VREF_COMP, IB_TESTC,HIGH_VOLTAGE, CONFGAIN};
|
||||
#define DEFAULT_DAC_VALS { \
|
||||
660, /* VREF_DS */ \
|
||||
650, /* VCASCN_PB */ \
|
||||
1480, /* VCASCP_PB */ \
|
||||
1520, /* VOUT_CM */ \
|
||||
1320, /* VCASC_OUT */ \
|
||||
1350, /* VIN_CM */ \
|
||||
350, /* VREF_COMP */ \
|
||||
2001 /* IB_TESTC */ \
|
||||
};
|
||||
|
||||
/* DAC adresses */
|
||||
#define DACCS {0,0,1,1,2,2,3,3,4,4,5,5,6,6}
|
||||
#define DACADDR {0,1,0,1,0,1,0,1,0,1,0,1,0,1}
|
||||
|
||||
//Register Definitions for temp,hv,dac gain
|
||||
enum adcVals{TEMP_FPGA, TEMP_ADC};
|
||||
|
||||
//dynamic range
|
||||
/*
|
||||
#define MAX5523 commented out by dhanya
|
||||
#ifndef MAX5523
|
||||
#define MAX5533
|
||||
#endif
|
||||
#ifdef MAX5533
|
||||
#define DAC_DR 4096
|
||||
#endif
|
||||
#ifdef MAX5523
|
||||
*/
|
||||
#define DAC_DR 1024
|
||||
//#endif
|
||||
|
||||
|
||||
//reference voltage
|
||||
#define DAC_REFOUT1
|
||||
#ifdef DAC_REFOUT2
|
||||
#define DAC_MAX 2.425
|
||||
#define DAC_REFOUT 2
|
||||
#define DAC_REFOUT1
|
||||
#endif
|
||||
#ifdef DAC_REFOUT3
|
||||
#define DAC_MAX 3.885
|
||||
#define DAC_REFOUT 3
|
||||
#define DAC_REFOUT1
|
||||
#endif
|
||||
#ifdef DAC_REFOUT0
|
||||
#define DAC_MAX 1.214
|
||||
#define DAC_REFOUT 0
|
||||
#endif
|
||||
#ifdef DAC_REFOUT1
|
||||
#define DAC_MAX 1.940
|
||||
#define DAC_REFOUT 1
|
||||
#endif
|
||||
|
||||
/* dac calibration constants */
|
||||
|
||||
#define VA 1.11
|
||||
|
||||
#define CVTRIM 52.430851
|
||||
#define BVTRIM -0.102022
|
||||
#define AVTRIM 0.000050
|
||||
|
||||
#define PARTREF {100,1.55,-2.5,-2.5,0,-2.5}
|
||||
#define PARTR1 {78,10,10,10,10,10}
|
||||
#define PARTR2 {0,4.7,27,47,22,47}
|
||||
|
||||
|
||||
//chip shiftin register meaning
|
||||
#define OUTMUX_OFFSET 20
|
||||
#define PROBES_OFFSET 4
|
||||
#define OUTBUF_OFFSET 0
|
||||
|
||||
|
||||
void showbits(int h);
|
||||
|
||||
int initDetector();
|
||||
int setDefaultDacs();
|
||||
int copyChannel(sls_detector_channel *destChan, sls_detector_channel *srcChan);
|
||||
int copyChip(sls_detector_chip *destChip, sls_detector_chip *srcChip);
|
||||
int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod);
|
||||
|
||||
/* Register commands */
|
||||
int clearDACSregister(int imod );
|
||||
int nextDAC(int imod );
|
||||
int clearCSregister(int imod );
|
||||
int setCSregister(int imod );
|
||||
int nextChip(int imod );
|
||||
int firstChip(int imod );
|
||||
int clearSSregister(int imod );
|
||||
int setSSregister(int imod );
|
||||
int nextStrip(int imod );
|
||||
int selChannel(int strip,int imod );
|
||||
int selChip(int chip,int imod );
|
||||
int selMod(int mod,int imod );
|
||||
|
||||
/* DACs routines */
|
||||
int program_one_dac(int addr, int value,int imod );
|
||||
int set_one_dac(int imod);
|
||||
int initDAC(int dac_addr, int value,int imod );
|
||||
int initDACs(int* v,int imod );
|
||||
int setSettings(int i,int imod);
|
||||
int initDACbyIndex(int ind,int val, int imod);
|
||||
int initDACbyIndexDACU(int ind,int val, int imod, int mV, int retval[]);
|
||||
int getDACbyIndexDACU(int ind, int imod);
|
||||
|
||||
/* Other DAC index routines*/
|
||||
int getTemperatureByModule(int tempSensor, int imod);
|
||||
int initHighVoltageByModule(int val, int imod);
|
||||
int initConfGainByModule(int isettings,int val,int imod);
|
||||
|
||||
/* Initialization*/
|
||||
int initChannel(int ft,int cae, int ae, int coe, int ocoe, int counts,int imod );
|
||||
int initChannelbyNumber(sls_detector_channel myChan);
|
||||
int getChannelbyNumber(sls_detector_channel*);
|
||||
|
||||
int getTrimbit(int imod, int ichip, int ichan);
|
||||
|
||||
int initChip(int obe, int ow,int imod );
|
||||
|
||||
int initChipWithProbes(int obe, int ow,int nprobes, int imod);
|
||||
//int getNProbes();
|
||||
|
||||
int initChipbyNumber(sls_detector_chip myChip);
|
||||
int getChipbyNumber(sls_detector_chip*);
|
||||
int initMCBregisters(int cm,int imod );
|
||||
int initModulebyNumber(sls_detector_module);
|
||||
int getModulebyNumber(sls_detector_module*);
|
||||
|
||||
/* To chips */
|
||||
int clearCounter(int imod );
|
||||
int clearOutReg(int imod);
|
||||
int setOutReg(int imod );
|
||||
int extPulse(int ncal,int imod );
|
||||
int calPulse(int ncal,int imod );
|
||||
int counterClear(int imod );
|
||||
int countEnable(int imod );
|
||||
int counterSet(int imod );
|
||||
|
||||
|
||||
/* moved from firmware_funcs */
|
||||
|
||||
int readOutChan(int *val);
|
||||
|
||||
int getModuleNumber(int modnum);
|
||||
int testShiftIn(int imod);
|
||||
int testShiftOut(int imod);
|
||||
int testShiftStSel(int imod);
|
||||
int testDataInOut(int num, int imod);
|
||||
int testExtPulse(int imod);
|
||||
int testExtPulseMux(int imod, int ow);
|
||||
int testDataInOutMux(int imod, int ow, int num);
|
||||
int testOutMux(int imod);
|
||||
int testFpgaMux(int imod);
|
||||
int calibration_sensor(int num, int *values, int *dacs) ;
|
||||
int calibration_chip(int num, int *values, int *dacs);
|
||||
|
||||
|
||||
|
||||
ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
315
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/registers_g.h
Executable file
315
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/registers_g.h
Executable file
@ -0,0 +1,315 @@
|
||||
#ifndef REGISTERS_G_H
|
||||
#define REGISTERS_G_H
|
||||
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
|
||||
/* Definitions for FPGA*/
|
||||
#define CSP0 0x20200000
|
||||
#define MEM_SIZE 0x100000
|
||||
|
||||
|
||||
|
||||
/* values defined for FPGA */
|
||||
#define MCSNUM 0x0
|
||||
#define FIXED_PATT_VAL 0xacdc1980
|
||||
|
||||
|
||||
#define FPGA_INIT_PAT 0x60008
|
||||
#define FPGA_INIT_ADDR 0xb0000000
|
||||
|
||||
|
||||
|
||||
|
||||
/* registers defined in FPGA */
|
||||
#define PCB_REV_REG 0x2c<<11
|
||||
#define GAIN_REG 0x10<<11
|
||||
//#define FLOW_CONTROL_REG 0x11<<11
|
||||
//#define FLOW_STATUS_REG 0x12<<11
|
||||
//#define FRAME_REG 0x13<<11
|
||||
#define MULTI_PURPOSE_REG 0x14<<11
|
||||
#define DAQ_REG 0x15<<11
|
||||
//#define TIME_FROM_START_REG 0x16<<11
|
||||
#define MCB_CNTRL_REG_OFF 0x17<<11// control the dacs
|
||||
//ADC
|
||||
#define ADC_SPI_REG 0x18<<11
|
||||
|
||||
#define ADC_SERIAL_CLK_OUT_OFST (0)
|
||||
#define ADC_SERIAL_CLK_OUT_MSK (0x00000001 << ADC_SERIAL_CLK_OUT_OFST)
|
||||
#define ADC_SERIAL_DATA_OUT_OFST (1)
|
||||
#define ADC_SERIAL_DATA_OUT_MSK (0x00000001 << ADC_SERIAL_DATA_OUT_OFST)
|
||||
#define ADC_SERIAL_CS_OUT_OFST (2)
|
||||
#define ADC_SERIAL_CS_OUT_MSK (0x0000000F << ADC_SERIAL_CS_OUT_OFST)
|
||||
|
||||
|
||||
#define ADC_SYNC_REG 0x19<<11
|
||||
//#define MUTIME_REG 0x1a<<11
|
||||
//temperature
|
||||
#define TEMP_IN_REG 0x1b<<11
|
||||
#define TEMP_OUT_REG 0x1c<<11
|
||||
//configure MAC
|
||||
#define TSE_CONF_REG 0x1d<<11
|
||||
#define ENET_CONF_REG 0x1e<<11
|
||||
//#define WRTSE_SHAD_REG 0x1f<<11
|
||||
//HV
|
||||
#define HV_REG 0x20<<11
|
||||
|
||||
|
||||
#define DUMMY_REG 0x21<<11
|
||||
#define FPGA_VERSION_REG 0x22<<11
|
||||
#define FIX_PATT_REG 0x23<<11
|
||||
#define CONTROL_REG 0x24<<11
|
||||
#define STATUS_REG 0x25<<11
|
||||
#define CONFIG_REG 0x26<<11
|
||||
#define EXT_SIGNAL_REG 0x27<<11
|
||||
#define FPGA_SVN_REG 0x29<<11
|
||||
|
||||
|
||||
#define CHIP_OF_INTRST_REG 0x2A<<11
|
||||
|
||||
//FIFO
|
||||
#define LOOK_AT_ME_REG 0x28<<11
|
||||
|
||||
#define FIFO_DATA_REG_OFF 0x50<<11 ///////
|
||||
|
||||
|
||||
//to read back dac registers
|
||||
#define MOD_DACS1_REG 0x65<<11
|
||||
#define MOD_DACS2_REG 0x66<<11
|
||||
#define MOD_DACS3_REG 0x67<<11
|
||||
|
||||
//user entered
|
||||
#define SET_DELAY_LSB_REG 0x68<<11
|
||||
#define SET_DELAY_MSB_REG 0x69<<11
|
||||
#define GET_DELAY_LSB_REG 0x6a<<11
|
||||
#define GET_DELAY_MSB_REG 0x6b<<11
|
||||
|
||||
#define SET_TRAINS_LSB_REG 0x6c<<11
|
||||
#define SET_TRAINS_MSB_REG 0x6d<<11
|
||||
#define GET_TRAINS_LSB_REG 0x6e<<11
|
||||
#define GET_TRAINS_MSB_REG 0x6f<<11
|
||||
|
||||
#define SET_FRAMES_LSB_REG 0x70<<11
|
||||
#define SET_FRAMES_MSB_REG 0x71<<11
|
||||
#define GET_FRAMES_LSB_REG 0x72<<11
|
||||
#define GET_FRAMES_MSB_REG 0x73<<11
|
||||
|
||||
#define SET_PERIOD_LSB_REG 0x74<<11
|
||||
#define SET_PERIOD_MSB_REG 0x75<<11
|
||||
#define GET_PERIOD_LSB_REG 0x76<<11
|
||||
#define GET_PERIOD_MSB_REG 0x77<<11
|
||||
|
||||
#define SET_EXPTIME_LSB_REG 0x78<<11
|
||||
#define SET_EXPTIME_MSB_REG 0x79<<11
|
||||
#define GET_EXPTIME_LSB_REG 0x7a<<11
|
||||
#define GET_EXPTIME_MSB_REG 0x7b<<11
|
||||
|
||||
#define SET_GATES_LSB_REG 0x7c<<11
|
||||
#define SET_GATES_MSB_REG 0x7d<<11
|
||||
#define GET_GATES_LSB_REG 0x7e<<11
|
||||
#define GET_GATES_MSB_REG 0x7f<<11
|
||||
|
||||
|
||||
|
||||
|
||||
//image
|
||||
#define DARK_IMAGE_REG 0x81<<11
|
||||
#define GAIN_IMAGE_REG 0x82<<11
|
||||
|
||||
//counter block memory
|
||||
#define COUNTER_MEMORY_REG 0x85<<11
|
||||
|
||||
|
||||
#define GET_MEASUREMENT_TIME_LSB_REG 0x023000
|
||||
#define GET_MEASUREMENT_TIME_MSB_REG 0x024000
|
||||
|
||||
#define GET_ACTUAL_TIME_LSB_REG 0x025000
|
||||
#define GET_ACTUAL_TIME_MSB_REG 0x026000
|
||||
|
||||
|
||||
//not used
|
||||
//#define MCB_DOUT_REG_OFF 0x200000
|
||||
//#define FIFO_CNTRL_REG_OFF 0x300000
|
||||
//#define FIFO_COUNTR_REG_OFF 0x400000
|
||||
//not used so far
|
||||
//#define SPEED_REG 0x006000
|
||||
//#define SET_NBITS_REG 0x008000
|
||||
//not used
|
||||
//#define GET_SHIFT_IN_REG 0x022000
|
||||
|
||||
|
||||
|
||||
#define SHIFTMOD 2
|
||||
#define SHIFTFIFO 9
|
||||
|
||||
/** for PCB_REV_REG */
|
||||
#define DETECTOR_TYPE_MASK 0xF0000
|
||||
#define DETECTOR_TYPE_OFFSET 16
|
||||
#define BOARD_REVISION_MASK 0xFFFF
|
||||
#define MOENCH_MODULE 2
|
||||
|
||||
|
||||
|
||||
|
||||
/* for control register */
|
||||
#define START_ACQ_BIT 0x00000001
|
||||
#define STOP_ACQ_BIT 0x00000002
|
||||
#define START_FIFOTEST_BIT 0x00000004 // ?????
|
||||
#define STOP_FIFOTEST_BIT 0x00000008 // ??????
|
||||
#define START_READOUT_BIT 0x00000010
|
||||
#define STOP_READOUT_BIT 0x00000020
|
||||
#define START_EXPOSURE_BIT 0x00000040
|
||||
#define STOP_EXPOSURE_BIT 0x00000080
|
||||
#define START_TRAIN_BIT 0x00000100
|
||||
#define STOP_TRAIN_BIT 0x00000200
|
||||
#define SYNC_RESET 0x00000400
|
||||
|
||||
/* for status register */
|
||||
#define RUN_BUSY_BIT 0x00000001
|
||||
#define READOUT_BUSY_BIT 0x00000002
|
||||
#define FIFOTEST_BUSY_BIT 0x00000004 //????
|
||||
#define WAITING_FOR_TRIGGER_BIT 0x00000008
|
||||
#define DELAYBEFORE_BIT 0x00000010
|
||||
#define DELAYAFTER_BIT 0x00000020
|
||||
#define EXPOSING_BIT 0x00000040
|
||||
#define COUNT_ENABLE_BIT 0x00000080
|
||||
#define READSTATE_0_BIT 0x00000100
|
||||
#define READSTATE_1_BIT 0x00000200
|
||||
#define READSTATE_2_BIT 0x00000400
|
||||
|
||||
#define RUNSTATE_0_BIT 0x00001000
|
||||
#define RUNSTATE_1_BIT 0x00002000
|
||||
#define RUNSTATE_2_BIT 0x00004000
|
||||
#define SOME_FIFO_FULL_BIT 0x00008000 // error!
|
||||
#define ALL_FIFO_EMPTY_BIT 0x00010000 // data ready
|
||||
#define RUNMACHINE_BUSY_BIT 0x00020000
|
||||
#define READMACHINE_BUSY_BIT 0x00040000
|
||||
#define STOPPED_BIT 0x00100000
|
||||
|
||||
|
||||
|
||||
/* for fifo status register */
|
||||
#define FIFO_ENABLED_BIT 0x80000000
|
||||
#define FIFO_DISABLED_BIT 0x01000000
|
||||
#define FIFO_ERROR_BIT 0x08000000
|
||||
#define FIFO_EMPTY_BIT 0x04000000
|
||||
#define FIFO_DATA_READY_BIT 0x02000000
|
||||
#define FIFO_COUNTER_MASK 0x000001ff
|
||||
#define FIFO_NM_MASK 0x00e00000
|
||||
#define FIFO_NM_OFF 21
|
||||
#define FIFO_NC_MASK 0x001ffe00
|
||||
#define FIFO_NC_OFF 9
|
||||
|
||||
/* for config register *///not really used yet
|
||||
#define TOT_ENABLE_BIT 0x00000002
|
||||
#define TIMED_GATE_BIT 0x00000004
|
||||
#define CONT_RO_ENABLE_BIT 0x00080000
|
||||
#define CPU_OR_RECEIVER_BIT 0x00001000
|
||||
|
||||
|
||||
|
||||
/* for speed register */
|
||||
#define CLK_DIVIDER_MASK 0x000000ff
|
||||
#define CLK_DIVIDER_OFFSET 0
|
||||
#define SET_LENGTH_MASK 0x00000f00
|
||||
#define SET_LENGTH_OFFSET 8
|
||||
#define WAIT_STATES_MASK 0x0000f000
|
||||
#define WAIT_STATES_OFFSET 12
|
||||
#define TOTCLK_DIVIDER_MASK 0xff000000
|
||||
#define TOTCLK_DIVIDER_OFFSET 24
|
||||
#define TOTCLK_DUTYCYCLE_MASK 0x00ff0000
|
||||
#define TOTCLK_DUTYCYCLE_OFFSET 16
|
||||
|
||||
/* for external signal register */
|
||||
#define SIGNAL_OFFSET 4
|
||||
#define SIGNAL_MASK 0xF
|
||||
#define EXT_SIG_OFF 0x0
|
||||
#define EXT_GATE_IN_ACTIVEHIGH 0x1
|
||||
#define EXT_GATE_IN_ACTIVELOW 0x2
|
||||
#define EXT_TRIG_IN_RISING 0x3
|
||||
#define EXT_TRIG_IN_FALLING 0x4
|
||||
#define EXT_RO_TRIG_IN_RISING 0x5
|
||||
#define EXT_RO_TRIG_IN_FALLING 0x6
|
||||
#define EXT_GATE_OUT_ACTIVEHIGH 0x7
|
||||
#define EXT_GATE_OUT_ACTIVELOW 0x8
|
||||
#define EXT_TRIG_OUT_RISING 0x9
|
||||
#define EXT_TRIG_OUT_FALLING 0xA
|
||||
#define EXT_RO_TRIG_OUT_RISING 0xB
|
||||
#define EXT_RO_TRIG_OUT_FALLING 0xC
|
||||
|
||||
|
||||
/* for temperature register */
|
||||
#define T1_CLK_BIT 0x00000001
|
||||
#define T1_CS_BIT 0x00000002
|
||||
#define T2_CLK_BIT 0x00000004
|
||||
#define T2_CS_BIT 0x00000008
|
||||
|
||||
|
||||
|
||||
/* fifo control register */
|
||||
#define FIFO_RESET_BIT 0x00000001
|
||||
#define FIFO_DISABLE_TOGGLE_BIT 0x00000002
|
||||
|
||||
|
||||
//chip shiftin register meaning
|
||||
#define OUTMUX_OFF 20
|
||||
#define OUTMUX_MASK 0x1f
|
||||
#define PROBES_OFF 4
|
||||
#define PROBES_MASK 0x7f
|
||||
#define OUTBUF_OFF 0
|
||||
#define OUTBUF_MASK 1
|
||||
|
||||
|
||||
/* multi purpose register */
|
||||
#define PHASE_STEP_BIT 0x00000001
|
||||
#define PHASE_STEP_OFFSET 0
|
||||
// #define xxx_BIT 0x00000002
|
||||
#define RESET_COUNTER_BIT 0x00000004
|
||||
#define RESET_COUNTER_OFFSET 2
|
||||
//#define xxx_BIT 0x00000008
|
||||
//#define xxx_BIT 0x00000010
|
||||
#define SW1_BIT 0x00000020
|
||||
#define SW1_OFFSET 5
|
||||
#define WRITE_BACK_BIT 0x00000040
|
||||
#define WRITE_BACK_OFFSET 6
|
||||
#define RESET_BIT 0x00000080
|
||||
#define RESET_OFFSET 7
|
||||
#define PLL_CLK_SEL_MSK 0x00000700
|
||||
#define PLL_CLK_SEL_OFFSET 8
|
||||
#define PLL_CLK_SEL_MASTER_VAL ((0x1 << PLL_CLK_SEL_OFFSET) & PLL_CLK_SEL_MSK)
|
||||
#define PLL_CLK_SEL_MASTER_ADC_VAL ((0x2 << PLL_CLK_SEL_OFFSET) & PLL_CLK_SEL_MSK)
|
||||
#define PLL_CLK_SEL_SLAVE_VAL ((0x3 << PLL_CLK_SEL_OFFSET) & PLL_CLK_SEL_MSK)
|
||||
#define PLL_CLK_SEL_SLAVE_ADC_VAL ((0x4 << PLL_CLK_SEL_OFFSET) & PLL_CLK_SEL_MSK)
|
||||
#define ENET_RESETN_BIT 0x00000800
|
||||
#define ENET_RESETN_OFFSET 11
|
||||
#define INT_RSTN_BIT 0x00001000
|
||||
#define INT_RSTN_OFFSET 12
|
||||
#define DIGITAL_TEST_BIT 0x00004000
|
||||
#define DIGITAL_TEST_OFFSET 14
|
||||
//#define CHANGE_AT_POWER_ON_BIT 0x00008000
|
||||
//#define CHANGE_AT_POWER_ON_OFFSET 15
|
||||
#define RST_TO_SW1_DELAY_MSK 0x000F0000
|
||||
#define RST_TO_SW1_DELAY_OFFSET 16
|
||||
#define START_ACQ_DELAY_MSK 0x00F00000
|
||||
#define START_ACQ_DELAY_OFFSET 20
|
||||
|
||||
/* settings/conf gain register */
|
||||
#define GAIN_MASK 0x000000ff
|
||||
#define GAIN_OFFSET 0
|
||||
#define SETTINGS_MASK 0x0000ff00
|
||||
#define SETTINGS_OFFSET 8
|
||||
|
||||
|
||||
/* CHIP_OF_INTRST_REG */
|
||||
#define CHANNEL_MASK 0xffff0000
|
||||
#define CHANNEL_OFFSET 16
|
||||
#define ACTIVE_ADC_MASK 0x0000001f
|
||||
|
||||
|
||||
|
||||
/**ADC SYNC CLEAN FIFO*/
|
||||
#define ADCSYNC_CLEAN_FIFO_BITS 0x300000
|
||||
|
||||
#endif
|
||||
|
||||
103
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/server.c
Executable file
103
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/server.c
Executable file
@ -0,0 +1,103 @@
|
||||
/* A simple server in the internet domain using TCP
|
||||
The port number is passed as an argument */
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#include "communication_funcs.h"
|
||||
#include "server_funcs.h"
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
|
||||
|
||||
extern int sockfd;
|
||||
extern int phase_shift;
|
||||
|
||||
|
||||
|
||||
void error(char *msg)
|
||||
{
|
||||
perror(msg);
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int portno, b;
|
||||
char cmd[100];
|
||||
int retval=OK;
|
||||
int sd, fd;
|
||||
int iarg;
|
||||
for(iarg=1; iarg<argc; iarg++){
|
||||
if(!strcasecmp(argv[iarg],"-phaseshift")){
|
||||
if ( sscanf(argv[iarg+1],"%d",&phase_shift)==0) {
|
||||
printf("could not decode phase shift\n");
|
||||
return 1;
|
||||
}
|
||||
argc=1;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
if (argc==1) {
|
||||
portno = DEFAULT_PORTNO;
|
||||
sprintf(cmd,"%s %d &",argv[0],DEFAULT_PORTNO+1);
|
||||
printf("\n\nControl Server\nOpening control server on port %d\n",portno );
|
||||
system(cmd);
|
||||
b=1;
|
||||
} else {
|
||||
portno = DEFAULT_PORTNO+1;
|
||||
if ( sscanf(argv[1],"%d",&portno) ==0) {
|
||||
printf("could not open stop server: unknown port\n");
|
||||
return 1;
|
||||
}
|
||||
b=0;
|
||||
printf("\n\nStop Server\nOpening stop server on port %d\n",portno);
|
||||
}
|
||||
init_detector(b);
|
||||
|
||||
|
||||
sd=bindSocket(portno);
|
||||
|
||||
sockfd=sd;
|
||||
|
||||
|
||||
if (getServerError(sd)) {
|
||||
printf("server error!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* assign function table */
|
||||
function_table();
|
||||
#ifdef VERBOSE
|
||||
printf("function table assigned \n");
|
||||
#endif
|
||||
|
||||
|
||||
/* waits for connection */
|
||||
while(retval!=GOODBYE) {
|
||||
#ifdef VERBOSE
|
||||
printf("\n");
|
||||
#endif
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("Waiting for client call\n");
|
||||
#endif
|
||||
fd=acceptConnection(sockfd);
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("Conenction accepted\n");
|
||||
#endif
|
||||
retval=decode_function(fd);
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("function executed\n");
|
||||
#endif
|
||||
closeConnection(fd);
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("connection closed\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
exitServer(sockfd);
|
||||
printf("Goodbye!\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
60
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/server_defs.h
Executable file
60
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/server_defs.h
Executable file
@ -0,0 +1,60 @@
|
||||
#ifndef SERVER_DEFS_H
|
||||
#define SERVER_DEFS_H
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
// Hardware definitions
|
||||
|
||||
#define NCHAN 128
|
||||
#define NCHIP 10
|
||||
#define NMAXMODX 1
|
||||
#define NMAXMODY 1
|
||||
#define NMAXMOD NMAXMODX*NMAXMODY
|
||||
#define NDAC 8
|
||||
#define NADC 5
|
||||
|
||||
#define NCHANS NCHAN*NCHIP*NMAXMOD
|
||||
#define NDACS NDAC*NMAXMOD
|
||||
|
||||
#define NTRIMBITS 6
|
||||
#define NCOUNTBITS 24
|
||||
|
||||
#define NCHIPS_PER_ADC 2
|
||||
|
||||
// for 25 um
|
||||
#define CONFIG_FILE "config.txt"
|
||||
|
||||
|
||||
//#define TRIM_DR ((2**NTRIMBITS)-1)
|
||||
//#define COUNT_DR ((2**NCOUNTBITS)-1)
|
||||
#define TRIM_DR (((int)pow(2,NTRIMBITS))-1)
|
||||
#define COUNT_DR (((int)pow(2,NCOUNTBITS))-1)
|
||||
|
||||
|
||||
#define ALLMOD 0xffff
|
||||
#define ALLFIFO 0xffff
|
||||
|
||||
|
||||
#define ADCSYNC_VAL 0x32214
|
||||
#define TOKEN_RESTART_DELAY 0x88000000
|
||||
#define TOKEN_RESTART_DELAY_ROI 0x1b000000
|
||||
#define TOKEN_TIMING_REV1 0x1f16
|
||||
#define TOKEN_TIMING_REV2 0x1f0f
|
||||
|
||||
#define DEFAULT_PHASE_SHIFT 120
|
||||
#define DEFAULT_IP_PACKETSIZE 0x0522
|
||||
#define DEFAULT_UDP_PACKETSIZE 0x050E
|
||||
#define ADC1_IP_PACKETSIZE (256*2+14+20)
|
||||
#define ADC1_UDP_PACKETSIZE (256*2+4+8+2)
|
||||
|
||||
#ifdef VIRTUAL
|
||||
#define DEBUGOUT
|
||||
#endif
|
||||
|
||||
#define CLK_FREQ 32.007729
|
||||
|
||||
|
||||
#endif
|
||||
3152
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/server_funcs.c
Executable file
3152
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/server_funcs.c
Executable file
File diff suppressed because it is too large
Load Diff
99
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/server_funcs.h
Executable file
99
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/server_funcs.h
Executable file
@ -0,0 +1,99 @@
|
||||
#ifndef SERVER_FUNCS_H
|
||||
#define SERVER_FUNCS_H
|
||||
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
/*
|
||||
#include <sys/types.h>
|
||||
#include <sys/socket.h>
|
||||
#include <netinet/in.h>
|
||||
*/
|
||||
#include "communication_funcs.h"
|
||||
|
||||
|
||||
|
||||
|
||||
#define GOODBYE -200
|
||||
|
||||
int sockfd;
|
||||
|
||||
int function_table();
|
||||
|
||||
int decode_function(int);
|
||||
int init_detector(int);
|
||||
|
||||
int M_nofunc(int);
|
||||
int exit_server(int);
|
||||
|
||||
|
||||
|
||||
|
||||
// General purpose functions
|
||||
int get_detector_type(int);
|
||||
int set_number_of_modules(int);
|
||||
int get_max_number_of_modules(int);
|
||||
|
||||
|
||||
int exec_command(int);
|
||||
int set_external_signal_flag(int);
|
||||
int set_external_communication_mode(int);
|
||||
int get_id(int);
|
||||
int digital_test(int);
|
||||
int write_register(int);
|
||||
int read_register(int);
|
||||
int set_dac(int);
|
||||
int get_adc(int);
|
||||
int set_channel(int);
|
||||
int set_chip(int);
|
||||
int set_module(int);
|
||||
int get_channel(int);
|
||||
int get_chip(int);
|
||||
int get_module(int);
|
||||
|
||||
int get_threshold_energy(int);
|
||||
int set_threshold_energy(int);
|
||||
int set_settings(int);
|
||||
int start_acquisition(int);
|
||||
int stop_acquisition(int);
|
||||
int start_readout(int);
|
||||
int get_run_status(int);
|
||||
int read_frame(int);
|
||||
int read_all(int);
|
||||
int start_and_read_all(int);
|
||||
int set_timer(int);
|
||||
int get_time_left(int);
|
||||
int set_dynamic_range(int);
|
||||
int set_roi(int);
|
||||
int get_roi(int);
|
||||
int set_speed(int);
|
||||
void configureADC();
|
||||
int set_readout_flags(int);
|
||||
int execute_trimming(int);
|
||||
int lock_server(int);
|
||||
int set_port(int);
|
||||
int get_last_client_ip(int);
|
||||
int set_master(int);
|
||||
int set_synchronization(int);
|
||||
|
||||
int update_client(int);
|
||||
int send_update(int);
|
||||
int configure_mac(int);
|
||||
|
||||
int load_image(int);
|
||||
int read_counter_block(int);
|
||||
int reset_counter_block(int);
|
||||
|
||||
int start_receiver(int);
|
||||
int stop_receiver(int);
|
||||
|
||||
|
||||
int calibrate_pedestal(int);
|
||||
|
||||
int set_roi(int);
|
||||
|
||||
int write_adc_register(int);
|
||||
int check_version(int);
|
||||
#endif
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/sls_detector_defs.h
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/sls_detector_funcs.h
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/sls_receiver_defs.h
|
||||
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/sls_receiver_funcs.h
|
||||
46
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/stop_server.c
Executable file
46
slsDetectorSoftware/slsDetectorServers/gotthardDetectorServer/stop_server.c
Executable file
@ -0,0 +1,46 @@
|
||||
/* A simple server in the internet domain using TCP
|
||||
The port number is passed as an argument */
|
||||
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
|
||||
#include "communication_funcs.h"
|
||||
#include "firmware_funcs.h"
|
||||
|
||||
|
||||
int sockfd;
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int portno;
|
||||
int retval=0;
|
||||
|
||||
portno = DEFAULT_PORTNO;
|
||||
|
||||
|
||||
bindSocket(portno);
|
||||
if (getServerError())
|
||||
return -1;
|
||||
|
||||
|
||||
|
||||
/* waits for connection */
|
||||
while(retval!=GOODBYE) {
|
||||
#ifdef VERBOSE
|
||||
printf("\n");
|
||||
#endif
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("Stop server: waiting for client call\n");
|
||||
#endif
|
||||
acceptConnection();
|
||||
retval=stopStateMachine();
|
||||
closeConnection();
|
||||
}
|
||||
|
||||
exitServer();
|
||||
printf("Goodbye!\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -0,0 +1,7 @@
|
||||
SRCFILE=gitInfoGotthard.h
|
||||
DSTFILE=versionAPI.h
|
||||
|
||||
SRCPATTERN=GITDATE
|
||||
DSTPATTERN=APIGOTTHARD
|
||||
|
||||
awk -v a="$SRCFILE" -v b="$DSTFILE" -v c="$SRCPATTERN" -v d="$DSTPATTERN" 'FNR==NR&&$2==c{x=$3} NR!=FNR{if($2==d){$3="0x"substr(x,5)}print > b}' $SRCFILE $DSTFILE
|
||||
@ -0,0 +1,30 @@
|
||||
SERVER=gotthardDetectorServer
|
||||
MAINDIR=slsDetectorsPackage
|
||||
SPECDIR=slsDetectorSoftware/$SERVER
|
||||
TMPFILE=gitInfoGotthardTmp.h
|
||||
INCLFILE=gitInfoGotthard.h
|
||||
|
||||
#evaluate the variables
|
||||
EVALFILE=../../evalVersionVariables.sh
|
||||
source $EVALFILE
|
||||
|
||||
|
||||
#get modified date
|
||||
#RDATE1='git log --pretty=format:"%ci" -1'
|
||||
RDATE1="find . -type f -exec stat --format '%Y :%y %n' '{}' \; | sort -nr | cut -d: -f2- | egrep -v 'gitInfo|.git|updateGitVersion|.o' | head -n 1"
|
||||
RDATE=`eval $RDATE1`
|
||||
NEWDATE=$(sed "s/-//g" <<< $RDATE | awk '{print $1;}')
|
||||
NEWDATE=${NEWDATE/#/0x}
|
||||
|
||||
|
||||
#get old date from INCLFILE
|
||||
OLDDATE=$(more $INCLFILE | grep '#define GITDATE' | awk '{print $3}')
|
||||
|
||||
|
||||
#update INCLFILE if changes
|
||||
if [ "$OLDDATE" != "$NEWDATE" ]; then
|
||||
echo Path: ${MAINDIR}/${SPECDIR} $'\n'URL: ${GITREPO} $'\n'Repository Root: ${GITREPO} $'\n'Repsitory UUID: ${REPUID} $'\n'Revision: ${FOLDERREV} $'\n'Branch: ${BRANCH} $'\n'Last Changed Author: ${AUTH1}_${AUTH2} $'\n'Last Changed Rev: ${REV} $'\n'Last Changed Date: ${RDATE} > gitInfo.txt
|
||||
cd ../../
|
||||
./genVersionHeader.sh $SPECDIR/gitInfo.txt $SPECDIR/$TMPFILE $SPECDIR/$INCLFILE
|
||||
cd $WD
|
||||
fi
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/versionAPI.h
|
||||
141
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/AD9257.h
Executable file
141
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/AD9257.h
Executable file
@ -0,0 +1,141 @@
|
||||
#ifndef AD9257_H
|
||||
#define AD9257_H
|
||||
|
||||
#include "ansi.h"
|
||||
|
||||
#include "commonServerFunctions.h"
|
||||
#include <stdio.h>
|
||||
|
||||
/* AD9257 ADC DEFINES */
|
||||
#define AD9257_ADC_NUMBITS (24)
|
||||
|
||||
#define AD9257_DEV_IND_2_REG (0x04)
|
||||
#define AD9257_CHAN_H_OFST (0)
|
||||
#define AD9257_CHAN_H_MSK (0x00000001 << AD9257_CHAN_H_OFST)
|
||||
#define AD9257_CHAN_G_OFST (1)
|
||||
#define AD9257_CHAN_G_MSK (0x00000001 << AD9257_CHAN_G_OFST)
|
||||
#define AD9257_CHAN_F_OFST (2)
|
||||
#define AD9257_CHAN_F_MSK (0x00000001 << AD9257_CHAN_F_OFST)
|
||||
#define AD9257_CHAN_E_OFST (3)
|
||||
#define AD9257_CHAN_E_MSK (0x00000001 << AD9257_CHAN_E_OFST)
|
||||
|
||||
#define AD9257_DEV_IND_1_REG (0x05)
|
||||
#define AD9257_CHAN_D_OFST (0)
|
||||
#define AD9257_CHAN_D_MSK (0x00000001 << AD9257_CHAN_D_OFST)
|
||||
#define AD9257_CHAN_C_OFST (1)
|
||||
#define AD9257_CHAN_C_MSK (0x00000001 << AD9257_CHAN_C_OFST)
|
||||
#define AD9257_CHAN_B_OFST (2)
|
||||
#define AD9257_CHAN_B_MSK (0x00000001 << AD9257_CHAN_B_OFST)
|
||||
#define AD9257_CHAN_A_OFST (3)
|
||||
#define AD9257_CHAN_A_MSK (0x00000001 << AD9257_CHAN_A_OFST)
|
||||
#define AD9257_CLK_CH_DCO_OFST (4)
|
||||
#define AD9257_CLK_CH_DCO_MSK (0x00000001 << AD9257_CLK_CH_DCO_OFST)
|
||||
#define AD9257_CLK_CH_IFCO_OFST (5)
|
||||
#define AD9257_CLK_CH_IFCO_MSK (0x00000001 << AD9257_CLK_CH_IFCO_OFST)
|
||||
|
||||
#define AD9257_POWER_MODE_REG (0x08)
|
||||
#define AD9257_POWER_INTERNAL_OFST (0)
|
||||
#define AD9257_POWER_INTERNAL_MSK (0x00000003 << AD9257_POWER_INTERNAL_OFST)
|
||||
#define AD9257_INT_RESET_VAL (0x3)
|
||||
#define AD9257_INT_CHIP_RUN_VAL (0x0)
|
||||
#define AD9257_POWER_EXTERNAL_OFST (5)
|
||||
#define AD9257_POWER_EXTERNAL_MSK (0x00000001 << AD9257_POWER_EXTERNAL_OFST)
|
||||
#define AD9257_EXT_FULL_POWER_VAL (0x0)
|
||||
#define AD9257_EXT_STANDBY_VAL (0x1)
|
||||
|
||||
#define AD9257_OUT_MODE_REG (0x14)
|
||||
#define AD9257_OUT_FORMAT_OFST (0)
|
||||
#define AD9257_OUT_FORMAT_MSK (0x00000001 << AD9257_OUT_FORMAT_OFST)
|
||||
#define AD9257_OUT_BINARY_OFST_VAL (0)
|
||||
#define AD9257_OUT_TWOS_COMPL_VAL (1)
|
||||
#define AD9257_OUT_LVDS_OPT_OFST (6)
|
||||
#define AD9257_OUT_LVDS_OPT_MSK (0x00000001 << AD9257_OUT_LVDS_OPT_OFST)
|
||||
#define AD9257_OUT_LVDS_ANSI_VAL (0)
|
||||
#define AD9257_OUT_LVDS_IEEE_VAL (1)
|
||||
|
||||
#define AD9257_OUT_PHASE_REG (0x16)
|
||||
#define AD9257_OUT_CLK_OFST (0)
|
||||
#define AD9257_OUT_CLK_MSK (0x0000000F << AD9257_OUT_CLK_OFST)
|
||||
#define AD9257_OUT_CLK_60_VAL (0x1)
|
||||
#define AD9257_IN_CLK_OFST (4)
|
||||
#define AD9257_IN_CLK_MSK (0x00000007 << AD9257_IN_CLK_OFST)
|
||||
#define AD9257_IN_CLK_0_VAL (0x0)
|
||||
|
||||
#define AD9257_VREF_REG (0x18)
|
||||
#define AD9257_VREF_OFST (0)
|
||||
#define AD9257_VREF_MSK (0x00000003 << AD9257_VREF_OFST)
|
||||
#define AD9257_VREF_1_33_VAL (0x2)
|
||||
|
||||
#define AD9257_TEST_MODE_REG (0x0D)
|
||||
#define AD9257_OUT_TEST_OFST (0)
|
||||
#define AD9257_OUT_TEST_MSK (0x0000000F << AD9257_OUT_TEST_OFST)
|
||||
#define AD9257_NONE_VAL (0x0)
|
||||
#define AD9257_MIXED_BIT_FREQ_VAL (0xC)
|
||||
#define AD9257_TEST_RESET_SHORT_GEN (4)
|
||||
#define AD9257_TEST_RESET_LONG_GEN (5)
|
||||
#define AD9257_USER_IN_MODE_OFST (6)
|
||||
#define AD9257_USER_IN_MODE_MSK (0x00000003 << AD9257_USER_IN_MODE_OFST)
|
||||
|
||||
|
||||
void setAdc(int addr, int val) {
|
||||
|
||||
u_int32_t codata;
|
||||
codata = val + (addr << 8);
|
||||
printf(" Setting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr);
|
||||
serializeToSPI(ADC_SPI_REG, codata, ADC_SERIAL_CS_OUT_MSK, AD9257_ADC_NUMBITS,
|
||||
ADC_SERIAL_CLK_OUT_MSK, ADC_SERIAL_DATA_OUT_MSK, ADC_SERIAL_DATA_OUT_OFST);
|
||||
}
|
||||
|
||||
void prepareADC(){
|
||||
printf("\n\nPreparing ADC ... \n");
|
||||
|
||||
//power mode reset
|
||||
printf("power mode reset:\n");
|
||||
setAdc(AD9257_POWER_MODE_REG,
|
||||
(AD9257_INT_RESET_VAL << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK);
|
||||
|
||||
//power mode chip run
|
||||
printf("power mode chip run:\n");
|
||||
setAdc(AD9257_POWER_MODE_REG,
|
||||
(AD9257_INT_CHIP_RUN_VAL << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK);
|
||||
|
||||
//output clock phase
|
||||
printf("output clock phase:\n");
|
||||
setAdc(AD9257_OUT_PHASE_REG,
|
||||
(AD9257_OUT_CLK_60_VAL << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK);
|
||||
|
||||
// lvds-iee reduced , binary offset
|
||||
printf("lvds-iee reduced, binary offset:\n");
|
||||
setAdc(AD9257_OUT_MODE_REG,
|
||||
(AD9257_OUT_LVDS_IEEE_VAL << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK);
|
||||
|
||||
// all devices on chip to receive next command
|
||||
printf("all devices on chip to receive next command:\n");
|
||||
setAdc(AD9257_DEV_IND_2_REG,
|
||||
AD9257_CHAN_H_MSK | AD9257_CHAN_G_MSK | AD9257_CHAN_F_MSK | AD9257_CHAN_E_MSK);
|
||||
setAdc(AD9257_DEV_IND_1_REG,
|
||||
AD9257_CHAN_D_MSK | AD9257_CHAN_C_MSK | AD9257_CHAN_B_MSK | AD9257_CHAN_A_MSK |
|
||||
AD9257_CLK_CH_DCO_MSK | AD9257_CLK_CH_IFCO_MSK);
|
||||
|
||||
// vref 1.33
|
||||
printf("vref 1.33:\n");
|
||||
setAdc(AD9257_VREF_REG,
|
||||
(AD9257_VREF_1_33_VAL << AD9257_VREF_OFST) & AD9257_VREF_MSK);
|
||||
|
||||
// no test mode
|
||||
printf("no test mode:\n");
|
||||
setAdc(AD9257_TEST_MODE_REG,
|
||||
(AD9257_NONE_VAL << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK);
|
||||
|
||||
#ifdef TESTADC
|
||||
printf("***************************************** *******\n");
|
||||
printf("******* PUTTING ADC IN TEST MODE!!!!!!!!! *******\n");
|
||||
printf("***************************************** *******\n");
|
||||
// mixed bit frequency test mode
|
||||
printf("mixed bit frequency test mode:\n");
|
||||
setAdc(AD9257_TEST_MODE_REG,
|
||||
(AD9257_MIXED_BIT_FREQ_VAL << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif //AD9257_H
|
||||
@ -0,0 +1,59 @@
|
||||
# $Id: Makefile,v 1.1.1.1 2006/02/04 03:35:01 freza Exp $
|
||||
# first compile
|
||||
# make cris-axis-linux-gnu
|
||||
|
||||
|
||||
CROSS = bfin-uclinux-
|
||||
CC = $(CROSS)gcc
|
||||
|
||||
CFLAGS += -Wall -DMOENCHD -DMCB_FUNCS -DDACS_INT -DDEBUG -DV1 -DCTB -DOLDVERSION #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL #-DDACS_INT_CSERVER
|
||||
|
||||
|
||||
PROGS= jctbDetectorServer
|
||||
INSTDIR= /tftpboot
|
||||
INSTMODE= 0777
|
||||
|
||||
|
||||
|
||||
BINS = testlib_sharedlibc
|
||||
SRCS = server.c server_funcs.c communication_funcs.c firmware_funcs.c slow_adc.c blackfin.c
|
||||
#mcb_funcs.c sharedmemory.c
|
||||
OBJS = $(SRCS:%.c=%.o)
|
||||
|
||||
|
||||
|
||||
all: clean versioning $(PROGS)
|
||||
|
||||
test: clean jungfrauADCTEst
|
||||
|
||||
boot: $(OBJS)
|
||||
|
||||
versioning:
|
||||
@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
|
||||
|
||||
jctbDetectorServerNew: $(OBJS)
|
||||
echo $(OBJS)
|
||||
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@)
|
||||
|
||||
jctbDetectorServer: $(OBJS)
|
||||
echo $(OBJS)
|
||||
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@) -DOLDVERSION
|
||||
|
||||
jungfrauADCTEst: $(OBJS)
|
||||
echo $(OBJS)
|
||||
$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@) -DTESTADC
|
||||
|
||||
|
||||
|
||||
|
||||
install: $(PROGS)
|
||||
$(INSTALL) -d $(INSTDIR)
|
||||
$(INSTALL) -m $(INSTMODE) $(PROGS) $(INSTDIR)
|
||||
|
||||
|
||||
romfs:
|
||||
$(ROMFSINST) /bin/$(PROGS)
|
||||
|
||||
clean:
|
||||
rm -rf $(PROGS) *.o *.gdb
|
||||
|
||||
1
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/ansi.h
Symbolic link
1
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/ansi.h
Symbolic link
@ -0,0 +1 @@
|
||||
../../slsReceiverSoftware/include/ansi.h
|
||||
@ -0,0 +1 @@
|
||||
export PATH=/afs/psi.ch/project/sls_det_firmware/jungfrau_software/uClinux-2010_64bit/bfin-uclinux/bin:$PATH
|
||||
@ -0,0 +1,150 @@
|
||||
#include "blackfin.h"
|
||||
|
||||
#include <sys/ipc.h>
|
||||
#include <sys/shm.h>
|
||||
|
||||
#include <sys/time.h>
|
||||
#include <string.h>
|
||||
#include <sys/utsname.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/socket.h>
|
||||
#include <netinet/in.h>
|
||||
#include <netinet/tcp.h>
|
||||
#include <arpa/inet.h>
|
||||
#include <netdb.h>
|
||||
#include <time.h>
|
||||
#include <sys/time.h>
|
||||
#include <sys/mman.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/stat.h>
|
||||
#include <errno.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdarg.h>
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <unistd.h>
|
||||
#include "server_defs.h"
|
||||
#include "registers_m.h"
|
||||
|
||||
//for memory mapping
|
||||
u_int32_t CSP0BASE;
|
||||
|
||||
u_int16_t volatile *values;
|
||||
|
||||
int mapCSP0(void) {
|
||||
printf("Mapping memory\n");
|
||||
#ifndef VIRTUAL
|
||||
int fd;
|
||||
fd = open("/dev/mem", O_RDWR | O_SYNC, 0);
|
||||
if (fd == -1) {
|
||||
printf("\nCan't find /dev/mem!\n");
|
||||
return FAIL;
|
||||
}
|
||||
printf("/dev/mem opened\n");
|
||||
|
||||
CSP0BASE = (u_int32_t)mmap(0, MEM_SIZE, PROT_READ|PROT_WRITE, MAP_FILE|MAP_SHARED, fd, CSP0);
|
||||
if (CSP0BASE == (u_int32_t)MAP_FAILED) {
|
||||
printf("\nCan't map memmory area!!\n");
|
||||
return FAIL;
|
||||
}
|
||||
printf("CSP0 mapped\n");
|
||||
|
||||
#endif
|
||||
#ifdef VIRTUAL
|
||||
CSP0BASE = malloc(MEM_SIZE);
|
||||
printf("memory allocated\n");
|
||||
#endif
|
||||
#ifdef SHAREDMEMORY
|
||||
if ( (res=inism(SMSV))<0) {
|
||||
printf("error attaching shared memory! %i",res);
|
||||
return FAIL;
|
||||
}
|
||||
#endif
|
||||
printf("CSPObase is 0x%08x \n",CSP0BASE);
|
||||
printf("CSPOBASE=from %08x to %08x\n",CSP0BASE,CSP0BASE+MEM_SIZE);
|
||||
|
||||
u_int32_t address;
|
||||
address = FIFO_DATA_REG;//_OFF;
|
||||
//values=(u_int32_t*)(CSP0BASE+address*2);
|
||||
values=(u_int16_t*)(CSP0BASE+address*2);
|
||||
printf("statusreg=%08x\n",bus_r(STATUS_REG));
|
||||
printf("\n\n");
|
||||
return OK;
|
||||
}
|
||||
|
||||
u_int16_t bus_r16(u_int32_t offset){
|
||||
volatile u_int16_t *ptr1;
|
||||
ptr1=(u_int16_t*)(CSP0BASE+offset*2);
|
||||
return *ptr1;
|
||||
}
|
||||
|
||||
u_int16_t bus_w16(u_int32_t offset, u_int16_t data) {
|
||||
volatile u_int16_t *ptr1;
|
||||
ptr1=(u_int16_t*)(CSP0BASE+offset*2);
|
||||
*ptr1=data;
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
u_int32_t bus_w(u_int32_t offset, u_int32_t data) {
|
||||
volatile u_int32_t *ptr1;
|
||||
|
||||
ptr1=(u_int32_t*)(CSP0BASE+offset*2);
|
||||
*ptr1=data;
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
|
||||
u_int32_t bus_r(u_int32_t offset) {
|
||||
volatile u_int32_t *ptr1;
|
||||
ptr1=(u_int32_t*)(CSP0BASE+offset*2);
|
||||
return *ptr1;
|
||||
}
|
||||
|
||||
// program dacq settings
|
||||
|
||||
int64_t set64BitReg(int64_t value, int aLSB, int aMSB){
|
||||
int64_t v64;
|
||||
u_int32_t vLSB,vMSB;
|
||||
if (value!=-1) {
|
||||
vLSB=value&(0xffffffff);
|
||||
bus_w(aLSB,vLSB);
|
||||
v64=value>> 32;
|
||||
vMSB=v64&(0xffffffff);
|
||||
bus_w(aMSB,vMSB);
|
||||
// printf("Wreg64(%x,%x) %08x %08x %016llx\n", aLSB>>11, aMSB>>11, vLSB, vMSB, value);
|
||||
}
|
||||
return get64BitReg(aLSB, aMSB);
|
||||
|
||||
}
|
||||
|
||||
int64_t get64BitReg(int aLSB, int aMSB){
|
||||
int64_t v64;
|
||||
u_int32_t vLSB,vMSB;
|
||||
vLSB=bus_r(aLSB);
|
||||
vMSB=bus_r(aMSB);
|
||||
v64=vMSB;
|
||||
v64=(v64<<32) | vLSB;
|
||||
|
||||
// printf("reg64(%x,%x) %x %x %llx\n", aLSB, aMSB, vLSB, vMSB, v64);
|
||||
|
||||
return v64;
|
||||
}
|
||||
|
||||
/* /\** */
|
||||
/* /\** ramType is DARK_IMAGE_REG or GAIN_IMAGE_REG *\/ */
|
||||
/* u_int16_t ram_w16(u_int32_t ramType, int adc, int adcCh, int Ch, u_int16_t data) { */
|
||||
/* unsigned int adr = (ramType | adc << 8 | adcCh << 5 | Ch ); */
|
||||
/* // printf("Writing to addr:%x\n",adr); */
|
||||
/* return bus_w16(adr,data); */
|
||||
/* } */
|
||||
|
||||
/* /\** ramType is DARK_IMAGE_REG or GAIN_IMAGE_REG *\/ */
|
||||
/* u_int16_t ram_r16(u_int32_t ramType, int adc, int adcCh, int Ch){ */
|
||||
/* unsigned int adr = (ramType | adc << 8 | adcCh << 5 | Ch ); */
|
||||
/* // printf("Reading from addr:%x\n",adr); */
|
||||
/* return bus_r16(adr); */
|
||||
/* } */
|
||||
/* **\/ */
|
||||
@ -0,0 +1,25 @@
|
||||
#ifndef BLACKFIN_H
|
||||
#define BLACKFIN_H
|
||||
|
||||
#define CSP0 0x20200000
|
||||
#define MEM_SIZE 0x100000
|
||||
#ifndef OLDVERSION
|
||||
#define MEM_MAP_SHIFT 1
|
||||
#endif
|
||||
#ifdef OLDVERSION
|
||||
#define MEM_MAP_SHIFT 11
|
||||
#endif
|
||||
#include <sys/types.h>
|
||||
|
||||
int mapCSP0(void);
|
||||
|
||||
u_int16_t bus_r16(u_int32_t offset);
|
||||
u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
|
||||
u_int32_t bus_w(u_int32_t offset, u_int32_t data);
|
||||
u_int32_t bus_r(u_int32_t offset);
|
||||
|
||||
int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
|
||||
int64_t get64BitReg(int aLSB, int aMSB);
|
||||
|
||||
|
||||
#endif
|
||||
@ -0,0 +1,73 @@
|
||||
#ifndef COMMON_SERVER_FUNCTIONS_H
|
||||
#define COMMON_SERVER_FUNCTIONS_H
|
||||
|
||||
#ifndef GOTTHARDD //gotthard already had bus_w etc defined in its firmware_funcs.c (not yet made with common files)
|
||||
#include "blackfin.h"
|
||||
#endif
|
||||
|
||||
/* global variables */
|
||||
|
||||
void SPIChipSelect (u_int32_t* valw, u_int32_t addr, u_int32_t csmask) {
|
||||
|
||||
// start point
|
||||
(*valw) = 0xffffffff; // old board compatibility (not using specific bits)
|
||||
bus_w (addr, (*valw));
|
||||
|
||||
// chip sel bar down
|
||||
(*valw) &= ~csmask; /* todo with test: done a bit different, not with previous value */
|
||||
bus_w (addr, (*valw));
|
||||
}
|
||||
|
||||
|
||||
void SPIChipDeselect (u_int32_t* valw, u_int32_t addr, u_int32_t csmask, u_int32_t clkmask) {
|
||||
// chip sel bar up
|
||||
(*valw) |= csmask; /* todo with test: not done for spi */
|
||||
bus_w (addr, (*valw));
|
||||
|
||||
//clk down
|
||||
(*valw) &= ~clkmask;
|
||||
bus_w (addr, (*valw));
|
||||
|
||||
// stop point = start point of course
|
||||
(*valw) = 0xffffffff; // old board compatibility (not using specific bits)
|
||||
bus_w (addr, (*valw));
|
||||
}
|
||||
|
||||
void sendDataToSPI (u_int32_t* valw, u_int32_t addr, u_int32_t val, int numbitstosend, u_int32_t clkmask, u_int32_t digoutmask, int digofset) {
|
||||
int i = 0;
|
||||
for (i = 0; i < numbitstosend; ++i) {
|
||||
|
||||
// clk down
|
||||
(*valw) &= ~clkmask;
|
||||
bus_w (addr, (*valw));
|
||||
|
||||
// write data (i)
|
||||
(*valw) = (((*valw) & ~digoutmask) + // unset bit
|
||||
(((val >> (numbitstosend - 1 - i)) & 0x1) << digofset)); // each bit from val starting from msb
|
||||
bus_w (addr, (*valw));
|
||||
|
||||
// clk up
|
||||
(*valw) |= clkmask ;
|
||||
bus_w (addr, (*valw));
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
void serializeToSPI(u_int32_t addr, u_int32_t val, u_int32_t csmask, int numbitstosend, u_int32_t clkmask, u_int32_t digoutmask, int digofset) {
|
||||
#ifdef VERBOSE
|
||||
if (numbitstosend == 16)
|
||||
printf("Writing to SPI Register: 0x%04x\n",val);
|
||||
else
|
||||
printf("Writing to SPI Register: 0x%08x\n", val);
|
||||
#endif
|
||||
|
||||
u_int32_t valw;
|
||||
|
||||
SPIChipSelect (&valw, addr, csmask);
|
||||
|
||||
sendDataToSPI(&valw, addr, val, numbitstosend, clkmask, digoutmask, digofset);
|
||||
|
||||
SPIChipDeselect(&valw, addr, csmask, clkmask);
|
||||
}
|
||||
|
||||
#endif //COMMON_SERVER_FUNCTIONS_H
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/communication_funcs.c
|
||||
@ -0,0 +1 @@
|
||||
../commonFiles/communication_funcs.h
|
||||
@ -0,0 +1,58 @@
|
||||
// Converts POF files into RAW files for flashing
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
|
||||
// Warning: This program is for testing only.
|
||||
// It makes some assumptions regarding the pof file and the flash size that might be wrong.
|
||||
// It also overwrites the destination file without any hesitation.
|
||||
// Handle with care.
|
||||
|
||||
int main(int argc, char* argv[])
|
||||
{
|
||||
FILE* src;
|
||||
FILE* dst;
|
||||
int x;
|
||||
int y;
|
||||
int i;
|
||||
int filepos;
|
||||
|
||||
if (argc < 3)
|
||||
{
|
||||
printf("%s Sourcefile Destinationfile\n",argv[0]);
|
||||
return -1;
|
||||
}
|
||||
|
||||
src = fopen(argv[1],"rb");
|
||||
dst = fopen(argv[2],"wb");
|
||||
|
||||
// Remove header (0...11C)
|
||||
for (filepos=0; filepos < 0x11C; filepos++)
|
||||
fgetc(src);
|
||||
|
||||
// Write 0x80 times 0xFF (0...7F)
|
||||
for (filepos=0; filepos < 0x80; filepos++)
|
||||
fputc(0xFF,dst);
|
||||
|
||||
// Swap bits and write to file
|
||||
for (filepos=0x80; filepos < 0x1000000; filepos++)
|
||||
{
|
||||
x = fgetc(src);
|
||||
if (x < 0) break;
|
||||
|
||||
y=0;
|
||||
for (i=0; i < 8; i++)
|
||||
y=y| ( (( x & (1<<i) ) >> i) << (7-i) ); // This swaps the bits
|
||||
|
||||
fputc(y,dst);
|
||||
}
|
||||
if (filepos < 0x1000000)
|
||||
printf("ERROR: EOF before end of flash\n");
|
||||
|
||||
printf("To flash the file in Linux do:\n");
|
||||
printf(" cat /proc/mtd (to findout the right mtd)\n");
|
||||
printf(" flash_eraseall /dev/mtdX\n");
|
||||
printf(" cat file > /dev/mtdX\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
4072
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/firmware_funcs.c
Executable file
4072
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/firmware_funcs.c
Executable file
File diff suppressed because it is too large
Load Diff
239
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/firmware_funcs.h
Executable file
239
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/firmware_funcs.h
Executable file
@ -0,0 +1,239 @@
|
||||
#ifndef FIRMWARE_FUNCS_H
|
||||
#define FIRMWARE_FUNCS_H
|
||||
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <sys/mman.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdarg.h>
|
||||
#include <unistd.h>
|
||||
//#include <asm/page.h>
|
||||
#include <sys/mman.h>
|
||||
#include <sys/types.h>
|
||||
#include <sys/stat.h>
|
||||
#include <fcntl.h>
|
||||
#include <stdarg.h>
|
||||
#include <unistd.h>
|
||||
|
||||
|
||||
int mapCSP0(void);
|
||||
|
||||
u_int16_t bus_r16(u_int32_t offset);
|
||||
u_int16_t bus_w16(u_int32_t offset, u_int16_t data);//aldos function
|
||||
u_int32_t bus_w(u_int32_t offset, u_int32_t data);
|
||||
u_int32_t bus_r(u_int32_t offset);
|
||||
|
||||
//int setPhaseShiftOnce();
|
||||
//int phaseStep(int st);
|
||||
//int dbitPhaseStep(int st);
|
||||
//int getDbitPhase();
|
||||
int getPhase(int i);
|
||||
int cleanFifo();
|
||||
int setDAQRegister();
|
||||
int configurePhase(int val, int i);
|
||||
int configureFrequency(int val, int i);
|
||||
|
||||
u_int32_t putout(char *s, int modnum);
|
||||
u_int32_t readin(int modnum);
|
||||
//u_int32_t setClockDivider(int d, int ic);
|
||||
//u_int32_t getClockDivider(int ic);
|
||||
|
||||
void resetPLL();
|
||||
u_int32_t setPllReconfigReg(u_int32_t reg, u_int32_t val, int trig);
|
||||
u_int32_t getPllReconfigReg(u_int32_t reg, int trig);
|
||||
|
||||
u_int32_t setSetLength(int d);
|
||||
u_int32_t getSetLength();
|
||||
u_int32_t setWaitStates(int d);
|
||||
u_int32_t getWaitStates();
|
||||
//u_int32_t setTotClockDivider(int d);
|
||||
//u_int32_t getTotClockDivider();
|
||||
//u_int32_t setTotDutyCycle(int d);
|
||||
//u_int32_t getTotDutyCycle();
|
||||
u_int32_t setOversampling(int d);
|
||||
u_int32_t adcPipeline(int d);
|
||||
u_int32_t dbitPipeline(int d);
|
||||
|
||||
u_int32_t setExtSignal(int d, enum externalSignalFlag mode);
|
||||
int getExtSignal(int d);
|
||||
|
||||
u_int32_t setFPGASignal(int d, enum externalSignalFlag mode);
|
||||
int getFPGASignal(int d);
|
||||
|
||||
int setTiming(int t);
|
||||
|
||||
|
||||
int setConfigurationRegister(int d);
|
||||
int setToT(int d);
|
||||
int setContinousReadOut(int d);
|
||||
int startReceiver(int d);
|
||||
|
||||
int setDACRegister(int idac, int val, int imod);
|
||||
int getDacRegister(int dacnum);
|
||||
|
||||
|
||||
int getTemperature(int tempSensor);
|
||||
int initHighVoltage(int val,int imod);
|
||||
int initConfGain(int isettings,int val,int imod);
|
||||
|
||||
//int setADC(int adc);
|
||||
//int configureMAC(int ipad, long long int macad, long long int detectormacadd, int detipad, int ival, int udpport);
|
||||
int configureMAC(uint32_t destip,uint64_t destmac,uint64_t sourcemac,int detipad,int ival,uint32_t destport);
|
||||
int getAdcConfigured();
|
||||
|
||||
|
||||
u_int64_t getDetectorNumber();
|
||||
u_int32_t getFirmwareVersion();
|
||||
u_int32_t getFirmwareSVNVersion();
|
||||
|
||||
int testFifos(void);
|
||||
u_int32_t testFpga(void);
|
||||
u_int32_t testRAM(void);
|
||||
int testBus(void);
|
||||
int setDigitalTestBit(int ival);
|
||||
|
||||
int64_t set64BitReg(int64_t value, int aLSB, int aMSB);
|
||||
int64_t get64BitReg(int aLSB, int aMSB);
|
||||
|
||||
int64_t setFrames(int64_t value);
|
||||
int64_t getFrames();
|
||||
|
||||
int64_t setExposureTime(int64_t value);
|
||||
int64_t getExposureTime();
|
||||
|
||||
int64_t setGates(int64_t value);
|
||||
int64_t getGates();
|
||||
|
||||
int64_t setDelay(int64_t value);
|
||||
int64_t getDelay();
|
||||
|
||||
int64_t setPeriod(int64_t value);
|
||||
int64_t getPeriod();
|
||||
|
||||
int64_t setTrains(int64_t value);
|
||||
int64_t getTrains();
|
||||
|
||||
int64_t setProbes(int64_t value);
|
||||
int64_t getProbes();
|
||||
|
||||
int64_t getProgress();
|
||||
int64_t setProgress();
|
||||
|
||||
int64_t getActualTime();
|
||||
int64_t getMeasurementTime();
|
||||
int64_t getFramesFromStart();
|
||||
|
||||
u_int32_t runBusy(void);
|
||||
u_int32_t runState(void);
|
||||
u_int32_t dataPresent(void);
|
||||
|
||||
|
||||
int startStateMachine();
|
||||
int stopStateMachine();
|
||||
int startReadOut();
|
||||
u_int32_t fifoReset(void);
|
||||
u_int32_t fifoReadCounter(int fifonum);
|
||||
u_int32_t fifoReadStatus();
|
||||
|
||||
|
||||
u_int32_t fifo_full(void);
|
||||
|
||||
|
||||
|
||||
u_int16_t* fifo_read_event(int ns);
|
||||
u_int16_t* fifo_read_frame();
|
||||
u_int32_t* decode_data(int* datain);
|
||||
//u_int32_t move_data(u_int64_t* datain, u_int64_t* dataout);
|
||||
int setDynamicRange(int dr);
|
||||
int getDynamicRange();
|
||||
int getNModBoard();
|
||||
int setNMod(int n);
|
||||
int getNMod();
|
||||
|
||||
int setStoreInRAM(int b);
|
||||
int allocateRAM();
|
||||
|
||||
|
||||
int writeADC(int addr, int val);
|
||||
//int prepareADC();
|
||||
|
||||
|
||||
|
||||
int clearRAM();
|
||||
|
||||
|
||||
int setMaster(int f);
|
||||
int setSynchronization(int s);
|
||||
|
||||
int loadImage(int index, short int ImageVals[]);
|
||||
int readCounterBlock(int startACQ, short int CounterVals[]);
|
||||
int resetCounterBlock(int startACQ);
|
||||
|
||||
int calibratePedestal(int frames);
|
||||
|
||||
uint64_t writePatternWord(int addr, uint64_t word);
|
||||
uint64_t writePatternIOControl(uint64_t word);
|
||||
uint64_t writePatternClkControl(uint64_t word);
|
||||
int setPatternLoop(int level, int *start, int *stop, int *n);
|
||||
int setPatternWaitAddress(int level, int addr);
|
||||
uint64_t setPatternWaitTime(int level, uint64_t t);
|
||||
|
||||
|
||||
void initDac(int dacnum);
|
||||
int setDac(int dacnum,int dacvalue);
|
||||
|
||||
int setPower(int ind, int val);
|
||||
|
||||
int setROI(int nroi,ROI* arg,int *retvalsize, int *ret);
|
||||
int getChannels();
|
||||
|
||||
int getCurrent(int idac);
|
||||
int getVoltage(int idac);
|
||||
|
||||
void defineGPIOpins();
|
||||
void resetFPGA();
|
||||
void FPGAdontTouchFlash();
|
||||
void FPGATouchFlash();
|
||||
|
||||
int startWritingFPGAprogram(FILE** filefp);
|
||||
int stopWritingFPGAprogram(FILE* filefp);
|
||||
int writeFPGAProgram(char* fpgasrc, size_t fsize, FILE* filefp);
|
||||
void eraseFlash();
|
||||
|
||||
|
||||
|
||||
/*
|
||||
|
||||
u_int32_t setNBits(u_int32_t);
|
||||
u_int32_t getNBits();
|
||||
*/
|
||||
|
||||
/*
|
||||
//move to mcb_funcs?
|
||||
|
||||
int readOutChan(int *val);
|
||||
u_int32_t getModuleNumber(int modnum);
|
||||
int testShiftIn(int imod);
|
||||
int testShiftOut(int imod);
|
||||
int testShiftStSel(int imod);
|
||||
int testDataInOut(int num, int imod);
|
||||
int testExtPulse(int imod);
|
||||
int testExtPulseMux(int imod, int ow);
|
||||
int testDataInOutMux(int imod, int ow, int num);
|
||||
int testOutMux(int imod);
|
||||
int testFpgaMux(int imod);
|
||||
int calibration_sensor(int num, int *values, int *dacs) ;
|
||||
int calibration_chip(int num, int *values, int *dacs);
|
||||
*/
|
||||
|
||||
int64_t setSamples(int64_t value);
|
||||
//int setOutputMode(int d);
|
||||
int setReadOutMode(int arg);
|
||||
int vLimitCompliant(int val_mV)
|
||||
|
||||
#endif
|
||||
12
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/get_server.sh
Executable file
12
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/get_server.sh
Executable file
@ -0,0 +1,12 @@
|
||||
#!/bin/sh
|
||||
serv="pc8498"
|
||||
f="jungfrauDetectorServerTest"
|
||||
if [ "$#" -gt 0 ]; then
|
||||
f=$1
|
||||
fi
|
||||
if [ "$#" -gt 1 ]; then
|
||||
serv=$2
|
||||
fi
|
||||
tftp $serv -r $f -g
|
||||
chmod a+xrw $f
|
||||
|
||||
@ -0,0 +1,9 @@
|
||||
Path: slsDetectorsPackage/slsDetectorSoftware/jctbDetectorServer
|
||||
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
|
||||
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
|
||||
Repsitory UUID: 9ae128961675230ad322ff2867f1862dbe8566a7
|
||||
Revision: 25
|
||||
Branch: developer
|
||||
Last Changed Author: Anna_Bergamaschi
|
||||
Last Changed Rev: 3764
|
||||
Last Changed Date: 2018-05-07 14:30:14.000000002 +0200 ./Makefile
|
||||
@ -0,0 +1,6 @@
|
||||
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
|
||||
#define GITREPUUID "9ae128961675230ad322ff2867f1862dbe8566a7"
|
||||
#define GITAUTH "Anna_Bergamaschi"
|
||||
#define GITREV 0x3764
|
||||
#define GITDATE 0x20180507
|
||||
#define GITBRANCH "developer"
|
||||
@ -0,0 +1,6 @@
|
||||
#define GITURL ""
|
||||
#define GITREPUUID ""
|
||||
#define GITAUTH ""
|
||||
#define GITREV ""
|
||||
#define GITDATE ""
|
||||
#define GITBRANCH ""
|
||||
Binary file not shown.
2696
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/mcb_funcs.c
Executable file
2696
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/mcb_funcs.c
Executable file
File diff suppressed because it is too large
Load Diff
174
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/mcb_funcs.h
Executable file
174
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/mcb_funcs.h
Executable file
@ -0,0 +1,174 @@
|
||||
#ifdef MCB_FUNCS
|
||||
|
||||
#ifndef MCB_FUNCS_H
|
||||
#define MCB_FUNCS_H
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#define RGPRVALS {100,50,200}
|
||||
#define RGSH1VALS {300,200,400}
|
||||
#define RGSH2VALS {260,300,260}
|
||||
|
||||
|
||||
#define DEFAULTGAIN {11.66,9.32,14.99}
|
||||
#define DEFAULTOFFSET {817.5,828.6,804.2}
|
||||
|
||||
// DAC definitions
|
||||
enum dacsVal{VDAC0, VDAC1, VDAC2, VDAC3, VDAC4, VDAC5, VDAC6, VDAC7, HIGH_VOLTAGE, CONFGAIN};
|
||||
|
||||
/* DAC adresses */
|
||||
#define DACCS {0,0,1,1,2,2,3,3,4,4,5,5,6,6}
|
||||
#define DACADDR {0,1,0,1,0,1,0,1,0,1,0,1,0,1}
|
||||
|
||||
//Register Definitions for temp,hv,dac gain
|
||||
enum adcVals{TEMP_FPGA, TEMP_ADC};
|
||||
|
||||
//dynamic range
|
||||
/*
|
||||
#define MAX5523 commented out by dhanya
|
||||
#ifndef MAX5523
|
||||
#define MAX5533
|
||||
#endif
|
||||
#ifdef MAX5533
|
||||
#define DAC_DR 4096
|
||||
#endif
|
||||
#ifdef MAX5523
|
||||
*/
|
||||
#define DAC_DR 1024
|
||||
//#endif
|
||||
|
||||
|
||||
//reference voltage
|
||||
#define DAC_REFOUT1
|
||||
#ifdef DAC_REFOUT2
|
||||
#define DAC_MAX 2.425
|
||||
#define DAC_REFOUT 2
|
||||
#define DAC_REFOUT1
|
||||
#endif
|
||||
#ifdef DAC_REFOUT3
|
||||
#define DAC_MAX 3.885
|
||||
#define DAC_REFOUT 3
|
||||
#define DAC_REFOUT1
|
||||
#endif
|
||||
#ifdef DAC_REFOUT0
|
||||
#define DAC_MAX 1.214
|
||||
#define DAC_REFOUT 0
|
||||
#endif
|
||||
#ifdef DAC_REFOUT1
|
||||
#define DAC_MAX 1.940
|
||||
#define DAC_REFOUT 1
|
||||
#endif
|
||||
|
||||
/* dac calibration constants */
|
||||
|
||||
#define VA 1.11
|
||||
|
||||
#define CVTRIM 52.430851
|
||||
#define BVTRIM -0.102022
|
||||
#define AVTRIM 0.000050
|
||||
|
||||
#define PARTREF {100,1.55,-2.5,-2.5,0,-2.5}
|
||||
#define PARTR1 {78,10,10,10,10,10}
|
||||
#define PARTR2 {0,4.7,27,47,22,47}
|
||||
|
||||
|
||||
//chip shiftin register meaning
|
||||
#define OUTMUX_OFFSET 20
|
||||
#define PROBES_OFFSET 4
|
||||
#define OUTBUF_OFFSET 0
|
||||
|
||||
|
||||
void showbits(int h);
|
||||
|
||||
int initDetector();
|
||||
int copyChannel(sls_detector_channel *destChan, sls_detector_channel *srcChan);
|
||||
int copyChip(sls_detector_chip *destChip, sls_detector_chip *srcChip);
|
||||
int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod);
|
||||
|
||||
/* Register commands */
|
||||
/* int clearDACSregister(int imod ); */
|
||||
/* int nextDAC(int imod ); */
|
||||
int clearCSregister(int imod );
|
||||
int setCSregister(int imod );
|
||||
int nextChip(int imod );
|
||||
int firstChip(int imod );
|
||||
int clearSSregister(int imod );
|
||||
int setSSregister(int imod );
|
||||
int nextStrip(int imod );
|
||||
int selChannel(int strip,int imod );
|
||||
int selChip(int chip,int imod );
|
||||
int selMod(int mod,int imod );
|
||||
|
||||
/* DACs routines */
|
||||
/* int program_one_dac(int addr, int value,int imod ); */
|
||||
/* int set_one_dac(int imod); */
|
||||
/* int initDAC(int dac_addr, int value,int imod ); */
|
||||
/* int initDACs(int* v,int imod ); */
|
||||
/* int initDACbyIndex(int ind,int val, int imod); */
|
||||
/* int initDACbyIndexDACU(int ind,int val, int imod); */
|
||||
/* int getDACbyIndexDACU(int ind, int imod); */
|
||||
/* int getThresholdEnergy(); */
|
||||
/* int setThresholdEnergy(int ethr); */
|
||||
|
||||
|
||||
int setSettings(int i,int imod);
|
||||
|
||||
|
||||
/* Other DAC index routines*/
|
||||
int getTemperatureByModule(int tempSensor, int imod);
|
||||
int initHighVoltageByModule(int val, int imod);
|
||||
int initConfGainByModule(int isettings,int val,int imod);
|
||||
|
||||
/* Initialization*/
|
||||
int initChannel(int ft,int cae, int ae, int coe, int ocoe, int counts,int imod );
|
||||
int initChannelbyNumber(sls_detector_channel myChan);
|
||||
int getChannelbyNumber(sls_detector_channel*);
|
||||
|
||||
int getTrimbit(int imod, int ichip, int ichan);
|
||||
|
||||
int initChip(int obe, int ow,int imod );
|
||||
|
||||
int initChipWithProbes(int obe, int ow,int nprobes, int imod);
|
||||
//int getNProbes();
|
||||
|
||||
int initChipbyNumber(sls_detector_chip myChip);
|
||||
int getChipbyNumber(sls_detector_chip*);
|
||||
int initMCBregisters(int cm,int imod );
|
||||
int initModulebyNumber(sls_detector_module);
|
||||
int getModulebyNumber(sls_detector_module*);
|
||||
|
||||
/* To chips */
|
||||
int clearCounter(int imod );
|
||||
int clearOutReg(int imod);
|
||||
int setOutReg(int imod );
|
||||
int extPulse(int ncal,int imod );
|
||||
int calPulse(int ncal,int imod );
|
||||
int counterClear(int imod );
|
||||
int countEnable(int imod );
|
||||
int counterSet(int imod );
|
||||
|
||||
|
||||
/* moved from firmware_funcs */
|
||||
|
||||
int readOutChan(int *val);
|
||||
|
||||
int getModuleNumber(int modnum);
|
||||
int testShiftIn(int imod);
|
||||
int testShiftOut(int imod);
|
||||
int testShiftStSel(int imod);
|
||||
int testDataInOut(int num, int imod);
|
||||
int testExtPulse(int imod);
|
||||
int testExtPulseMux(int imod, int ow);
|
||||
int testDataInOutMux(int imod, int ow, int num);
|
||||
int testOutMux(int imod);
|
||||
int testFpgaMux(int imod);
|
||||
int calibration_sensor(int num, int *values, int *dacs) ;
|
||||
int calibration_chip(int num, int *values, int *dacs);
|
||||
|
||||
|
||||
|
||||
//ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret);
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
30
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/program_fpga.sh
Executable file
30
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/program_fpga.sh
Executable file
@ -0,0 +1,30 @@
|
||||
#!/bin/sh
|
||||
serv="pc8498"
|
||||
f="Jungfrau_CTB.rawbin"
|
||||
if [ "$#" -gt 0 ]; then
|
||||
f=$1
|
||||
fi
|
||||
if [ "$#" -gt 1 ]; then
|
||||
serv=$2
|
||||
fi
|
||||
echo "File is $f server is $serv"
|
||||
mount -t tmpfs none /mnt/
|
||||
|
||||
cd /mnt/
|
||||
tftp -r $f -g $serv
|
||||
|
||||
echo 7 > /sys/class/gpio/export
|
||||
echo 9 > /sys/class/gpio/export
|
||||
echo in > /sys/class/gpio/gpio7/direction
|
||||
echo out > /sys/class/gpio/gpio9/direction
|
||||
|
||||
|
||||
echo 0 > /sys/class/gpio/gpio9/value
|
||||
|
||||
|
||||
flash_eraseall /dev/mtd3
|
||||
cat /mnt/$f > /dev/mtd3
|
||||
|
||||
echo 1 > /sys/class/gpio/gpio9/value
|
||||
cat /sys/class/gpio/gpio7/value
|
||||
|
||||
@ -0,0 +1,551 @@
|
||||
#ifndef REGISTERS_G_H
|
||||
#define REGISTERS_G_H
|
||||
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
|
||||
/* Definitions for FPGA*/
|
||||
#define CSP0 0x20200000
|
||||
#define MEM_SIZE 0x100000
|
||||
|
||||
|
||||
|
||||
/* values defined for FPGA */
|
||||
#define MCSNUM 0x0
|
||||
#define FIXED_PATT_VAL 0xacdc1980
|
||||
|
||||
|
||||
#define FPGA_INIT_PAT 0x60008
|
||||
#define FPGA_INIT_ADDR 0xb0000000
|
||||
|
||||
//#ifdef JUNGFRAU_DHANYA
|
||||
#define POWER_ON_REG 0x5e << MEM_MAP_SHIFT
|
||||
// Pwr_I2C_SDA <= PowerReg_s(1) when PowerReg_s(3)='1' else 'Z';
|
||||
// Pwr_I2C_SCL <= PowerReg_s(0) when PowerReg_s(2)='1' else 'Z';
|
||||
|
||||
#define PWR_I2C_SCL_BIT 0
|
||||
#define PWR_I2C_SDA_BIT 1
|
||||
#define PWR_I2C_SCL_EN_BIT 2
|
||||
#define PWR_I2C_SDA_EN_BIT 3
|
||||
|
||||
#define POWER_STATUS_REG 41 << MEM_MAP_SHIFT
|
||||
|
||||
#define ADCREG1 0x08
|
||||
#define ADCREG2 0x14//20
|
||||
#define ADCREG3 0x4
|
||||
#define ADCREG4 0x5
|
||||
#define ADCREG_VREFS 24
|
||||
#define DBIT_PIPELINE_REG 89 << MEM_MAP_SHIFT //0x59 same PATTERN_N_LOOP2_REG
|
||||
#define MEM_MACHINE_FIFOS_REG 79 << MEM_MAP_SHIFT //from gotthard
|
||||
#define CONFGAIN_REG 93 << MEM_MAP_SHIFT //from gotthard
|
||||
#define ADC_PIPELINE_REG 66 << MEM_MAP_SHIFT //0x42 same as ADC_OFFSET_REG
|
||||
//#endif
|
||||
|
||||
//#define ADC_OFFSET_REG 93 << MEM_MAP_SHIFT //same as DAQ_REG
|
||||
#define ADC_INVERSION_REG 67 << MEM_MAP_SHIFT
|
||||
|
||||
#define DAC_REG 64 << MEM_MAP_SHIFT//0x17 << MEM_MAP_SHIFT// control the dacs
|
||||
//ADC
|
||||
#define ADC_WRITE_REG 65 << MEM_MAP_SHIFT//0x18 << MEM_MAP_SHIFT
|
||||
//#define ADC_SYNC_REG 66 << MEM_MAP_SHIFT//0x19 << MEM_MAP_SHIFT
|
||||
//#define HV_REG 67 << MEM_MAP_SHIFT//0x20 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
|
||||
|
||||
//#define MUTIME_REG 0x1a << MEM_MAP_SHIFT
|
||||
//temperature
|
||||
#define TEMP_IN_REG 0x1b << MEM_MAP_SHIFT
|
||||
#define TEMP_OUT_REG 0x1c << MEM_MAP_SHIFT
|
||||
//configure MAC
|
||||
#define TSE_CONF_REG 0x1d << MEM_MAP_SHIFT
|
||||
#define ENET_CONF_REG 0x1e << MEM_MAP_SHIFT
|
||||
//#define WRTSE_SHAD_REG 0x1f << MEM_MAP_SHIFT
|
||||
//HV
|
||||
|
||||
|
||||
#define DUMMY_REG 68 << MEM_MAP_SHIFT//0x21 << MEM_MAP_SHIFT
|
||||
#define FPGA_VERSION_REG 0 << MEM_MAP_SHIFT //0x22 << MEM_MAP_SHIFT
|
||||
#define PCB_REV_REG 0 << MEM_MAP_SHIFT
|
||||
#define FIX_PATT_REG 1 << MEM_MAP_SHIFT //0x23 << MEM_MAP_SHIFT
|
||||
#define CONTROL_REG 79 << MEM_MAP_SHIFT//0x24 << MEM_MAP_SHIFT
|
||||
#define STATUS_REG 2 << MEM_MAP_SHIFT //0x25 << MEM_MAP_SHIFT
|
||||
#define CONFIG_REG 77 << MEM_MAP_SHIFT//0x26 << MEM_MAP_SHIFT
|
||||
#define EXT_SIGNAL_REG 78 << MEM_MAP_SHIFT// 0x27 << MEM_MAP_SHIFT
|
||||
//#define FPGA_SVN_REG 0x29 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
#define CHIP_OF_INTRST_REG 0x2A << MEM_MAP_SHIFT
|
||||
|
||||
//FIFO
|
||||
#define LOOK_AT_ME_REG 3 << MEM_MAP_SHIFT //0x28 << MEM_MAP_SHIFT
|
||||
#define SYSTEM_STATUS_REG 4 << MEM_MAP_SHIFT
|
||||
|
||||
#define FIFO_DATA_REG 6 << MEM_MAP_SHIFT
|
||||
#define FIFO_STATUS_REG 7 << MEM_MAP_SHIFT
|
||||
|
||||
// constant FifoDigitalInReg_c : integer := 60;
|
||||
#define FIFO_DIGITAL_DATA_LSB_REG 60 << MEM_MAP_SHIFT
|
||||
#define FIFO_DIGITAL_DATA_MSB_REG 61 << MEM_MAP_SHIFT
|
||||
|
||||
#define FIFO_DATA_REG_OFF 0x50 << MEM_MAP_SHIFT ///////
|
||||
//to read back dac registers
|
||||
//#define MOD_DACS1_REG 0x65 << MEM_MAP_SHIFT
|
||||
//#define MOD_DACS2_REG 0x66 << MEM_MAP_SHIFT
|
||||
//#define MOD_DACS3_REG 0x67 << MEM_MAP_SHIFT
|
||||
|
||||
//user entered
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define GET_ACTUAL_TIME_LSB_REG 16 << MEM_MAP_SHIFT
|
||||
#define GET_ACTUAL_TIME_MSB_REG 17 << MEM_MAP_SHIFT
|
||||
|
||||
#define GET_MEASUREMENT_TIME_LSB_REG 38 << MEM_MAP_SHIFT
|
||||
#define GET_MEASUREMENT_TIME_MSB_REG 39 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
#define SET_DELAY_LSB_REG 96 << MEM_MAP_SHIFT //0x68 << MEM_MAP_SHIFT
|
||||
#define SET_DELAY_MSB_REG 97 << MEM_MAP_SHIFT //0x69 << MEM_MAP_SHIFT
|
||||
#define GET_DELAY_LSB_REG 18 << MEM_MAP_SHIFT//0x6a << MEM_MAP_SHIFT
|
||||
#define GET_DELAY_MSB_REG 19 << MEM_MAP_SHIFT//0x6b << MEM_MAP_SHIFT
|
||||
|
||||
#define SET_CYCLES_LSB_REG 98 << MEM_MAP_SHIFT//0x6c << MEM_MAP_SHIFT
|
||||
#define SET_CYCLES_MSB_REG 99 << MEM_MAP_SHIFT//0x6d << MEM_MAP_SHIFT
|
||||
#define GET_CYCLES_LSB_REG 20 << MEM_MAP_SHIFT//0x6e << MEM_MAP_SHIFT
|
||||
#define GET_CYCLES_MSB_REG 21 << MEM_MAP_SHIFT//0x6f << MEM_MAP_SHIFT
|
||||
|
||||
#define SET_FRAMES_LSB_REG 100 << MEM_MAP_SHIFT//0x70 << MEM_MAP_SHIFT
|
||||
#define SET_FRAMES_MSB_REG 101 << MEM_MAP_SHIFT//0x71 << MEM_MAP_SHIFT
|
||||
#define GET_FRAMES_LSB_REG 22 << MEM_MAP_SHIFT//0x72 << MEM_MAP_SHIFT
|
||||
#define GET_FRAMES_MSB_REG 23 << MEM_MAP_SHIFT//0x73 << MEM_MAP_SHIFT
|
||||
|
||||
#define SET_PERIOD_LSB_REG 102 << MEM_MAP_SHIFT//0x74 << MEM_MAP_SHIFT
|
||||
#define SET_PERIOD_MSB_REG 103 << MEM_MAP_SHIFT//0x75 << MEM_MAP_SHIFT
|
||||
#define GET_PERIOD_LSB_REG 24 << MEM_MAP_SHIFT//0x76 << MEM_MAP_SHIFT
|
||||
#define GET_PERIOD_MSB_REG 25 << MEM_MAP_SHIFT//0x77 << MEM_MAP_SHIFT
|
||||
|
||||
//#define PATTERN_WAIT0_TIME_REG_LSB 114 << MEM_MAP_SHIFT
|
||||
//#define PATTERN_WAIT0_TIME_REG_MSB 115 << MEM_MAP_SHIFT
|
||||
#define SET_EXPTIME_LSB_REG 114 << MEM_MAP_SHIFT//0x78 << MEM_MAP_SHIFT
|
||||
#define SET_EXPTIME_MSB_REG 115 << MEM_MAP_SHIFT//0x79 << MEM_MAP_SHIFT
|
||||
#define GET_EXPTIME_LSB_REG 26 << MEM_MAP_SHIFT//0x7a << MEM_MAP_SHIFT
|
||||
#define GET_EXPTIME_MSB_REG 27 << MEM_MAP_SHIFT//0x7b << MEM_MAP_SHIFT
|
||||
|
||||
#define SET_GATES_LSB_REG 106 << MEM_MAP_SHIFT//0x7c << MEM_MAP_SHIFT
|
||||
#define SET_GATES_MSB_REG 107 << MEM_MAP_SHIFT//0x7d << MEM_MAP_SHIFT
|
||||
#define GET_GATES_LSB_REG 28 << MEM_MAP_SHIFT//0x7e << MEM_MAP_SHIFT
|
||||
#define GET_GATES_MSB_REG 29 << MEM_MAP_SHIFT//0x7f << MEM_MAP_SHIFT
|
||||
|
||||
#define DATA_IN_LSB_REG 30 << MEM_MAP_SHIFT
|
||||
#define DATA_IN_MSB_REG 31 << MEM_MAP_SHIFT
|
||||
|
||||
#define PATTERN_OUT_LSB_REG 32 << MEM_MAP_SHIFT
|
||||
#define PATTERN_OUT_MSB_REG 33 << MEM_MAP_SHIFT
|
||||
|
||||
#define FRAMES_FROM_START_LSB_REG 34 << MEM_MAP_SHIFT
|
||||
#define FRAMES_FROM_START_MSB_REG 35 << MEM_MAP_SHIFT
|
||||
|
||||
#define FRAMES_FROM_START_PG_LSB_REG 36 << MEM_MAP_SHIFT
|
||||
#define FRAMES_FROM_START_PG_MSB_REG 37 << MEM_MAP_SHIFT
|
||||
|
||||
#define SLOW_ADC_REG 43 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
|
||||
#define PLL_PARAM_REG 80 << MEM_MAP_SHIFT//0x37 << MEM_MAP_SHIFT
|
||||
#define PLL_PARAM_OUT_REG 5 << MEM_MAP_SHIFT //0x38 << MEM_MAP_SHIFT
|
||||
#define PLL_CNTRL_REG 81 << MEM_MAP_SHIFT//0x34 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
#ifdef NEW_GBE_INTERFACE
|
||||
#define GBE_PARAM_OUT_REG 40 << MEM_MAP_SHIFT
|
||||
#define GBE_PARAM_REG 69 << MEM_MAP_SHIFT
|
||||
#define GBE_CNTRL_REG 70 << MEM_MAP_SHIFT
|
||||
#else
|
||||
#define RX_UDP_AREG 69 << MEM_MAP_SHIFT //rx_udpip_AReg_c : integer:= 69; *\/
|
||||
#define UDPPORTS_AREG 70 << MEM_MAP_SHIFT// udpports_AReg_c : integer:= 70; *\/
|
||||
#define RX_UDPMACL_AREG 71 << MEM_MAP_SHIFT//rx_udpmacL_AReg_c : integer:= 71; *\/
|
||||
#define RX_UDPMACH_AREG 72 << MEM_MAP_SHIFT//rx_udpmacH_AReg_c : integer:= 72; *\/
|
||||
#define DETECTORMACL_AREG 73 << MEM_MAP_SHIFT//detectormacL_AReg_c : integer:= 73; *\/
|
||||
#define DETECTORMACH_AREG 74 << MEM_MAP_SHIFT//detectormacH_AReg_c : integer:= 74; *\/
|
||||
#define DETECTORIP_AREG 75 << MEM_MAP_SHIFT//detectorip_AReg_c : integer:= 75; *\/
|
||||
#define IPCHKSUM_AREG 76 << MEM_MAP_SHIFT//ipchksum_AReg_c : integer:= 76; *\/ */
|
||||
#endif
|
||||
|
||||
|
||||
#define PATTERN_CNTRL_REG 82 << MEM_MAP_SHIFT
|
||||
#define PATTERN_LIMITS_AREG 83 << MEM_MAP_SHIFT
|
||||
|
||||
#define PATTERN_LOOP0_AREG 84 << MEM_MAP_SHIFT
|
||||
#define PATTERN_N_LOOP0_REG 85 << MEM_MAP_SHIFT
|
||||
|
||||
#define PATTERN_LOOP1_AREG 86 << MEM_MAP_SHIFT
|
||||
#define PATTERN_N_LOOP1_REG 87 << MEM_MAP_SHIFT
|
||||
|
||||
#define PATTERN_LOOP2_AREG 88 << MEM_MAP_SHIFT
|
||||
#define PATTERN_N_LOOP2_REG 89 << MEM_MAP_SHIFT
|
||||
|
||||
#define PATTERN_WAIT0_AREG 90 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT1_AREG 91 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT2_AREG 92 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
|
||||
//#define DAQ_REG 93 << MEM_MAP_SHIFT //unused
|
||||
#define NSAMPLES_REG 93 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
#define HV_REG 95 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
|
||||
#define PATTERN_IOCTRL_REG_LSB 108 << MEM_MAP_SHIFT
|
||||
#define PATTERN_IOCTRL_REG_MSB 109 << MEM_MAP_SHIFT
|
||||
|
||||
#define PATTERN_IOCLKCTRL_REG_LSB 110 << MEM_MAP_SHIFT
|
||||
#define PATTERN_IOCLKCTRL_REG_MSB 111 << MEM_MAP_SHIFT
|
||||
#define PATTERN_IN_REG_LSB 112 << MEM_MAP_SHIFT
|
||||
#define PATTERN_IN_REG_MSB 113 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT0_TIME_REG_LSB 114 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT0_TIME_REG_MSB 115 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT1_TIME_REG_LSB 116 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT1_TIME_REG_MSB 117 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT2_TIME_REG_LSB 118 << MEM_MAP_SHIFT
|
||||
#define PATTERN_WAIT2_TIME_REG_MSB 119 << MEM_MAP_SHIFT
|
||||
|
||||
//#define DAC_REG_OFF 120
|
||||
//#define DAC_0_1_VAL_REG 120 << MEM_MAP_SHIFT
|
||||
//#define DAC_2_3_VAL_REG 121 << MEM_MAP_SHIFT
|
||||
//#define DAC_4_5_VAL_REG 122 << MEM_MAP_SHIFT
|
||||
//#define DAC_6_7_VAL_REG 123 << MEM_MAP_SHIFT
|
||||
//#define DAC_8_9_VAL_REG 124 << MEM_MAP_SHIFT
|
||||
//#define DAC_10_11_VAL_REG 125 << MEM_MAP_SHIFT
|
||||
//#define DAC_12_13_VAL_REG 126 << MEM_MAP_SHIFT
|
||||
//#define DAC_14_15_VAL_REG 127 << MEM_MAP_SHIFT
|
||||
#define DAC_VAL_REG 121 << MEM_MAP_SHIFT
|
||||
#define DAC_NUM_REG 122 << MEM_MAP_SHIFT
|
||||
#define DAC_VAL_OUT_REG 42 << MEM_MAP_SHIFT
|
||||
#define ADC_LATCH_DISABLE_REG 120 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/* registers defined in FPGA */
|
||||
#define GAIN_REG 0
|
||||
//#define FLOW_CONTROL_REG 0x11 << MEM_MAP_SHIFT
|
||||
//#define FLOW_STATUS_REG 0x12 << MEM_MAP_SHIFT
|
||||
//#define FRAME_REG 0x13 << MEM_MAP_SHIFT
|
||||
#define MULTI_PURPOSE_REG 0
|
||||
//#define TIME_FROM_START_REG 0x16 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
#define ROI_REG 0 // 0x35 << MEM_MAP_SHIFT
|
||||
#define OVERSAMPLING_REG 0 // 0x36 << MEM_MAP_SHIFT
|
||||
#define MOENCH_CNTR_REG 0 // 0x31 << MEM_MAP_SHIFT
|
||||
#define MOENCH_CNTR_OUT_REG 0 // 0x33 << MEM_MAP_SHIFT
|
||||
#define MOENCH_CNTR_CONF_REG 0 // 0x32 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
|
||||
//image
|
||||
#define DARK_IMAGE_REG 0 // 0x81 << MEM_MAP_SHIFT
|
||||
#define GAIN_IMAGE_REG 0 // 0x82 << MEM_MAP_SHIFT
|
||||
|
||||
//counter block memory
|
||||
#define COUNTER_MEMORY_REG 0 // 0x85 << MEM_MAP_SHIFT
|
||||
|
||||
|
||||
//not used
|
||||
//#define MCB_DOUT_REG_OFF 0 // 0x200000
|
||||
//#define FIFO_CNTRL_REG_OFF 0 // 0x300000
|
||||
//#define FIFO_COUNTR_REG_OFF 0 // 0x400000
|
||||
//not used so far
|
||||
//#define SPEED_REG 0 // 0x006000
|
||||
//#define SET_NBITS_REG 0 // 0x008000
|
||||
//not used
|
||||
//#define GET_SHIFT_IN_REG 0 // 0x022000
|
||||
|
||||
|
||||
|
||||
#define SHIFTMOD 2
|
||||
#define SHIFTFIFO 9
|
||||
|
||||
/** for PCB_REV_REG */
|
||||
#define DETECTOR_TYPE_MASK 0xFF000000
|
||||
#define DETECTOR_TYPE_OFFSET 24
|
||||
#define BOARD_REVISION_MASK 0xFFFFFF
|
||||
#define MOENCH03_MODULE_ID 2
|
||||
#define JUNGFRAU_MODULE_ID 1
|
||||
#define JUNGFRAU_CTB_ID 3
|
||||
|
||||
|
||||
|
||||
|
||||
/* for control register (16bit only)*/
|
||||
#define START_ACQ_BIT 0x0001
|
||||
#define STOP_ACQ_BIT 0x0002
|
||||
#define START_FIFOTEST_BIT 0x0004 // ?????
|
||||
#define STOP_FIFOTEST_BIT 0x0008 // ??????
|
||||
#define START_READOUT_BIT 0x0010
|
||||
#define STOP_READOUT_BIT 0x0020
|
||||
#define START_EXPOSURE_BIT 0x0040
|
||||
#define STOP_EXPOSURE_BIT 0x0080
|
||||
#define START_TRAIN_BIT 0x0100
|
||||
#define STOP_TRAIN_BIT 0x0200
|
||||
#define FIFO_RESET_BIT 0x8000
|
||||
#define SYNC_RESET 0x0400
|
||||
#define GB10_RESET_BIT 0x0800
|
||||
#define MEM_RESET_BIT 0x1000
|
||||
|
||||
/* for status register */
|
||||
#define RUN_BUSY_BIT 0x00000001
|
||||
#define READOUT_BUSY_BIT 0x00000002
|
||||
#define FIFOTEST_BUSY_BIT 0x00000004 //????
|
||||
#define WAITING_FOR_TRIGGER_BIT 0x00000008
|
||||
#define DELAYBEFORE_BIT 0x00000010
|
||||
#define DELAYAFTER_BIT 0x00000020
|
||||
#define EXPOSING_BIT 0x00000040
|
||||
#define COUNT_ENABLE_BIT 0x00000080
|
||||
#define READSTATE_0_BIT 0x00000100
|
||||
#define READSTATE_1_BIT 0x00000200
|
||||
#define READSTATE_2_BIT 0x00000400
|
||||
#define LAM_BIT 0x00000400 // error!
|
||||
#define SOME_FIFO_FULL_BIT 0x00000800 // error!
|
||||
|
||||
|
||||
|
||||
#define RUNSTATE_0_BIT 0x00001000
|
||||
#define RUNSTATE_1_BIT 0x00002000
|
||||
#define RUNSTATE_2_BIT 0x00004000
|
||||
#define STOPPED_BIT 0x00008000 // stopped!
|
||||
#define ALL_FIFO_EMPTY_BIT 0x00010000 // data ready
|
||||
#define RUNMACHINE_BUSY_BIT 0x00020000
|
||||
#define READMACHINE_BUSY_BIT 0x00040000
|
||||
#define PLL_RECONFIG_BUSY 0x00100000
|
||||
|
||||
|
||||
|
||||
/* for fifo status register */
|
||||
#define FIFO_ENABLED_BIT 0x80000000
|
||||
#define FIFO_DISABLED_BIT 0x01000000
|
||||
#define FIFO_ERROR_BIT 0x08000000
|
||||
#define FIFO_EMPTY_BIT 0x04000000
|
||||
#define FIFO_DATA_READY_BIT 0x02000000
|
||||
#define FIFO_COUNTER_MASK 0x000001ff
|
||||
#define FIFO_NM_MASK 0x00e00000
|
||||
#define FIFO_NM_OFF 21
|
||||
#define FIFO_NC_MASK 0x001ffe00
|
||||
#define FIFO_NC_OFF 9
|
||||
|
||||
/* for config register *///not really used yet
|
||||
#define TOT_ENABLE_BIT 0x00000002
|
||||
#define TIMED_GATE_BIT 0x00000004
|
||||
#define CONT_RO_ENABLE_BIT 0x00080000
|
||||
#define GB10_NOT_CPU_BIT 0x00001000
|
||||
#define ADC_OUTPUT_DISABLE_BIT 0x00100
|
||||
#define DIGITAL_OUTPUT_ENABLE_BIT 0x00200
|
||||
|
||||
|
||||
/* for speed register */
|
||||
#define CLK_DIVIDER_MASK 0x000000ff
|
||||
#define CLK_DIVIDER_OFFSET 0
|
||||
#define SET_LENGTH_MASK 0x00000f00
|
||||
#define SET_LENGTH_OFFSET 8
|
||||
#define WAIT_STATES_MASK 0x0000f000
|
||||
#define WAIT_STATES_OFFSET 12
|
||||
#define TOTCLK_DIVIDER_MASK 0xff000000
|
||||
#define TOTCLK_DIVIDER_OFFSET 24
|
||||
#define TOTCLK_DUTYCYCLE_MASK 0x00ff0000
|
||||
#define TOTCLK_DUTYCYCLE_OFFSET 16
|
||||
|
||||
/* for external signal register */
|
||||
#define SIGNAL_OFFSET 4
|
||||
#define SIGNAL_MASK 0xF
|
||||
#define EXT_SIG_OFF 0x0
|
||||
#define EXT_GATE_IN_ACTIVEHIGH 0x1
|
||||
#define EXT_GATE_IN_ACTIVELOW 0x2
|
||||
#define EXT_TRIG_IN_RISING 0x3
|
||||
#define EXT_TRIG_IN_FALLING 0x4
|
||||
#define EXT_RO_TRIG_IN_RISING 0x5
|
||||
#define EXT_RO_TRIG_IN_FALLING 0x6
|
||||
#define EXT_GATE_OUT_ACTIVEHIGH 0x7
|
||||
#define EXT_GATE_OUT_ACTIVELOW 0x8
|
||||
#define EXT_TRIG_OUT_RISING 0x9
|
||||
#define EXT_TRIG_OUT_FALLING 0xA
|
||||
#define EXT_RO_TRIG_OUT_RISING 0xB
|
||||
#define EXT_RO_TRIG_OUT_FALLING 0xC
|
||||
|
||||
|
||||
|
||||
/* for temperature register */
|
||||
#define T1_CLK_BIT 0x00000001
|
||||
#define T1_CS_BIT 0x00000002
|
||||
#define T2_CLK_BIT 0x00000004
|
||||
#define T2_CS_BIT 0x00000008
|
||||
|
||||
|
||||
|
||||
/* fifo control register */
|
||||
//#define FIFO_RESET_BIT 0x00000001
|
||||
//#define FIFO_DISABLE_TOGGLE_BIT 0x00000002
|
||||
|
||||
|
||||
//chip shiftin register meaning
|
||||
#define OUTMUX_OFF 20
|
||||
#define OUTMUX_MASK 0x1f
|
||||
#define PROBES_OFF 4
|
||||
#define PROBES_MASK 0x7f
|
||||
#define OUTBUF_OFF 0
|
||||
#define OUTBUF_MASK 1
|
||||
|
||||
|
||||
/* multi purpose register */
|
||||
#define PHASE_STEP_BIT 0x00000001
|
||||
#define PHASE_STEP_OFFSET 0
|
||||
// #define xxx_BIT 0x00000002
|
||||
#define RESET_COUNTER_BIT 0x00000004
|
||||
#define RESET_COUNTER_OFFSET 2
|
||||
//#define xxx_BIT 0x00000008
|
||||
//#define xxx_BIT 0x00000010
|
||||
#define SW1_BIT 0x00000020
|
||||
#define SW1_OFFSET 5
|
||||
#define WRITE_BACK_BIT 0x00000040
|
||||
#define WRITE_BACK_OFFSET 6
|
||||
#define RESET_BIT 0x00000080
|
||||
#define RESET_OFFSET 7
|
||||
#define ENET_RESETN_BIT 0x00000800
|
||||
#define ENET_RESETN_OFFSET 11
|
||||
#define INT_RSTN_BIT 0x00002000
|
||||
#define INT_RSTN_OFFSET 13
|
||||
#define DIGITAL_TEST_BIT 0x00004000
|
||||
#define DIGITAL_TEST_OFFSET 14
|
||||
//#define CHANGE_AT_POWER_ON_BIT 0x00008000
|
||||
//#define CHANGE_AT_POWER_ON_OFFSET 15
|
||||
|
||||
|
||||
/* settings/conf gain register */
|
||||
#define GAIN_MASK 0x0000000f
|
||||
#define GAIN_OFFSET 0
|
||||
#define SETTINGS_MASK 0x000000f0
|
||||
#define SETTINGS_OFFSET 4
|
||||
|
||||
|
||||
/* CHIP_OF_INTRST_REG */
|
||||
#define CHANNEL_MASK 0xffff0000
|
||||
#define CHANNEL_OFFSET 16
|
||||
#define ACTIVE_ADC_MASK 0x0000001f
|
||||
|
||||
|
||||
|
||||
/**ADC SYNC CLEAN FIFO*/
|
||||
#define ADCSYNC_CLEAN_FIFO_BITS 0x300000
|
||||
#define CLEAN_FIFO_MASK 0x0fffff
|
||||
|
||||
|
||||
|
||||
|
||||
enum {run_clk_c, adc_clk_c, sync_clk_c, dbit_clk_c};
|
||||
|
||||
|
||||
|
||||
|
||||
#define PLL_CNTR_ADDR_OFF 16 //PLL_CNTR_REG bits 21 downto 16 represent the counter address
|
||||
|
||||
#define PLL_CNTR_RECONFIG_RESET_BIT 0
|
||||
#define PLL_CNTR_READ_BIT 1
|
||||
#define PLL_CNTR_WRITE_BIT 2
|
||||
#define PLL_CNTR_PLL_RESET_BIT 3
|
||||
|
||||
|
||||
#define PLL_CNTR_PHASE_EN_BIT 8
|
||||
#define PLL_CNTR_UPDN_BIT 9
|
||||
#define PLL_CNTR_CNTSEL_OFF 10
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
#define PLL_MODE_REG 0x0
|
||||
#define PLL_STATUS_REG 0x1
|
||||
#define PLL_START_REG 0x2
|
||||
#define PLL_N_COUNTER_REG 0x3
|
||||
#define PLL_M_COUNTER_REG 0x4
|
||||
#define PLL_C_COUNTER_REG 0x5 //which ccounter stands in param 22:18; 7:0 lowcount 15:8 highcount; 16 bypassenable; 17 oddivision
|
||||
#define PLL_PHASE_SHIFT_REG 0x6 // which ccounter stands in param 16:20; 21 updown (1 up, 0 down)
|
||||
#define PLL_K_COUNTER_REG 0x7
|
||||
#define PLL_BANDWIDTH_REG 0x8
|
||||
#define PLL_CHARGEPUMP_REG 0x9
|
||||
#define PLL_VCO_DIV_REG 0x1c
|
||||
#define PLL_MIF_REG 0x1f
|
||||
|
||||
#define PPL_M_CNT_PARAM_DEFAULT 0x4040
|
||||
#define PPL_N_CNT_PARAM_DEFAULT 0x20D0C
|
||||
#define PPL_C0_CNT_PARAM_DEFAULT 0x20D0C
|
||||
#define PPL_C1_CNT_PARAM_DEFAULT 0xA0A0
|
||||
#define PPL_C2_CNT_PARAM_DEFAULT 0x20D0C
|
||||
#define PPL_C3_CNT_PARAM_DEFAULT 0x0808
|
||||
#define PPL_BW_PARAM_DEFAULT 0x2EE0
|
||||
#define PPL_VCO_PARAM_DEFAULT 0x1
|
||||
|
||||
#define NEW_PLL_RECONFIG
|
||||
|
||||
#ifdef NEW_PLL_RECONFIG
|
||||
#define PLL_VCO_FREQ_MHZ 400//480//800
|
||||
#else
|
||||
#define PLL_VCO_FREQ_MHZ 480//800
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
/*
|
||||
GBE parameter and control registers definitions
|
||||
*/
|
||||
|
||||
#define GBE_CTRL_WSTROBE 0
|
||||
#define GBE_CTRL_VAR_OFFSET 16
|
||||
#define GBE_CTRL_VAR_MASK 0XF
|
||||
#define GBE_CTRL_RAMADDR_OFFSET 24
|
||||
#define GBE_CTRL_RAMADDR_MASK 0X3F
|
||||
#define GBE_CTRL_INTERFACE 23
|
||||
|
||||
#define RX_UDP_IP_ADDR 0
|
||||
#define RX_UDP_PORTS_ADDR 1
|
||||
#define RX_UDP_MAC_L_ADDR 2
|
||||
#define RX_UDP_MAC_H_ADDR 3
|
||||
#define IPCHECKSUM_ADDR 4
|
||||
#define GBE_DELAY_ADDR 5
|
||||
#define GBE_RESERVED1_ADDR 6
|
||||
#define GBE_RESERVED2_ADDR 7
|
||||
#define DETECTOR_MAC_L_ADDR 8
|
||||
#define DETECTOR_MAC_H_ADDR 9
|
||||
#define DETECTOR_IP_ADDR 10
|
||||
|
||||
|
||||
|
||||
/**------------------
|
||||
-- pattern registers definitions
|
||||
--------------------------------------------- */
|
||||
#define IOSIGNALS_MASK 0xfffffffffffff
|
||||
#define ADC_ENABLE_BIT 63
|
||||
#define APATTERN_MASK 0xffff
|
||||
#define ASTART_OFFSET 0
|
||||
#define ASTOP_OFFSET 16
|
||||
#define PATTERN_CTRL_WRITE_BIT 0
|
||||
#define PATTERN_CTRL_READ_BIT 1
|
||||
#define PATTERN_CTRL_ADDR_OFFSET 16
|
||||
#define MAX_PATTERN_LENGTH 1024
|
||||
|
||||
|
||||
#endif
|
||||
|
||||
139
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/server.c
Executable file
139
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/server.c
Executable file
@ -0,0 +1,139 @@
|
||||
/* A simple server in the internet domain using TCP
|
||||
The port number is passed as an argument */
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "communication_funcs.h"
|
||||
#include "server_funcs.h"
|
||||
#include <string.h>
|
||||
|
||||
|
||||
|
||||
extern int sockfd;
|
||||
extern int phase_shift;
|
||||
|
||||
|
||||
|
||||
void error(char *msg)
|
||||
{
|
||||
perror(msg);
|
||||
}
|
||||
|
||||
int main(int argc, char *argv[])
|
||||
{
|
||||
int portno, b;
|
||||
char cmd[500];
|
||||
int retval=OK;
|
||||
int sd, fd;
|
||||
int iarg;
|
||||
int checkType = 1;
|
||||
|
||||
|
||||
for(iarg=1; iarg<argc; iarg++){
|
||||
|
||||
if(!strcasecmp(argv[iarg],"-phaseshift")){
|
||||
if(argc==iarg+1){
|
||||
printf("No phaseshift given. Exiting.\n");
|
||||
return 1;
|
||||
}
|
||||
if ( sscanf(argv[iarg+1],"%d",&phase_shift)==0) {
|
||||
printf("could not decode phase shift\n");
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
else if(!strcasecmp(argv[iarg],"-test")){
|
||||
if(argc==iarg+1){
|
||||
printf("No test condition given. Exiting.\n");
|
||||
return 1;
|
||||
}
|
||||
if(!strcasecmp(argv[iarg+1],"with_gotthard")){
|
||||
checkType = 0;
|
||||
}else{
|
||||
printf("could not decode test condition. Possible arguments: with_gotthard. Exiting\n");
|
||||
return 1;
|
||||
}
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
//stop server
|
||||
if ((argc > 2) && (!strcasecmp(argv[2],"stopserver"))){
|
||||
portno = DEFAULT_PORTNO+1;
|
||||
if ( sscanf(argv[1],"%d",&portno) ==0) {
|
||||
printf("could not open stop server: unknown port\n");
|
||||
return 1;
|
||||
}
|
||||
b=0;
|
||||
printf("\n\nStop Server\nOpening stop server on port %d\n",portno);
|
||||
checkType=0;
|
||||
|
||||
}
|
||||
|
||||
//control server
|
||||
else {
|
||||
portno = DEFAULT_PORTNO;
|
||||
if(checkType)
|
||||
sprintf(cmd,"%s %d stopserver &",argv[0],DEFAULT_PORTNO+1);
|
||||
else
|
||||
sprintf(cmd,"%s %d stopserver -test with_gotthard &",argv[0],DEFAULT_PORTNO+1);
|
||||
printf("\n\nControl Server\nOpening control server on port %d\n",portno );
|
||||
|
||||
//printf("\n\ncmd:%s\n",cmd);
|
||||
system(cmd);
|
||||
b=1;
|
||||
checkType=1;
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
init_detector(b, checkType);
|
||||
|
||||
|
||||
sd=bindSocket(portno);
|
||||
sockfd=sd;
|
||||
if (getServerError(sd)) {
|
||||
printf("server error!\n");
|
||||
return -1;
|
||||
}
|
||||
|
||||
/* assign function table */
|
||||
function_table();
|
||||
#ifdef VERBOSE
|
||||
printf("function table assigned \n");
|
||||
#endif
|
||||
|
||||
|
||||
/* waits for connection */
|
||||
while(retval!=GOODBYE) {
|
||||
#ifdef VERBOSE
|
||||
printf("\n");
|
||||
#endif
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("Waiting for client call\n");
|
||||
#endif
|
||||
fd=acceptConnection(sockfd);
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("Conenction accepted\n");
|
||||
#endif
|
||||
retval=decode_function(fd);
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("function executed\n");
|
||||
#endif
|
||||
closeConnection(fd);
|
||||
#ifdef VERY_VERBOSE
|
||||
printf("connection closed\n");
|
||||
#endif
|
||||
}
|
||||
|
||||
exitServer(sockfd);
|
||||
printf("Goodbye!\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
62
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/server_defs.h
Executable file
62
slsDetectorSoftware/slsDetectorServers/jctbDetectorServer/server_defs.h
Executable file
@ -0,0 +1,62 @@
|
||||
#ifndef SERVER_DEFS_H
|
||||
#define SERVER_DEFS_H
|
||||
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
|
||||
// Hardware definitions
|
||||
|
||||
#define NCHAN 36
|
||||
#define NCHIP 1
|
||||
#define NADC 9 //
|
||||
|
||||
/* #ifdef CTB */
|
||||
/* #define NDAC 24 */
|
||||
/* #define NPWR 5 */
|
||||
/* #else */
|
||||
/* #define NDAC 16 */
|
||||
/* #define NPWR 0 */
|
||||
/* #endif */
|
||||
#define DAC_CMD_OFF 20
|
||||
|
||||
#define NMAXMODX 1
|
||||
#define NMAXMODY 1
|
||||
#define NMAXMOD (NMAXMODX*NMAXMODY)
|
||||
|
||||
#define NCHANS (NCHAN*NCHIP*NMAXMOD)
|
||||
#define NDACS (NDAC*NMAXMOD)
|
||||
|
||||
|
||||
/**when moench readout tested with gotthard module*/
|
||||
|
||||
#define TRIM_DR (((int)pow(2,NTRIMBITS))-1)
|
||||
#define COUNT_DR (((int)pow(2,NCOUNTBITS))-1)
|
||||
|
||||
|
||||
#define ALLMOD 0xffff
|
||||
#define ALLFIFO 0xffff
|
||||
|
||||
#define GOTTHARD_ADCSYNC_VAL 0x32214
|
||||
#define ADCSYNC_VAL 0x02111
|
||||
#define TOKEN_RESTART_DELAY 0x88000000
|
||||
#define TOKEN_RESTART_DELAY_ROI 0x1b000000
|
||||
#define TOKEN_TIMING_REV1 0x1f16
|
||||
#define TOKEN_TIMING_REV2 0x1f0f
|
||||
|
||||
#define DEFAULT_PHASE_SHIFT 0 // 120
|
||||
#define DEFAULT_IP_PACKETSIZE 0x0522
|
||||
#define DEFAULT_UDP_PACKETSIZE 0x050E
|
||||
#define ADC1_IP_PACKETSIZE 256*2+14+20
|
||||
#define ADC1_UDP_PACKETSIZE 256*2+4+8+2
|
||||
|
||||
#ifdef VIRTUAL
|
||||
#define DEBUGOUT
|
||||
#endif
|
||||
|
||||
#define CLK_FREQ 156.25E+6
|
||||
#define ADC_CLK_FREQ 32E+6
|
||||
|
||||
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user