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MY3.0:read and write Registers, frames, cycles, delay (#64)

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* MY3.0:read and write Registers, frames, cycles, delay

* write pattern seems to work

* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)

* clk check for aquistition time

* clk check for aquistition time

* Update slsDetectorServer_defs.h

* Update slsDetectorFunctionList.c
This commit is contained in:
Marie Andrä
2019-09-30 14:36:33 +02:00
committed by Dhanya Thattil
parent 3d52a2f169
commit 6e6fcec698
9 changed files with 490 additions and 56 deletions
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4
slsDetectorServers/slsDetectorServer/src/nios.c
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@ -9,7 +9,7 @@
/* global variables */
u_int32_t* csp0base = 0;
#define CSP0 0x18000000
#define CSP0 0x18060000
#define MEM_SIZE 0x100000
@ -21,7 +21,7 @@ void bus_w(u_int32_t offset, u_int32_t data) {
u_int32_t bus_r(u_int32_t offset) {
volatile u_int32_t *ptr1;
ptr1=(u_int32_t*)(csp0base + offset/(sizeof(u_int32_t)));
ptr1=(u_int32_t*)(csp0base + offset/(sizeof(u_int32_t)));
return *ptr1;
}