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MY3.0:read and write Registers, frames, cycles, delay (#64)

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* MY3.0:read and write Registers, frames, cycles, delay

* write pattern seems to work

* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)

* clk check for aquistition time

* clk check for aquistition time

* Update slsDetectorServer_defs.h

* Update slsDetectorFunctionList.c
This commit is contained in:
Marie Andrä
2019-09-30 14:36:33 +02:00
committed by Dhanya Thattil
parent 3d52a2f169
commit 6e6fcec698
9 changed files with 490 additions and 56 deletions
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12
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
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@ -1,6 +1,5 @@
#pragma once
#include "sls_detector_defs.h"
#include "RegisterDefs.h"
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
@ -9,20 +8,23 @@
#define NCHAN (128)
#define NCHIP (10)
#define NDAC (16)
#define TEMP_CLK (20) /* MHz */
#define HV_SOFT_MAX_VOLTAGE (200)
#define HV_HARD_MAX_VOLTAGE (530)
#define HV_DRIVER_FILE_NAME ("/root/devlinks/hvdac")
#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
/** Default Parameters */
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (100*1000*1000) //ns
#define DEFAULT_PERIOD (2*1000*1000) //ns
#define DEFAULT_DELAY_AFTER_TRIGGER (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_RUN_CLK (125)
#define DEFAULT_TICK_CLK (20) // will be fixed later. Not configurable
#define DEFAULT_SAMPLING_CLK (80)
/* Enums */
enum CLKINDEX {RUN_CLK, TICK_CLK, SAMPLING_CLK, NUM_CLOCKS};
enum DACINDEX {VIBIASSH, VTRIM, VIPRE, VRFSHNPOL, VTH1, VIPREOUT, VRF, VTH2, CAS, CASSH, VPL, VDCSH, VICIN, VICINSH, VICBIAS, VPH, VTH3, VRFSH};
#define DEFAULT_DAC_VALS {1200, /* vIbiasSh */ \
2300, /* vTrim */ \
@ -45,3 +47,5 @@ enum DACINDEX {VIBIASSH, VTRIM, VIPRE, VRFSHNPOL, VTH1, VIPREOUT, VRF, VTH2, C
};
/* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0x8192) // maximum number of words (64bit)