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MY3.0:read and write Registers, frames, cycles, delay (#64)

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* MY3.0:read and write Registers, frames, cycles, delay

* write pattern seems to work

* done all corrections. added default clks: run_clk=125MHz, tick_clk=20MHz (fix), sampling_clk=80MHz (from Carlos)

* clk check for aquistition time

* clk check for aquistition time

* Update slsDetectorServer_defs.h

* Update slsDetectorFunctionList.c
This commit is contained in:
Marie Andrä
2019-09-30 14:36:33 +02:00
committed by Dhanya Thattil
parent 3d52a2f169
commit 6e6fcec698
9 changed files with 490 additions and 56 deletions
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5
slsDetectorServers/mythen3DetectorServer/CMakeLists.txt
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@@ -3,11 +3,10 @@ add_executable(mythen3DetectorServer_virtual
../slsDetectorServer/src/slsDetectorServer.c
../slsDetectorServer/src/slsDetectorServer_funcs.c
../slsDetectorServer/src/communication_funcs.c
# ../slsDetectorServer/src/blackfin.c
../slsDetectorServer/src/communication_funcs_UDP.c
../slsDetectorServer/src/nios.c
../slsDetectorServer/src/communication_funcs_UDP.c
../slsDetectorServer/src/DAC6571.c
../slsDetectorServer/src/common.c
../slsDetectorServer/src/nios.c
)
include_directories(