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ctb fix: reset pll reset also adc and dbit phase (fixed), also required adcs to be configured again(due to adc clock being stopped temporarily

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maliakal_d
2019-06-17 17:24:59 +02:00
parent c96939cf94
commit 6e14a2efe2
3 changed files with 25 additions and 7 deletions
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2
slsDetectorServers/slsDetectorServer/ALTERA_PLL.h
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@@ -225,7 +225,7 @@ int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value) {
// write frequency (post-scale output counter C)
ALTERA_PLL_SetPllReconfigReg(ALTERA_PLL_C_COUNTER_REG, val);
// reset required to keep the phase
// reset required to keep the phase (must reconfigure adcs again after this as adc clock is stopped temporarily when resetting pll)
ALTERA_PLL_ResetPLL ();
/*double temp = ((double)pllVCOFreqMhz / (double)(low_count + high_count));