mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 10:07:59 +02:00
moench: first version
This commit is contained in:
@ -34,6 +34,7 @@ $(PROGS): $(OBJS)
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mv $(PROGS) $(DESTDIR)
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rm *.gdb
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rm $(main_src)*.o
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rm *.o
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clean:
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rm -rf $(DESTDIR)/$(PROGS) *.o *.gdb $(main_src)*.o
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@ -16,7 +16,7 @@
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/* Fix pattern RO register */
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#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
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#define FIX_PATT_VAL (0xACDC2014)
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#define FIX_PATT_VAL (0xACDC2016)
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/* Status RO register */
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#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
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@ -289,7 +289,7 @@
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/* Configuration RW register */
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#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
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#define CONFIG_LED_DSBL_OFST (0)
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#define CONFIG_LED_DSBL_OFST (0) // Not used in firmware or software
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#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
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#define CONFIG_DSBL_ANLG_OTPT_OFST (8)
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#define CONFIG_DSBL_ANLG_OTPT_MSK (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
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@ -365,23 +365,23 @@
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#define PATTERN_CNTRL_RD_OFST (1)
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#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
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#define PATTERN_CNTRL_ADDR_OFST (16)
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#define PATTERN_CNTRL_ADDR_MSK (0x0000FFFF << PATTERN_CNTRL_ADDR_OFST)
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#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
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/* Pattern Limit RW regiser */
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#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
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#define PATTERN_LIMIT_STRT_OFST (0)
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#define PATTERN_LIMIT_STRT_MSK (0x0000FFFF << PATTERN_LIMIT_STRT_OFST)
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#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
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#define PATTERN_LIMIT_STP_OFST (16)
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#define PATTERN_LIMIT_STP_MSK (0x0000FFFF << PATTERN_LIMIT_STP_OFST)
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#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
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/* Pattern Loop 0 Address RW regiser */
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#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
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#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
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#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_0_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_0_ADDR_STP_OFST)
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#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
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/* Pattern Loop 0 Iteration RW regiser */
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#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
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@ -390,9 +390,9 @@
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#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
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#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
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#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_1_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_1_ADDR_STP_OFST)
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#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
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/* Pattern Loop 1 Iteration RW regiser */
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#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
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@ -401,9 +401,9 @@
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#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
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#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x0000FFFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
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#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
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#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_2_ADDR_STP_MSK (0x0000FFFF << PATTERN_LOOP_2_ADDR_STP_OFST)
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#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
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/* Pattern Loop 2 Iteration RW regiser */
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#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
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@ -412,31 +412,36 @@
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#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_0_ADDR_OFST (0)
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#define PATTERN_WAIT_0_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_0_ADDR_OFST)
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#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
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//FIXME: is mask 3FF
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/* Pattern Wait 1 RW regiser */
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#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_1_ADDR_OFST (0)
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#define PATTERN_WAIT_1_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_1_ADDR_OFST)
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#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
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/* Pattern Wait 2 RW regiser */
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#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_2_ADDR_OFST (0)
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#define PATTERN_WAIT_2_ADDR_MSK (0x0000FFFF << PATTERN_WAIT_2_ADDR_OFST)
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#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
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/* Samples RW register */
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#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
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#define SAMPLES_DIGITAL_OFST (0)
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#define SAMPLES_DIGITAL_MSK (0x0000FFFF << SAMPLES_DIGITAL_OFST)
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#define SAMPLES_ANALOG_OFST (16)
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#define SAMPLES_ANALOG_MSK (0x0000FFFF << SAMPLES_ANALOG_OFST)
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/** Power RW register */
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#define POWER_REG (0x5E << MEM_MAP_SHIFT)
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#define POWER_ENBL_VLTG_RGLTR_OFST (16)
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#define POWER_ENBL_VLTG_RGLTR_MSK (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
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#define POWER_HV_SLCT_OFST (31)
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#define POWER_HV_SLCT_MSK (0x00000001 << POWER_HV_SLCT_OFST)
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#define POWER_CHIP_OFST (16)
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#define POWER_CHIP_MSK (0x00000001 << POWER_CHIP_OFST)
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#define POWER_HV_INTERNAL_SLCT_OFST (31)
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#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
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/* Number of Words RW register TODO */
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#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
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@ -493,17 +498,16 @@
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#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
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#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
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/* ADC Disable RW register TODO */
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#define ADC_DISABLE_REG (0x78 << MEM_MAP_SHIFT)
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/* Readout enable RW register */
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#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
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/* DAC Value RW register TODO */
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//#define DAC_VALUE_REG (0x79 << MEM_MAP_SHIFT)
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/* DAC Number RW register TODO */
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//#define DAC_NUMBER_REG (0x7A << MEM_MAP_SHIFT)
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#define READOUT_10G_ENABLE_ANLG_OFST (0)
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#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
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#define READOUT_10G_ENABLE_DGTL_OFST (8)
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#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
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/* Digital Bit External Trigger RW register */
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#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
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#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT) // Not used in firmware or software
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#define DBIT_EXT_TRG_SRC_OFST (0)
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#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
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@ -511,7 +515,8 @@
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#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
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/* Pin Delay 0 RW register */
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#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
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#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT) // Not used in firmware or software
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#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
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#define OUTPUT_DELAY_0_OTPT_STTNG_OFST (0) //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
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#define OUTPUT_DELAY_0_OTPT_STTNG_MSK (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
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@ -523,7 +528,7 @@
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/* Pin Delay 1 RW register
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* Each bit configured as enable for dynamic output delay configuration */
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#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
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#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT) // Not used in firmware or software
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/** Pattern Mask 64 bit RW regiser */
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#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
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@ -533,7 +538,7 @@
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#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
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#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
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/* Round Robin */
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#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)
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BIN
slsDetectorServers/moenchDetectorServer/bin/moenchDetectorServer_developer
Executable file
BIN
slsDetectorServers/moenchDetectorServer/bin/moenchDetectorServer_developer
Executable file
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@ -4,27 +4,51 @@
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#define MIN_REQRD_VRSN_T_RD_API 0x180314
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#define REQRD_FRMWR_VRSN 0x180314
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#define REQRD_FRMWR_VRSN 0x200302
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#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
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#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
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/* Struct Definitions */
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typedef struct ip_header_struct {
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uint16_t ip_len;
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uint8_t ip_tos;
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uint8_t ip_ihl:4 ,ip_ver:4;
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uint16_t ip_offset:13,ip_flag:3;
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uint16_t ip_ident;
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uint16_t ip_chksum;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint32_t ip_sourceip;
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uint32_t ip_destip;
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} ip_header;
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typedef struct udp_header_struct {
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uint32_t udp_destmac_msb;
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uint16_t udp_srcmac_msb;
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uint16_t udp_destmac_lsb;
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uint32_t udp_srcmac_lsb;
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uint8_t ip_tos;
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uint8_t ip_ihl: 4, ip_ver: 4;
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uint16_t udp_ethertype;
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uint16_t ip_identification;
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uint16_t ip_totallength;
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uint8_t ip_protocol;
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uint8_t ip_ttl;
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uint16_t ip_fragmentoffset: 13, ip_flags: 3;
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uint16_t ip_srcip_msb;
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uint16_t ip_checksum;
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uint16_t ip_destip_msb;
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uint16_t ip_srcip_lsb;
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uint16_t udp_srcport;
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uint16_t ip_destip_lsb;
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uint16_t udp_checksum;
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uint16_t udp_destport;
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} udp_header;
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#define IP_HEADER_SIZE (20)
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#define UDP_IP_HEADER_LENGTH_BYTES (28)
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/* Enums */
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enum DACINDEX {MO_VBP_COLBUF, MO_VIPRE, MO_VIN_CM, MO_VB_SDA, MO_VCASC_SFP, MO_VOUT_CM, MO_VIPRE_CDS, MO_IBIAS_SFP};
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#define DEFAULT_DAC_VALS { 1300, /* MO_VBP_COLBUF */ \
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1000, /* MO_VIPRE */ \
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1400, /* MO_VIN_CM */ \
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680, /* MO_VB_SDA */ \
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1428, /* MO_VCASC_SFP */ \
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1200, /* MO_VOUT_CM */ \
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800, /* MO_VIPRE_CDS */ \
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900 /* MO_IBIAS_SFP */ \
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};
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enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
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enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7};
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#define CLK_NAMES "run", "adc", "sync", "dbit"
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/* Hardware Definitions */
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#define NCHAN (32)
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@ -33,12 +57,13 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7};
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#define DYNAMIC_RANGE (16)
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#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
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#define CLK_FREQ (156.25) /* MHz */
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#define NSAMPLES_PER_ROW (25)
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/** Default Parameters */
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#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
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#define DEFAULT_NUM_SAMPLES (1)
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#define DEFAULT_NUM_SAMPLES (5000)
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#define DEFAULT_EXPTIME (0)
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#define DEFAULT_NUM_FRAMES (100 * 1000 * 1000)
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_PERIOD (1 * 1000 * 1000) //ns
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#define DEFAULT_DELAY (0)
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@ -46,35 +71,37 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7};
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#define DEFAULT_VLIMIT (-100)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_TX_UDP_PORT (0x7e9a)
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#define DEFAULT_RUN_CLK (40)
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#define DEFAULT_ADC_CLK (20)
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#define DEFAULT_SYNC_CLK (20)
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#define DEFAULT_DBIT_CLK (200)
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#define DEFAULT_RUN_CLK (40)
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#define DEFAULT_ADC_CLK (20)
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#define DEFAULT_SYNC_CLK (20)
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#define DEFAULT_DBIT_CLK (20)
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#define DEFAULT_ADC_PHASE_DEG (30)
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#define DEFAULT_PIPELINE (14)
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#define HIGHVOLTAGE_MIN (60)
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#define HIGHVOLTAGE_MAX (200)
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#define HIGHVOLTAGE_MAX (200) // min dac val
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2500)
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/* Defines in the Firmware */
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#define MAX_PATTERN_LENGTH (0x7FFF)
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#define MAX_PATTERN_LENGTH (0x2000)
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#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
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#define MAX_PHASE_SHIFTS_STEPS (8)
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#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
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#define WAIT_TIME_US_PLL (10 * 1000)
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#define WAIT_TIME_US_STP_ACQ (100)
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#define WAIT_TIME_CONFIGURE_MAC (500 * 1000)
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#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
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#define WAIT_TIME_PATTERN_READ (10)
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#define WAIT_TIME_FIFO_RD_STROBE (10)
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#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
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/* MSB & LSB DEFINES */
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#define MSB_OF_64_BIT_REG_OFST (32)
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#define LSB_OF_64_BIT_REG_OFST (0)
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#define BIT_32_MSK (0xFFFFFFFF)
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#define BIT32_MSK (0xFFFFFFFF)
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#define BIT16_MASK (0xFFFF)
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#define IP_PACKETSIZE (0x2032)
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#define ADC_PORT_INVERT_VAL (0x453b2593) //FIXME: a default value?
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#define MAXIMUM_ADC_CLK (40)
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#define ADC_PORT_INVERT_VAL (0x4a342593)
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#define MAXIMUM_ADC_CLK (20)
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#define PLL_VCO_FREQ_MHZ (800)
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