detectors/slsDetectorPackage
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changed speed to readoutspeed, added g2 speeds (108, 144)

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This commit is contained in:
maliakal_d
2021-10-07 18:39:18 +02:00
parent e2aa426966
commit 6b0e6a72df
18 changed files with 299 additions and 173 deletions
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26
slsDetectorServers/gotthard2DetectorServer/slsDetectorFunctionList.c
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@ -2083,6 +2083,32 @@ int getVCOFrequency(enum CLKINDEX ind) {
return ALTERA_PLL_C10_GetVCOFrequency(pllIndex);
}
int setReadoutSpeed(int val) {
switch (val)
}
int getReadoutSpeed(int* retval) {
//TODO ASIC and ADIFreg need to check????
// clkdiv 2, 3, 4, 5?
if (clkDivider[READOUT_C0] == SPEED_108_CLKDIV_0 &&
clkDivider[READOUT_C1] == SPEED_108_CLKDIV_1 &&
getPhase(READOUT_C0, 1) == SPEED_108_CLKPHASE_DEG_1) {
*retval = G_108MHZ;
}
else if (clkDivider[READOUT_C0] == SPEED_144_CLKDIV_0 &&
clkDivider[READOUT_C1] == SPEED_144_CLKDIV_1 &&
getPhase(READOUT_C0, 1) == SPEED_144_CLKPHASE_DEG_1) {
*retval = G_144MHZ;
}
else {
*retval = -1;
return FAIL;
}
return OK;
}
int getMaxClockDivider() { return ALTERA_PLL_C10_GetMaxClockDivider(); }
int setClockDivider(enum CLKINDEX ind, int val) {

8
slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
View File

@ -59,6 +59,14 @@
#define DEFAULT_SYSTEM_C2 (5) //(144444448) // sync_clk, 144 MHz
#define DEFAULT_SYSTEM_C3 (5) //(144444448) // str_clk, 144 MHz
#define DEFAULT_READOUT_SPEED (G_108MHz)
#define SPEED_144_CLKDIV_0 (6)
#define SPEED_144_CLKDIV_1 (6)
#define SPEED_144_CLKPHASE_DEG_1 (125)
#define SPEED_108_CLKDIV_0 (8)
#define SPEED_108_CLKDIV_1 (8)
#define SPEED_108_CLKPHASE_DEG_1 (270)
/* Firmware Definitions */
#define FIXED_PLL_FREQUENCY (20000000) // 20MHz
#define INT_SYSTEM_C0_FREQUENCY (144000000) // 144 MHz