Jungfrau bug fix: cannot give same adcphase value to pll, updated recommended default of adcphase for half speed and quarter speed, updated client manuals for both adcphase and clkdivider

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2018-03-20 12:12:38 +01:00
parent 85aa47b835
commit 688dd15fe9
37 changed files with 71 additions and 66 deletions

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@ -183,7 +183,7 @@ Versions</a></h2>
Speed</a></h2>
<p>commands to configure speed of detector</p>
<ul>
<li><b>clkdivider [i]</b> sets/gets the readout clock divider. EIGER, JUNGFRAU [0(fast speed), 1(half speed), 2(quarter speed)]. MYTHEN[???]. <code>Returns</code> <code></code>(int)</li>
<li><b>clkdivider [i]</b> sets/gets the readout clock divider. EIGER, JUNGFRAU [0(fast speed), 1(half speed), 2(quarter speed)]. Jungfrau, full speed is not implemented and overwrites adcphase to recommended default. MYTHEN[???]. <code>Returns</code> <code></code>(int)</li>
</ul>
<ul>
<li><b>setlength [i]</b> sets/gets length of set/reset signals (in clock cycles). Used in MYTHEN only. <code>Returns</code> <code></code>(int)</li>
@ -207,7 +207,7 @@ Speed</a></h2>
<li><b>adcclk [i]</b> sets/gets the ADC clock frequency in MHz. For the new chiptestboard!<code>Returns</code> <code></code>(int)</li>
</ul>
<ul>
<li><b>adcphase [i]</b> Sets/gets the ADC clock frequency in MHz. For the new chiptestboard!<code>Returns</code> <code></code>(int)</li>
<li><b>adcphase [i]</b> Sets/gets phase of the sampling clock. For JUNGFRAU, setting speed (clkdivider) overwrites adcphase to its default recommended value. (Not for EIGER) <code>Returns</code> <code></code>(int)</li>
</ul>
<ul>
<li><b>adcpipeline [i]</b> Sets/gets the pipeline of the ADC. For the new chiptestbaord!<code>Returns</code> <code></code>(int)</li>
@ -251,7 +251,7 @@ Detector Parameters</a></h2>
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