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format slsdetectorservers

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This commit is contained in:
maliakal_d 2020-05-05 15:23:11 +02:00
parent 31ec3c8cf7
commit 671cf45fd7
49 changed files with 3750 additions and 3409 deletions
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1
CMakeLists.txt
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@ -50,7 +50,6 @@ option(SLS_TUNE_LOCAL "tune to local machine" OFF)
set(ClangFormat_EXCLUDE_PATTERNS "build/"
"libs/"
"slsDetectorCalibration/"
"slsDetectorServers/"
"ctbGui/"
"manual/"
"python/"

726
slsDetectorServers/ctbDetectorServer/RegisterDefs.h Executable file → Normal file
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@ -4,552 +4,576 @@
#define MEM_MAP_SHIFT 1
/* FPGA Version RO register */
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
#define FPGA_VERSION_BRD_RVSN_OFST (0)
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_CTB_VAL ((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
#define FPGA_VERSION_BRD_RVSN_OFST (0)
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_CTB_VAL \
((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
/* Fix pattern RO register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
#define FIX_PATT_VAL (0xACDC2016)
#define FIX_PATT_VAL (0xACDC2016)
/* Status RO register */
#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
#define STATUS_RN_BSY_OFST (0)
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
#define STATUS_ANY_FF_FLL_OFST (2)
#define STATUS_ANY_FF_FLL_MSK (0x00000001 << STATUS_ANY_FF_FLL_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4)
#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
#define STATUS_DLY_AFTR_OFST (5)
#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
#define STATUS_EXPSNG_OFST (6)
#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
#define STATUS_CNT_ENBL_OFST (7)
#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
#define STATUS_SM_FF_FLL_OFST (11)
#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
#define STATUS_STPPD_OFST (15)
#define STATUS_STPPD_MSK (0x00000001 << STATUS_STPPD_OFST)
#define STATUS_ALL_FF_EMPTY_OFST (16)
#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
#define STATUS_CYCL_RN_BSY_OFST (17)
#define STATUS_CYCL_RN_BSY_MSK (0x00000001 << STATUS_CYCL_RN_BSY_OFST)
#define STATUS_FRM_RN_BSY_OFST (18)
#define STATUS_FRM_RN_BSY_MSK (0x00000001 << STATUS_FRM_RN_BSY_OFST)
#define STATUS_ADC_DESERON_OFST (19)
#define STATUS_ADC_DESERON_MSK (0x00000001 << STATUS_ADC_DESERON_OFST)
#define STATUS_PLL_RCNFG_BSY_OFST (20)
#define STATUS_PLL_RCNFG_BSY_MSK (0x00000001 << STATUS_PLL_RCNFG_BSY_OFST)
#define STATUS_DT_STRMNG_BSY_OFST (21)
#define STATUS_DT_STRMNG_BSY_MSK (0x00000001 << STATUS_DT_STRMNG_BSY_OFST)
#define STATUS_FRM_PCKR_BSY_OFST (22)
#define STATUS_FRM_PCKR_BSY_MSK (0x00000001 << STATUS_FRM_PCKR_BSY_OFST)
#define STATUS_PLL_PHS_DN_OFST (23)
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x677FF)
#define STATUS_RN_BSY_OFST (0)
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
#define STATUS_ANY_FF_FLL_OFST (2)
#define STATUS_ANY_FF_FLL_MSK (0x00000001 << STATUS_ANY_FF_FLL_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4)
#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
#define STATUS_DLY_AFTR_OFST (5)
#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
#define STATUS_EXPSNG_OFST (6)
#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
#define STATUS_CNT_ENBL_OFST (7)
#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
#define STATUS_SM_FF_FLL_OFST (11)
#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
#define STATUS_STPPD_OFST (15)
#define STATUS_STPPD_MSK (0x00000001 << STATUS_STPPD_OFST)
#define STATUS_ALL_FF_EMPTY_OFST (16)
#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
#define STATUS_CYCL_RN_BSY_OFST (17)
#define STATUS_CYCL_RN_BSY_MSK (0x00000001 << STATUS_CYCL_RN_BSY_OFST)
#define STATUS_FRM_RN_BSY_OFST (18)
#define STATUS_FRM_RN_BSY_MSK (0x00000001 << STATUS_FRM_RN_BSY_OFST)
#define STATUS_ADC_DESERON_OFST (19)
#define STATUS_ADC_DESERON_MSK (0x00000001 << STATUS_ADC_DESERON_OFST)
#define STATUS_PLL_RCNFG_BSY_OFST (20)
#define STATUS_PLL_RCNFG_BSY_MSK (0x00000001 << STATUS_PLL_RCNFG_BSY_OFST)
#define STATUS_DT_STRMNG_BSY_OFST (21)
#define STATUS_DT_STRMNG_BSY_MSK (0x00000001 << STATUS_DT_STRMNG_BSY_OFST)
#define STATUS_FRM_PCKR_BSY_OFST (22)
#define STATUS_FRM_PCKR_BSY_MSK (0x00000001 << STATUS_FRM_PCKR_BSY_OFST)
#define STATUS_PLL_PHS_DN_OFST (23)
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK \
(0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x677FF)
/* Look at me RO register TODO */
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
/* System Status RO register */
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK (0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK (0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK \
(0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as PLL_PARAM_REG 0x50 */
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as
* PLL_PARAM_REG 0x50 */
//#define PLL_PARAM_REG (0x05 << MEM_MAP_SHIFT)
/* FIFO Data RO register TODO */
#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK \
(0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
//#define FIFO_DATA_WRD_OFST (16)
//#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
/* FIFO Status RO register TODO */
#define FIFO_STATUS_REG (0x07 << MEM_MAP_SHIFT)
#define FIFO_STATUS_REG (0x07 << MEM_MAP_SHIFT)
/* FIFO Empty RO register TODO */
#define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT)
#define FIFO_EMPTY_ALL_EMPTY_MSK (0xFFFFFFFF)
#define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT)
#define FIFO_EMPTY_ALL_EMPTY_MSK (0xFFFFFFFF)
/* FIFO Full RO register TODO */
#define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT)
#define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT)
/* MCB Serial Number RO register */
#define MOD_SERIAL_NUMBER_REG (0x0A << MEM_MAP_SHIFT)
#define MOD_SERIAL_NUMBER_REG (0x0A << MEM_MAP_SHIFT)
#define MOD_SERIAL_NUMBER_OFST (0)
#define MOD_SERIAL_NUMBER_MSK (0x000000FF << MOD_SERIAL_NUMBER_OFST)
#define MOD_SERIAL_NUMBER_VRSN_OFST (16)
#define MOD_SERIAL_NUMBER_VRSN_MSK (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
#define MOD_SERIAL_NUMBER_OFST (0)
#define MOD_SERIAL_NUMBER_MSK (0x000000FF << MOD_SERIAL_NUMBER_OFST)
#define MOD_SERIAL_NUMBER_VRSN_OFST (16)
#define MOD_SERIAL_NUMBER_VRSN_MSK (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
/* API Version RO register */
#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DTCTR_TYP_OFST (24)
#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DTCTR_TYP_OFST (24)
#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
* CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
/* Delay Left 64 bit RO register. t = DLY x 50 ns. TODO */
#define DELAY_LEFT_LSB_REG (0x12 << MEM_MAP_SHIFT)
#define DELAY_LEFT_MSB_REG (0x13 << MEM_MAP_SHIFT)
#define DELAY_LEFT_LSB_REG (0x12 << MEM_MAP_SHIFT)
#define DELAY_LEFT_MSB_REG (0x13 << MEM_MAP_SHIFT)
/* Triggers Left 64 bit RO register TODO */
#define CYCLES_LEFT_LSB_REG (0x14 << MEM_MAP_SHIFT)
#define CYCLES_LEFT_MSB_REG (0x15 << MEM_MAP_SHIFT)
#define CYCLES_LEFT_LSB_REG (0x14 << MEM_MAP_SHIFT)
#define CYCLES_LEFT_MSB_REG (0x15 << MEM_MAP_SHIFT)
/* Frames Left 64 bit RO register TODO */
#define FRAMES_LEFT_LSB_REG (0x16 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_MSB_REG (0x17 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_LSB_REG (0x16 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_MSB_REG (0x17 << MEM_MAP_SHIFT)
/* Period Left 64 bit RO register. t = T x 50 ns. TODO */
#define PERIOD_LEFT_LSB_REG (0x18 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_LSB_REG (0x18 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
/* Exposure Time Left 64 bit RO register */
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
//used in FW #define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT)
//// Not used in FW
/* Gates Left 64 bit RO register */
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not
//used in FW #define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT)
//// Not used in FW
/* Data In 64 bit RO register TODO */
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
#define DATA_IN_MSB_REG (0x1F << MEM_MAP_SHIFT)
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
#define DATA_IN_MSB_REG (0x1F << MEM_MAP_SHIFT)
/* Pattern Out 64 bit RO register */
#define PATTERN_OUT_LSB_REG (0x20 << MEM_MAP_SHIFT)
#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
#define PATTERN_OUT_LSB_REG (0x20 << MEM_MAP_SHIFT)
#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
/* Frames From Start 64 bit RO register TODO */
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not
//used in FW #define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT)
//// Not used in FW
/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
* start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
/* Power Status RO register */
#define POWER_STATUS_REG (0x29 << MEM_MAP_SHIFT)
#define POWER_STATUS_REG (0x29 << MEM_MAP_SHIFT)
#define POWER_STATUS_ALRT_OFST (27)
#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
#define POWER_STATUS_ALRT_OFST (27)
#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
/* DAC Value Out RO register */
//#define DAC_VAL_OUT_REG (0x2A << MEM_MAP_SHIFT)
/* Slow ADC SPI Value RO register */
#define ADC_SPI_SLOW_VAL_REG (0x2B << MEM_MAP_SHIFT)
#define ADC_SPI_SLOW_VAL_REG (0x2B << MEM_MAP_SHIFT)
/* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK \
(0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK \
(0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
/* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
#define FIFO_DIN_MSB_REG (0x3D << MEM_MAP_SHIFT)
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
#define FIFO_DIN_MSB_REG (0x3D << MEM_MAP_SHIFT)
/* SPI (Serial Peripheral Interface) DAC, HV RW register */
#define SPI_REG (0x40 << MEM_MAP_SHIFT)
#define SPI_REG (0x40 << MEM_MAP_SHIFT)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_CS_OTPT_OFST (2)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_HV_SRL_DGTL_OTPT_OFST (8)
#define SPI_HV_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
#define SPI_HV_SRL_CLK_OTPT_OFST (9)
#define SPI_HV_SRL_CLK_OTPT_MSK (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
#define SPI_HV_SRL_CS_OTPT_OFST (10)
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_CS_OTPT_OFST (2)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_HV_SRL_DGTL_OTPT_OFST (8)
#define SPI_HV_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
#define SPI_HV_SRL_CLK_OTPT_OFST (9)
#define SPI_HV_SRL_CLK_OTPT_MSK (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
#define SPI_HV_SRL_CS_OTPT_OFST (10)
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
/* ADC SPI (Serial Peripheral Interface) RW register */
#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
#define ADC_SPI_SLOW_SRL_DT_OFST (8)
#define ADC_SPI_SLOW_SRL_DT_MSK (0x00000001 << ADC_SPI_SLOW_SRL_DT_OFST)
#define ADC_SPI_SLOW_SRL_CLK_OFST (9)
#define ADC_SPI_SLOW_SRL_CLK_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CLK_OFST)
#define ADC_SPI_SLOW_SRL_CNV_OFST (10)
#define ADC_SPI_SLOW_SRL_CNV_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CNV_OFST)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
#define ADC_SPI_SLOW_SRL_DT_OFST (8)
#define ADC_SPI_SLOW_SRL_DT_MSK (0x00000001 << ADC_SPI_SLOW_SRL_DT_OFST)
#define ADC_SPI_SLOW_SRL_CLK_OFST (9)
#define ADC_SPI_SLOW_SRL_CLK_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CLK_OFST)
#define ADC_SPI_SLOW_SRL_CNV_OFST (10)
#define ADC_SPI_SLOW_SRL_CNV_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CNV_OFST)
/* ADC Offset RW register */
#define ADC_OFFSET_REG (0x42 << MEM_MAP_SHIFT)
#define ADC_OFFSET_REG (0x42 << MEM_MAP_SHIFT)
#define ADC_OFFSET_ADC_PPLN_OFST (0)
#define ADC_OFFSET_ADC_PPLN_MSK (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
#define ADC_OFFSET_DBT_PPLN_OFST (16)
#define ADC_OFFSET_DBT_PPLN_MSK (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
#define ADC_OFFSET_ADC_PPLN_OFST (0)
#define ADC_OFFSET_ADC_PPLN_MSK (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
#define ADC_OFFSET_DBT_PPLN_OFST (16)
#define ADC_OFFSET_DBT_PPLN_MSK (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
/* ADC Port Invert RW register */
#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_0_INPT_OFST (0)
#define ADC_PORT_INVERT_0_INPT_MSK (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
#define ADC_PORT_INVERT_1_INPT_OFST (8)
#define ADC_PORT_INVERT_1_INPT_MSK (0x000000FF << ADC_PORT_INVERT_1_INPT_OFST)
#define ADC_PORT_INVERT_2_INPT_OFST (16)
#define ADC_PORT_INVERT_2_INPT_MSK (0x000000FF << ADC_PORT_INVERT_2_INPT_OFST)
#define ADC_PORT_INVERT_3_INPT_OFST (24)
#define ADC_PORT_INVERT_3_INPT_MSK (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
#define ADC_PORT_INVERT_0_INPT_OFST (0)
#define ADC_PORT_INVERT_0_INPT_MSK (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
#define ADC_PORT_INVERT_1_INPT_OFST (8)
#define ADC_PORT_INVERT_1_INPT_MSK (0x000000FF << ADC_PORT_INVERT_1_INPT_OFST)
#define ADC_PORT_INVERT_2_INPT_OFST (16)
#define ADC_PORT_INVERT_2_INPT_MSK (0x000000FF << ADC_PORT_INVERT_2_INPT_OFST)
#define ADC_PORT_INVERT_3_INPT_OFST (24)
#define ADC_PORT_INVERT_3_INPT_MSK (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
/* Dummy RW register */
#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK \
(0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK \
(0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
/* Receiver IP Address RW register */
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
/* UDP Port RW register */
#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT)
#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT)
#define UDP_PORT_RX_OFST (0)
#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
#define UDP_PORT_TX_OFST (16)
#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
#define UDP_PORT_RX_OFST (0)
#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
#define UDP_PORT_TX_OFST (16)
#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
/* Receiver Mac Address 64 bit RW register */
#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT)
#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT)
#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT)
#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT)
#define RX_MAC_LSB_OFST (0)
#define RX_MAC_LSB_MSK (0xFFFFFFFF << RX_MAC_LSB_OFST)
#define RX_MAC_MSB_OFST (0)
#define RX_MAC_MSB_MSK (0x0000FFFF << RX_MAC_MSB_OFST)
#define RX_MAC_LSB_OFST (0)
#define RX_MAC_LSB_MSK (0xFFFFFFFF << RX_MAC_LSB_OFST)
#define RX_MAC_MSB_OFST (0)
#define RX_MAC_MSB_MSK (0x0000FFFF << RX_MAC_MSB_OFST)
/* Detector/ Transmitter Mac Address 64 bit RW register */
#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT)
#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT)
#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT)
#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT)
#define TX_MAC_LSB_OFST (0)
#define TX_MAC_LSB_MSK (0xFFFFFFFF << TX_MAC_LSB_OFST)
#define TX_MAC_MSB_OFST (0)
#define TX_MAC_MSB_MSK (0x0000FFFF << TX_MAC_MSB_OFST)
#define TX_MAC_LSB_OFST (0)
#define TX_MAC_LSB_MSK (0xFFFFFFFF << TX_MAC_LSB_OFST)
#define TX_MAC_MSB_OFST (0)
#define TX_MAC_MSB_MSK (0x0000FFFF << TX_MAC_MSB_OFST)
/* Detector/ Transmitter IP Address RW register */
#define TX_IP_REG (0x4B << MEM_MAP_SHIFT)
#define TX_IP_REG (0x4B << MEM_MAP_SHIFT)
/* Detector/ Transmitter IP Checksum RW register */
#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT)
#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT)
#define TX_IP_CHECKSUM_OFST (0)
#define TX_IP_CHECKSUM_MSK (0x0000FFFF << TX_IP_CHECKSUM_OFST)
#define TX_IP_CHECKSUM_OFST (0)
#define TX_IP_CHECKSUM_MSK (0x0000FFFF << TX_IP_CHECKSUM_OFST)
/* Configuration RW register */
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
#define CONFIG_LED_DSBL_OFST (0)
#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
#define CONFIG_DSBL_ANLG_OTPT_OFST (8)
#define CONFIG_DSBL_ANLG_OTPT_MSK (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
#define CONFIG_ENBLE_DGTL_OTPT_OFST (9)
#define CONFIG_ENBLE_DGTL_OTPT_MSK (0x00000001 << CONFIG_ENBLE_DGTL_OTPT_OFST)
#define CONFIG_GB10_SND_UDP_OFST (12)
#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
#define CONFIG_LED_DSBL_OFST (0)
#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
#define CONFIG_DSBL_ANLG_OTPT_OFST (8)
#define CONFIG_DSBL_ANLG_OTPT_MSK (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
#define CONFIG_ENBLE_DGTL_OTPT_OFST (9)
#define CONFIG_ENBLE_DGTL_OTPT_MSK (0x00000001 << CONFIG_ENBLE_DGTL_OTPT_OFST)
#define CONFIG_GB10_SND_UDP_OFST (12)
#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
/* External Signal RW register */
#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_AUTO_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_AUTO_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/* Control RW register */
#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
//#define CONTROL_STRT_FF_TST_OFST (2)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
//#define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
//#define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_RDT_OFST (5)
//#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 <<
//CONTROL_STRT_FF_TST_OFST) #define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 <<
//CONTROL_STP_FF_TST_OFST) #define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 <<
//CONTROL_STRT_RDT_OFST) #define CONTROL_STP_RDT_OFST (5) #define
//CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
//#define CONTROL_STP_EXPSR_OFST (7)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STRT_TRN_OFST (8)
//#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 <<
//CONTROL_STP_RDT_OFST) #define CONTROL_STRT_TRN_OFST (8) #define
//CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_TRN_OFST (9)
//#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_MMRY_RST_OFST (12)
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
//#define CONTROL_STP_TRN_MSK (0x00000001 <<
//CONTROL_STP_RDT_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_MMRY_RST_OFST (12)
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
//#define CONTROL_PLL_RCNFG_WR_OFST (13)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 << CONTROL_PLL_RCNFG_WR_OFST)
#define CONTROL_SND_10GB_PCKT_OFST (14)
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 <<
//CONTROL_PLL_RCNFG_WR_OFST)
#define CONTROL_SND_10GB_PCKT_OFST (14)
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
/* Reconfiguratble PLL Paramater RW register */
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
/* Reconfiguratble PLL Control RW regiser */
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
/* Pattern Control RW register */
#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
#define PATTERN_CNTRL_RD_OFST (1)
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
#define PATTERN_CNTRL_ADDR_OFST (16)
#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
#define PATTERN_CNTRL_RD_OFST (1)
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
#define PATTERN_CNTRL_ADDR_OFST (16)
#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
/* Pattern Limit RW regiser */
#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
/* Pattern Loop 0 Address RW regiser */
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
/* Pattern Loop 0 Iteration RW regiser */
#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
/* Pattern Loop 1 Address RW regiser */
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
/* Pattern Loop 1 Iteration RW regiser */
#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
/* Pattern Loop 2 Address RW regiser */
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern Loop 2 Iteration RW regiser */
#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
/* Pattern Wait 0 RW regiser */
#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
//FIXME: is mask 3FF
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
// FIXME: is mask 3FF
/* Pattern Wait 1 RW regiser */
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Wait 2 RW regiser */
#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
/* Samples RW register */
#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
#define SAMPLES_DIGITAL_OFST (0)
#define SAMPLES_DIGITAL_MSK (0x0000FFFF << SAMPLES_DIGITAL_OFST)
#define SAMPLES_ANALOG_OFST (16)
#define SAMPLES_ANALOG_MSK (0x0000FFFF << SAMPLES_ANALOG_OFST)
#define SAMPLES_DIGITAL_OFST (0)
#define SAMPLES_DIGITAL_MSK (0x0000FFFF << SAMPLES_DIGITAL_OFST)
#define SAMPLES_ANALOG_OFST (16)
#define SAMPLES_ANALOG_MSK (0x0000FFFF << SAMPLES_ANALOG_OFST)
/** Power RW register */
#define POWER_REG (0x5E << MEM_MAP_SHIFT)
#define POWER_REG (0x5E << MEM_MAP_SHIFT)
#define POWER_ENBL_VLTG_RGLTR_OFST (16)
#define POWER_ENBL_VLTG_RGLTR_MSK (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
#define POWER_HV_INTERNAL_SLCT_OFST (31)
#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
#define POWER_ENBL_VLTG_RGLTR_OFST (16)
#define POWER_ENBL_VLTG_RGLTR_MSK (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
#define POWER_HV_INTERNAL_SLCT_OFST (31)
#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
/* Number of Words RW register TODO */
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
/* Delay 64 bit RW register. t = DLY x 50 ns. */
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
/* Triggers 64 bit RW register */
#define CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
#define CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
#define CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
#define CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
/* Frames 64 bit RW register */
#define FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
#define FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
#define FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
#define FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
#define PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
#define PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
//Not used in FW #define EXPTIME_MSB_REG (0x69 <<
//MEM_MAP_SHIFT) // Not used in FW
/* Gates 64 bit RW register */
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used
//in FW #define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) //
//Not used in FW
/* Pattern IO Control 64 bit RW regiser
* Each bit configured as output(1)/ input(0) */
#define PATTERN_IO_CNTRL_LSB_REG (0x6C << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_MSB_REG (0x6D << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_LSB_REG (0x6C << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_MSB_REG (0x6D << MEM_MAP_SHIFT)
/* Pattern IO Clock Control 64 bit RW regiser
* When bit n enabled (1), clocked output for DIO[n] (T run clock)
* When bit n disabled (0), Dio[n] driven by its pattern output */
#define PATTERN_IO_CLK_CNTRL_LSB_REG (0x6E << MEM_MAP_SHIFT)
#define PATTERN_IO_CLK_CNTRL_MSB_REG (0x6F << MEM_MAP_SHIFT)
#define PATTERN_IO_CLK_CNTRL_LSB_REG (0x6E << MEM_MAP_SHIFT)
#define PATTERN_IO_CLK_CNTRL_MSB_REG (0x6F << MEM_MAP_SHIFT)
/* Pattern In 64 bit RW register */
#define PATTERN_IN_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define PATTERN_IN_MSB_REG (0x71 << MEM_MAP_SHIFT)
#define PATTERN_IN_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define PATTERN_IN_MSB_REG (0x71 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 0 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x73 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x73 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 1 64 bit RW register. t = PWT2 x T run clock */
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x75 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x75 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 2 64 bit RW register. t = PWT3 x T run clock */
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
/* Readout enable RW register */
#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
#define READOUT_10G_ENABLE_ANLG_OFST (0)
#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
#define READOUT_10G_ENABLE_DGTL_OFST (8)
#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
#define READOUT_10G_ENABLE_ANLG_OFST (0)
#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
#define READOUT_10G_ENABLE_DGTL_OFST (8)
#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
/* Digital Bit External Trigger RW register */
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
#define DBIT_EXT_TRG_SRC_OFST (0)
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
#define DBIT_EXT_TRG_OPRTN_MD_OFST (16)
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
#define DBIT_EXT_TRG_SRC_OFST (0)
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
#define DBIT_EXT_TRG_OPRTN_MD_OFST (16)
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
/* Pin Delay 0 RW register */
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST (0) //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK (0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL (1)
#define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST \
(0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK \
(0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay
// configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK \
(0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL (1)
#define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
/* Pin Delay 1 RW register
* Each bit configured as enable for dynamic output delay configuration */
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
/** Pattern Mask 64 bit RW regiser */
#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
#define PATTERN_MASK_MSB_REG (0x81 << MEM_MAP_SHIFT)
#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
#define PATTERN_MASK_MSB_REG (0x81 << MEM_MAP_SHIFT)
/** Pattern Set 64 bit RW regiser */
#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
/** I2C Control register */
#define I2C_TRANSFER_COMMAND_FIFO_REG (0x100 << MEM_MAP_SHIFT)
#define I2C_RX_DATA_FIFO_REG (0x101 << MEM_MAP_SHIFT)
#define I2C_CONTROL_REG (0x102 << MEM_MAP_SHIFT)
#define I2C_STATUS_REG (0x105 << MEM_MAP_SHIFT)
#define I2C_RX_DATA_FIFO_LEVEL_REG (0x107 << MEM_MAP_SHIFT)
#define I2C_SCL_LOW_COUNT_REG (0x108 << MEM_MAP_SHIFT)
#define I2C_SCL_HIGH_COUNT_REG (0x109 << MEM_MAP_SHIFT)
#define I2C_SDA_HOLD_REG (0x10A << MEM_MAP_SHIFT)
//fixme: upto 0x10f
#define I2C_TRANSFER_COMMAND_FIFO_REG (0x100 << MEM_MAP_SHIFT)
#define I2C_RX_DATA_FIFO_REG (0x101 << MEM_MAP_SHIFT)
#define I2C_CONTROL_REG (0x102 << MEM_MAP_SHIFT)
#define I2C_STATUS_REG (0x105 << MEM_MAP_SHIFT)
#define I2C_RX_DATA_FIFO_LEVEL_REG (0x107 << MEM_MAP_SHIFT)
#define I2C_SCL_LOW_COUNT_REG (0x108 << MEM_MAP_SHIFT)
#define I2C_SCL_HIGH_COUNT_REG (0x109 << MEM_MAP_SHIFT)
#define I2C_SDA_HOLD_REG (0x10A << MEM_MAP_SHIFT)
// fixme: upto 0x10f
/* Round Robin */
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)

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slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
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#pragma once
#include "sls_detector_defs.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x181130
#define REQRD_FRMWR_VRSN 0x191127
#define MIN_REQRD_VRSN_T_RD_API 0x181130
#define REQRD_FRMWR_VRSN 0x191127
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
/* Struct Definitions */
typedef struct udp_header_struct {
uint32_t udp_destmac_msb;
uint16_t udp_srcmac_msb;
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl: 4, ip_ver: 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
uint16_t ip_srcip_lsb;
uint16_t udp_srcport;
uint16_t ip_destip_lsb;
uint16_t udp_checksum;
uint16_t udp_destport;
uint32_t udp_destmac_msb;
uint16_t udp_srcmac_msb;
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl : 4, ip_ver : 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
uint16_t ip_srcip_lsb;
uint16_t udp_srcport;
uint16_t ip_destip_lsb;
uint16_t udp_checksum;
uint16_t udp_destport;
} udp_header;
#define IP_HEADER_SIZE (20)
#define UDP_IP_HEADER_LENGTH_BYTES (28)
#define IP_HEADER_SIZE (20)
#define UDP_IP_HEADER_LENGTH_BYTES (28)
/* Enums */
enum ADCINDEX {V_PWR_IO, V_PWR_A, V_PWR_B, V_PWR_C, V_PWR_D, I_PWR_IO, I_PWR_A, I_PWR_B, I_PWR_C, I_PWR_D, S_ADC0, S_ADC1, S_ADC2, S_ADC3, S_ADC4, S_ADC5, S_ADC6, S_ADC7, S_TMP};
enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
D10, D11, D12, D13, D14, D15, D16, D17,
D_PWR_D, D_PWR_CHIP, D_PWR_C, D_PWR_B, D_PWR_A, D_PWR_IO};
enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
#define CLK_NAMES "run", "adc", "sync", "dbit"
enum ADCINDEX {
V_PWR_IO,
V_PWR_A,
V_PWR_B,
V_PWR_C,
V_PWR_D,
I_PWR_IO,
I_PWR_A,
I_PWR_B,
I_PWR_C,
I_PWR_D,
S_ADC0,
S_ADC1,
S_ADC2,
S_ADC3,
S_ADC4,
S_ADC5,
S_ADC6,
S_ADC7,
S_TMP
};
enum DACINDEX {
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D8,
D9,
D10,
D11,
D12,
D13,
D14,
D15,
D16,
D17,
D_PWR_D,
D_PWR_CHIP,
D_PWR_C,
D_PWR_B,
D_PWR_A,
D_PWR_IO
};
enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "sync", "dbit"
/* Hardware Definitions */
#define NCHAN (36)
#define NCHAN_ANALOG (32)
#define NCHAN_DIGITAL (64)
#define NCHIP (1)
#define NDAC (24)
#define NPWR (6)
#define NDAC_ONLY (NDAC - NPWR)
#define DYNAMIC_RANGE (16)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define CLK_FREQ (156.25) /* MHz */
#define I2C_POWER_VIO_DEVICE_ID (0x40)
#define I2C_POWER_VA_DEVICE_ID (0x41)
#define I2C_POWER_VB_DEVICE_ID (0x42)
#define I2C_POWER_VC_DEVICE_ID (0x43)
#define I2C_POWER_VD_DEVICE_ID (0x44)
#define I2C_SHUNT_RESISTER_OHMS (0.005)
#define NCHAN (36)
#define NCHAN_ANALOG (32)
#define NCHAN_DIGITAL (64)
#define NCHIP (1)
#define NDAC (24)
#define NPWR (6)
#define NDAC_ONLY (NDAC - NPWR)
#define DYNAMIC_RANGE (16)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define CLK_FREQ (156.25) /* MHz */
#define I2C_POWER_VIO_DEVICE_ID (0x40)
#define I2C_POWER_VA_DEVICE_ID (0x41)
#define I2C_POWER_VB_DEVICE_ID (0x42)
#define I2C_POWER_VC_DEVICE_ID (0x43)
#define I2C_POWER_VD_DEVICE_ID (0x44)
#define I2C_SHUNT_RESISTER_OHMS (0.005)
/** Default Parameters */
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define DEFAULT_NUM_SAMPLES (1)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_EXPTIME (0)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_PERIOD (1 * 1000 * 1000) //ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_VLIMIT (-100)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_RUN_CLK (200) // 40
#define DEFAULT_ADC_CLK (40) // 20
#define DEFAULT_SYNC_CLK (40) // 20
#define DEFAULT_DBIT_CLK (200)
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define DEFAULT_NUM_SAMPLES (1)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_EXPTIME (0)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_PERIOD (1 * 1000 * 1000) // ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_VLIMIT (-100)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_RUN_CLK (200) // 40
#define DEFAULT_ADC_CLK (40) // 20
#define DEFAULT_SYNC_CLK (40) // 20
#define DEFAULT_DBIT_CLK (200)
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200) // min dac val
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
#define VCHIP_MIN_MV (1673)
#define VCHIP_MAX_MV (2668) // min dac val
#define POWER_RGLTR_MIN (636)
#define POWER_RGLTR_MAX (2638) // min dac val (not vchip-max) because of dac conversions
#define VCHIP_POWER_INCRMNT (200)
#define VIO_MIN_MV (1200) // for fpga to function
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200) // min dac val
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
#define VCHIP_MIN_MV (1673)
#define VCHIP_MAX_MV (2668) // min dac val
#define POWER_RGLTR_MIN (636)
#define POWER_RGLTR_MAX \
(2638) // min dac val (not vchip-max) because of dac conversions
#define VCHIP_POWER_INCRMNT (200)
#define VIO_MIN_MV (1200) // for fpga to function
/* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0x2000)
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_STEPS (8)
#define MAX_PATTERN_LENGTH (0x2000)
#define DIGITAL_IO_DELAY_MAXIMUM_PS \
((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_STEPS (8)
#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
#define WAIT_TIME_PATTERN_READ (10)
#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
#define WAIT_TME_US_FR_ACQDONE_REG \
(100) // wait time in us after acquisition done to ensure there is no data
// in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
#define WAIT_TIME_PATTERN_READ (10)
#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
/* MSB & LSB DEFINES */
#define MSB_OF_64_BIT_REG_OFST (32)
#define LSB_OF_64_BIT_REG_OFST (0)
#define BIT32_MSK (0xFFFFFFFF)
#define BIT16_MASK (0xFFFF)
#define MAXIMUM_ADC_CLK (65)
#define PLL_VCO_FREQ_MHZ (800)
#define MSB_OF_64_BIT_REG_OFST (32)
#define LSB_OF_64_BIT_REG_OFST (0)
#define BIT32_MSK (0xFFFFFFFF)
#define BIT16_MASK (0xFFFF)
#define MAXIMUM_ADC_CLK (65)
#define PLL_VCO_FREQ_MHZ (800)

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slsDetectorServers/eigerDetectorServer/Beb.h Executable file → Normal file
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#pragma once
#include "LocalLinkInterface.h"
#include "slsDetectorServer_defs.h"
struct BebInfo{
unsigned int beb_number;
unsigned int serial_address;
char src_mac_1GbE[50];
char src_mac_10GbE[50];
char src_ip_1GbE[50];
char src_ip_10GbE[50];
unsigned int src_port_1GbE;
unsigned int src_port_10GbE;
struct BebInfo {
unsigned int beb_number;
unsigned int serial_address;
char src_mac_1GbE[50];
char src_mac_10GbE[50];
char src_ip_1GbE[50];
char src_ip_10GbE[50];
unsigned int src_port_1GbE;
unsigned int src_port_10GbE;
};
void BebInfo_BebInfo(struct BebInfo* bebInfo, unsigned int beb_num);
void BebInfo_BebDstInfo(struct BebInfo* bebInfo, unsigned int beb_num);
int BebInfo_SetSerialAddress(struct BebInfo* bebInfo, unsigned int add);
int BebInfo_SetHeaderInfo(struct BebInfo* bebInfo, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);//src_port fixed 42000+beb_number or 52000 + beb_number);
unsigned int BebInfo_GetBebNumber(struct BebInfo* bebInfo);
unsigned int BebInfo_GetSerialAddress(struct BebInfo* bebInfo);
char* BebInfo_GetSrcMAC(struct BebInfo* bebInfo, int ten_gig);
char* BebInfo_GetSrcIP(struct BebInfo* bebInfo, int ten_gig);
unsigned int BebInfo_GetSrcPort(struct BebInfo* bebInfo, int ten_gig);
void BebInfo_Print(struct BebInfo* bebInfo);
void BebInfo_BebInfo(struct BebInfo *bebInfo, unsigned int beb_num);
void BebInfo_BebDstInfo(struct BebInfo *bebInfo, unsigned int beb_num);
int BebInfo_SetSerialAddress(struct BebInfo *bebInfo, unsigned int add);
int BebInfo_SetHeaderInfo(
struct BebInfo *bebInfo, int ten_gig, char *src_mac, char *src_ip,
unsigned int
src_port); // src_port fixed 42000+beb_number or 52000 + beb_number);
unsigned int BebInfo_GetBebNumber(struct BebInfo *bebInfo);
unsigned int BebInfo_GetSerialAddress(struct BebInfo *bebInfo);
char *BebInfo_GetSrcMAC(struct BebInfo *bebInfo, int ten_gig);
char *BebInfo_GetSrcIP(struct BebInfo *bebInfo, int ten_gig);
unsigned int BebInfo_GetSrcPort(struct BebInfo *bebInfo, int ten_gig);
void BebInfo_Print(struct BebInfo *bebInfo);
void Beb_ClearBebInfos();
int Beb_InitBebInfos();
int Beb_CheckSourceStuffBebInfo();
unsigned int Beb_GetBebInfoIndex(unsigned int beb_numb);
void Beb_GetModuleConfiguration(int* master, int* top, int* normal);
int Beb_IsTransmitting(int* retval, int tengiga, int waitForDelay);
void Beb_GetModuleConfiguration(int *master, int *top, int *normal);
int Beb_IsTransmitting(int *retval, int tengiga, int waitForDelay);
int Beb_SetMasterViaSoftware();
int Beb_SetSlaveViaSoftware();
@ -56,27 +55,43 @@ u_int32_t Beb_GetFirmwareRevision();
u_int32_t Beb_GetFirmwareSoftwareAPIVersion();
void Beb_ResetFrameNumber();
int Beb_WriteTo(unsigned int index);
int Beb_SetMAC(char* mac, uint8_t* dst_ptr);
int Beb_SetIP(char* ip, uint8_t* dst_ptr);
int Beb_SetPortNumber(unsigned int port_number, uint8_t* dst_ptr);
int Beb_SetMAC(char *mac, uint8_t *dst_ptr);
int Beb_SetIP(char *ip, uint8_t *dst_ptr);
int Beb_SetPortNumber(unsigned int port_number, uint8_t *dst_ptr);
void Beb_AdjustIPChecksum(struct udp_header_type *ip);
int Beb_SetHeaderData(unsigned int beb_number, int ten_gig, char* dst_mac, char* dst_ip, unsigned int dst_port);
int Beb_SetHeaderData1(char* src_mac, char* src_ip, unsigned int src_port, char* dst_mac, char* dst_ip, unsigned int dst_port);
int Beb_SetHeaderData(unsigned int beb_number, int ten_gig, char *dst_mac,
char *dst_ip, unsigned int dst_port);
int Beb_SetHeaderData1(char *src_mac, char *src_ip, unsigned int src_port,
char *dst_mac, char *dst_ip, unsigned int dst_port);
void Beb_SwapDataFun(int little_endian, unsigned int n, unsigned int *d);
int Beb_SetByteOrder();
void Beb_Beb();
int Beb_SetBebSrcHeaderInfos(unsigned int beb_number, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);
int Beb_SetUpUDPHeader(unsigned int beb_number, int ten_gig, unsigned int header_number, char* dst_mac, char* dst_ip, unsigned int dst_port);
int Beb_SetBebSrcHeaderInfos(unsigned int beb_number, int ten_gig,
char *src_mac, char *src_ip,
unsigned int src_port);
int Beb_SetUpUDPHeader(unsigned int beb_number, int ten_gig,
unsigned int header_number, char *dst_mac, char *dst_ip,
unsigned int dst_port);
/*int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty=1);*/
int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty);
/*int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int
* left_right, int ten_gig, unsigned int dst_number, unsigned int npackets,
* unsigned int packet_size, int stop_read_when_fifo_empty=1);*/
int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right,
int ten_gig, unsigned int dst_number,
unsigned int npackets, unsigned int packet_size,
int stop_read_when_fifo_empty);
int Beb_StopAcquisition();
int Beb_SetUpTransferParameters(short the_bit_mode);
/*int Beb_RequestNImages(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait=0); //all images go to the same destination!*/
int Beb_RequestNImages(unsigned int beb_number, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait);
/*int Beb_RequestNImages(unsigned int beb_number, unsigned int left_right, int
* ten_gig, unsigned int dst_number, unsigned int nimages, int
* test_just_send_out_packets_no_wait=0); //all images go to the same
* destination!*/
int Beb_RequestNImages(unsigned int beb_number, int ten_gig,
unsigned int dst_number, unsigned int nimages,
int test_just_send_out_packets_no_wait);
int Beb_Test(unsigned int beb_number);
@ -85,17 +100,15 @@ int Beb_GetBebFPGATemp();
void Beb_SetDetectorNumber(uint32_t detid);
int Beb_SetQuad(int value);
int Beb_GetQuad();
int* Beb_GetDetectorPosition();
int *Beb_GetDetectorPosition();
int Beb_SetDetectorPosition(int pos[]);
int Beb_SetStartingFrameNumber(uint64_t value);
int Beb_GetStartingFrameNumber(uint64_t* retval, int tengigaEnable);
int Beb_GetStartingFrameNumber(uint64_t *retval, int tengigaEnable);
void Beb_SetReadNLines(int value);
uint16_t Beb_swap_uint16( uint16_t val);
int Beb_open(u_int32_t** csp0base, u_int32_t offset);
u_int32_t Beb_Read32 (u_int32_t* baseaddr, u_int32_t offset);
u_int32_t Beb_Write32 (u_int32_t* baseaddr, u_int32_t offset, u_int32_t data);
void Beb_close(int fd,u_int32_t* csp0base);
uint16_t Beb_swap_uint16(uint16_t val);
int Beb_open(u_int32_t **csp0base, u_int32_t offset);
u_int32_t Beb_Read32(u_int32_t *baseaddr, u_int32_t offset);
u_int32_t Beb_Write32(u_int32_t *baseaddr, u_int32_t offset, u_int32_t data);
void Beb_close(int fd, u_int32_t *csp0base);

149
slsDetectorServers/eigerDetectorServer/FebControl.h Executable file → Normal file
View File

@ -2,49 +2,51 @@
#include "FebInterface.h"
#include <netinet/in.h>
struct Module {
unsigned int module_number;
int top_address_valid;
unsigned int top_left_address;
unsigned int top_right_address;
int bottom_address_valid;
unsigned int bottom_left_address;
unsigned int bottom_right_address;
struct Module{
unsigned int module_number;
int top_address_valid;
unsigned int top_left_address;
unsigned int top_right_address;
int bottom_address_valid;
unsigned int bottom_left_address;
unsigned int bottom_right_address;
unsigned int idelay_top[4]; //ll,lr,rl,ll
unsigned int idelay_bottom[4]; //ll,lr,rl,ll
float high_voltage;
int* top_dac;
int* bottom_dac;
unsigned int idelay_top[4]; // ll,lr,rl,ll
unsigned int idelay_bottom[4]; // ll,lr,rl,ll
float high_voltage;
int *top_dac;
int *bottom_dac;
};
void Module_Module(struct Module *mod, unsigned int number,
unsigned int address_top);
void Module_ModuleBottom(struct Module *mod, unsigned int number,
unsigned int address_bottom);
void Module_Module1(struct Module *mod, unsigned int number,
unsigned int address_top, unsigned int address_bottom);
unsigned int Module_GetModuleNumber(struct Module *mod);
int Module_TopAddressIsValid(struct Module *mod);
unsigned int Module_GetTopBaseAddress(struct Module *mod);
unsigned int Module_GetTopLeftAddress(struct Module *mod);
unsigned int Module_GetTopRightAddress(struct Module *mod);
unsigned int Module_GetBottomBaseAddress(struct Module *mod);
int Module_BottomAddressIsValid(struct Module *mod);
unsigned int Module_GetBottomLeftAddress(struct Module *mod);
unsigned int Module_GetBottomRightAddress(struct Module *mod);
unsigned int Module_SetTopIDelay(struct Module *mod, unsigned int chip,
unsigned int value);
unsigned int Module_GetTopIDelay(struct Module *mod, unsigned int chip);
unsigned int Module_SetBottomIDelay(struct Module *mod, unsigned int chip,
unsigned int value);
unsigned int Module_GetBottomIDelay(struct Module *mod, unsigned int chip);
void Module_Module(struct Module* mod,unsigned int number, unsigned int address_top);
void Module_ModuleBottom(struct Module* mod,unsigned int number, unsigned int address_bottom);
void Module_Module1(struct Module* mod,unsigned int number, unsigned int address_top, unsigned int address_bottom);
unsigned int Module_GetModuleNumber(struct Module* mod);
int Module_TopAddressIsValid(struct Module* mod);
unsigned int Module_GetTopBaseAddress(struct Module* mod);
unsigned int Module_GetTopLeftAddress(struct Module* mod) ;
unsigned int Module_GetTopRightAddress(struct Module* mod);
unsigned int Module_GetBottomBaseAddress(struct Module* mod);
int Module_BottomAddressIsValid(struct Module* mod);
unsigned int Module_GetBottomLeftAddress(struct Module* mod);
unsigned int Module_GetBottomRightAddress(struct Module* mod);
unsigned int Module_SetTopIDelay(struct Module* mod,unsigned int chip,unsigned int value);
unsigned int Module_GetTopIDelay(struct Module* mod,unsigned int chip) ;
unsigned int Module_SetBottomIDelay(struct Module* mod,unsigned int chip,unsigned int value);
unsigned int Module_GetBottomIDelay(struct Module* mod,unsigned int chip);
float Module_SetHighVoltage(struct Module* mod,float value);
float Module_GetHighVoltage(struct Module* mod);
int Module_SetTopDACValue(struct Module* mod,unsigned int i, int value);
int Module_GetTopDACValue(struct Module* mod,unsigned int i);
int Module_SetBottomDACValue(struct Module* mod,unsigned int i, int value);
int Module_GetBottomDACValue(struct Module* mod,unsigned int i);
float Module_SetHighVoltage(struct Module *mod, float value);
float Module_GetHighVoltage(struct Module *mod);
int Module_SetTopDACValue(struct Module *mod, unsigned int i, int value);
int Module_GetTopDACValue(struct Module *mod, unsigned int i);
int Module_SetBottomDACValue(struct Module *mod, unsigned int i, int value);
int Module_GetBottomDACValue(struct Module *mod, unsigned int i);
void Feb_Control_activate(int activate);
@ -52,22 +54,30 @@ int Feb_Control_IsBottomModule();
int Feb_Control_GetModuleNumber();
void Feb_Control_PrintModuleList();
int Feb_Control_GetModuleIndex(unsigned int module_number, unsigned int* module_index);
int Feb_Control_CheckModuleAddresses(struct Module* m);
int Feb_Control_GetModuleIndex(unsigned int module_number,
unsigned int *module_index);
int Feb_Control_CheckModuleAddresses(struct Module *m);
int Feb_Control_AddModule(unsigned int module_number, unsigned int top_address);
int Feb_Control_AddModule1(unsigned int module_number, int top_enable, unsigned int top_address, unsigned int bottom_address, int half_module);
int Feb_Control_GetDACNumber(char* s, unsigned int* n);
int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch, unsigned int* value);
int Feb_Control_VoltageToDAC(float value, unsigned int* digital, unsigned int nsteps, float vmin, float vmax);
float Feb_Control_DACToVoltage(unsigned int digital,unsigned int nsteps,float vmin,float vmax);
int Feb_Control_SendIDelays(unsigned int dst_num, int chip_lr, unsigned int channels, unsigned int ndelay_units);
int Feb_Control_AddModule1(unsigned int module_number, int top_enable,
unsigned int top_address,
unsigned int bottom_address, int half_module);
int Feb_Control_GetDACNumber(char *s, unsigned int *n);
int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch,
unsigned int *value);
int Feb_Control_VoltageToDAC(float value, unsigned int *digital,
unsigned int nsteps, float vmin, float vmax);
float Feb_Control_DACToVoltage(unsigned int digital, unsigned int nsteps,
float vmin, float vmax);
int Feb_Control_SendIDelays(unsigned int dst_num, int chip_lr,
unsigned int channels, unsigned int ndelay_units);
int Feb_Control_SetStaticBits();
int Feb_Control_SetStaticBits1(unsigned int the_static_bits);
int Feb_Control_SendBitModeToBebServer();
unsigned int Feb_Control_ConvertTimeToRegister(float time_in_sec);
unsigned int Feb_Control_AddressToAll();
int Feb_Control_SetCommandRegister(unsigned int cmd);
int Feb_Control_GetDAQStatusRegister(unsigned int dst_address, unsigned int* ret_status);
int Feb_Control_GetDAQStatusRegister(unsigned int dst_address,
unsigned int *ret_status);
int Feb_Control_StartDAQOnlyNWaitForFinish(int sleep_time_us);
int Feb_Control_ResetChipCompletely();
int Feb_Control_ResetChipPartially();
@ -80,21 +90,24 @@ unsigned int Feb_Control_GetNModules();
unsigned int Feb_Control_GetNHalfModules();
int Feb_Control_SetHighVoltage(int value);
int Feb_Control_GetHighVoltage(int* value);
int Feb_Control_GetHighVoltage(int *value);
int Feb_Control_SendHighVoltage(int dacvalue);
int Feb_Control_ReceiveHighVoltage(unsigned int* value);
int Feb_Control_ReceiveHighVoltage(unsigned int *value);
int Feb_Control_SetIDelays(unsigned int module_num, unsigned int ndelay_units);
int Feb_Control_SetIDelays1(unsigned int module_num, unsigned int chip_pos, unsigned int ndelay_units);
int Feb_Control_SetIDelays(unsigned int module_num, unsigned int ndelay_units);
int Feb_Control_SetIDelays1(unsigned int module_num, unsigned int chip_pos,
unsigned int ndelay_units);
int Feb_Control_DecodeDACString(char* dac_str, unsigned int* module_index, int* top, int* bottom, unsigned int* dac_ch);
int Feb_Control_SetDAC(char* s, int value, int is_a_voltage_mv);
int Feb_Control_GetDAC(char* s, int* ret_value, int voltage_mv);
int Feb_Control_GetDACName(unsigned int dac_num,char* s);
int Feb_Control_DecodeDACString(char *dac_str, unsigned int *module_index,
int *top, int *bottom, unsigned int *dac_ch);
int Feb_Control_SetDAC(char *s, int value, int is_a_voltage_mv);
int Feb_Control_GetDAC(char *s, int *ret_value, int voltage_mv);
int Feb_Control_GetDACName(unsigned int dac_num, char *s);
int Feb_Control_SetTrimbits(unsigned int module_num, unsigned int* trimbits, int top);
unsigned int* Feb_Control_GetTrimbits();
int Feb_Control_SetTrimbits(unsigned int module_num, unsigned int *trimbits,
int top);
unsigned int *Feb_Control_GetTrimbits();
int Feb_Control_SaveAllTrimbitsTo(int value, int top);
int Feb_Control_Reset();
int Feb_Control_PrepareForAcquisition();
@ -111,7 +124,8 @@ unsigned int Feb_Control_GetNExposures();
int Feb_Control_SetExposureTime(double the_exposure_time_in_sec);
double Feb_Control_GetExposureTime();
int64_t Feb_Control_GetExposureTime_in_nsec();
int Feb_Control_SetSubFrameExposureTime(int64_t the_subframe_exposure_time_in_10nsec);
int Feb_Control_SetSubFrameExposureTime(
int64_t the_subframe_exposure_time_in_10nsec);
int64_t Feb_Control_GetSubFrameExposureTime();
int Feb_Control_SetSubFramePeriod(int64_t the_subframe_period_in_10nsec);
int64_t Feb_Control_GetSubFramePeriod();
@ -119,17 +133,23 @@ int Feb_Control_SetExposurePeriod(double the_exposure_period_in_sec);
double Feb_Control_GetExposurePeriod();
int Feb_Control_SetDynamicRange(unsigned int four_eight_sixteen_or_thirtytwo);
unsigned int Feb_Control_GetDynamicRange();
int Feb_Control_SetReadoutSpeed(unsigned int readout_speed); //0 was default, 0->full,1->half,2->quarter or 3->super_slow
int Feb_Control_SetReadoutMode(unsigned int readout_mode); ///0 was default,0->parallel,1->non-parallel,2-> safe_mode
int Feb_Control_SetTriggerMode(unsigned int trigger_mode, int polarity);//0 and 1 was default,
int Feb_Control_SetExternalEnableMode(int use_external_enable, int polarity);//0 and 1 was default,
int Feb_Control_SetReadoutSpeed(
unsigned int readout_speed); // 0 was default, 0->full,1->half,2->quarter or
// 3->super_slow
int Feb_Control_SetReadoutMode(unsigned int readout_mode); /// 0 was
/// default,0->parallel,1->non-parallel,2->
/// safe_mode
int Feb_Control_SetTriggerMode(unsigned int trigger_mode,
int polarity); // 0 and 1 was default,
int Feb_Control_SetExternalEnableMode(int use_external_enable,
int polarity); // 0 and 1 was default,
int Feb_Control_SetInTestModeVariable(int on);
int Feb_Control_GetTestModeVariable();
void Feb_Control_Set_Counter_Bit(int value);
int Feb_Control_Get_Counter_Bit();
int Feb_Control_Pulse_Pixel(int npulses,int x, int y);
int Feb_Control_Pulse_Pixel(int npulses, int x, int y);
int Feb_Control_PulsePixelNMove(int npulses, int inc_x_pos, int inc_y_pos);
int Feb_Control_Shift32InSerialIn(unsigned int value_to_shift_in);
int Feb_Control_SendTokenIn();
@ -158,5 +178,4 @@ int Feb_Control_SetReadNLines(int value);
int Feb_Control_GetReadNLines();
int Feb_Control_WriteRegister(uint32_t offset, uint32_t data);
int Feb_Control_ReadRegister(uint32_t offset, uint32_t* retval);
int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval);

28
slsDetectorServers/eigerDetectorServer/FebInterface.h Executable file → Normal file
View File

@ -3,12 +3,24 @@
int Feb_Interface_WriteTo(unsigned int ch);
int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys);
void Feb_Interface_FebInterface();
void Feb_Interface_SendCompleteList(unsigned int n,unsigned int* list);
void Feb_Interface_SendCompleteList(unsigned int n, unsigned int *list);
int Feb_Interface_SetByteOrder();
int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read);
int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read);
int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address);
int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses);
int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,
unsigned int *value_read);
int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads,
unsigned int *reg_nums,
unsigned int *values_read);
int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,
unsigned int value, int wait_on,
unsigned int wait_on_address);
int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites,
unsigned int *reg_nums, unsigned int *values,
int *wait_ons,
unsigned int *wait_on_addresses);
int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num,
unsigned int start_address,
unsigned int nwrites,
unsigned int *values);
int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num,
unsigned int start_address, unsigned int nwrites,
unsigned int *values);

326
slsDetectorServers/eigerDetectorServer/FebRegisterDefs.h Executable file → Normal file
View File

@ -1,228 +1,224 @@
//daq register definitions
#define DAQ_REG_CTRL 1
#define DAQ_REG_CHIP_CMDS 2
#define DAQ_REG_STATIC_BITS 3
#define DAQ_REG_CLK_ROW_CLK_NTIMES 3
#define DAQ_REG_SHIFT_IN_32 3
#define DAQ_REG_READOUT_NROWS 3
#define DAQ_REG_SEND_N_TESTPULSES 3
// daq register definitions
#define DAQ_REG_CTRL 1
#define DAQ_REG_CHIP_CMDS 2
#define DAQ_REG_STATIC_BITS 3
#define DAQ_REG_CLK_ROW_CLK_NTIMES 3
#define DAQ_REG_SHIFT_IN_32 3
#define DAQ_REG_READOUT_NROWS 3
#define DAQ_REG_SEND_N_TESTPULSES 3
#define DAQ_REG_NEXPOSURES 3
#define DAQ_REG_EXPOSURE_TIMER 4 // == (31 downto 3) * 10^(2 downto 0)
#define DAQ_REG_EXPOSURE_REPEAT_TIMER 5 // == (31 downto 3) * 10^(2 downto 0)
#define DAQ_REG_SUBFRAME_EXPOSURES 6
#define DAQ_REG_SUBFRAME_PERIOD 7 //also pg and fifo status register
#define DAQ_REG_PARTIAL_READOUT 8
#define DAQ_REG_NEXPOSURES 3
#define DAQ_REG_EXPOSURE_TIMER 4 // == (31 downto 3) * 10^(2 downto 0)
#define DAQ_REG_EXPOSURE_REPEAT_TIMER 5 // == (31 downto 3) * 10^(2 downto 0)
#define DAQ_REG_SUBFRAME_EXPOSURES 6
#define DAQ_REG_SUBFRAME_PERIOD 7 // also pg and fifo status register
#define DAQ_REG_PARTIAL_READOUT 8
#define DAQ_REG_HRDWRE 12
#define DAQ_REG_HRDWRE 12
#define DAQ_REG_HRDWRE_OW_OFST (0)
#define DAQ_REG_HRDWRE_OW_MSK (0x00000001 << DAQ_REG_HRDWRE_OW_OFST)
#define DAQ_REG_HRDWRE_TOP_OFST (1)
#define DAQ_REG_HRDWRE_TOP_MSK (0x00000001 << DAQ_REG_HRDWRE_TOP_OFST)
#define DAQ_REG_HRDWRE_INTRRPT_SF_OFST (2)
#define DAQ_REG_HRDWRE_INTRRPT_SF_MSK (0x00000001 << DAQ_REG_HRDWRE_INTRRPT_SF_OFST)
#define DAQ_REG_HRDWRE_OW_OFST (0)
#define DAQ_REG_HRDWRE_OW_MSK (0x00000001 << DAQ_REG_HRDWRE_OW_OFST)
#define DAQ_REG_HRDWRE_TOP_OFST (1)
#define DAQ_REG_HRDWRE_TOP_MSK (0x00000001 << DAQ_REG_HRDWRE_TOP_OFST)
#define DAQ_REG_HRDWRE_INTRRPT_SF_OFST (2)
#define DAQ_REG_HRDWRE_INTRRPT_SF_MSK \
(0x00000001 << DAQ_REG_HRDWRE_INTRRPT_SF_OFST)
#define DAQ_REG_RO_OFFSET 20
#define DAQ_REG_STATUS (DAQ_REG_RO_OFFSET + 0) //also pg and fifo status register
#define FEB_REG_STATUS (DAQ_REG_RO_OFFSET + 3)
#define MEAS_SUBPERIOD_REG (DAQ_REG_RO_OFFSET + 4)
#define MEAS_PERIOD_REG (DAQ_REG_RO_OFFSET + 5)
#define DAQ_REG_RO_OFFSET 20
#define DAQ_REG_STATUS \
(DAQ_REG_RO_OFFSET + 0) // also pg and fifo status register
#define FEB_REG_STATUS (DAQ_REG_RO_OFFSET + 3)
#define MEAS_SUBPERIOD_REG (DAQ_REG_RO_OFFSET + 4)
#define MEAS_PERIOD_REG (DAQ_REG_RO_OFFSET + 5)
#define DAQ_CTRL_RESET 0x80000000
#define DAQ_CTRL_START 0x40000000
#define ACQ_CTRL_START 0x50000000 // this is 0x10000000 (acq) | 0x40000000 (daq)
#define DAQ_CTRL_STOP 0x00000000
// direct chip commands to the DAQ_REG_CHIP_CMDS register
#define DAQ_SET_STATIC_BIT 0x00000001
#define DAQ_RESET_COMPLETELY 0x0000000E
#define DAQ_RESET_PERIPHERY 0x00000002
#define DAQ_RESET_PIXEL_COUNTERS 0x00000004
#define DAQ_RESET_COLUMN_SELECT 0x00000008
#define DAQ_CTRL_RESET 0x80000000
#define DAQ_CTRL_START 0x40000000
#define ACQ_CTRL_START 0x50000000 //this is 0x10000000 (acq) | 0x40000000 (daq)
#define DAQ_CTRL_STOP 0x00000000
//direct chip commands to the DAQ_REG_CHIP_CMDS register
#define DAQ_SET_STATIC_BIT 0x00000001
#define DAQ_RESET_COMPLETELY 0x0000000E
#define DAQ_RESET_PERIPHERY 0x00000002
#define DAQ_RESET_PIXEL_COUNTERS 0x00000004
#define DAQ_RESET_COLUMN_SELECT 0x00000008
#define DAQ_STORE_IMAGE 0x00000010
#define DAQ_RELEASE_IMAGE_STORE 0x00000020
#define DAQ_STORE_IMAGE 0x00000010
#define DAQ_RELEASE_IMAGE_STORE 0x00000020
#define DAQ_SEND_A_TOKEN_IN 0x00000040
#define DAQ_CLK_ROW_CLK_NTIMES 0x00000080
#define DAQ_SERIALIN_SHIFT_IN_32 0x00000100
#define DAQ_LOAD_16ROWS_OF_TRIMBITS 0x00000200
#define DAQ_IGNORE_INITIAL_CRAP 0x00000400 //crap before readout
#define DAQ_READOUT_NROWS 0x00000800
#define DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START 0x00001000 //last 4 bit of data in the last frame
#define DAQ_IGNORE_INITIAL_CRAP 0x00000400 // crap before readout
#define DAQ_READOUT_NROWS 0x00000800
#define DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START \
0x00001000 // last 4 bit of data in the last frame
#define DAQ_RELEASE_IMAGE_STORE_AFTER_READOUT 0x00002000
#define DAQ_RESET_PIXEL_COUNTERS_AFTER_READOUT 0x00004000
#define DAQ_CLK_ROW_CLK_TO_SELECT_NEXT_ROW 0x00008000
#define DAQ_CLK_MAIN_CLK_TO_SELECT_NEXT_PIXEL 0x00010000
#define DAQ_SEND_N_TEST_PULSES 0x00020000
#define DAQ_CLK_ROW_CLK_TO_SELECT_NEXT_ROW 0x00008000
#define DAQ_CLK_MAIN_CLK_TO_SELECT_NEXT_PIXEL 0x00010000
#define DAQ_SEND_N_TEST_PULSES 0x00020000
#define DAQ_CHIP_CONTROLLER_HALF_SPEED 0x00040000 //everything at 100 MHz (50MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_QUARTER_SPEED 0x00080000 //everything at 50 MHz (25MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED 0x000c0000 //everything at ~200 kHz (200 kHz MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_HALF_SPEED \
0x00040000 // everything at 100 MHz (50MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_QUARTER_SPEED \
0x00080000 // everything at 50 MHz (25MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED \
0x000c0000 // everything at ~200 kHz (200 kHz MHz ddr readout)
//#define DAQ_FIFO_ENABLE 0x00100000 commented out as it is not used anywhere
#define DAQ_REG_CHIP_CMDS_INT_TRIGGER 0x00100000
//#define DAQ_FIFO_ENABLE 0x00100000 commented out as it
//is not used anywhere
#define DAQ_REG_CHIP_CMDS_INT_TRIGGER 0x00100000
//direct chip commands to the DAQ_REG_CHIP_CMDS register
#define DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE 0x00200000 //row clk is before main clk readout sequence
#define DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE 0x00400000 //expose ->readout ->expose -> ..., with store is always closed
#define DAQ_NEXPOSURERS_PARALLEL_MODE 0x00600000 //parallel acquire/read mode
// direct chip commands to the DAQ_REG_CHIP_CMDS register
#define DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE \
0x00200000 // row clk is before main clk readout sequence
#define DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE \
0x00400000 // expose ->readout ->expose -> ..., with store is always closed
#define DAQ_NEXPOSURERS_PARALLEL_MODE 0x00600000 // parallel acquire/read mode
//DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES is old now hard-wired in the firmware that every image comes with a header
//#define DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES 0x00800000 //DAQ_IGNORE_INITIAL_CRAP and DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START
// DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES is old now hard-wired in the firmware
// that every image comes with a header #define
//DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES 0x00800000
////DAQ_IGNORE_INITIAL_CRAP and DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START
#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING 0x01000000
#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING_POLARITY 0x02000000
#define DAQ_NEXPOSURERS_EXTERNAL_TRIGGER_POLARITY 0x04000000
#define DAQ_NEXPOSURERS_INTERNAL_ACQUISITION 0x00000000 //internally controlled
#define DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START 0x08000000 //external acquisition start
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START 0x10000000 //external image start
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP 0x18000000 //externally controlly, external image start and stop
#define DAQ_NEXPOSURERS_INTERNAL_ACQUISITION 0x00000000 // internally controlled
#define DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START \
0x08000000 // external acquisition start
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START 0x10000000 // external image start
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP \
0x18000000 // externally controlly, external image start and stop
#define DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING 0x20000000
#define DAQ_NEXPOSURERS_ACTIVATE_RATE_CORRECTION 0x40000000
#define DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING 0x20000000
#define DAQ_NEXPOSURERS_ACTIVATE_RATE_CORRECTION 0x40000000
//#define DAQ_MASTER_HALF_MODULE 0x80000000 currently not used
//#define DAQ_MASTER_HALF_MODULE 0x80000000 currently not
//used
// chips static bits
#define DAQ_STATIC_BIT_PROGRAM 0x00000001
#define DAQ_STATIC_BIT_M4 0x00000002 // these are the status bits, not bit mode
#define DAQ_STATIC_BIT_M8 0x00000004 // these are the status bits, not bit mode
#define DAQ_STATIC_BIT_M12 \
0x00000000 // these are the status bits, not bit mode, ie. "00" is 12 bit
// mode
#define DAQ_STATIC_BIT_CHIP_TEST 0x00000008
#define DAQ_STATIC_BIT_ROTEST 0x00000010
#define DAQ_CS_BAR_LEFT 0x00000020
#define DAQ_CS_BAR_RIGHT 0x00000040
//chips static bits
#define DAQ_STATIC_BIT_PROGRAM 0x00000001
#define DAQ_STATIC_BIT_M4 0x00000002 //these are the status bits, not bit mode
#define DAQ_STATIC_BIT_M8 0x00000004 //these are the status bits, not bit mode
#define DAQ_STATIC_BIT_M12 0x00000000 //these are the status bits, not bit mode, ie. "00" is 12 bit mode
#define DAQ_STATIC_BIT_CHIP_TEST 0x00000008
#define DAQ_STATIC_BIT_ROTEST 0x00000010
#define DAQ_CS_BAR_LEFT 0x00000020
#define DAQ_CS_BAR_RIGHT 0x00000040
//status flags
#define DAQ_STATUS_DAQ_RUNNING 0x01
#define DAQ_DATA_COLLISION_ERROR 0x02
// status flags
#define DAQ_STATUS_DAQ_RUNNING 0x01
#define DAQ_DATA_COLLISION_ERROR 0x02
#define DAQ_STATUS_CURRENT_M4 0x04
#define DAQ_STATUS_CURRENT_M8 0x08
#define DAQ_STATUS_CURRENT_M12 0x00 //in 12 bit mode both are cleared
#define DAQ_STATUS_CURRENT_M12 0x00 // in 12 bit mode both are cleared
#define DAQ_STATUS_CURRENT_TESTMODE 0x10
#define DAQ_STATUS_TOKEN_OUT 0x20
#define DAQ_STATUS_SERIAL_OUT 0x40
#define DAQ_STATUS_PIXELS_ARE_ENABLED 0x80
#define DAQ_STATUS_DAQ_RUN_TOGGLE 0x200
//data delay registers
#define CHIP_DATA_OUT_DELAY_REG_CTRL 1
#define CHIP_DATA_OUT_DELAY_REG2 2
#define CHIP_DATA_OUT_DELAY_REG3 3
#define CHIP_DATA_OUT_DELAY_REG4 4
#define CHIP_DATA_OUT_DELAY_SET 0x20000000
// data delay registers
#define CHIP_DATA_OUT_DELAY_REG_CTRL 1
#define CHIP_DATA_OUT_DELAY_REG2 2
#define CHIP_DATA_OUT_DELAY_REG3 3
#define CHIP_DATA_OUT_DELAY_REG4 4
#define CHIP_DATA_OUT_DELAY_SET 0x20000000
//module configuration
#define TOP_BIT_MASK 0x00f
#define MASTER_BIT_MASK 0x200
#define NORMAL_MODULE_BIT_MASK 0x400
// module configuration
#define TOP_BIT_MASK 0x00f
#define MASTER_BIT_MASK 0x200
#define NORMAL_MODULE_BIT_MASK 0x400
// Master Slave Top Bottom Definition
#define MODULE_CONFIGURATION_MASK 0x84
//Software Configuration
#define MASTERCONFIG_OFFSET 0x160 //0x20 * 11 (P11)
#define MASTER_BIT 0x1
#define OVERWRITE_HARDWARE_BIT 0x2
#define DEACTIVATE_BIT 0x4
// Software Configuration
#define MASTERCONFIG_OFFSET 0x160 // 0x20 * 11 (P11)
#define MASTER_BIT 0x1
#define OVERWRITE_HARDWARE_BIT 0x2
#define DEACTIVATE_BIT 0x4
#define FPGA_TEMP_OFFSET 0x200
#define FPGA_TEMP_OFFSET 0x200
#define TXM_DELAY_LEFT_OFFSET 0x180
#define TXM_DELAY_RIGHT_OFFSET 0x1A0
#define TXM_DELAY_FRAME_OFFSET 0x1C0
#define FLOW_REG_OFFSET 0x140
#define TXM_DELAY_LEFT_OFFSET 0x180
#define TXM_DELAY_RIGHT_OFFSET 0x1A0
#define TXM_DELAY_FRAME_OFFSET 0x1C0
#define FLOW_REG_OFFSET 0x140
#define FLOW_REG_TXM_FLOW_CNTRL_10G_OFST (0)
#define FLOW_REG_TXM_FLOW_CNTRL_10G_MSK (0x1 << FLOW_REG_TXM_FLOW_CNTRL_10G_OFST)
#define FLOW_REG_OVERFLOW_32_BIT_OFST (2)
#define FLOW_REG_OVERFLOW_32_BIT_MSK (0x1 << FLOW_REG_OVERFLOW_32_BIT_OFST)
#define FLOW_REG_TXM_FLOW_CNTRL_10G_OFST (0)
#define FLOW_REG_TXM_FLOW_CNTRL_10G_MSK \
(0x1 << FLOW_REG_TXM_FLOW_CNTRL_10G_OFST)
#define FLOW_REG_OVERFLOW_32_BIT_OFST (2)
#define FLOW_REG_OVERFLOW_32_BIT_MSK (0x1 << FLOW_REG_OVERFLOW_32_BIT_OFST)
//command memory
#define LEFT_OFFSET 0x0
#define RIGHT_OFFSET 0x100
// command memory
#define LEFT_OFFSET 0x0
#define RIGHT_OFFSET 0x100
#define FIRST_CMD_PART1_OFFSET 0x8
#define FIRST_CMD_PART2_OFFSET 0xc
#define SECOND_CMD_PART1_OFFSET 0x10
#define SECOND_CMD_PART2_OFFSET 0x14
#define COMMAND_COUNTER_OFFSET 0x18
#define STOP_ACQ_OFFSET 0x1c
#define STOP_ACQ_BIT 0x40000000
#define TWO_REQUESTS_OFFSET 0x1c
#define TWO_REQUESTS_BIT 0x80000000
#define FIRST_CMD_PART1_OFFSET 0x8
#define FIRST_CMD_PART2_OFFSET 0xc
#define SECOND_CMD_PART1_OFFSET 0x10
#define SECOND_CMD_PART2_OFFSET 0x14
#define COMMAND_COUNTER_OFFSET 0x18
#define STOP_ACQ_OFFSET 0x1c
#define STOP_ACQ_BIT 0x40000000
#define TWO_REQUESTS_OFFSET 0x1c
#define TWO_REQUESTS_BIT 0x80000000
//version
#define FIRMWARE_VERSION_OFFSET 0x4
// version
#define FIRMWARE_VERSION_OFFSET 0x4
#define FIRMWARESOFTWARE_API_OFFSET 0x0
#define FRAME_NUM_RESET_OFFSET 0xA0
#define FRAME_NUM_RESET_OFFSET 0xA0
//1g counters
#define ONE_GIGA_LEFT_INDEX_LSB_COUNTER 0x04
#define ONE_GIGA_LEFT_INDEX_MSB_COUNTER 0x24
// 1g counters
#define ONE_GIGA_LEFT_INDEX_LSB_COUNTER 0x04
#define ONE_GIGA_LEFT_INDEX_MSB_COUNTER 0x24
#define ONE_GIGA_LEFT_TXN_DELAY_COUNTER 0x104
#define ONE_GIGA_LEFT_FRAME_DELAY_COUNTER 0x124
#define ONE_GIGA_LEFT_TXN_DELAY_COUNTER 0x104
#define ONE_GIGA_LEFT_FRAME_DELAY_COUNTER 0x124
#define ONE_GIGA_RIGHT_INDEX_LSB_COUNTER 0x44
#define ONE_GIGA_RIGHT_INDEX_MSB_COUNTER 0x64
#define ONE_GIGA_RIGHT_INDEX_LSB_COUNTER 0x44
#define ONE_GIGA_RIGHT_INDEX_MSB_COUNTER 0x64
#define ONE_GIGA_RIGHT_TXN_DELAY_COUNTER 0x144
#define ONE_GIGA_RIGHT_FRAME_DELAY_COUNTER 0x164
#define ONE_GIGA_RIGHT_TXN_DELAY_COUNTER 0x144
#define ONE_GIGA_RIGHT_FRAME_DELAY_COUNTER 0x164
//10g counters
#define TEN_GIGA_LEFT_INDEX_LSB_COUNTER 0x84
#define TEN_GIGA_LEFT_INDEX_MSB_COUNTER 0xa4
// 10g counters
#define TEN_GIGA_LEFT_INDEX_LSB_COUNTER 0x84
#define TEN_GIGA_LEFT_INDEX_MSB_COUNTER 0xa4
#define TEN_GIGA_LEFT_TXN_DELAY_COUNTER 0x184
#define TEN_GIGA_LEFT_FRAME_DELAY_COUNTER 0x1a4
#define TEN_GIGA_LEFT_TXN_DELAY_COUNTER 0x184
#define TEN_GIGA_LEFT_FRAME_DELAY_COUNTER 0x1a4
#define TEN_GIGA_RIGHT_INDEX_LSB_COUNTER 0xc4
#define TEN_GIGA_RIGHT_INDEX_MSB_COUNTER 0xe4
#define TEN_GIGA_RIGHT_INDEX_LSB_COUNTER 0xc4
#define TEN_GIGA_RIGHT_INDEX_MSB_COUNTER 0xe4
#define TEN_GIGA_RIGHT_TXN_DELAY_COUNTER 0x1c4
#define TEN_GIGA_RIGHT_FRAME_DELAY_COUNTER 0x1e4
#define TEN_GIGA_RIGHT_TXN_DELAY_COUNTER 0x1c4
#define TEN_GIGA_RIGHT_FRAME_DELAY_COUNTER 0x1e4
// udp header (position, id)
#define UDP_HEADER_A_LEFT_OFST 0x00C0
#define UDP_HEADER_B_LEFT_OFST 0x00E0
#define UDP_HEADER_A_RIGHT_OFST 0x0100
#define UDP_HEADER_B_RIGHT_OFST 0x0120
#define UDP_HEADER_X_OFST (0)
#define UDP_HEADER_X_MSK (0xFFFF << UDP_HEADER_X_OFST)
#define UDP_HEADER_ID_OFST (16)
#define UDP_HEADER_ID_MSK (0xFFFF << UDP_HEADER_ID_OFST)
#define UDP_HEADER_Z_OFST (0)
#define UDP_HEADER_Z_MSK (0xFFFF << UDP_HEADER_Z_OFST)
#define UDP_HEADER_Y_OFST (16)
#define UDP_HEADER_Y_MSK (0xFFFF << UDP_HEADER_Y_OFST)
#define UDP_HEADER_A_LEFT_OFST 0x00C0
#define UDP_HEADER_B_LEFT_OFST 0x00E0
#define UDP_HEADER_A_RIGHT_OFST 0x0100
#define UDP_HEADER_B_RIGHT_OFST 0x0120
#define UDP_HEADER_X_OFST (0)
#define UDP_HEADER_X_MSK (0xFFFF << UDP_HEADER_X_OFST)
#define UDP_HEADER_ID_OFST (16)
#define UDP_HEADER_ID_MSK (0xFFFF << UDP_HEADER_ID_OFST)
#define UDP_HEADER_Z_OFST (0)
#define UDP_HEADER_Z_MSK (0xFFFF << UDP_HEADER_Z_OFST)
#define UDP_HEADER_Y_OFST (16)
#define UDP_HEADER_Y_MSK (0xFFFF << UDP_HEADER_Y_OFST)

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slsDetectorServers/eigerDetectorServer/HardwareIO.h Executable file → Normal file
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@ -1,16 +1,13 @@
//Class initially from Gerd and was called mmap_test.c
// Class initially from Gerd and was called mmap_test.c
#pragma once
#include "xfs_types.h"
xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress);
xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress);
xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress);
xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress);
xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress);
xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress);
void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value);
void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value);
void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value);
void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value);
void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value);
void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value);

59
slsDetectorServers/eigerDetectorServer/HardwareMMappingDefs.h Executable file → Normal file
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@ -1,11 +1,10 @@
//from Gerd and was called mmap_test.h
// from Gerd and was called mmap_test.h
#ifndef __PLB_LL_FIFO_H__
#define __PLB_LL_FIFO_H__
/******************************************************************************/
/* definitions */
/******************************************************************************/
@ -14,49 +13,43 @@
#define PLB_LL_FIFO_REG_STATUS 1
#define PLB_LL_FIFO_REG_FIFO 2
#define PLB_LL_FIFO_CTRL_LL_REM_SHIFT 30
#define PLB_LL_FIFO_CTRL_LL_REM 0xC0000000
#define PLB_LL_FIFO_CTRL_LL_EOF 0x20000000
#define PLB_LL_FIFO_CTRL_LL_SOF 0x10000000
#define PLB_LL_FIFO_CTRL_LL_MASK 0xF0000000
#define PLB_LL_FIFO_CTRL_LL_REM_SHIFT 30
#define PLB_LL_FIFO_CTRL_LL_REM 0xC0000000
#define PLB_LL_FIFO_CTRL_LL_EOF 0x20000000
#define PLB_LL_FIFO_CTRL_LL_SOF 0x10000000
#define PLB_LL_FIFO_CTRL_LL_MASK 0xF0000000
#define PLB_LL_FIFO_CTRL_TX_RESET 0x08000000
#define PLB_LL_FIFO_CTRL_RX_RESET 0x04000000
#define PLB_LL_FIFO_CTRL_TX_RESET 0x08000000
#define PLB_LL_FIFO_CTRL_RX_RESET 0x04000000
#define PLB_LL_FIFO_CTRL_RESET_STATUS 0x00800000
#define PLB_LL_FIFO_CTRL_RESET_USER 0x00400000
#define PLB_LL_FIFO_CTRL_RESET_LINK 0x00200000
#define PLB_LL_FIFO_CTRL_RESET_GT 0x00100000
#define PLB_LL_FIFO_CTRL_RESET_STATUS 0x00800000
#define PLB_LL_FIFO_CTRL_RESET_USER 0x00400000
#define PLB_LL_FIFO_CTRL_RESET_LINK 0x00200000
#define PLB_LL_FIFO_CTRL_RESET_GT 0x00100000
#define PLB_LL_FIFO_CTRL_RESET_ALL 0x0CF00000
#define PLB_LL_FIFO_CTRL_RESET_ALL 0x0CF00000
// do not reset complete gtx dual in std. case
// cause this would reset PLL and stop LL clk
#define PLB_LL_FIFO_CTRL_RESET_STD 0x0CE00000
#define PLB_LL_FIFO_CTRL_RESET_STD 0x0CE00000
// reset Rx and Tx Fifo and set User Reset
#define PLB_LL_FIFO_CTRL_RESET_FIFO 0x0C400000
#define PLB_LL_FIFO_CTRL_RESET_FIFO 0x0C400000
#define PLB_LL_FIFO_CTRL_CONFIG_VECTOR 0x000FFFFF
#define PLB_LL_FIFO_CTRL_CONFIG_VECTOR 0x000FFFFF
#define PLB_LL_FIFO_STATUS_LL_REM_SHIFT 30
#define PLB_LL_FIFO_STATUS_LL_REM 0xC0000000
#define PLB_LL_FIFO_STATUS_LL_EOF 0x20000000
#define PLB_LL_FIFO_STATUS_LL_SOF 0x10000000
#define PLB_LL_FIFO_STATUS_EMPTY 0x08000000
#define PLB_LL_FIFO_STATUS_ALMOSTEMPTY 0x04000000
#define PLB_LL_FIFO_STATUS_FULL 0x02000000
#define PLB_LL_FIFO_STATUS_ALMOSTFULL 0x01000000
#define PLB_LL_FIFO_STATUS_LL_REM_SHIFT 30
#define PLB_LL_FIFO_STATUS_LL_REM 0xC0000000
#define PLB_LL_FIFO_STATUS_LL_EOF 0x20000000
#define PLB_LL_FIFO_STATUS_LL_SOF 0x10000000
#define PLB_LL_FIFO_STATUS_EMPTY 0x08000000
#define PLB_LL_FIFO_STATUS_ALMOSTEMPTY 0x04000000
#define PLB_LL_FIFO_STATUS_FULL 0x02000000
#define PLB_LL_FIFO_STATUS_ALMOSTFULL 0x01000000
#define PLB_LL_FIFO_STATUS_VECTOR 0x000FFFFF
#define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
#define PLB_LL_FIFO_STATUS_VECTOR 0x000FFFFF
#define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
#endif // __PLB_LL_FIFO_H__

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slsDetectorServers/eigerDetectorServer/LocalLinkInterface.h Executable file → Normal file
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@ -2,20 +2,23 @@
#include "HardwareIO.h"
struct LocalLinkInterface{
xfs_u32 ll_fifo_base;
unsigned int ll_fifo_ctrl_reg;
struct LocalLinkInterface {
xfs_u32 ll_fifo_base;
unsigned int ll_fifo_ctrl_reg;
};
int Local_Init(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr);
int Local_Reset1(struct LocalLinkInterface* ll,unsigned int rst_mask);
int Local_ctrl_reg_write_mask(struct LocalLinkInterface* ll,unsigned int mask, unsigned int val);
void Local_LocalLinkInterface1(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr);
unsigned int Local_StatusVector(struct LocalLinkInterface* ll);
int Local_Reset(struct LocalLinkInterface* ll);
int Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
int Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
void Local_LocalLinkInterface(struct LocalLinkInterface* ll);
int Local_Init(struct LocalLinkInterface *ll, unsigned int ll_fifo_badr);
int Local_Reset1(struct LocalLinkInterface *ll, unsigned int rst_mask);
int Local_ctrl_reg_write_mask(struct LocalLinkInterface *ll, unsigned int mask,
unsigned int val);
void Local_LocalLinkInterface1(struct LocalLinkInterface *ll,
unsigned int ll_fifo_badr);
unsigned int Local_StatusVector(struct LocalLinkInterface *ll);
int Local_Reset(struct LocalLinkInterface *ll);
int Local_Write(struct LocalLinkInterface *ll, unsigned int buffer_len,
void *buffer);
int Local_Read(struct LocalLinkInterface *ll, unsigned int buffer_len,
void *buffer);
int Local_Test(struct LocalLinkInterface *ll, unsigned int buffer_len,
void *buffer);
void Local_LocalLinkInterface(struct LocalLinkInterface *ll);

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slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
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@ -1,97 +1,127 @@
#pragma once
#include "sls_detector_defs.h"
#define REQUIRED_FIRMWARE_VERSION (24)
#define IDFILECOMMAND "more /home/root/executables/detid.txt"
#define FIRMWARE_VERSION_SAME_TOP_BOT_ADDR (26)
#define REQUIRED_FIRMWARE_VERSION (24)
#define IDFILECOMMAND "more /home/root/executables/detid.txt"
#define FIRMWARE_VERSION_SAME_TOP_BOT_ADDR (26)
#define STATUS_IDLE 0
#define STATUS_RUNNING 1
#define STATUS_ERROR 2
#define STATUS_IDLE 0
#define STATUS_RUNNING 1
#define STATUS_ERROR 2
/* Enums */
enum DACINDEX {E_SVP,E_VTR,E_VRF,E_VRS,E_SVN,E_VTGSTV,E_VCMP_LL,E_VCMP_LR,E_CAL,E_VCMP_RL,E_RXB_RB,E_RXB_LB,E_VCMP_RR,E_VCP,E_VCN,E_VIS,E_VTHRESHOLD};
#define DEFAULT_DAC_VALS { \
0, /* SvP */ \
2480, /* Vtr */ \
3300, /* Vrf */ \
1400, /* Vrs */ \
4000, /* SvN */ \
2556, /* Vtgstv */ \
1000, /* Vcmp_ll */ \
1000, /* Vcmp_lr */ \
0, /* cal */ \
1000, /* Vcmp_rl */ \
1100, /* rxb_rb */ \
1100, /* rxb_lb */ \
1000, /* Vcmp_rr */ \
1000, /* Vcp */ \
2000, /* Vcn */ \
1550 /* Vis */ \
};
enum ADCINDEX {TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
enum NETWORKINDEX {TXN_LEFT, TXN_RIGHT, TXN_FRAME,FLOWCTRL_10G};
enum ROINDEX {E_PARALLEL, E_NON_PARALLEL};
enum CLKINDEX {RUN_CLK, NUM_CLOCKS};
#define CLK_NAMES "run"
enum DACINDEX {
E_SVP,
E_VTR,
E_VRF,
E_VRS,
E_SVN,
E_VTGSTV,
E_VCMP_LL,
E_VCMP_LR,
E_CAL,
E_VCMP_RL,
E_RXB_RB,
E_RXB_LB,
E_VCMP_RR,
E_VCP,
E_VCN,
E_VIS,
E_VTHRESHOLD
};
#define DEFAULT_DAC_VALS \
{ \
0, /* SvP */ \
2480, /* Vtr */ \
3300, /* Vrf */ \
1400, /* Vrs */ \
4000, /* SvN */ \
2556, /* Vtgstv */ \
1000, /* Vcmp_ll */ \
1000, /* Vcmp_lr */ \
0, /* cal */ \
1000, /* Vcmp_rl */ \
1100, /* rxb_rb */ \
1100, /* rxb_lb */ \
1000, /* Vcmp_rr */ \
1000, /* Vcp */ \
2000, /* Vcn */ \
1550 /* Vis */ \
};
enum ADCINDEX {
TEMP_FPGAEXT,
TEMP_10GE,
TEMP_DCDC,
TEMP_SODL,
TEMP_SODR,
TEMP_FPGA,
TEMP_FPGAFEBL,
TEMP_FPGAFEBR
};
enum NETWORKINDEX { TXN_LEFT, TXN_RIGHT, TXN_FRAME, FLOWCTRL_10G };
enum ROINDEX { E_PARALLEL, E_NON_PARALLEL };
enum CLKINDEX { RUN_CLK, NUM_CLOCKS };
#define CLK_NAMES "run"
/* Hardware Definitions */
#define NCHAN (256 * 256)
#define NCHIP (4)
#define NDAC (16)
#define NCHAN (256 * 256)
#define NCHIP (4)
#define NDAC (16)
#define TEN_GIGA_BUFFER_SIZE (4112)
#define ONE_GIGA_BUFFER_SIZE (1040)
#define TEN_GIGA_CONSTANT (4)
#define ONE_GIGA_CONSTANT (16)
#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
#define NORMAL_HIGHVOLTAGE_OUTPUTPORT "/sys/class/hwmon/hwmon5/device/out0_output"
#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE (16)
#define DEFAULT_UDP_SOURCE_PORT (0xE185)
#define TEN_GIGA_BUFFER_SIZE (4112)
#define ONE_GIGA_BUFFER_SIZE (1040)
#define TEN_GIGA_CONSTANT (4)
#define ONE_GIGA_CONSTANT (16)
#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
#define NORMAL_HIGHVOLTAGE_OUTPUTPORT \
"/sys/class/hwmon/hwmon5/device/out0_output"
#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE (16)
#define DEFAULT_UDP_SOURCE_PORT (0xE185)
/** Default Parameters */
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_STARTING_FRAME_NUMBER (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (1E9) //ns
#define DEFAULT_PERIOD (1E9) //ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_SUBFRAME_EXPOSURE (2621440) // 2.6ms
#define DEFAULT_SUBFRAME_DEADTIME (0)
#define DEFAULT_DYNAMIC_RANGE (16)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_STARTING_FRAME_NUMBER (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (1E9) // ns
#define DEFAULT_PERIOD (1E9) // ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_SUBFRAME_EXPOSURE (2621440) // 2.6ms
#define DEFAULT_SUBFRAME_DEADTIME (0)
#define DEFAULT_DYNAMIC_RANGE (16)
#define DEFAULT_PARALLEL_MODE (1)
#define DEFAULT_READOUT_STOREINRAM_MODE (0)
#define DEFAULT_READOUT_OVERFLOW32_MODE (0)
#define DEFAULT_CLK_SPEED (FULL_SPEED)
#define DEFAULT_IO_DELAY (650)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_PHOTON_ENERGY (-1)
#define DEFAULT_RATE_CORRECTION (0)
#define DEFAULT_EXT_GATING_ENABLE (0)
#define DEFAULT_EXT_GATING_POLARITY (1) //positive
#define DEFAULT_TEST_MODE (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_PARALLEL_MODE (1)
#define DEFAULT_READOUT_STOREINRAM_MODE (0)
#define DEFAULT_READOUT_OVERFLOW32_MODE (0)
#define DEFAULT_CLK_SPEED (FULL_SPEED)
#define DEFAULT_IO_DELAY (650)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_PHOTON_ENERGY (-1)
#define DEFAULT_RATE_CORRECTION (0)
#define DEFAULT_EXT_GATING_ENABLE (0)
#define DEFAULT_EXT_GATING_POLARITY (1) // positive
#define DEFAULT_TEST_MODE (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define MAX_TRIMBITS_VALUE (63)
#define MAX_TRIMBITS_VALUE (63)
#define MAX_ROWS_PER_READOUT (256)
#define MAX_PACKETS_PER_REQUEST (256)
#define MAX_ROWS_PER_READOUT (256)
#define MAX_PACKETS_PER_REQUEST (256)
#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
#define UDP_HEADER_MAX_FRAME_VALUE (0xFFFFFFFFFFFF)
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2048)
#define LTC2620_MIN_VAL (0) // including LTC defines instead of LTC262.h (includes bit banging and blackfin read and write)
#define LTC2620_MAX_VAL (4095) // 12 bits
#define DAC_MAX_STEPS (4096)
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2048)
#define LTC2620_MIN_VAL \
(0) // including LTC defines instead of LTC262.h (includes bit banging and
// blackfin read and write)
#define LTC2620_MAX_VAL (4095) // 12 bits
#define DAC_MAX_STEPS (4096)
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS (0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
#define SLAVE_HIGH_VOLTAGE_READ_VAL (-999)
#define HIGH_VOLTAGE_TOLERANCE (5)
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS \
(0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
#define SLAVE_HIGH_VOLTAGE_READ_VAL (-999)
#define HIGH_VOLTAGE_TOLERANCE (5)

50
slsDetectorServers/eigerDetectorServer/xfs_types.h Executable file → Normal file
View File

@ -14,35 +14,29 @@ typedef signed int xfs_i32;
typedef signed short xfs_i16;
typedef signed char xfs_i8;
// UDP Header
struct udp_header_type
{
// ethternet frame (14 byte)
uint8_t dst_mac[6];
uint8_t src_mac[6];
uint8_t len_type[2];
struct udp_header_type {
// ethternet frame (14 byte)
uint8_t dst_mac[6];
uint8_t src_mac[6];
uint8_t len_type[2];
// ip header (20 byte)
uint8_t ver_headerlen[1];
uint8_t service_type[1];
uint8_t total_length[2];
uint8_t identification[2];
uint8_t flags[1];
uint8_t frag_offset[1];
uint8_t time_to_live[1];
uint8_t protocol[1];
uint8_t ip_header_checksum[2];
uint8_t src_ip[4];
uint8_t dst_ip[4];
// udp header (8 byte)
uint8_t src_port[2];
uint8_t dst_port[2];
uint8_t udp_message_len[2];
uint8_t udp_checksum[2];
// ip header (20 byte)
uint8_t ver_headerlen[1];
uint8_t service_type[1];
uint8_t total_length[2];
uint8_t identification[2];
uint8_t flags[1];
uint8_t frag_offset[1];
uint8_t time_to_live[1];
uint8_t protocol[1];
uint8_t ip_header_checksum[2];
uint8_t src_ip[4];
uint8_t dst_ip[4];
// udp header (8 byte)
uint8_t src_port[2];
uint8_t dst_port[2];
uint8_t udp_message_len[2];
uint8_t udp_checksum[2];
};

570
slsDetectorServers/eigerDetectorServer/xparameters.h Executable file → Normal file
View File

@ -1,4 +1,5 @@
/* ONLY THOSE ARE USED IN THIS SOFTWARE. If one of those is modified in xilinx compilation, this file should be replaced with updated values
/* ONLY THOSE ARE USED IN THIS SOFTWARE. If one of those is modified in xilinx
compilation, this file should be replaced with updated values
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR
XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR
XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR
@ -19,32 +20,27 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
*
*******************************************************************/
#define STDIN_BASEADDRESS 0xC0000000
#define STDIN_BASEADDRESS 0xC0000000
#define STDOUT_BASEADDRESS 0xC0000000
/******************************************************************/
/* Definitions for peripheral BB_IO_SHIFT_REG_PPC440 */
#define XPAR_BB_IO_SHIFT_REG_PPC440_BASEADDR 0xD3000000
#define XPAR_BB_IO_SHIFT_REG_PPC440_HIGHADDR 0xD300FFFF
/* Definitions for peripheral EIGER_BEB_SYNCH_IO_PPC440 */
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_BASEADDR 0xD3100000
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_HIGHADDR 0xD310FFFF
/* Definitions for peripheral PLB_BRAM_10G */
#define XPAR_PLB_BRAM_10G_MEM0_BASEADDR 0xD4100000
#define XPAR_PLB_BRAM_10G_MEM0_HIGHADDR 0xD410FFFF
/* Definitions for peripheral PLB_BRAM_TEMAC */
#define XPAR_PLB_BRAM_TEMAC_MEM0_BASEADDR 0xD4000000
#define XPAR_PLB_BRAM_TEMAC_MEM0_HIGHADDR 0xD400FFFF
/* Definitions for peripheral PLB_GPIO_SYS */
#define XPAR_PLB_GPIO_SYS_BASEADDR 0xD1000000
#define XPAR_PLB_GPIO_SYS_HIGHADDR 0xD100FFFF
@ -52,38 +48,30 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
/** Command Generator */
#define XPAR_CMD_GENERATOR 0xC5000000
/** Version Numbers */
#define XPAR_VERSION 0xc6000000
#define XPAR_VERSION 0xc6000000
/* Definitions for peripheral PLB_GPIO_TEST */
#define XPAR_PLB_GPIO_TEST_BASEADDR 0xD1010000
#define XPAR_PLB_GPIO_TEST_HIGHADDR 0xD101FFFF
// udp header (set frame number)
#define UDP_HEADER_FRAME_NUMBER_LSB_OFST (0x0140)
#define UDP_HEADER_FRAME_NUMBER_MSB_OFST (0x0160)
#define UDP_HEADER_FRAME_NUMBER_LSB_OFST (0x0140)
#define UDP_HEADER_FRAME_NUMBER_MSB_OFST (0x0160)
/* Definitions for packet, frame and delay down counters */
#define XPAR_COUNTER_BASEADDR 0xD1020000
#define XPAR_COUNTER_HIGHADDR 0xD102FFFF
// udp header (get frame number)
#define UDP_HEADER_GET_FNUM_1G_LEFT_LSB_OFST (0x0004)
#define UDP_HEADER_GET_FNUM_1G_LEFT_MSB_OFST (0x0024)
#define UDP_HEADER_GET_FNUM_1G_RIGHT_LSB_OFST (0x0044)
#define UDP_HEADER_GET_FNUM_1G_RIGHT_MSB_OFST (0x0064)
#define UDP_HEADER_GET_FNUM_10G_LEFT_LSB_OFST (0x0084)
#define UDP_HEADER_GET_FNUM_10G_LEFT_MSB_OFST (0x00A4)
#define UDP_HEADER_GET_FNUM_10G_RIGHT_LSB_OFST (0x00C4)
#define UDP_HEADER_GET_FNUM_10G_RIGHT_MSB_OFST (0x00E4)
#define UDP_HEADER_GET_FNUM_1G_LEFT_LSB_OFST (0x0004)
#define UDP_HEADER_GET_FNUM_1G_LEFT_MSB_OFST (0x0024)
#define UDP_HEADER_GET_FNUM_1G_RIGHT_LSB_OFST (0x0044)
#define UDP_HEADER_GET_FNUM_1G_RIGHT_MSB_OFST (0x0064)
#define UDP_HEADER_GET_FNUM_10G_LEFT_LSB_OFST (0x0084)
#define UDP_HEADER_GET_FNUM_10G_LEFT_MSB_OFST (0x00A4)
#define UDP_HEADER_GET_FNUM_10G_RIGHT_LSB_OFST (0x00C4)
#define UDP_HEADER_GET_FNUM_10G_RIGHT_MSB_OFST (0x00E4)
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT */
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR 0xC4100000
@ -92,46 +80,37 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
/* Definitions for a new memory */
//#define XPAR_PLB_LL_NEW_MEMORY 0xD1000000//0xD1000084//0xC4200000
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT */
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR 0xC4110000
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_HIGHADDR 0xC411FFFF
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_LEFT */
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR 0xC4120000
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_HIGHADDR 0xC412FFFF
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT */
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR 0xC4130000
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_HIGHADDR 0xC413FFFF
/* Definitions for peripheral PLB_LL_FIFO_XAUI_10G */
#define XPAR_PLB_LL_FIFO_XAUI_10G_BASEADDR 0xC4140000
#define XPAR_PLB_LL_FIFO_XAUI_10G_HIGHADDR 0xC414FFFF
/* Definitions for peripheral PLB_V46_CPU_TO_PLB_V46_BRIDGED */
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_BASEADDR 0xCFFF0000
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_HIGHADDR 0xCFFFFFFF
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_BASEADDR 0xD0000000
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_HIGHADDR 0xDFFFFFFF
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_BASEADDR 0xD0000000
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_HIGHADDR 0xDFFFFFFF
/* Definitions for peripheral PPC_SRAM */
#define XPAR_PPC_SRAM_BASEADDR 0x00000000
#define XPAR_PPC_SRAM_HIGHADDR 0x01FFFFFF
/******************************************************************/
/* Definitions for peripheral PFLASH */
#define XPAR_PFLASH_NUM_BANKS_MEM 1
/******************************************************************/
/* Definitions for peripheral PFLASH */
@ -152,15 +131,13 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
/* Definitions for peripheral PLB_SHT1X_IF_CH1 */
#define XPAR_PLB_SHT1X_IF_CH1_DEVICE_ID 0
#define XPAR_PLB_SHT1X_IF_CH1_BASEADDR 0xD2200000
#define XPAR_PLB_SHT1X_IF_CH1_HIGHADDR 0xD220FFFF
#define XPAR_PLB_SHT1X_IF_CH1_BASEADDR 0xD2200000
#define XPAR_PLB_SHT1X_IF_CH1_HIGHADDR 0xD220FFFF
/* Definitions for peripheral PLB_SHT1X_IF_CH2 */
#define XPAR_PLB_SHT1X_IF_CH2_DEVICE_ID 1
#define XPAR_PLB_SHT1X_IF_CH2_BASEADDR 0xD2210000
#define XPAR_PLB_SHT1X_IF_CH2_HIGHADDR 0xD221FFFF
#define XPAR_PLB_SHT1X_IF_CH2_BASEADDR 0xD2210000
#define XPAR_PLB_SHT1X_IF_CH2_HIGHADDR 0xD221FFFF
/******************************************************************/
@ -168,28 +145,25 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XUARTLITE_NUM_INSTANCES 1
/* Definitions for peripheral RS232 */
#define XPAR_RS232_BASEADDR 0xC0000000
#define XPAR_RS232_HIGHADDR 0xC000FFFF
#define XPAR_RS232_DEVICE_ID 0
#define XPAR_RS232_BAUDRATE 115200
#define XPAR_RS232_BASEADDR 0xC0000000
#define XPAR_RS232_HIGHADDR 0xC000FFFF
#define XPAR_RS232_DEVICE_ID 0
#define XPAR_RS232_BAUDRATE 115200
#define XPAR_RS232_USE_PARITY 0
#define XPAR_RS232_ODD_PARITY 0
#define XPAR_RS232_DATA_BITS 8
#define XPAR_RS232_DATA_BITS 8
/******************************************************************/
/* Canonical definitions for peripheral RS232 */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0xC0000000
#define XPAR_UARTLITE_0_HIGHADDR 0xC000FFFF
#define XPAR_UARTLITE_0_BAUDRATE 115200
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0xC0000000
#define XPAR_UARTLITE_0_HIGHADDR 0xC000FFFF
#define XPAR_UARTLITE_0_BAUDRATE 115200
#define XPAR_UARTLITE_0_USE_PARITY 0
#define XPAR_UARTLITE_0_ODD_PARITY 0
#define XPAR_UARTLITE_0_DATA_BITS 8
#define XPAR_UARTLITE_0_SIO_CHAN 1
#define XPAR_UARTLITE_0_DATA_BITS 8
#define XPAR_UARTLITE_0_SIO_CHAN 1
/******************************************************************/
@ -197,144 +171,137 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XSPI_NUM_INSTANCES 2
/* Definitions for peripheral SPI_FLASH */
#define XPAR_SPI_FLASH_DEVICE_ID 0
#define XPAR_SPI_FLASH_BASEADDR 0xD2000000
#define XPAR_SPI_FLASH_HIGHADDR 0xD200FFFF
#define XPAR_SPI_FLASH_FIFO_EXIST 1
#define XPAR_SPI_FLASH_SPI_SLAVE_ONLY 0
#define XPAR_SPI_FLASH_NUM_SS_BITS 1
#define XPAR_SPI_FLASH_DEVICE_ID 0
#define XPAR_SPI_FLASH_BASEADDR 0xD2000000
#define XPAR_SPI_FLASH_HIGHADDR 0xD200FFFF
#define XPAR_SPI_FLASH_FIFO_EXIST 1
#define XPAR_SPI_FLASH_SPI_SLAVE_ONLY 0
#define XPAR_SPI_FLASH_NUM_SS_BITS 1
#define XPAR_SPI_FLASH_NUM_TRANSFER_BITS 8
/* Definitions for peripheral XPS_SPI_FEB_CFG */
#define XPAR_XPS_SPI_FEB_CFG_DEVICE_ID 1
#define XPAR_XPS_SPI_FEB_CFG_BASEADDR 0xD2010000
#define XPAR_XPS_SPI_FEB_CFG_HIGHADDR 0xD201FFFF
#define XPAR_XPS_SPI_FEB_CFG_FIFO_EXIST 1
#define XPAR_XPS_SPI_FEB_CFG_SPI_SLAVE_ONLY 0
#define XPAR_XPS_SPI_FEB_CFG_NUM_SS_BITS 2
#define XPAR_XPS_SPI_FEB_CFG_DEVICE_ID 1
#define XPAR_XPS_SPI_FEB_CFG_BASEADDR 0xD2010000
#define XPAR_XPS_SPI_FEB_CFG_HIGHADDR 0xD201FFFF
#define XPAR_XPS_SPI_FEB_CFG_FIFO_EXIST 1
#define XPAR_XPS_SPI_FEB_CFG_SPI_SLAVE_ONLY 0
#define XPAR_XPS_SPI_FEB_CFG_NUM_SS_BITS 2
#define XPAR_XPS_SPI_FEB_CFG_NUM_TRANSFER_BITS 8
/******************************************************************/
/* Canonical definitions for peripheral SPI_FLASH */
#define XPAR_SPI_0_DEVICE_ID XPAR_SPI_FLASH_DEVICE_ID
#define XPAR_SPI_0_BASEADDR 0xD2000000
#define XPAR_SPI_0_HIGHADDR 0xD200FFFF
#define XPAR_SPI_0_FIFO_EXIST 1
#define XPAR_SPI_0_SPI_SLAVE_ONLY 0
#define XPAR_SPI_0_NUM_SS_BITS 1
#define XPAR_SPI_0_DEVICE_ID XPAR_SPI_FLASH_DEVICE_ID
#define XPAR_SPI_0_BASEADDR 0xD2000000
#define XPAR_SPI_0_HIGHADDR 0xD200FFFF
#define XPAR_SPI_0_FIFO_EXIST 1
#define XPAR_SPI_0_SPI_SLAVE_ONLY 0
#define XPAR_SPI_0_NUM_SS_BITS 1
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
/* Canonical definitions for peripheral XPS_SPI_FEB_CFG */
#define XPAR_SPI_1_DEVICE_ID XPAR_XPS_SPI_FEB_CFG_DEVICE_ID
#define XPAR_SPI_1_BASEADDR 0xD2010000
#define XPAR_SPI_1_HIGHADDR 0xD201FFFF
#define XPAR_SPI_1_FIFO_EXIST 1
#define XPAR_SPI_1_SPI_SLAVE_ONLY 0
#define XPAR_SPI_1_NUM_SS_BITS 2
#define XPAR_SPI_1_DEVICE_ID XPAR_XPS_SPI_FEB_CFG_DEVICE_ID
#define XPAR_SPI_1_BASEADDR 0xD2010000
#define XPAR_SPI_1_HIGHADDR 0xD201FFFF
#define XPAR_SPI_1_FIFO_EXIST 1
#define XPAR_SPI_1_SPI_SLAVE_ONLY 0
#define XPAR_SPI_1_NUM_SS_BITS 2
#define XPAR_SPI_1_NUM_TRANSFER_BITS 8
/******************************************************************/
/* Definitions for driver LLTEMAC */
#define XPAR_XLLTEMAC_NUM_INSTANCES 1
/* Definitions for peripheral TEMAC_INST Channel 0 */
#define XPAR_TEMAC_INST_CHAN_0_DEVICE_ID 0
#define XPAR_TEMAC_INST_CHAN_0_BASEADDR 0xC3000000
#define XPAR_TEMAC_INST_CHAN_0_HIGHADDR 0xC30FFFFF
#define XPAR_TEMAC_INST_CHAN_0_TXCSUM 0
#define XPAR_TEMAC_INST_CHAN_0_RXCSUM 0
#define XPAR_TEMAC_INST_CHAN_0_PHY_TYPE 4
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TRAN 0
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TRAN 0
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TAG 0
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TAG 0
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_STRP 0
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_STRP 0
#define XPAR_TEMAC_INST_CHAN_0_DEVICE_ID 0
#define XPAR_TEMAC_INST_CHAN_0_BASEADDR 0xC3000000
#define XPAR_TEMAC_INST_CHAN_0_HIGHADDR 0xC30FFFFF
#define XPAR_TEMAC_INST_CHAN_0_TXCSUM 0
#define XPAR_TEMAC_INST_CHAN_0_RXCSUM 0
#define XPAR_TEMAC_INST_CHAN_0_PHY_TYPE 4
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TRAN 0
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TRAN 0
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_TAG 0
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_TAG 0
#define XPAR_TEMAC_INST_CHAN_0_TXVLAN_STRP 0
#define XPAR_TEMAC_INST_CHAN_0_RXVLAN_STRP 0
#define XPAR_TEMAC_INST_CHAN_0_MCAST_EXTEND 0
/* Canonical definitions for peripheral TEMAC_INST Channel 0 */
#define XPAR_LLTEMAC_0_DEVICE_ID 0
#define XPAR_LLTEMAC_0_BASEADDR 0xC3000000
#define XPAR_LLTEMAC_0_HIGHADDR 0xC30FFFFF
#define XPAR_LLTEMAC_0_TXCSUM 0
#define XPAR_LLTEMAC_0_RXCSUM 0
#define XPAR_LLTEMAC_0_PHY_TYPE 4
#define XPAR_LLTEMAC_0_TXVLAN_TRAN 0
#define XPAR_LLTEMAC_0_RXVLAN_TRAN 0
#define XPAR_LLTEMAC_0_TXVLAN_TAG 0
#define XPAR_LLTEMAC_0_RXVLAN_TAG 0
#define XPAR_LLTEMAC_0_TXVLAN_STRP 0
#define XPAR_LLTEMAC_0_RXVLAN_STRP 0
#define XPAR_LLTEMAC_0_DEVICE_ID 0
#define XPAR_LLTEMAC_0_BASEADDR 0xC3000000
#define XPAR_LLTEMAC_0_HIGHADDR 0xC30FFFFF
#define XPAR_LLTEMAC_0_TXCSUM 0
#define XPAR_LLTEMAC_0_RXCSUM 0
#define XPAR_LLTEMAC_0_PHY_TYPE 4
#define XPAR_LLTEMAC_0_TXVLAN_TRAN 0
#define XPAR_LLTEMAC_0_RXVLAN_TRAN 0
#define XPAR_LLTEMAC_0_TXVLAN_TAG 0
#define XPAR_LLTEMAC_0_RXVLAN_TAG 0
#define XPAR_LLTEMAC_0_TXVLAN_STRP 0
#define XPAR_LLTEMAC_0_RXVLAN_STRP 0
#define XPAR_LLTEMAC_0_MCAST_EXTEND 0
#define XPAR_LLTEMAC_0_INTR 1
#define XPAR_LLTEMAC_0_INTR 1
/* LocalLink TYPE Enumerations */
#define XPAR_LL_FIFO 1
#define XPAR_LL_DMA 2
#define XPAR_LL_FIFO 1
#define XPAR_LL_DMA 2
/* Canonical LocalLink parameters for TEMAC_INST */
/******************************************************************/
/* Definitions for peripheral XPS_BRAM_IF_CNTLR_PPC440 */
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_BASEADDR 0xFFFC0000
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_HIGHADDR 0xFFFFFFFF
/******************************************************************/
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 5
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_USE_DCR 0
#define XPAR_XINTC_HAS_IPR 1
#define XPAR_XINTC_USE_DCR 0
/* Definitions for driver INTC */
#define XPAR_XINTC_NUM_INSTANCES 1
/* Definitions for peripheral XPS_INTC_PPC440 */
#define XPAR_XPS_INTC_PPC440_DEVICE_ID 0
#define XPAR_XPS_INTC_PPC440_BASEADDR 0xC1000000
#define XPAR_XPS_INTC_PPC440_HIGHADDR 0xC100FFFF
#define XPAR_XPS_INTC_PPC440_DEVICE_ID 0
#define XPAR_XPS_INTC_PPC440_BASEADDR 0xC1000000
#define XPAR_XPS_INTC_PPC440_HIGHADDR 0xC100FFFF
#define XPAR_XPS_INTC_PPC440_KIND_OF_INTR 0xFFFFFFF4
/******************************************************************/
#define XPAR_INTC_SINGLE_BASEADDR 0xC1000000
#define XPAR_INTC_SINGLE_HIGHADDR 0xC100FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
#define XPAR_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_MASK 0X000001
#define XPAR_INTC_SINGLE_BASEADDR 0xC1000000
#define XPAR_INTC_SINGLE_HIGHADDR 0xC100FFFF
#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
#define XPAR_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_MASK 0X000001
#define XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR 0
#define XPAR_TEMAC_INST_TEMACINTC0_IRPT_MASK 0X000002
#define XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR 1
#define XPAR_XPS_TIMER_PPC440_INTERRUPT_MASK 0X000004
#define XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR 2
#define XPAR_SPI_FLASH_IP2INTC_IRPT_MASK 0X000008
#define XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR 3
#define XPAR_RS232_INTERRUPT_MASK 0X000010
#define XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR 4
#define XPAR_TEMAC_INST_TEMACINTC0_IRPT_MASK 0X000002
#define XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR 1
#define XPAR_XPS_TIMER_PPC440_INTERRUPT_MASK 0X000004
#define XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR 2
#define XPAR_SPI_FLASH_IP2INTC_IRPT_MASK 0X000008
#define XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR 3
#define XPAR_RS232_INTERRUPT_MASK 0X000010
#define XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR 4
/******************************************************************/
/* Canonical definitions for peripheral XPS_INTC_PPC440 */
#define XPAR_INTC_0_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
#define XPAR_INTC_0_BASEADDR 0xC1000000
#define XPAR_INTC_0_HIGHADDR 0xC100FFFF
#define XPAR_INTC_0_DEVICE_ID XPAR_XPS_INTC_PPC440_DEVICE_ID
#define XPAR_INTC_0_BASEADDR 0xC1000000
#define XPAR_INTC_0_HIGHADDR 0xC100FFFF
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFF4
#define XPAR_INTC_0_LLFIFO_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_LLTEMAC_0_VEC_ID XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_LLFIFO_0_VEC_ID \
XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_LLTEMAC_0_VEC_ID \
XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
#define XPAR_INTC_0_TMRCTR_0_VEC_ID \
XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
#define XPAR_INTC_0_SPI_0_VEC_ID \
XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR
/******************************************************************/
@ -344,17 +311,15 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
/* Definitions for peripheral XPS_LL_FIFO_TEMAC */
#define XPAR_XPS_LL_FIFO_TEMAC_DEVICE_ID 0
#define XPAR_XPS_LL_FIFO_TEMAC_BASEADDR 0xC4000000
#define XPAR_XPS_LL_FIFO_TEMAC_HIGHADDR 0xC400FFFF
#define XPAR_XPS_LL_FIFO_TEMAC_BASEADDR 0xC4000000
#define XPAR_XPS_LL_FIFO_TEMAC_HIGHADDR 0xC400FFFF
/******************************************************************/
/* Canonical definitions for peripheral XPS_LL_FIFO_TEMAC */
#define XPAR_LLFIFO_0_DEVICE_ID XPAR_XPS_LL_FIFO_TEMAC_DEVICE_ID
#define XPAR_LLFIFO_0_BASEADDR 0xC4000000
#define XPAR_LLFIFO_0_HIGHADDR 0xC400FFFF
#define XPAR_LLFIFO_0_BASEADDR 0xC4000000
#define XPAR_LLFIFO_0_HIGHADDR 0xC400FFFF
/******************************************************************/
@ -362,22 +327,19 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XSYSMON_NUM_INSTANCES 1
/* Definitions for peripheral XPS_SYSMON_ADC_PPC440 */
#define XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID 0
#define XPAR_XPS_SYSMON_ADC_PPC440_BASEADDR 0xD0010000
#define XPAR_XPS_SYSMON_ADC_PPC440_HIGHADDR 0xD001FFFF
#define XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID 0
#define XPAR_XPS_SYSMON_ADC_PPC440_BASEADDR 0xD0010000
#define XPAR_XPS_SYSMON_ADC_PPC440_HIGHADDR 0xD001FFFF
#define XPAR_XPS_SYSMON_ADC_PPC440_INCLUDE_INTR 1
/******************************************************************/
/* Canonical definitions for peripheral XPS_SYSMON_ADC_PPC440 */
#define XPAR_SYSMON_0_DEVICE_ID XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID
#define XPAR_SYSMON_0_BASEADDR 0xD0010000
#define XPAR_SYSMON_0_HIGHADDR 0xD001FFFF
#define XPAR_SYSMON_0_DEVICE_ID XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID
#define XPAR_SYSMON_0_BASEADDR 0xD0010000
#define XPAR_SYSMON_0_HIGHADDR 0xD001FFFF
#define XPAR_SYSMON_0_INCLUDE_INTR 1
/******************************************************************/
/* Definitions for driver TMRCTR */
@ -385,18 +347,15 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
/* Definitions for peripheral XPS_TIMER_PPC440 */
#define XPAR_XPS_TIMER_PPC440_DEVICE_ID 0
#define XPAR_XPS_TIMER_PPC440_BASEADDR 0xC2000000
#define XPAR_XPS_TIMER_PPC440_HIGHADDR 0xC200FFFF
#define XPAR_XPS_TIMER_PPC440_BASEADDR 0xC2000000
#define XPAR_XPS_TIMER_PPC440_HIGHADDR 0xC200FFFF
/******************************************************************/
/* Canonical definitions for peripheral XPS_TIMER_PPC440 */
#define XPAR_TMRCTR_0_DEVICE_ID XPAR_XPS_TIMER_PPC440_DEVICE_ID
#define XPAR_TMRCTR_0_BASEADDR 0xC2000000
#define XPAR_TMRCTR_0_HIGHADDR 0xC200FFFF
#define XPAR_TMRCTR_0_BASEADDR 0xC2000000
#define XPAR_TMRCTR_0_HIGHADDR 0xC200FFFF
/******************************************************************/
@ -408,149 +367,148 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_PROC_BUS_0_FREQ_HZ 100000000
/******************************************************************/
#define XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_CPU_PPC440_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_PPC440_VIRTEX5_CORE_CLOCK_FREQ_HZ 400000000
#define XPAR_CPU_PPC440_IDCR_BASEADDR 0x00000000
#define XPAR_CPU_PPC440_IDCR_BASEADDR 0x00000000
/******************************************************************/
#define XPAR_CPU_ID 0
#define XPAR_PPC440_VIRTEX5_ID 0
#define XPAR_PPC440_VIRTEX5_PIR 0b1111
#define XPAR_PPC440_VIRTEX5_ENDIAN_RESET 0
#define XPAR_PPC440_VIRTEX5_USER_RESET 0b0000
#define XPAR_PPC440_VIRTEX5_INTERCONNECT_IMASK 0xffffffff
#define XPAR_PPC440_VIRTEX5_ICU_RD_FETCH_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_ICU_RD_SPEC_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_ICU_RD_TOUCH_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_RD_LD_CACHE_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_RD_NONCACHE_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_RD_TOUCH_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_RD_URGENT_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_WR_FLUSH_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_WR_STORE_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_WR_URGENT_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DMA0_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DMA1_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DMA2_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DMA3_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_IDCR_BASEADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_IDCR_HIGHADDR 0x000000FF
#define XPAR_PPC440_VIRTEX5_APU_CONTROL 0b00010000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_0 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_1 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_2 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_3 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_4 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_5 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_6 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_7 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_8 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_9 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_10 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_11 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_12 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_13 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_14 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_15 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_BASE 0x00000000
#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_HIGH 0X01FFFFFF
#define XPAR_PPC440_VIRTEX5_PPC440MC_ROW_CONFLICT_MASK 0x00000000
#define XPAR_CPU_ID 0
#define XPAR_PPC440_VIRTEX5_ID 0
#define XPAR_PPC440_VIRTEX5_PIR 0b1111
#define XPAR_PPC440_VIRTEX5_ENDIAN_RESET 0
#define XPAR_PPC440_VIRTEX5_USER_RESET 0b0000
#define XPAR_PPC440_VIRTEX5_INTERCONNECT_IMASK 0xffffffff
#define XPAR_PPC440_VIRTEX5_ICU_RD_FETCH_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_ICU_RD_SPEC_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_ICU_RD_TOUCH_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_RD_LD_CACHE_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_RD_NONCACHE_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_RD_TOUCH_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_RD_URGENT_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_WR_FLUSH_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_WR_STORE_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DCU_WR_URGENT_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DMA0_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DMA1_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DMA2_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_DMA3_PLB_PRIO 0b00
#define XPAR_PPC440_VIRTEX5_IDCR_BASEADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_IDCR_HIGHADDR 0x000000FF
#define XPAR_PPC440_VIRTEX5_APU_CONTROL 0b00010000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_0 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_1 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_2 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_3 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_4 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_5 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_6 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_7 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_8 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_9 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_10 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_11 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_12 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_13 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_14 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_APU_UDI_15 0b000000000000000000000000
#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_BASE 0x00000000
#define XPAR_PPC440_VIRTEX5_PPC440MC_ADDR_HIGH 0X01FFFFFF
#define XPAR_PPC440_VIRTEX5_PPC440MC_ROW_CONFLICT_MASK 0x00000000
#define XPAR_PPC440_VIRTEX5_PPC440MC_BANK_CONFLICT_MASK 0x00000000
#define XPAR_PPC440_VIRTEX5_PPC440MC_CONTROL 0X8140008F
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_ICU 4
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUW 3
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUR 2
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB1 0
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB0 1
#define XPAR_PPC440_VIRTEX5_PPC440MC_ARB_MODE 0
#define XPAR_PPC440_VIRTEX5_PPC440MC_MAX_BURST 8
#define XPAR_PPC440_VIRTEX5_MPLB_AWIDTH 32
#define XPAR_PPC440_VIRTEX5_MPLB_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_MPLB_NATIVE_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_MPLB_COUNTER 0x00000500
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_ICU 4
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUW 3
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUR 2
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB1 0
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB0 1
#define XPAR_PPC440_VIRTEX5_MPLB_ARB_MODE 0
#define XPAR_PPC440_VIRTEX5_MPLB_SYNC_TATTRIBUTE 0
#define XPAR_PPC440_VIRTEX5_MPLB_MAX_BURST 8
#define XPAR_PPC440_VIRTEX5_MPLB_ALLOW_LOCK_XFER 1
#define XPAR_PPC440_VIRTEX5_MPLB_READ_PIPE_ENABLE 1
#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_PIPE_ENABLE 1
#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_POST_ENABLE 1
#define XPAR_PPC440_VIRTEX5_MPLB_P2P 0
#define XPAR_PPC440_VIRTEX5_MPLB_WDOG_ENABLE 1
#define XPAR_PPC440_VIRTEX5_SPLB0_AWIDTH 32
#define XPAR_PPC440_VIRTEX5_SPLB0_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_SPLB0_NATIVE_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_SPLB0_SUPPORT_BURSTS 1
#define XPAR_PPC440_VIRTEX5_SPLB0_USE_MPLB_ADDR 0
#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MPLB_ADDR_RNG 0
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MASTERS 1
#define XPAR_PPC440_VIRTEX5_SPLB0_MID_WIDTH 1
#define XPAR_PPC440_VIRTEX5_SPLB0_ALLOW_LOCK_XFER 1
#define XPAR_PPC440_VIRTEX5_SPLB0_READ_PIPE_ENABLE 1
#define XPAR_PPC440_VIRTEX5_SPLB0_PROPAGATE_MIRQ 0
#define XPAR_PPC440_VIRTEX5_SPLB0_P2P -1
#define XPAR_PPC440_VIRTEX5_SPLB1_AWIDTH 32
#define XPAR_PPC440_VIRTEX5_SPLB1_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_SPLB1_NATIVE_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_SPLB1_SUPPORT_BURSTS 1
#define XPAR_PPC440_VIRTEX5_SPLB1_USE_MPLB_ADDR 0
#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MPLB_ADDR_RNG 0
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MASTERS 1
#define XPAR_PPC440_VIRTEX5_SPLB1_MID_WIDTH 1
#define XPAR_PPC440_VIRTEX5_SPLB1_ALLOW_LOCK_XFER 1
#define XPAR_PPC440_VIRTEX5_SPLB1_READ_PIPE_ENABLE 1
#define XPAR_PPC440_VIRTEX5_SPLB1_PROPAGATE_MIRQ 0
#define XPAR_PPC440_VIRTEX5_SPLB1_P2P -1
#define XPAR_PPC440_VIRTEX5_NUM_DMA 0
#define XPAR_PPC440_VIRTEX5_DMA0_TXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA0_RXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA0_CONTROL 0b00000000
#define XPAR_PPC440_VIRTEX5_DMA0_TXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA0_RXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA1_TXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA1_RXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA1_CONTROL 0b00000000
#define XPAR_PPC440_VIRTEX5_DMA1_TXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA1_RXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA2_TXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA2_RXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA2_CONTROL 0b00000000
#define XPAR_PPC440_VIRTEX5_DMA2_TXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA2_RXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA3_TXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA3_RXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA3_CONTROL 0b00000000
#define XPAR_PPC440_VIRTEX5_DMA3_TXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA3_RXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DCR_AUTOLOCK_ENABLE 1
#define XPAR_PPC440_VIRTEX5_PPCDM_ASYNCMODE 0
#define XPAR_PPC440_VIRTEX5_PPCDS_ASYNCMODE 0
#define XPAR_PPC440_VIRTEX5_GENERATE_PLB_TIMESPECS 1
#define XPAR_PPC440_VIRTEX5_HW_VER "1.01.a"
#define XPAR_PPC440_VIRTEX5_PPC440MC_CONTROL 0X8140008F
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_ICU 4
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUW 3
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_DCUR 2
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB1 0
#define XPAR_PPC440_VIRTEX5_PPC440MC_PRIO_SPLB0 1
#define XPAR_PPC440_VIRTEX5_PPC440MC_ARB_MODE 0
#define XPAR_PPC440_VIRTEX5_PPC440MC_MAX_BURST 8
#define XPAR_PPC440_VIRTEX5_MPLB_AWIDTH 32
#define XPAR_PPC440_VIRTEX5_MPLB_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_MPLB_NATIVE_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_MPLB_COUNTER 0x00000500
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_ICU 4
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUW 3
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_DCUR 2
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB1 0
#define XPAR_PPC440_VIRTEX5_MPLB_PRIO_SPLB0 1
#define XPAR_PPC440_VIRTEX5_MPLB_ARB_MODE 0
#define XPAR_PPC440_VIRTEX5_MPLB_SYNC_TATTRIBUTE 0
#define XPAR_PPC440_VIRTEX5_MPLB_MAX_BURST 8
#define XPAR_PPC440_VIRTEX5_MPLB_ALLOW_LOCK_XFER 1
#define XPAR_PPC440_VIRTEX5_MPLB_READ_PIPE_ENABLE 1
#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_PIPE_ENABLE 1
#define XPAR_PPC440_VIRTEX5_MPLB_WRITE_POST_ENABLE 1
#define XPAR_PPC440_VIRTEX5_MPLB_P2P 0
#define XPAR_PPC440_VIRTEX5_MPLB_WDOG_ENABLE 1
#define XPAR_PPC440_VIRTEX5_SPLB0_AWIDTH 32
#define XPAR_PPC440_VIRTEX5_SPLB0_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_SPLB0_NATIVE_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_SPLB0_SUPPORT_BURSTS 1
#define XPAR_PPC440_VIRTEX5_SPLB0_USE_MPLB_ADDR 0
#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MPLB_ADDR_RNG 0
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG_MC_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG0_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG1_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG2_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB0_RNG3_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB0_NUM_MASTERS 1
#define XPAR_PPC440_VIRTEX5_SPLB0_MID_WIDTH 1
#define XPAR_PPC440_VIRTEX5_SPLB0_ALLOW_LOCK_XFER 1
#define XPAR_PPC440_VIRTEX5_SPLB0_READ_PIPE_ENABLE 1
#define XPAR_PPC440_VIRTEX5_SPLB0_PROPAGATE_MIRQ 0
#define XPAR_PPC440_VIRTEX5_SPLB0_P2P -1
#define XPAR_PPC440_VIRTEX5_SPLB1_AWIDTH 32
#define XPAR_PPC440_VIRTEX5_SPLB1_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_SPLB1_NATIVE_DWIDTH 128
#define XPAR_PPC440_VIRTEX5_SPLB1_SUPPORT_BURSTS 1
#define XPAR_PPC440_VIRTEX5_SPLB1_USE_MPLB_ADDR 0
#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MPLB_ADDR_RNG 0
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG_MC_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG0_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG1_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG2_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_BASEADDR 0xFFFFFFFF
#define XPAR_PPC440_VIRTEX5_SPLB1_RNG3_MPLB_HIGHADDR 0x00000000
#define XPAR_PPC440_VIRTEX5_SPLB1_NUM_MASTERS 1
#define XPAR_PPC440_VIRTEX5_SPLB1_MID_WIDTH 1
#define XPAR_PPC440_VIRTEX5_SPLB1_ALLOW_LOCK_XFER 1
#define XPAR_PPC440_VIRTEX5_SPLB1_READ_PIPE_ENABLE 1
#define XPAR_PPC440_VIRTEX5_SPLB1_PROPAGATE_MIRQ 0
#define XPAR_PPC440_VIRTEX5_SPLB1_P2P -1
#define XPAR_PPC440_VIRTEX5_NUM_DMA 0
#define XPAR_PPC440_VIRTEX5_DMA0_TXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA0_RXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA0_CONTROL 0b00000000
#define XPAR_PPC440_VIRTEX5_DMA0_TXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA0_RXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA1_TXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA1_RXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA1_CONTROL 0b00000000
#define XPAR_PPC440_VIRTEX5_DMA1_TXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA1_RXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA2_TXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA2_RXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA2_CONTROL 0b00000000
#define XPAR_PPC440_VIRTEX5_DMA2_TXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA2_RXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA3_TXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA3_RXCHANNELCTRL 0x01010000
#define XPAR_PPC440_VIRTEX5_DMA3_CONTROL 0b00000000
#define XPAR_PPC440_VIRTEX5_DMA3_TXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DMA3_RXIRQTIMER 0b1111111111
#define XPAR_PPC440_VIRTEX5_DCR_AUTOLOCK_ENABLE 1
#define XPAR_PPC440_VIRTEX5_PPCDM_ASYNCMODE 0
#define XPAR_PPC440_VIRTEX5_PPCDS_ASYNCMODE 0
#define XPAR_PPC440_VIRTEX5_GENERATE_PLB_TIMESPECS 1
#define XPAR_PPC440_VIRTEX5_HW_VER "1.01.a"
/******************************************************************/

281
slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h
View File

@ -1,251 +1,256 @@
#pragma once
#define REG_OFFSET (4)
#define REG_OFFSET (4)
/* Base addresses 0x1804 0000 ---------------------------------------------*/
/* Reconfiguration core for readout pll */
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
/* Reconfiguration core for system pll */
#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
/* Clock Generation */
#define BASE_CLK_GENERATION (0x1000) // 0x1804_1000 - 0x1804_XXXX //TODO
#define BASE_CLK_GENERATION (0x1000) // 0x1804_1000 - 0x1804_XXXX //TODO
/* Base addresses 0x1806 0000 ---------------------------------------------*/
/* General purpose control and status registers */
#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF
#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/ctrl/ctrl.vhd
/* ASIC Control */
#define BASE_ASIC (0x0100) // 0x1806_0100 - 0x1806_011F
#define BASE_ASIC (0x0100) // 0x1806_0100 - 0x1806_011F
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/asic/asic_ctrl.vhd
/* ASIC Digital Interface. Data recovery core */
#define BASE_ADIF (0x0120) // 0x1806_0120 - 0x1806_012F
#define BASE_ADIF (0x0120) // 0x1806_0120 - 0x1806_012F
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/adif/adif_ctrl.vhd
/* Formatting of data core */
#define BASE_FMT (0x0130) // 0x1806_0130 - 0x1806_013F
#define BASE_FMT (0x0130) // 0x1806_0130 - 0x1806_013F
/* Packetizer */
#define BASE_PKT (0x0140) // 0x1806_0140 - 0x1806_014F
#define BASE_PKT (0x0140) // 0x1806_0140 - 0x1806_014F
// https://git.psi.ch/sls_detectors_firmware/gotthard_II_mcb/blob/master/code/hdl/pkt/pkt_ctrl.vhd
/* Flow control and status registers */
#define BASE_FLOW_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
#define BASE_FLOW_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/f37608230b4721661f29aacc20124555705ee705/flow/flow_ctrl.vhd
/* UDP datagram generator */
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
/* Clock Generation registers ------------------------------------------------------*/
#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
#define PLL_RESET_READOUT_OFST (0)
#define PLL_RESET_READOUT_MSK (0x00000001 << PLL_RESET_READOUT_OFST)
#define PLL_RESET_SYSTEM_OFST (1)
#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
/* Clock Generation registers
* ------------------------------------------------------*/
#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
#define PLL_RESET_READOUT_OFST (0)
#define PLL_RESET_READOUT_MSK (0x00000001 << PLL_RESET_READOUT_OFST)
#define PLL_RESET_SYSTEM_OFST (1)
#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
/* Control registers --------------------------------------------------*/
/* Module Control Board Serial Number register */
#define MCB_SERIAL_NO_REG (0x00 * REG_OFFSET + BASE_CONTROL)
#define MCB_SERIAL_NO_REG (0x00 * REG_OFFSET + BASE_CONTROL)
#define MCB_SERIAL_NO_VRSN_OFST (16)
#define MCB_SERIAL_NO_VRSN_MSK (0x0000001F << MCB_SERIAL_NO_VRSN_OFST)
#define MCB_SERIAL_NO_VRSN_OFST (16)
#define MCB_SERIAL_NO_VRSN_MSK (0x0000001F << MCB_SERIAL_NO_VRSN_OFST)
/* FPGA Version register */
#define FPGA_VERSION_REG (0x01 * REG_OFFSET + BASE_CONTROL)
#define FPGA_VERSION_REG (0x01 * REG_OFFSET + BASE_CONTROL)
#define FPGA_COMPILATION_DATE_OFST (0)
#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
#define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
#define FPGA_COMPILATION_DATE_OFST (0)
#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
#define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
/* API Version register */
#define API_VERSION_REG (0x02 * REG_OFFSET + BASE_CONTROL)
#define API_VERSION_REG (0x02 * REG_OFFSET + BASE_CONTROL)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK \
(0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
/* Fix pattern register */
#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
#define FIX_PATT_VAL (0xACDC2019)
#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
#define FIX_PATT_VAL (0xACDC2019)
/* Status register */
#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL)
#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL)
/* Look at me read only register */
#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL)
#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL)
/* System status register */
#define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL)
#define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL)
/* Config RW regiseter */
#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL)
#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL)
/* Control RW register */
#define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL)
#define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
#define CONTROL_TIMING_SOURCE_EXT_OFST (17)
#define CONTROL_TIMING_SOURCE_EXT_MSK (0x00000001 << CONTROL_TIMING_SOURCE_EXT_OFST)
#define CONTROL_PWR_CHIP_OFST (31)
#define CONTROL_PWR_CHIP_MSK (0x00000001 << CONTROL_PWR_CHIP_OFST)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
#define CONTROL_TIMING_SOURCE_EXT_OFST (17)
#define CONTROL_TIMING_SOURCE_EXT_MSK \
(0x00000001 << CONTROL_TIMING_SOURCE_EXT_OFST)
#define CONTROL_PWR_CHIP_OFST (31)
#define CONTROL_PWR_CHIP_MSK (0x00000001 << CONTROL_PWR_CHIP_OFST)
/** DTA Offset Register */
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
/* ASIC registers --------------------------------------------------*/
/* ASIC Config register */
#define ASIC_CONFIG_REG (0x00 * REG_OFFSET + BASE_ASIC)
#define ASIC_CONFIG_REG (0x00 * REG_OFFSET + BASE_ASIC)
#define ASIC_CONFIG_RUN_MODE_OFST (0)
#define ASIC_CONFIG_RUN_MODE_MSK (0x00000003 << ASIC_CONFIG_RUN_MODE_OFST)
#define ASIC_CONFIG_RUN_MODE_INT_BURST_VAL ((0x1 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_CONT_VAL ((0x2 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL ((0x3 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_GAIN_OFST (4)
#define ASIC_CONFIG_GAIN_MSK (0x00000003 << ASIC_CONFIG_GAIN_OFST)
#define ASIC_CONFIG_DYNAMIC_GAIN_VAL ((0x0 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_1_VAL ((0x1 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_2_VAL ((0x2 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_RESERVED_VAL ((0x3 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_RUN_MODE_OFST (0)
#define ASIC_CONFIG_RUN_MODE_MSK (0x00000003 << ASIC_CONFIG_RUN_MODE_OFST)
#define ASIC_CONFIG_RUN_MODE_INT_BURST_VAL \
((0x1 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_CONT_VAL \
((0x2 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL \
((0x3 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_GAIN_OFST (4)
#define ASIC_CONFIG_GAIN_MSK (0x00000003 << ASIC_CONFIG_GAIN_OFST)
#define ASIC_CONFIG_DYNAMIC_GAIN_VAL \
((0x0 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_1_VAL \
((0x1 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_2_VAL \
((0x2 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_RESERVED_VAL \
((0x3 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_CURRENT_SRC_EN_OFST (7)
#define ASIC_CONFIG_CURRENT_SRC_EN_MSK (0x00000001 << ASIC_CONFIG_CURRENT_SRC_EN_OFST)
#define ASIC_CONFIG_RST_DAC_OFST (15)
#define ASIC_CONFIG_RST_DAC_MSK (0x00000001 << ASIC_CONFIG_RST_DAC_OFST)
#define ASIC_CONFIG_DONE_OFST (31)
#define ASIC_CONFIG_DONE_MSK (0x00000001 << ASIC_CONFIG_DONE_OFST)
#define ASIC_CONFIG_CURRENT_SRC_EN_MSK \
(0x00000001 << ASIC_CONFIG_CURRENT_SRC_EN_OFST)
#define ASIC_CONFIG_RST_DAC_OFST (15)
#define ASIC_CONFIG_RST_DAC_MSK (0x00000001 << ASIC_CONFIG_RST_DAC_OFST)
#define ASIC_CONFIG_DONE_OFST (31)
#define ASIC_CONFIG_DONE_MSK (0x00000001 << ASIC_CONFIG_DONE_OFST)
/* ASIC Internal Frames Register */
#define ASIC_INT_FRAMES_REG (0x01 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_FRAMES_REG (0x01 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_FRAMES_OFST (0)
#define ASIC_INT_FRAMES_MSK (0x00000FFF << ASIC_INT_FRAMES_OFST)
#define ASIC_INT_FRAMES_OFST (0)
#define ASIC_INT_FRAMES_MSK (0x00000FFF << ASIC_INT_FRAMES_OFST)
/* ASIC Period 64bit Register */
#define ASIC_INT_PERIOD_LSB_REG (0x02 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_PERIOD_MSB_REG (0x03 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_PERIOD_LSB_REG (0x02 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_PERIOD_MSB_REG (0x03 * REG_OFFSET + BASE_ASIC)
/* ASIC Exptime 64bit Register */
#define ASIC_INT_EXPTIME_LSB_REG (0x04 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_EXPTIME_MSB_REG (0x05 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_EXPTIME_LSB_REG (0x04 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_EXPTIME_MSB_REG (0x05 * REG_OFFSET + BASE_ASIC)
/* Packetizer -------------------------------------------------------------*/
/* Packetizer Config Register */
#define PKT_CONFIG_REG (0x00 * REG_OFFSET + BASE_PKT)
#define PKT_CONFIG_REG (0x00 * REG_OFFSET + BASE_PKT)
#define PKT_CONFIG_NRXR_MAX_OFST (0)
#define PKT_CONFIG_NRXR_MAX_MSK (0x0000003F << PKT_CONFIG_NRXR_MAX_OFST)
#define PKT_CONFIG_RXR_START_ID_OFST (8)
#define PKT_CONFIG_RXR_START_ID_MSK (0x0000003F << PKT_CONFIG_RXR_START_ID_OFST)
#define PKT_CONFIG_NRXR_MAX_OFST (0)
#define PKT_CONFIG_NRXR_MAX_MSK (0x0000003F << PKT_CONFIG_NRXR_MAX_OFST)
#define PKT_CONFIG_RXR_START_ID_OFST (8)
#define PKT_CONFIG_RXR_START_ID_MSK (0x0000003F << PKT_CONFIG_RXR_START_ID_OFST)
/* Module Coordinates Register */
#define COORD_0_REG (0x02 * REG_OFFSET + BASE_PKT)
#define COORD_ROW_OFST (0)
#define COORD_ROW_MSK (0x0000FFFF << COORD_ROW_OFST)
#define COORD_COL_OFST (16)
#define COORD_COL_MSK (0x0000FFFF << COORD_COL_OFST)
#define COORD_0_REG (0x02 * REG_OFFSET + BASE_PKT)
#define COORD_ROW_OFST (0)
#define COORD_ROW_MSK (0x0000FFFF << COORD_ROW_OFST)
#define COORD_COL_OFST (16)
#define COORD_COL_MSK (0x0000FFFF << COORD_COL_OFST)
/* Module ID Register */
#define COORD_1_REG (0x03 * REG_OFFSET + BASE_PKT)
#define COORD_RESERVED_OFST (0)
#define COORD_RESERVED_MSK (0x0000FFFF << COORD_RESERVED_OFST)
#define COORD_ID_OFST (16) // Not connected in firmware TODO
#define COORD_ID_MSK (0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
#define COORD_1_REG (0x03 * REG_OFFSET + BASE_PKT)
#define COORD_RESERVED_OFST (0)
#define COORD_RESERVED_MSK (0x0000FFFF << COORD_RESERVED_OFST)
#define COORD_ID_OFST (16) // Not connected in firmware TODO
#define COORD_ID_MSK \
(0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
/* Flow control registers --------------------------------------------------*/
/* Flow status Register*/
#define FLOW_STATUS_REG (0x00 * REG_OFFSET + BASE_FLOW_CONTROL)
#define FLOW_STATUS_REG (0x00 * REG_OFFSET + BASE_FLOW_CONTROL)
#define FLOW_STATUS_RUN_BUSY_OFST (0)
#define FLOW_STATUS_RUN_BUSY_MSK (0x00000001 << FLOW_STATUS_RUN_BUSY_OFST)
#define FLOW_STATUS_RUN_BUSY_MSK (0x00000001 << FLOW_STATUS_RUN_BUSY_OFST)
#define FLOW_STATUS_WAIT_FOR_TRGGR_OFST (3)
#define FLOW_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << FLOW_STATUS_WAIT_FOR_TRGGR_OFST)
#define FLOW_STATUS_WAIT_FOR_TRGGR_MSK \
(0x00000001 << FLOW_STATUS_WAIT_FOR_TRGGR_OFST)
#define FLOW_STATUS_DLY_BFRE_TRGGR_OFST (4)
#define FLOW_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << FLOW_STATUS_DLY_BFRE_TRGGR_OFST)
#define FLOW_STATUS_DLY_BFRE_TRGGR_MSK \
(0x00000001 << FLOW_STATUS_DLY_BFRE_TRGGR_OFST)
#define FLOW_STATUS_FIFO_FULL_OFST (5)
#define FLOW_STATUS_FIFO_FULL_MSK (0x00000001 << FLOW_STATUS_FIFO_FULL_OFST)
#define FLOW_STATUS_FIFO_FULL_MSK (0x00000001 << FLOW_STATUS_FIFO_FULL_OFST)
#define FLOW_STATUS_DLY_AFTR_TRGGR_OFST (15)
#define FLOW_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << FLOW_STATUS_DLY_AFTR_TRGGR_OFST)
#define FLOW_STATUS_CSM_BUSY_OFST (17)
#define FLOW_STATUS_CSM_BUSY_MSK (0x00000001 << FLOW_STATUS_CSM_BUSY_OFST)
#define FLOW_STATUS_DLY_AFTR_TRGGR_MSK \
(0x00000001 << FLOW_STATUS_DLY_AFTR_TRGGR_OFST)
#define FLOW_STATUS_CSM_BUSY_OFST (17)
#define FLOW_STATUS_CSM_BUSY_MSK (0x00000001 << FLOW_STATUS_CSM_BUSY_OFST)
/* Delay left 64bit Register */
#define GET_DELAY_LSB_REG (0x02 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_DELAY_MSB_REG (0x03 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_DELAY_LSB_REG (0x02 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_DELAY_MSB_REG (0x03 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Triggers left 64bit Register */
#define GET_CYCLES_LSB_REG (0x04 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_CYCLES_MSB_REG (0x05 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_CYCLES_LSB_REG (0x04 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_CYCLES_MSB_REG (0x05 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Frames left 64bit Register */
#define GET_FRAMES_LSB_REG (0x06 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_FRAMES_MSB_REG (0x07 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_FRAMES_LSB_REG (0x06 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_FRAMES_MSB_REG (0x07 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Period left 64bit Register */
#define GET_PERIOD_LSB_REG (0x08 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_PERIOD_MSB_REG (0x09 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_PERIOD_LSB_REG (0x08 * REG_OFFSET + BASE_FLOW_CONTROL)
#define GET_PERIOD_MSB_REG (0x09 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Time from Start 64 bit register */
#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_FLOW_CONTROL)
#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_FLOW_CONTROL)
#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_FLOW_CONTROL)
#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_FLOW_CONTROL)
/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_FLOW_CONTROL)
#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_FLOW_CONTROL)
/* Get Frames from Start 64 bit register (frames from last reset using
* CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_FLOW_CONTROL)
#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_FLOW_CONTROL)
/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
#define START_FRAME_TIME_LSB_REG (0x0E * REG_OFFSET + BASE_FLOW_CONTROL)
#define START_FRAME_TIME_MSB_REG (0x0F * REG_OFFSET + BASE_FLOW_CONTROL)
#define START_FRAME_TIME_LSB_REG (0x0E * REG_OFFSET + BASE_FLOW_CONTROL)
#define START_FRAME_TIME_MSB_REG (0x0F * REG_OFFSET + BASE_FLOW_CONTROL)
/* Delay 64bit Write-register */
#define SET_DELAY_LSB_REG (0x22 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_DELAY_MSB_REG (0x23 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_DELAY_LSB_REG (0x22 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_DELAY_MSB_REG (0x23 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Cylces (also #bursts) 64bit Write-register */
#define SET_CYCLES_LSB_REG (0x24 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_CYCLES_MSB_REG (0x25 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_CYCLES_LSB_REG (0x24 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_CYCLES_MSB_REG (0x25 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Frames 64bit Write-register */
#define SET_FRAMES_LSB_REG (0x26 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_FRAMES_MSB_REG (0x27 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_FRAMES_LSB_REG (0x26 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_FRAMES_MSB_REG (0x27 * REG_OFFSET + BASE_FLOW_CONTROL)
/* Period (also burst period) 64bit Write-register */
#define SET_PERIOD_LSB_REG (0x28 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_PERIOD_MSB_REG (0x29 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_PERIOD_LSB_REG (0x28 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_PERIOD_MSB_REG (0x29 * REG_OFFSET + BASE_FLOW_CONTROL)
/* External Signal register */
#define EXT_SIGNAL_REG (0x30 * REG_OFFSET + BASE_FLOW_CONTROL)
#define EXT_SIGNAL_REG (0x30 * REG_OFFSET + BASE_FLOW_CONTROL)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
/* Trigger Delay 64 bit register */
#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_TRIGGER_DELAY_MSB_REG (0x33 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_FLOW_CONTROL)
#define SET_TRIGGER_DELAY_MSB_REG (0x33 * REG_OFFSET + BASE_FLOW_CONTROL)

234
slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
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@ -1,143 +1,159 @@
#pragma once
#include "sls_detector_defs.h"
#define REQRD_FRMWRE_VRSN (0x190000)
#define REQRD_FRMWRE_VRSN (0x190000)
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
/* Hardware Definitions */
#define NCHAN (128)
#define NCHIP (10)
#define NDAC (16)
#define NADC (32)
#define ONCHIP_NDAC (7)
#define NCHAN (128)
#define NCHIP (10)
#define NDAC (16)
#define NADC (32)
#define ONCHIP_NDAC (7)
#define DYNAMIC_RANGE (16)
#define HV_SOFT_MAX_VOLTAGE (200)
#define HV_HARD_MAX_VOLTAGE (530)
#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
#define DAC_DRIVER_FILE_NAME ("/etc/devlinks/dac")
#define ONCHIP_DAC_DRIVER_FILE_NAME ("/etc/devlinks/chipdac")
#define TYPE_FILE_NAME ("/etc/devlinks/type")
#define TYPE_FILE_NAME ("/etc/devlinks/type")
#define CONFIG_FILE ("config.txt")
#define DAC_MAX_MV (2048)
#define ONCHIP_DAC_MAX_VAL (0x3FF)
#define ADU_MAX_VAL (0xFFF)
#define ADU_MAX_BITS (12)
#define MAX_FRAMES_IN_BURST_MODE (2720)
#define TYPE_GOTTHARD2_MODULE_VAL (512)
#define TYPE_TOLERANCE (10)
#define TYPE_NO_MODULE_STARTING_VAL (800)
#define INITIAL_STARTUP_WAIT (1 * 1000 * 1000)
#define ONCHIP_DAC_MAX_VAL (0x3FF)
#define ADU_MAX_VAL (0xFFF)
#define ADU_MAX_BITS (12)
#define MAX_FRAMES_IN_BURST_MODE (2720)
#define TYPE_GOTTHARD2_MODULE_VAL (512)
#define TYPE_TOLERANCE (10)
#define TYPE_NO_MODULE_STARTING_VAL (800)
#define INITIAL_STARTUP_WAIT (1 * 1000 * 1000)
/** Default Parameters */
#define DEFAULT_BURST_MODE (BURST_INTERNAL)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_NUM_BURSTS (1)
#define DEFAULT_EXPTIME (0) // 0 ms (220ns in firmware)
#define DEFAULT_PERIOD (0) // 0 ms
#define DEFAULT_BURST_MODE (BURST_INTERNAL)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_NUM_BURSTS (1)
#define DEFAULT_EXPTIME (0) // 0 ms (220ns in firmware)
#define DEFAULT_PERIOD (0) // 0 ms
#define DEFAULT_DELAY_AFTER_TRIGGER (0)
#define DEFAULT_BURST_PERIOD (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_CURRENT_SOURCE (0)
#define DEFAULT_TIMING_SOURCE (TIMING_INTERNAL)
#define DEFAULT_BURST_PERIOD (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_CURRENT_SOURCE (0)
#define DEFAULT_TIMING_SOURCE (TIMING_INTERNAL)
#define DEFAULT_READOUT_C0 (8)//(108333336) // rdo_clk, 108 MHz
#define DEFAULT_READOUT_C1 (8)//(108333336) // rdo_x2_clk, 108 MHz
#define DEFAULT_SYSTEM_C0 (5)//(144444448) // run_clk, 144 MHz
#define DEFAULT_SYSTEM_C1 (10)//(72222224) // chip_clk, 72 MHz
#define DEFAULT_SYSTEM_C2 (5)//(144444448) // sync_clk, 144 MHz
#define DEFAULT_SYSTEM_C3 (5)//(144444448) // str_clk, 144 MHz
#define DEFAULT_READOUT_C0 (8) //(108333336) // rdo_clk, 108 MHz
#define DEFAULT_READOUT_C1 (8) //(108333336) // rdo_x2_clk, 108 MHz
#define DEFAULT_SYSTEM_C0 (5) //(144444448) // run_clk, 144 MHz
#define DEFAULT_SYSTEM_C1 (10) //(72222224) // chip_clk, 72 MHz
#define DEFAULT_SYSTEM_C2 (5) //(144444448) // sync_clk, 144 MHz
#define DEFAULT_SYSTEM_C3 (5) //(144444448) // str_clk, 144 MHz
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (20000000) // 20MHz
#define INT_SYSTEM_C0_FREQUENCY (144000000) //144 MHz
#define READOUT_PLL_VCO_FREQ_HZ (866666688) // 866 MHz
#define SYSTEM_PLL_VCO_FREQ_HZ (722222224) // 722 MHz
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (20000000) // 20MHz
#define INT_SYSTEM_C0_FREQUENCY (144000000) // 144 MHz
#define READOUT_PLL_VCO_FREQ_HZ (866666688) // 866 MHz
#define SYSTEM_PLL_VCO_FREQ_HZ (722222224) // 722 MHz
/** Other Definitions */
#define BIT16_MASK (0xFFFF)
#define BIT16_MASK (0xFFFF)
/* Enums */
enum DACINDEX {G2_VREF_H_ADC, /* 0 */ \
G2_DAC_UNUSED, /* 1 */ \
G2_VB_COMP_FE, /* 2 */ \
G2_VB_COMP_ADC, /* 3 */ \
G2_VCOM_CDS, /* 4 */ \
G2_VREF_RSTORE,/* 5 */ \
G2_VB_OPA_1ST, /* 6 */ \
G2_VREF_COMP_FE,/* 7 */ \
G2_VCOM_ADC1, /* 8 */ \
G2_VREF_PRECH, /* 9 */ \
G2_VREF_L_ADC, /* 10 */ \
G2_VREF_CDS, /* 11 */ \
G2_VB_CS, /* 12 */ \
G2_VB_OPA_FD, /* 13 */ \
G2_DAC_UNUSED2, /* 14 */ \
G2_VCOM_ADC2 /* 15*/ \
};
#define DAC_NAMES "vref_h_adc", "dac_unused", "vb_comp_fe", "vb_comp_adc", "vcom_cds", "vref_rstore", "vb_opa_1st", "vref_comp_fe", "vcom_adc1", "vref_prech", "vref_l_adc", "vref_cds", "vb_cs", "vb_opa_fd", "dac_unused2", "vcom_adc2"
enum DACINDEX {
G2_VREF_H_ADC, /* 0 */
G2_DAC_UNUSED, /* 1 */
G2_VB_COMP_FE, /* 2 */
G2_VB_COMP_ADC, /* 3 */
G2_VCOM_CDS, /* 4 */
G2_VREF_RSTORE, /* 5 */
G2_VB_OPA_1ST, /* 6 */
G2_VREF_COMP_FE, /* 7 */
G2_VCOM_ADC1, /* 8 */
G2_VREF_PRECH, /* 9 */
G2_VREF_L_ADC, /* 10 */
G2_VREF_CDS, /* 11 */
G2_VB_CS, /* 12 */
G2_VB_OPA_FD, /* 13 */
G2_DAC_UNUSED2, /* 14 */
G2_VCOM_ADC2 /* 15*/
};
#define DAC_NAMES \
"vref_h_adc", "dac_unused", "vb_comp_fe", "vb_comp_adc", "vcom_cds", \
"vref_rstore", "vb_opa_1st", "vref_comp_fe", "vcom_adc1", \
"vref_prech", "vref_l_adc", "vref_cds", "vb_cs", "vb_opa_fd", \
"dac_unused2", "vcom_adc2"
enum ONCHIP_DACINDEX {G2_VCHIP_COMP_FE, /* 0 */ \
G2_VCHIP_OPA_1ST, /* 1 */ \
G2_VCHIP_OPA_FD, /* 2 */ \
G2_VCHIP_COMP_ADC, /* 3 */ \
G2_VCHIP_UNUSED, /* 4 */ \
G2_VCHIP_REF_COMP_FE, /* 5 */ \
G2_VCHIP_CS /* 6 */ \
};
#define ONCHIP_DAC_NAMES "vchip_comp_fe", "vchip_opa_1st", "vchip_opa_fd", "vchip_comp_adc", "vchip_unused", "vchip_ref_comp_fe", "vchip_cs"
enum ONCHIP_DACINDEX {
G2_VCHIP_COMP_FE, /* 0 */
G2_VCHIP_OPA_1ST, /* 1 */
G2_VCHIP_OPA_FD, /* 2 */
G2_VCHIP_COMP_ADC, /* 3 */
G2_VCHIP_UNUSED, /* 4 */
G2_VCHIP_REF_COMP_FE, /* 5 */
G2_VCHIP_CS /* 6 */
};
#define ONCHIP_DAC_NAMES \
"vchip_comp_fe", "vchip_opa_1st", "vchip_opa_fd", "vchip_comp_adc", \
"vchip_unused", "vchip_ref_comp_fe", "vchip_cs"
enum CLKINDEX {
READOUT_C0,
READOUT_C1,
SYSTEM_C0,
SYSTEM_C1,
SYSTEM_C2,
SYSTEM_C3,
NUM_CLOCKS
};
#define CLK_NAMES \
"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", \
"SYSTEM_C3"
enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS};
#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3"
enum PLLINDEX {READOUT_PLL, SYSTEM_PLL};
enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
/** Chip Definitions */
#define ASIC_ADDR_MAX_BITS (4)
#define ASIC_CURRENT_INJECT_ADDR (0x9)
#define ASIC_VETO_REF_ADDR (0xA)
#define ASIC_CONF_ADC_ADDR (0xB)
#define ASIC_CONF_GLOBAL_SETT (0xC)
#define ASIC_ADDR_MAX_BITS (4)
#define ASIC_CURRENT_INJECT_ADDR (0x9)
#define ASIC_VETO_REF_ADDR (0xA)
#define ASIC_CONF_ADC_ADDR (0xB)
#define ASIC_CONF_GLOBAL_SETT (0xC)
#define ASIC_GAIN_MAX_BITS (2)
#define ASIC_GAIN_MSK (0x3)
#define ASIC_G0_VAL ((0x0 & ASIC_GAIN_MSK) << ADU_MAX_BITS)
#define ASIC_G1_VAL ((0x1 & ASIC_GAIN_MSK) << ADU_MAX_BITS)
#define ASIC_G2_VAL ((0x3 & ASIC_GAIN_MSK) << ADU_MAX_BITS)
#define ASIC_CONTINUOUS_MODE_MSK (0x7)
#define ASIC_ADC_MAX_BITS (7)
#define ASIC_ADC_MAX_VAL (0x7F)
#define ASIC_GLOBAL_SETT_MAX_BITS (6)
#define ASIC_GLOBAL_BURST_VALUE (0x0)
#define ASIC_GLOBAL_CONT_VALUE (0x1E)
#define ASIC_GAIN_MAX_BITS (2)
#define ASIC_GAIN_MSK (0x3)
#define ASIC_G0_VAL ((0x0 & ASIC_GAIN_MSK) << ADU_MAX_BITS)
#define ASIC_G1_VAL ((0x1 & ASIC_GAIN_MSK) << ADU_MAX_BITS)
#define ASIC_G2_VAL ((0x3 & ASIC_GAIN_MSK) << ADU_MAX_BITS)
#define ASIC_CONTINUOUS_MODE_MSK (0x7)
#define ASIC_ADC_MAX_BITS (7)
#define ASIC_ADC_MAX_VAL (0x7F)
#define ASIC_GLOBAL_SETT_MAX_BITS (6)
#define ASIC_GLOBAL_BURST_VALUE (0x0)
#define ASIC_GLOBAL_CONT_VALUE (0x1E)
/* Struct Definitions */
typedef struct udp_header_struct {
uint32_t udp_destmac_msb;
uint16_t udp_srcmac_msb;
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl: 4, ip_ver: 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
uint16_t ip_srcip_lsb;
uint16_t udp_srcport;
uint16_t ip_destip_lsb;
uint16_t udp_checksum;
uint16_t udp_destport;
uint32_t udp_destmac_msb;
uint16_t udp_srcmac_msb;
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl : 4, ip_ver : 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
uint16_t ip_srcip_lsb;
uint16_t udp_srcport;
uint16_t ip_destip_lsb;
uint16_t udp_checksum;
uint16_t udp_destport;
} udp_header;
#define UDP_IP_HEADER_LENGTH_BYTES (28)
#define UDP_IP_HEADER_LENGTH_BYTES (28)

477
slsDetectorServers/gotthardDetectorServer/RegisterDefs.h Executable file → Normal file
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@ -1,18 +1,23 @@
#pragma once
/* Definitions for FPGA*/
#define MEM_MAP_SHIFT (11)
#define MEM_MAP_SHIFT (11)
/** Gain register */
#define GAIN_REG (0x10 << MEM_MAP_SHIFT)
#define GAIN_REG (0x10 << MEM_MAP_SHIFT)
#define GAIN_CONFGAIN_OFST (0)
#define GAIN_CONFGAIN_MSK (0x000000FF << GAIN_CONFGAIN_OFST)
#define GAIN_CONFGAIN_HGH_GAIN_VAL ((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_DYNMC_GAIN_VAL ((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_LW_GAIN_VAL ((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_MDM_GAIN_VAL ((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL ((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_OFST (0)
#define GAIN_CONFGAIN_MSK (0x000000FF << GAIN_CONFGAIN_OFST)
#define GAIN_CONFGAIN_HGH_GAIN_VAL \
((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_DYNMC_GAIN_VAL \
((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_LW_GAIN_VAL \
((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_MDM_GAIN_VAL \
((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL \
((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
/** Flow Control register */
//#define FLOW_CONTROL_REG (0x11 << MEM_MAP_SHIFT)
@ -24,243 +29,261 @@
//#define FRAME_REG (0x13 << MEM_MAP_SHIFT)
/** Multi Purpose register */
#define MULTI_PURPOSE_REG (0x14 << MEM_MAP_SHIFT)
#define MULTI_PURPOSE_REG (0x14 << MEM_MAP_SHIFT)
#define PHS_STP_OFST (0)
#define PHS_STP_MSK (0x00000001 << PHS_STP_OFST)
#define RST_CNTR_OFST (2)
#define RST_CNTR_MSK (0x00000001 << RST_CNTR_OFST)
#define SW1_OFST (5)
#define SW1_MSK (0x00000001 << SW1_OFST)
#define WRT_BCK_OFST (6)
#define WRT_BCK_MSK (0x00000001 << WRT_BCK_OFST)
#define RST_OFST (7)
#define RST_MSK (0x00000001 << RST_OFST)
#define PLL_CLK_SL_OFST (8)
#define PLL_CLK_SL_MSK (0x00000007 << PLL_CLK_SL_OFST)
#define PLL_CLK_SL_MSTR_VAL ((0x1 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_MSTR_ADC_VAL ((0x2 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_SLV_VAL ((0x3 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_SLV_ADC_VAL ((0x4 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define ENT_RSTN_OFST (11)
#define ENT_RSTN_MSK (0x00000001 << ENT_RSTN_OFST)
#define INT_RSTN_OFST (12)
#define INT_RSTN_MSK (0x00000001 << INT_RSTN_OFST)
#define DGTL_TST_OFST (14)
#define DGTL_TST_MSK (0x00000001 << DGTL_TST_OFST)
#define CHNG_AT_PWR_ON_OFST (15) // Not used in SW
#define CHNG_AT_PWR_ON_MSK (0x00000001 << CHNG_AT_PWR_ON_OFST) // Not used in SW
#define RST_TO_SW1_DLY_OFST (16)
#define RST_TO_SW1_DLY_MSK (0x0000000F << RST_TO_SW1_DLY_OFST)
#define STRT_ACQ_DLY_OFST (20)
#define STRT_ACQ_DLY_MSK (0x0000000F << STRT_ACQ_DLY_OFST)
#define PHS_STP_OFST (0)
#define PHS_STP_MSK (0x00000001 << PHS_STP_OFST)
#define RST_CNTR_OFST (2)
#define RST_CNTR_MSK (0x00000001 << RST_CNTR_OFST)
#define SW1_OFST (5)
#define SW1_MSK (0x00000001 << SW1_OFST)
#define WRT_BCK_OFST (6)
#define WRT_BCK_MSK (0x00000001 << WRT_BCK_OFST)
#define RST_OFST (7)
#define RST_MSK (0x00000001 << RST_OFST)
#define PLL_CLK_SL_OFST (8)
#define PLL_CLK_SL_MSK (0x00000007 << PLL_CLK_SL_OFST)
#define PLL_CLK_SL_MSTR_VAL ((0x1 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_MSTR_ADC_VAL ((0x2 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_SLV_VAL ((0x3 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_SLV_ADC_VAL ((0x4 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define ENT_RSTN_OFST (11)
#define ENT_RSTN_MSK (0x00000001 << ENT_RSTN_OFST)
#define INT_RSTN_OFST (12)
#define INT_RSTN_MSK (0x00000001 << INT_RSTN_OFST)
#define DGTL_TST_OFST (14)
#define DGTL_TST_MSK (0x00000001 << DGTL_TST_OFST)
#define CHNG_AT_PWR_ON_OFST (15) // Not used in SW
#define CHNG_AT_PWR_ON_MSK (0x00000001 << CHNG_AT_PWR_ON_OFST) // Not used in SW
#define RST_TO_SW1_DLY_OFST (16)
#define RST_TO_SW1_DLY_MSK (0x0000000F << RST_TO_SW1_DLY_OFST)
#define STRT_ACQ_DLY_OFST (20)
#define STRT_ACQ_DLY_MSK (0x0000000F << STRT_ACQ_DLY_OFST)
/** DAQ register */
#define DAQ_REG (0x15 << MEM_MAP_SHIFT)
#define DAQ_REG (0x15 << MEM_MAP_SHIFT)
#define DAQ_TKN_TMNG_OFST (0)
#define DAQ_TKN_TMNG_MSK (0x0000FFFF << DAQ_TKN_TMNG_OFST)
#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL ((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL ((0x1f10 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_PCKT_LNGTH_OFST (16)
#define DAQ_PCKT_LNGTH_MSK (0x0000FFFF << DAQ_PCKT_LNGTH_OFST)
#define DAQ_PCKT_LNGTH_NO_ROI_VAL ((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
#define DAQ_PCKT_LNGTH_ROI_VAL ((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
#define DAQ_TKN_TMNG_OFST (0)
#define DAQ_TKN_TMNG_MSK (0x0000FFFF << DAQ_TKN_TMNG_OFST)
#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL \
((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL \
((0x1f10 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_PCKT_LNGTH_OFST (16)
#define DAQ_PCKT_LNGTH_MSK (0x0000FFFF << DAQ_PCKT_LNGTH_OFST)
#define DAQ_PCKT_LNGTH_NO_ROI_VAL \
((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
#define DAQ_PCKT_LNGTH_ROI_VAL \
((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
/** Time From Start register */
//#define TIME_FROM_START_REG (0x16 << MEM_MAP_SHIFT)
/** DAC Control register */
#define SPI_REG (0x17 << MEM_MAP_SHIFT)
#define SPI_REG (0x17 << MEM_MAP_SHIFT)
#define SPI_DAC_SRL_CS_OTPT_OFST (0)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (2)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
#define SPI_DAC_SRL_CS_OTPT_OFST (0)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (2)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
/** ADC SPI register */
#define ADC_SPI_REG (0x18 << MEM_MAP_SHIFT)
#define ADC_SPI_REG (0x18 << MEM_MAP_SHIFT)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000001F << ADC_SPI_SRL_CS_OTPT_OFST)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000001F << ADC_SPI_SRL_CS_OTPT_OFST)
/** ADC Sync register */
#define ADC_SYNC_REG (0x19 << MEM_MAP_SHIFT)
#define ADC_SYNC_REG (0x19 << MEM_MAP_SHIFT)
#define ADC_SYNC_ENET_STRT_DLY_OFST (0)
#define ADC_SYNC_ENET_STRT_DLY_MSK (0x0000000F << ADC_SYNC_ENET_STRT_DLY_OFST)
#define ADC_SYNC_ENET_STRT_DLY_VAL ((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
#define ADC_SYNC_TKN1_HGH_DLY_OFST (4)
#define ADC_SYNC_TKN1_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_HGH_DLY_OFST)
#define ADC_SYNC_TKN1_HGH_DLY_VAL ((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
#define ADC_SYNC_TKN2_HGH_DLY_OFST (8)
#define ADC_SYNC_TKN2_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_HGH_DLY_OFST)
#define ADC_SYNC_TKN2_HGH_DLY_VAL ((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
#define ADC_SYNC_TKN1_LOW_DLY_OFST (12)
#define ADC_SYNC_TKN1_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_LOW_DLY_OFST)
#define ADC_SYNC_TKN1_LOW_DLY_VAL ((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
#define ADC_SYNC_TKN2_LOW_DLY_OFST (16)
#define ADC_SYNC_TKN2_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_LOW_DLY_OFST)
#define ADC_SYNC_TKN2_LOW_DLY_VAL ((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
//0x32214
#define ADC_SYNC_TKN_VAL (ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL | ADC_SYNC_TKN2_LOW_DLY_VAL)
#define ADC_SYNC_CLEAN_FIFOS_OFST (20)
#define ADC_SYNC_CLEAN_FIFOS_MSK (0x00000001 << ADC_SYNC_CLEAN_FIFOS_OFST)
#define ADC_SYNC_ENET_DELAY_OFST (24)
#define ADC_SYNC_ENET_DELAY_MSK (0x000000FF << ADC_SYNC_ENET_DELAY_OFST)
#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL ((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_ROI_VAL ((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_STRT_DLY_OFST (0)
#define ADC_SYNC_ENET_STRT_DLY_MSK (0x0000000F << ADC_SYNC_ENET_STRT_DLY_OFST)
#define ADC_SYNC_ENET_STRT_DLY_VAL \
((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
#define ADC_SYNC_TKN1_HGH_DLY_OFST (4)
#define ADC_SYNC_TKN1_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_HGH_DLY_OFST)
#define ADC_SYNC_TKN1_HGH_DLY_VAL \
((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
#define ADC_SYNC_TKN2_HGH_DLY_OFST (8)
#define ADC_SYNC_TKN2_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_HGH_DLY_OFST)
#define ADC_SYNC_TKN2_HGH_DLY_VAL \
((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
#define ADC_SYNC_TKN1_LOW_DLY_OFST (12)
#define ADC_SYNC_TKN1_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_LOW_DLY_OFST)
#define ADC_SYNC_TKN1_LOW_DLY_VAL \
((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
#define ADC_SYNC_TKN2_LOW_DLY_OFST (16)
#define ADC_SYNC_TKN2_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_LOW_DLY_OFST)
#define ADC_SYNC_TKN2_LOW_DLY_VAL \
((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
// 0x32214
#define ADC_SYNC_TKN_VAL \
(ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | \
ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL | \
ADC_SYNC_TKN2_LOW_DLY_VAL)
#define ADC_SYNC_CLEAN_FIFOS_OFST (20)
#define ADC_SYNC_CLEAN_FIFOS_MSK (0x00000001 << ADC_SYNC_CLEAN_FIFOS_OFST)
#define ADC_SYNC_ENET_DELAY_OFST (24)
#define ADC_SYNC_ENET_DELAY_MSK (0x000000FF << ADC_SYNC_ENET_DELAY_OFST)
#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL \
((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_ROI_VAL \
((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
/** Time From Start register */
//#define MU_TIME_REG (0x1a << MEM_MAP_SHIFT)
/** Temperatre SPI In register */
#define TEMP_SPI_IN_REG (0x1b << MEM_MAP_SHIFT)
#define TEMP_SPI_IN_REG (0x1b << MEM_MAP_SHIFT)
#define TEMP_SPI_IN_T1_CLK_OFST (0)
#define TEMP_SPI_IN_T1_CLK_MSK (0x00000001 << TEMP_SPI_IN_T1_CLK_OFST)
#define TEMP_SPI_IN_T1_CS_OFST (1)
#define TEMP_SPI_IN_T1_CS_MSK (0x00000001 << TEMP_SPI_IN_T1_CS_OFST)
#define TEMP_SPI_IN_T2_CLK_OFST (2)
#define TEMP_SPI_IN_T2_CLK_MSK (0x00000001 << TEMP_SPI_IN_T2_CLK_OFST)
#define TEMP_SPI_IN_T2_CS_OFST (3)
#define TEMP_SPI_IN_T2_CS_MSK (0x00000001 << TEMP_SPI_IN_T2_CS_OFST)
#define TEMP_SPI_IN_IDLE_MSK (TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CS_MSK | TEMP_SPI_IN_T1_CLK_MSK | TEMP_SPI_IN_T2_CLK_MSK)
#define TEMP_SPI_IN_T1_CLK_OFST (0)
#define TEMP_SPI_IN_T1_CLK_MSK (0x00000001 << TEMP_SPI_IN_T1_CLK_OFST)
#define TEMP_SPI_IN_T1_CS_OFST (1)
#define TEMP_SPI_IN_T1_CS_MSK (0x00000001 << TEMP_SPI_IN_T1_CS_OFST)
#define TEMP_SPI_IN_T2_CLK_OFST (2)
#define TEMP_SPI_IN_T2_CLK_MSK (0x00000001 << TEMP_SPI_IN_T2_CLK_OFST)
#define TEMP_SPI_IN_T2_CS_OFST (3)
#define TEMP_SPI_IN_T2_CS_MSK (0x00000001 << TEMP_SPI_IN_T2_CS_OFST)
#define TEMP_SPI_IN_IDLE_MSK \
(TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CS_MSK | TEMP_SPI_IN_T1_CLK_MSK | \
TEMP_SPI_IN_T2_CLK_MSK)
/** Temperatre SPI Out register */
#define TEMP_SPI_OUT_REG (0x1c << MEM_MAP_SHIFT)
#define TEMP_SPI_OUT_REG (0x1c << MEM_MAP_SHIFT)
#define TEMP_SPI_OUT_T1_DT_OFST (0)
#define TEMP_SPI_OUT_T1_DT_MSK (0x00000001 << TEMP_SPI_OUT_T1_DT_OFST)
#define TEMP_SPI_OUT_T2_DT_OFST (1)
#define TEMP_SPI_OUT_T2_DT_MSK (0x00000001 << TEMP_SPI_OUT_T2_DT_OFST)
#define TEMP_SPI_OUT_T1_DT_OFST (0)
#define TEMP_SPI_OUT_T1_DT_MSK (0x00000001 << TEMP_SPI_OUT_T1_DT_OFST)
#define TEMP_SPI_OUT_T2_DT_OFST (1)
#define TEMP_SPI_OUT_T2_DT_MSK (0x00000001 << TEMP_SPI_OUT_T2_DT_OFST)
/** TSE Configure register */
#define TSE_CONF_REG (0x1d << MEM_MAP_SHIFT)
#define TSE_CONF_REG (0x1d << MEM_MAP_SHIFT)
/** SPI Configure register */
#define ENET_CONF_REG (0x1e << MEM_MAP_SHIFT)
#define ENET_CONF_REG (0x1e << MEM_MAP_SHIFT)
/** Write TSE Shadow register */
//#define WRITE_TSE_SHADOW_REG (0x1f << MEM_MAP_SHIFT)
/** High Voltage register */
#define HV_REG (0x20 << MEM_MAP_SHIFT)
#define HV_REG (0x20 << MEM_MAP_SHIFT)
#define HV_ENBL_OFST (0)
#define HV_ENBL_MSK (0x00000001 << HV_ENBL_OFST)
#define HV_SEL_OFST (1)
#define HV_SEL_MSK (0x00000007 << HV_SEL_OFST)
#define HV_SEL_90_VAL ((0x0 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_110_VAL ((0x1 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_120_VAL ((0x2 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_150_VAL ((0x3 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_180_VAL ((0x4 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_200_VAL ((0x5 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_ENBL_OFST (0)
#define HV_ENBL_MSK (0x00000001 << HV_ENBL_OFST)
#define HV_SEL_OFST (1)
#define HV_SEL_MSK (0x00000007 << HV_SEL_OFST)
#define HV_SEL_90_VAL ((0x0 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_110_VAL ((0x1 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_120_VAL ((0x2 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_150_VAL ((0x3 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_180_VAL ((0x4 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_200_VAL ((0x5 << HV_SEL_OFST) & HV_SEL_MSK)
/** Dummy register */
#define DUMMY_REG (0x21 << MEM_MAP_SHIFT)
#define DUMMY_REG (0x21 << MEM_MAP_SHIFT)
/** Firmware Version register */
#define FPGA_VERSION_REG (0x22 << MEM_MAP_SHIFT)
#define FPGA_VERSION_REG (0x22 << MEM_MAP_SHIFT)
#define FPGA_VERSION_OFST (0)
#define FPGA_VERSION_MSK (0x00FFFFFF << FPGA_VERSION_OFST) // to get in format yymmdd
#define FPGA_VERSION_OFST (0)
#define FPGA_VERSION_MSK \
(0x00FFFFFF << FPGA_VERSION_OFST) // to get in format yymmdd
/* Fix Pattern register */
#define FIX_PATT_REG (0x23 << MEM_MAP_SHIFT)
#define FIX_PATT_REG (0x23 << MEM_MAP_SHIFT)
#define FIX_PATT_VAL (0xACDC1980)
#define FIX_PATT_VAL (0xACDC1980)
/** 16 bit Control register */
#define CONTROL_REG (0x24 << MEM_MAP_SHIFT)
#define CONTROL_REG (0x24 << MEM_MAP_SHIFT)
#define CONTROL_STRT_ACQ_OFST (0)
#define CONTROL_STRT_ACQ_MSK (0x00000001 << CONTROL_STRT_ACQ_OFST)
#define CONTROL_STP_ACQ_OFST (1)
#define CONTROL_STP_ACQ_MSK (0x00000001 << CONTROL_STP_ACQ_OFST)
#define CONTROL_STRT_FF_TST_OFST (2) // Not used in FW & SW
#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
#define CONTROL_STP_FF_TST_OFST (3) // Not used in FW & SW
#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
#define CONTROL_STRT_RDT_OFST (4)
#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
#define CONTROL_STP_RDT_OFST (5)
#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
#define CONTROL_STP_EXPSR_OFST (7)
#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_EXPSR_OFST)
#define CONTROL_STRT_TRN_OFST (8)
#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_TRN_OFST)
#define CONTROL_STP_TRN_OFST (9)
#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_TRN_OFST)
#define CONTROL_SYNC_RST_OFST (10)
#define CONTROL_SYNC_RST_MSK (0x00000001 << CONTROL_SYNC_RST_OFST)
#define CONTROL_STRT_ACQ_OFST (0)
#define CONTROL_STRT_ACQ_MSK (0x00000001 << CONTROL_STRT_ACQ_OFST)
#define CONTROL_STP_ACQ_OFST (1)
#define CONTROL_STP_ACQ_MSK (0x00000001 << CONTROL_STP_ACQ_OFST)
#define CONTROL_STRT_FF_TST_OFST (2) // Not used in FW & SW
#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
#define CONTROL_STP_FF_TST_OFST (3) // Not used in FW & SW
#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
#define CONTROL_STRT_RDT_OFST (4)
#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
#define CONTROL_STP_RDT_OFST (5)
#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
#define CONTROL_STP_EXPSR_OFST (7)
#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_EXPSR_OFST)
#define CONTROL_STRT_TRN_OFST (8)
#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_TRN_OFST)
#define CONTROL_STP_TRN_OFST (9)
#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_TRN_OFST)
#define CONTROL_SYNC_RST_OFST (10)
#define CONTROL_SYNC_RST_MSK (0x00000001 << CONTROL_SYNC_RST_OFST)
/** Status register */
#define STATUS_REG (0x25 << MEM_MAP_SHIFT)
#define STATUS_REG (0x25 << MEM_MAP_SHIFT)
#define STATUS_RN_BSY_OFST (0)
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4)
#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
#define STATUS_DLY_AFTR_OFST (5)
#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
#define STATUS_EXPSNG_OFST (6)
#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
#define STATUS_CNT_ENBL_OFST (7)
#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
#define STATUS_RD_STT_OFST (8)
#define STATUS_RD_STT_MSK (0x00000007 << STATUS_RD_STT_OFST)
#define STATUS_RN_STT_OFST (12)
#define STATUS_RN_STT_MSK (0x00000007 << STATUS_RN_STT_OFST)
#define STATUS_SM_FF_FLL_OFST (15)
#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
#define STATUS_ALL_FF_EMPTY_OFST (11)
#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
#define STATUS_RN_MSHN_BSY_OFST (17)
#define STATUS_RN_MSHN_BSY_MSK (0x00000001 << STATUS_RN_MSHN_BSY_OFST)
#define STATUS_RD_MSHN_BSY_OFST (18)
#define STATUS_RD_MSHN_BSY_MSK (0x00000001 << STATUS_RD_MSHN_BSY_OFST)
#define STATUS_RN_FNSHD_OFST (20)
#define STATUS_RN_FNSHD_MSK (0x00000001 << STATUS_RN_FNSHD_OFST)
#define STATUS_IDLE_MSK (0x0000FFFF << 0)
#define STATUS_RN_BSY_OFST (0)
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4)
#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
#define STATUS_DLY_AFTR_OFST (5)
#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
#define STATUS_EXPSNG_OFST (6)
#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
#define STATUS_CNT_ENBL_OFST (7)
#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
#define STATUS_RD_STT_OFST (8)
#define STATUS_RD_STT_MSK (0x00000007 << STATUS_RD_STT_OFST)
#define STATUS_RN_STT_OFST (12)
#define STATUS_RN_STT_MSK (0x00000007 << STATUS_RN_STT_OFST)
#define STATUS_SM_FF_FLL_OFST (15)
#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
#define STATUS_ALL_FF_EMPTY_OFST (11)
#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
#define STATUS_RN_MSHN_BSY_OFST (17)
#define STATUS_RN_MSHN_BSY_MSK (0x00000001 << STATUS_RN_MSHN_BSY_OFST)
#define STATUS_RD_MSHN_BSY_OFST (18)
#define STATUS_RD_MSHN_BSY_MSK (0x00000001 << STATUS_RD_MSHN_BSY_OFST)
#define STATUS_RN_FNSHD_OFST (20)
#define STATUS_RN_FNSHD_MSK (0x00000001 << STATUS_RN_FNSHD_OFST)
#define STATUS_IDLE_MSK (0x0000FFFF << 0)
/** Config register */
#define CONFIG_REG (0x26 << MEM_MAP_SHIFT)
#define CONFIG_REG (0x26 << MEM_MAP_SHIFT)
#define CONFIG_SLAVE_OFST (0) // Not used in FW & SW
#define CONFIG_SLAVE_MSK (0x00000001 << CONFIG_SLAVE_OFST)
#define CONFIG_MASTER_OFST (1) // Not used in FW & SW
#define CONFIG_MASTER_MSK (0x00000001 << CONFIG_MASTER_OFST)
#define CONFIG_TM_GT_ENBL_OFST (2) // Not used in FW & SW
#define CONFIG_TM_GT_ENBL_MSK (0x00000001 << CONFIG_TM_GT_ENBL_OFST)
#define CONFIG_CPU_RDT_OFST (12)
#define CONFIG_CPU_RDT_MSK (0x00000001 << CONFIG_CPU_RDT_OFST)
#define CONFIG_CNTNS_RDT_OFST (23) // Not used in FW & SW
#define CONFIG_CNTNS_RDT_MSK (0x00000001 << CONFIG_CNTNS_RDT_OFST)
#define CONFIG_ACCMLT_CNTS_OFST (24) // Not used in FW & SW
#define CONFIG_ACCMLT_CNTS_MSK (0x00000001 << CONFIG_ACCMLT_CNTS_OFST)
#define CONFIG_SLAVE_OFST (0) // Not used in FW & SW
#define CONFIG_SLAVE_MSK (0x00000001 << CONFIG_SLAVE_OFST)
#define CONFIG_MASTER_OFST (1) // Not used in FW & SW
#define CONFIG_MASTER_MSK (0x00000001 << CONFIG_MASTER_OFST)
#define CONFIG_TM_GT_ENBL_OFST (2) // Not used in FW & SW
#define CONFIG_TM_GT_ENBL_MSK (0x00000001 << CONFIG_TM_GT_ENBL_OFST)
#define CONFIG_CPU_RDT_OFST (12)
#define CONFIG_CPU_RDT_MSK (0x00000001 << CONFIG_CPU_RDT_OFST)
#define CONFIG_CNTNS_RDT_OFST (23) // Not used in FW & SW
#define CONFIG_CNTNS_RDT_MSK (0x00000001 << CONFIG_CNTNS_RDT_OFST)
#define CONFIG_ACCMLT_CNTS_OFST (24) // Not used in FW & SW
#define CONFIG_ACCMLT_CNTS_MSK (0x00000001 << CONFIG_ACCMLT_CNTS_OFST)
/** External Signal register */
#define EXT_SIGNAL_REG (0x27 << MEM_MAP_SHIFT)
#define EXT_SIGNAL_REG (0x27 << MEM_MAP_SHIFT)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000007 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_OFF_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_RSNG_VAL ((0x3 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL ((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000007 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_OFF_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_RSNG_VAL ((0x3 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL \
((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/** Look at me register */
//#define LOOK_AT_ME_REG (0x28 << MEM_MAP_SHIFT)
@ -269,25 +292,26 @@
//#define FPGA_SVN_REG (0x29 << MEM_MAP_SHIFT)
/** Chip of Interest register */
#define CHIP_OF_INTRST_REG (0x2a << MEM_MAP_SHIFT)
#define CHIP_OF_INTRST_REG (0x2a << MEM_MAP_SHIFT)
#define CHIP_OF_INTRST_ADC_SEL_OFST (0)
#define CHIP_OF_INTRST_ADC_SEL_MSK (0x0000001F << CHIP_OF_INTRST_ADC_SEL_OFST)
#define CHIP_OF_INTRST_NUM_CHNNLS_OFST (16)
#define CHIP_OF_INTRST_NUM_CHNNLS_MSK (0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
#define CHIP_OF_INTRST_ADC_SEL_OFST (0)
#define CHIP_OF_INTRST_ADC_SEL_MSK (0x0000001F << CHIP_OF_INTRST_ADC_SEL_OFST)
#define CHIP_OF_INTRST_NUM_CHNNLS_OFST (16)
#define CHIP_OF_INTRST_NUM_CHNNLS_MSK \
(0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
/** Out MUX register */
//#define OUT_MUX_REG (0x2b << MEM_MAP_SHIFT)
/** Board Version register */
#define BOARD_REVISION_REG (0x2c << MEM_MAP_SHIFT)
#define BOARD_REVISION_REG (0x2c << MEM_MAP_SHIFT)
#define BOARD_REVISION_OFST (0)
#define BOARD_REVISION_MSK (0x0000FFFF << BOARD_REVISION_OFST)
#define DETECTOR_TYPE_OFST (16)
#define DETECTOR_TYPE_MSK (0x0000000F << DETECTOR_TYPE_OFST)
#define BOARD_REVISION_OFST (0)
#define BOARD_REVISION_MSK (0x0000FFFF << BOARD_REVISION_OFST)
#define DETECTOR_TYPE_OFST (16)
#define DETECTOR_TYPE_MSK (0x0000000F << DETECTOR_TYPE_OFST)
//#define DETECTOR_TYPE_GOTTHARD_VAL (??)
#define DETECTOR_TYPE_MOENCH_VAL (2)
#define DETECTOR_TYPE_MOENCH_VAL (2)
/** Memory Test register */
//#define MEMORY_TEST_REG (0x2d << MEM_MAP_SHIFT)
@ -299,7 +323,7 @@
//#define HIT_COUNT_REG (0x2f << MEM_MAP_SHIFT)
/* 16 bit Fifo Data register */
#define FIFO_DATA_REG (0x50 << MEM_MAP_SHIFT) // Not used in FW and SW (16bit)
#define FIFO_DATA_REG (0x50 << MEM_MAP_SHIFT) // Not used in FW and SW (16bit)
/** Dacs Set 1 register */
//#define DACS_SET_1_REG (0x65 << MEM_MAP_SHIFT)
@ -311,44 +335,44 @@
//#define DACS_SET_3_REG (0x67 << MEM_MAP_SHIFT)
/* Set Delay 64 bit register */
#define SET_DELAY_LSB_REG (0x68 << MEM_MAP_SHIFT)
#define SET_DELAY_MSB_REG (0x69 << MEM_MAP_SHIFT)
#define SET_DELAY_LSB_REG (0x68 << MEM_MAP_SHIFT)
#define SET_DELAY_MSB_REG (0x69 << MEM_MAP_SHIFT)
/* Get Delay 64 bit register */
#define GET_DELAY_LSB_REG (0x6a << MEM_MAP_SHIFT)
#define GET_DELAY_MSB_REG (0x6b << MEM_MAP_SHIFT)
#define GET_DELAY_LSB_REG (0x6a << MEM_MAP_SHIFT)
#define GET_DELAY_MSB_REG (0x6b << MEM_MAP_SHIFT)
/* Set Triggers 64 bit register */
#define SET_TRAINS_LSB_REG (0x6c << MEM_MAP_SHIFT)
#define SET_TRAINS_MSB_REG (0x6d << MEM_MAP_SHIFT)
#define SET_TRAINS_LSB_REG (0x6c << MEM_MAP_SHIFT)
#define SET_TRAINS_MSB_REG (0x6d << MEM_MAP_SHIFT)
/* Get Triggers 64 bit register */
#define GET_TRAINS_LSB_REG (0x6e << MEM_MAP_SHIFT)
#define GET_TRAINS_MSB_REG (0x6f << MEM_MAP_SHIFT)
#define GET_TRAINS_LSB_REG (0x6e << MEM_MAP_SHIFT)
#define GET_TRAINS_MSB_REG (0x6f << MEM_MAP_SHIFT)
/* Set Frames 64 bit register */
#define SET_FRAMES_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define SET_FRAMES_MSB_REG (0x71 << MEM_MAP_SHIFT)
#define SET_FRAMES_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define SET_FRAMES_MSB_REG (0x71 << MEM_MAP_SHIFT)
/* Get Frames 64 bit register */
#define GET_FRAMES_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define GET_FRAMES_MSB_REG (0x73 << MEM_MAP_SHIFT)
#define GET_FRAMES_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define GET_FRAMES_MSB_REG (0x73 << MEM_MAP_SHIFT)
/* Set Period 64 bit register */
#define SET_PERIOD_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define SET_PERIOD_MSB_REG (0x75 << MEM_MAP_SHIFT)
#define SET_PERIOD_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define SET_PERIOD_MSB_REG (0x75 << MEM_MAP_SHIFT)
/* Get Period 64 bit register */
#define GET_PERIOD_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define GET_PERIOD_MSB_REG (0x77 << MEM_MAP_SHIFT)
#define GET_PERIOD_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define GET_PERIOD_MSB_REG (0x77 << MEM_MAP_SHIFT)
/* Set Exptime 64 bit register */
#define SET_EXPTIME_LSB_REG (0x78 << MEM_MAP_SHIFT)
#define SET_EXPTIME_MSB_REG (0x79 << MEM_MAP_SHIFT)
#define SET_EXPTIME_LSB_REG (0x78 << MEM_MAP_SHIFT)
#define SET_EXPTIME_MSB_REG (0x79 << MEM_MAP_SHIFT)
/* Get Exptime 64 bit register */
#define GET_EXPTIME_LSB_REG (0x7a << MEM_MAP_SHIFT)
#define GET_EXPTIME_MSB_REG (0x7b << MEM_MAP_SHIFT)
#define GET_EXPTIME_LSB_REG (0x7a << MEM_MAP_SHIFT)
#define GET_EXPTIME_MSB_REG (0x7b << MEM_MAP_SHIFT)
/* Set Gates 64 bit register */
//#define SET_GATES_LSB_REG (0x7c << MEM_MAP_SHIFT)
@ -359,11 +383,10 @@
//#define GET_GATES_MSB_REG (0x7f << MEM_MAP_SHIFT)
/* Dark Image starting address */
#define DARK_IMAGE_REG (0x81 << MEM_MAP_SHIFT)
#define DARK_IMAGE_REG (0x81 << MEM_MAP_SHIFT)
/* Gain Image starting address */
#define GAIN_IMAGE_REG (0x82 << MEM_MAP_SHIFT)
#define GAIN_IMAGE_REG (0x82 << MEM_MAP_SHIFT)
/* Counter Block Memory starting address */
#define COUNTER_MEMORY_REG (0x85 << MEM_MAP_SHIFT)
#define COUNTER_MEMORY_REG (0x85 << MEM_MAP_SHIFT)

211
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
View File

@ -3,125 +3,136 @@
#include <stdlib.h>
/* Enums */
enum ADCINDEX {TEMP_FPGA, TEMP_ADC};
enum DACINDEX {G_VREF_DS, G_VCASCN_PB, G_VCASCP_PB, G_VOUT_CM, G_VCASC_OUT, G_VIN_CM, G_VREF_COMP, G_IB_TESTC};
enum CLKINDEX {ADC_CLK, NUM_CLOCKS};
#define CLK_NAMES "adc"
enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
enum DACINDEX {
G_VREF_DS,
G_VCASCN_PB,
G_VCASCP_PB,
G_VOUT_CM,
G_VCASC_OUT,
G_VIN_CM,
G_VREF_COMP,
G_IB_TESTC
};
enum CLKINDEX { ADC_CLK, NUM_CLOCKS };
#define CLK_NAMES "adc"
#define DEFAULT_DAC_VALS { \
660, /* G_VREF_DS */ \
650, /* G_VCASCN_PB */ \
1480, /* G_VCASCP_PB */ \
1520, /* G_VOUT_CM */ \
1320, /* G_VCASC_OUT */ \
1350, /* G_VIN_CM */ \
350, /* G_VREF_COMP */ \
2001 /* G_IB_TESTC */ \
};
#define DEFAULT_DAC_VALS \
{ \
660, /* G_VREF_DS */ \
650, /* G_VCASCN_PB */ \
1480, /* G_VCASCP_PB */ \
1520, /* G_VOUT_CM */ \
1320, /* G_VCASC_OUT */ \
1350, /* G_VIN_CM */ \
350, /* G_VREF_COMP */ \
2001 /* G_IB_TESTC */ \
};
/* for 25 um */
#define CONFIG_FILE "config.txt"
#define CONFIG_FILE "config.txt"
/* Hardware Definitions */
#define NCHAN (128)
#define NCHIP (10)
#define NDAC (8)
#define NCHIPS_PER_ADC (2)
#define NCHAN_PER_ADC (256)
#define DYNAMIC_RANGE (16)
#define NUM_BITS_PER_PIXEL (DYNAMIC_RANGE / 8)
#define DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define CLK_FREQ (32007729) /* Hz */
#define NCHAN (128)
#define NCHIP (10)
#define NDAC (8)
#define NCHIPS_PER_ADC (2)
#define NCHAN_PER_ADC (256)
#define DYNAMIC_RANGE (16)
#define NUM_BITS_PER_PIXEL (DYNAMIC_RANGE / 8)
#define DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define CLK_FREQ (32007729) /* Hz */
/** Firmware Definitions */
#define IP_PACKET_SIZE_NO_ROI (NCHIP * (NCHAN / 2) * 2 + 14 + 20) // 2 packets, so divide by 2
#define IP_PACKET_SIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20)
#define IP_PACKET_SIZE_NO_ROI \
(NCHIP * (NCHAN / 2) * 2 + 14 + 20) // 2 packets, so divide by 2
#define IP_PACKET_SIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20)
#define UDP_PACKETSIZE_NO_ROI (NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2) // 2 packets, so divide by 2
#define UDP_PACKETSIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2)
#define UDP_PACKETSIZE_NO_ROI \
(NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2) // 2 packets, so divide by 2
#define UDP_PACKETSIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2)
/** Default Parameters */
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (1 * 1000 * 1000) // 1 ms
#define DEFAULT_PERIOD (1 * 1000 * 1000 * 1000) // 1 s
#define DEFAULT_DELAY (0)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TRIGGER_MODE (TRIGGER_IN_RISING_EDGE)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_PHASE_SHIFT (120)
#define DEFAULT_TX_UDP_PORT (0xE185)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (1 * 1000 * 1000) // 1 ms
#define DEFAULT_PERIOD (1 * 1000 * 1000 * 1000) // 1 s
#define DEFAULT_DELAY (0)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TRIGGER_MODE (TRIGGER_IN_RISING_EDGE)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_PHASE_SHIFT (120)
#define DEFAULT_TX_UDP_PORT (0xE185)
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
/** ENEt conf structs */
typedef struct mac_header_struct{
u_int8_t mac_dest_mac2;
u_int8_t mac_dest_mac1;
u_int8_t mac_dummy1;
u_int8_t mac_dummy2;
u_int8_t mac_dest_mac6;
u_int8_t mac_dest_mac5;
u_int8_t mac_dest_mac4;
u_int8_t mac_dest_mac3;
u_int8_t mac_src_mac4;
u_int8_t mac_src_mac3;
u_int8_t mac_src_mac2;
u_int8_t mac_src_mac1;
u_int16_t mac_ether_type;
u_int8_t mac_src_mac6;
u_int8_t mac_src_mac5;
typedef struct mac_header_struct {
u_int8_t mac_dest_mac2;
u_int8_t mac_dest_mac1;
u_int8_t mac_dummy1;
u_int8_t mac_dummy2;
u_int8_t mac_dest_mac6;
u_int8_t mac_dest_mac5;
u_int8_t mac_dest_mac4;
u_int8_t mac_dest_mac3;
u_int8_t mac_src_mac4;
u_int8_t mac_src_mac3;
u_int8_t mac_src_mac2;
u_int8_t mac_src_mac1;
u_int16_t mac_ether_type;
u_int8_t mac_src_mac6;
u_int8_t mac_src_mac5;
} mac_header;
typedef struct ip_header_struct {
u_int16_t ip_len;
u_int8_t ip_tos;
u_int8_t ip_ihl:4 ,ip_ver:4;
u_int16_t ip_offset:13,ip_flag:3;
u_int16_t ip_ident;
u_int16_t ip_chksum;
u_int8_t ip_protocol;
u_int8_t ip_ttl;
u_int32_t ip_sourceip;
u_int32_t ip_destip;
u_int16_t ip_len;
u_int8_t ip_tos;
u_int8_t ip_ihl : 4, ip_ver : 4;
u_int16_t ip_offset : 13, ip_flag : 3;
u_int16_t ip_ident;
u_int16_t ip_chksum;
u_int8_t ip_protocol;
u_int8_t ip_ttl;
u_int32_t ip_sourceip;
u_int32_t ip_destip;
} ip_header;
typedef struct udp_header_struct{
u_int16_t udp_destport;
u_int16_t udp_srcport;
u_int16_t udp_chksum;
u_int16_t udp_len;
typedef struct udp_header_struct {
u_int16_t udp_destport;
u_int16_t udp_srcport;
u_int16_t udp_chksum;
u_int16_t udp_len;
} udp_header;
typedef struct mac_conf_struct{
mac_header mac;
ip_header ip;
udp_header udp;
u_int32_t npack;
u_int32_t lpack;
u_int32_t npad;
u_int32_t cdone;
typedef struct mac_conf_struct {
mac_header mac;
ip_header ip;
udp_header udp;
u_int32_t npack;
u_int32_t lpack;
u_int32_t npad;
u_int32_t cdone;
} mac_conf;
typedef struct tse_conf_struct{
u_int32_t rev; //0x0
u_int32_t scratch;
u_int32_t command_config;
u_int32_t mac_0; //0x3
u_int32_t mac_1;
u_int32_t frm_length;
u_int32_t pause_quant;
u_int32_t rx_section_empty; //0x7
u_int32_t rx_section_full;
u_int32_t tx_section_empty;
u_int32_t tx_section_full;
u_int32_t rx_almost_empty; //0xB
u_int32_t rx_almost_full;
u_int32_t tx_almost_empty;
u_int32_t tx_almost_full;
u_int32_t mdio_addr0; //0xF
u_int32_t mdio_addr1;
}tse_conf;
typedef struct tse_conf_struct {
u_int32_t rev; // 0x0
u_int32_t scratch;
u_int32_t command_config;
u_int32_t mac_0; // 0x3
u_int32_t mac_1;
u_int32_t frm_length;
u_int32_t pause_quant;
u_int32_t rx_section_empty; // 0x7
u_int32_t rx_section_full;
u_int32_t tx_section_empty;
u_int32_t tx_section_full;
u_int32_t rx_almost_empty; // 0xB
u_int32_t rx_almost_full;
u_int32_t tx_almost_empty;
u_int32_t tx_almost_full;
u_int32_t mdio_addr0; // 0xF
u_int32_t mdio_addr1;
} tse_conf;

668
slsDetectorServers/jungfrauDetectorServer/RegisterDefs.h Executable file → Normal file
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@ -4,441 +4,495 @@
#define MEM_MAP_SHIFT 1
/* FPGA Version register */
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
#define FPGA_COMPILATION_DATE_OFST (0)
#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
#define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
#define FPGA_COMPILATION_DATE_OFST (0)
#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
#define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
/* Fix pattern register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
#define FIX_PATT_VAL (0xACDC2014)
#define FIX_PATT_VAL (0xACDC2014)
/* Status register */
#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
#define RUN_BUSY_OFST (0)
#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
#define WAITING_FOR_TRIGGER_OFST (3)
#define WAITING_FOR_TRIGGER_MSK (0x00000001 << WAITING_FOR_TRIGGER_OFST)
#define DELAYBEFORE_OFST (4) //Not used in software
#define DELAYBEFORE_MSK (0x00000001 << DELAYBEFORE_OFST) //Not used in software
#define DELAYAFTER_OFST (5) //Not used in software
#define DELAYAFTER_MSK (0x00000001 << DELAYAFTER_OFST) //Not used in software
#define STOPPED_OFST (15)
#define STOPPED_MSK (0x00000001 << STOPPED_OFST)
#define RUNMACHINE_BUSY_OFST (17)
#define RUNMACHINE_BUSY_MSK (0x00000001 << RUNMACHINE_BUSY_OFST)
#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
#define RUN_BUSY_OFST (0)
#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
#define WAITING_FOR_TRIGGER_OFST (3)
#define WAITING_FOR_TRIGGER_MSK (0x00000001 << WAITING_FOR_TRIGGER_OFST)
#define DELAYBEFORE_OFST (4) // Not used in software
#define DELAYBEFORE_MSK (0x00000001 << DELAYBEFORE_OFST) // Not used in software
#define DELAYAFTER_OFST (5) // Not used in software
#define DELAYAFTER_MSK (0x00000001 << DELAYAFTER_OFST) // Not used in software
#define STOPPED_OFST (15)
#define STOPPED_MSK (0x00000001 << STOPPED_OFST)
#define RUNMACHINE_BUSY_OFST (17)
#define RUNMACHINE_BUSY_MSK (0x00000001 << RUNMACHINE_BUSY_OFST)
/* Look at me register */
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT) //Not used in firmware or software
#define LOOK_AT_ME_REG \
(0x03 << MEM_MAP_SHIFT) // Not used in firmware or software
/* System Status register */
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT) //Not used in software
#define DDR3_CAL_DONE_OFST (0) //Not used in software
#define DDR3_CAL_DONE_MSK (0x00000001 << DDR3_CAL_DONE_OFST) //Not used in software
#define DDR3_CAL_FAIL_OFST (1) //Not used in software
#define DDR3_CAL_FAIL_MSK (0x00000001 << DDR3_CAL_FAIL_OFST) //Not used in software
#define DDR3_INIT_DONE_OFST (2) //Not used in software
#define DDR3_INIT_DONE_MSK (0x00000001 << DDR3_INIT_DONE_OFST) //Not used in software
#define RECONFIG_PLL_LCK_OFST (3) //Not used in software
#define RECONFIG_PLL_LCK_MSK (0x00000001 << RECONFIG_PLL_LCK_OFST) //Not used in software
#define PLL_A_LCK_OFST (4) //Not used in software
#define PLL_A_LCK_MSK (0x00000001 << PLL_A_LCK_OFST) //Not used in software
#define DD3_PLL_LCK_OFST (5) //Not used in software
#define DD3_PLL_LCK_MSK (0x00000001 << DD3_PLL_LCK_OFST) //Not used in software
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT) // Not used in software
#define DDR3_CAL_DONE_OFST (0) // Not used in software
#define DDR3_CAL_DONE_MSK \
(0x00000001 << DDR3_CAL_DONE_OFST) // Not used in software
#define DDR3_CAL_FAIL_OFST (1) // Not used in software
#define DDR3_CAL_FAIL_MSK \
(0x00000001 << DDR3_CAL_FAIL_OFST) // Not used in software
#define DDR3_INIT_DONE_OFST (2) // Not used in software
#define DDR3_INIT_DONE_MSK \
(0x00000001 << DDR3_INIT_DONE_OFST) // Not used in software
#define RECONFIG_PLL_LCK_OFST (3) // Not used in software
#define RECONFIG_PLL_LCK_MSK \
(0x00000001 << RECONFIG_PLL_LCK_OFST) // Not used in software
#define PLL_A_LCK_OFST (4) // Not used in software
#define PLL_A_LCK_MSK (0x00000001 << PLL_A_LCK_OFST) // Not used in software
#define DD3_PLL_LCK_OFST (5) // Not used in software
#define DD3_PLL_LCK_MSK (0x00000001 << DD3_PLL_LCK_OFST) // Not used in software
/* Module Control Board Serial Number Register */
#define MOD_SERIAL_NUM_REG (0x0A << MEM_MAP_SHIFT)
#define HARDWARE_SERIAL_NUM_OFST (0)
#define HARDWARE_SERIAL_NUM_MSK (0x000000FF << HARDWARE_SERIAL_NUM_OFST)
#define HARDWARE_VERSION_NUM_OFST (16)
#define HARDWARE_VERSION_NUM_MSK (0x0000003F << HARDWARE_VERSION_NUM_OFST)
#define HARDWARE_VERSION_2_VAL ((0x2 << HARDWARE_VERSION_NUM_OFST) & HARDWARE_VERSION_NUM_MSK)
#define MOD_SERIAL_NUM_REG (0x0A << MEM_MAP_SHIFT)
#define HARDWARE_SERIAL_NUM_OFST (0)
#define HARDWARE_SERIAL_NUM_MSK (0x000000FF << HARDWARE_SERIAL_NUM_OFST)
#define HARDWARE_VERSION_NUM_OFST (16)
#define HARDWARE_VERSION_NUM_MSK (0x0000003F << HARDWARE_VERSION_NUM_OFST)
#define HARDWARE_VERSION_2_VAL \
((0x2 << HARDWARE_VERSION_NUM_OFST) & HARDWARE_VERSION_NUM_MSK)
/* API Version Register */
#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK \
(0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
/* Time from Start 64 bit register */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
/* Get Delay 64 bit register */
#define GET_DELAY_LSB_REG (0x12 << MEM_MAP_SHIFT) // different kind of delay
#define GET_DELAY_MSB_REG (0x13 << MEM_MAP_SHIFT) // different kind of delay
#define GET_DELAY_LSB_REG (0x12 << MEM_MAP_SHIFT) // different kind of delay
#define GET_DELAY_MSB_REG (0x13 << MEM_MAP_SHIFT) // different kind of delay
/* Get Triggers 64 bit register */
#define GET_CYCLES_LSB_REG (0x14 << MEM_MAP_SHIFT)
#define GET_CYCLES_MSB_REG (0x15 << MEM_MAP_SHIFT)
#define GET_CYCLES_LSB_REG (0x14 << MEM_MAP_SHIFT)
#define GET_CYCLES_MSB_REG (0x15 << MEM_MAP_SHIFT)
/* Get Frames 64 bit register */
#define GET_FRAMES_LSB_REG (0x16 << MEM_MAP_SHIFT)
#define GET_FRAMES_MSB_REG (0x17 << MEM_MAP_SHIFT)
#define GET_FRAMES_LSB_REG (0x16 << MEM_MAP_SHIFT)
#define GET_FRAMES_MSB_REG (0x17 << MEM_MAP_SHIFT)
/* Get Period 64 bit register tT = T x 50 ns */
#define GET_PERIOD_LSB_REG (0x18 << MEM_MAP_SHIFT)
#define GET_PERIOD_MSB_REG (0x19 << MEM_MAP_SHIFT)
#define GET_PERIOD_LSB_REG (0x18 << MEM_MAP_SHIFT)
#define GET_PERIOD_MSB_REG (0x19 << MEM_MAP_SHIFT)
/** Get Temperature Carlos, incorrectl as get gates */
#define GET_TEMPERATURE_TMP112_REG (0x1c << MEM_MAP_SHIFT) // (after multiplying by 625) in 10ths of millidegrees of TMP112
#define GET_TEMPERATURE_TMP112_REG \
(0x1c << MEM_MAP_SHIFT) // (after multiplying by 625) in 10ths of
// millidegrees of TMP112
#define TEMPERATURE_VALUE_BIT (0)
#define TEMPERATURE_VALUE_MSK (0x000007FF << TEMPERATURE_VALUE_BIT)
#define TEMPERATURE_POLARITY_BIT (11)
#define TEMPERATURE_POLARITY_MSK (0x00000001 << TEMPERATURE_POLARITY_BIT)
#define TEMPERATURE_VALUE_BIT (0)
#define TEMPERATURE_VALUE_MSK (0x000007FF << TEMPERATURE_VALUE_BIT)
#define TEMPERATURE_POLARITY_BIT (11)
#define TEMPERATURE_POLARITY_MSK (0x00000001 << TEMPERATURE_POLARITY_BIT)
/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT)
/* Get Frames from Start 64 bit register (frames from last reset using
* CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT)
/* Get Starting Frame Number */
#define GET_FRAME_NUMBER_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define GET_FRAME_NUMBER_MSB_REG (0x25 << MEM_MAP_SHIFT)
#define GET_FRAME_NUMBER_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define GET_FRAME_NUMBER_MSB_REG (0x25 << MEM_MAP_SHIFT)
/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
/* SPI (Serial Peripheral Interface) Register */
#define SPI_REG (0x40 << MEM_MAP_SHIFT)
#define SPI_REG (0x40 << MEM_MAP_SHIFT)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_CS_OTPT_OFST (2)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_HV_SRL_DGTL_OTPT_OFST (8)
#define SPI_HV_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
#define SPI_HV_SRL_CLK_OTPT_OFST (9)
#define SPI_HV_SRL_CLK_OTPT_MSK (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
#define SPI_HV_SRL_CS_OTPT_OFST (10)
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_CS_OTPT_OFST (2)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_HV_SRL_DGTL_OTPT_OFST (8)
#define SPI_HV_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
#define SPI_HV_SRL_CLK_OTPT_OFST (9)
#define SPI_HV_SRL_CLK_OTPT_MSK (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
#define SPI_HV_SRL_CS_OTPT_OFST (10)
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
/* ADC SPI (Serial Peripheral Interface) Register */
#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
/* ADC offset Register */
#define ADC_OFST_REG (0x42 << MEM_MAP_SHIFT)
#define ADC_OFST_REG (0x42 << MEM_MAP_SHIFT)
/* ADC Port Invert Register */
#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_ADC_0_OFST (0)
#define ADC_PORT_INVERT_ADC_0_MSK (0x000000FF << ADC_PORT_INVERT_ADC_0_OFST)
#define ADC_PORT_INVERT_ADC_1_OFST (8)
#define ADC_PORT_INVERT_ADC_1_MSK (0x000000FF << ADC_PORT_INVERT_ADC_1_OFST)
#define ADC_PORT_INVERT_ADC_2_OFST (16)
#define ADC_PORT_INVERT_ADC_2_MSK (0x000000FF << ADC_PORT_INVERT_ADC_2_OFST)
#define ADC_PORT_INVERT_ADC_3_OFST (24)
#define ADC_PORT_INVERT_ADC_3_MSK (0x000000FF << ADC_PORT_INVERT_ADC_3_OFST)
#define ADC_PORT_INVERT_ADC_0_OFST (0)
#define ADC_PORT_INVERT_ADC_0_MSK (0x000000FF << ADC_PORT_INVERT_ADC_0_OFST)
#define ADC_PORT_INVERT_ADC_1_OFST (8)
#define ADC_PORT_INVERT_ADC_1_MSK (0x000000FF << ADC_PORT_INVERT_ADC_1_OFST)
#define ADC_PORT_INVERT_ADC_2_OFST (16)
#define ADC_PORT_INVERT_ADC_2_MSK (0x000000FF << ADC_PORT_INVERT_ADC_2_OFST)
#define ADC_PORT_INVERT_ADC_3_OFST (24)
#define ADC_PORT_INVERT_ADC_3_MSK (0x000000FF << ADC_PORT_INVERT_ADC_3_OFST)
/* Configuration Register */
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
// readout timer (from chip) to stabilize (esp in burst acquisition mode) tRDT = (RDT + 1) * 25ns
// readout timer (from chip) to stabilize (esp in burst acquisition mode) tRDT =
// (RDT + 1) * 25ns
#define CONFIG_RDT_TMR_OFST (0)
#define CONFIG_RDT_TMR_MSK (0x0000FFFF << CONFIG_RDT_TMR_OFST)
#define CONFIG_OPRTN_MDE_2_X_10GbE_OFST (16)
#define CONFIG_OPRTN_MDE_2_X_10GbE_MSK (0x00000001 << CONFIG_OPRTN_MDE_2_X_10GbE_OFST)
#define CONFIG_OPRTN_MDE_2_X_10GbE_MSK \
(0x00000001 << CONFIG_OPRTN_MDE_2_X_10GbE_OFST)
// if 0, outer is the primary interface
#define CONFIG_INNR_PRIMRY_INTRFCE_OFST (17)
#define CONFIG_INNR_PRIMRY_INTRFCE_MSK (0x00000001 << CONFIG_INNR_PRIMRY_INTRFCE_OFST)
#define CONFIG_READOUT_SPEED_OFST (20)
#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST)
#define CONFIG_QUARTER_SPEED_10MHZ_VAL ((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_HALF_SPEED_20MHZ_VAL ((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_FULL_SPEED_40MHZ_VAL ((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_TDMA_ENABLE_OFST (24)
#define CONFIG_TDMA_ENABLE_MSK (0x00000001 << CONFIG_TDMA_ENABLE_OFST)
#define CONFIG_TDMA_TIMESLOT_OFST (25) // 1ms
#define CONFIG_TDMA_TIMESLOT_MSK (0x0000001F << CONFIG_TDMA_TIMESLOT_OFST)
#define CONFIG_ETHRNT_FLW_CNTRL_OFST (31)
#define CONFIG_ETHRNT_FLW_CNTRL_MSK (0x00000001 << CONFIG_ETHRNT_FLW_CNTRL_OFST)
#define CONFIG_INNR_PRIMRY_INTRFCE_MSK \
(0x00000001 << CONFIG_INNR_PRIMRY_INTRFCE_OFST)
#define CONFIG_READOUT_SPEED_OFST (20)
#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST)
#define CONFIG_QUARTER_SPEED_10MHZ_VAL \
((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_HALF_SPEED_20MHZ_VAL \
((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_FULL_SPEED_40MHZ_VAL \
((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_TDMA_ENABLE_OFST (24)
#define CONFIG_TDMA_ENABLE_MSK (0x00000001 << CONFIG_TDMA_ENABLE_OFST)
#define CONFIG_TDMA_TIMESLOT_OFST (25) // 1ms
#define CONFIG_TDMA_TIMESLOT_MSK (0x0000001F << CONFIG_TDMA_TIMESLOT_OFST)
#define CONFIG_ETHRNT_FLW_CNTRL_OFST (31)
#define CONFIG_ETHRNT_FLW_CNTRL_MSK (0x00000001 << CONFIG_ETHRNT_FLW_CNTRL_OFST)
/* External Signal Register */
#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
/* Control Register */
#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
#define CONTROL_START_ACQ_OFST (0)
#define CONTROL_START_ACQ_MSK (0x00000001 << CONTROL_START_ACQ_OFST)
#define CONTROL_STOP_ACQ_OFST (1)
#define CONTROL_STOP_ACQ_MSK (0x00000001 << CONTROL_STOP_ACQ_OFST)
#define CONTROL_CORE_RST_OFST (10)
#define CONTROL_CORE_RST_MSK (0x00000001 << CONTROL_CORE_RST_OFST)
#define CONTROL_PERIPHERAL_RST_OFST (11) //DDR3 HMem Ctrlr, GBE, Temp
#define CONTROL_PERIPHERAL_RST_MSK (0x00000001 << CONTROL_PERIPHERAL_RST_OFST) //DDR3 HMem Ctrlr, GBE, Temp
#define CONTROL_DDR3_MEM_RST_OFST (12) //only PHY, not DDR3 PLL ,Not used in software
#define CONTROL_DDR3_MEM_RST_MSK (0x00000001 << CONTROL_DDR3_MEM_RST_OFST) //only PHY, not DDR3 PLL ,Not used in software
#define CONTROL_ACQ_FIFO_CLR_OFST (14)
#define CONTROL_ACQ_FIFO_CLR_MSK (0x00000001 << CONTROL_ACQ_FIFO_CLR_OFST)
#define CONTROL_STORAGE_CELL_NUM_OFST (16)
#define CONTROL_STORAGE_CELL_NUM_MSK (0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
#define CONTROL_START_ACQ_OFST (0)
#define CONTROL_START_ACQ_MSK (0x00000001 << CONTROL_START_ACQ_OFST)
#define CONTROL_STOP_ACQ_OFST (1)
#define CONTROL_STOP_ACQ_MSK (0x00000001 << CONTROL_STOP_ACQ_OFST)
#define CONTROL_CORE_RST_OFST (10)
#define CONTROL_CORE_RST_MSK (0x00000001 << CONTROL_CORE_RST_OFST)
#define CONTROL_PERIPHERAL_RST_OFST (11) // DDR3 HMem Ctrlr, GBE, Temp
#define CONTROL_PERIPHERAL_RST_MSK \
(0x00000001 << CONTROL_PERIPHERAL_RST_OFST) // DDR3 HMem Ctrlr, GBE, Temp
#define CONTROL_DDR3_MEM_RST_OFST \
(12) // only PHY, not DDR3 PLL ,Not used in software
#define CONTROL_DDR3_MEM_RST_MSK \
(0x00000001 << CONTROL_DDR3_MEM_RST_OFST) // only PHY, not DDR3 PLL ,Not
// used in software
#define CONTROL_ACQ_FIFO_CLR_OFST (14)
#define CONTROL_ACQ_FIFO_CLR_MSK (0x00000001 << CONTROL_ACQ_FIFO_CLR_OFST)
#define CONTROL_STORAGE_CELL_NUM_OFST (16)
#define CONTROL_STORAGE_CELL_NUM_MSK \
(0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
#define CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST (20)
#define CONTROL_RX_ADDTNL_ENDPTS_NUM_MSK (0x0000003F << CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST)
#define CONTROL_RX_ENDPTS_START_OFST (26)
#define CONTROL_RX_ENDPTS_START_MSK (0x0000003F << CONTROL_RX_ENDPTS_START_OFST)
#define CONTROL_RX_ADDTNL_ENDPTS_NUM_MSK \
(0x0000003F << CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST)
#define CONTROL_RX_ENDPTS_START_OFST (26)
#define CONTROL_RX_ENDPTS_START_MSK (0x0000003F << CONTROL_RX_ENDPTS_START_OFST)
/* Reconfiguratble PLL Paramater Register */
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
/* Reconfiguratble PLL Control Regiser */
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0) //parameter reset
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST) //parameter reset
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
#define PLL_CNTRL_DBIT_WR_PRMTR_OFST (5)
#define PLL_CNTRL_DBIT_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_DBIT_WR_PRMTR_OFST)
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0) // parameter reset
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST) // parameter reset
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
#define PLL_CNTRL_DBIT_WR_PRMTR_OFST (5)
#define PLL_CNTRL_DBIT_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_DBIT_WR_PRMTR_OFST)
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
/* Sample Register */
#define SAMPLE_REG (0x59 << MEM_MAP_SHIFT)
#define SAMPLE_REG (0x59 << MEM_MAP_SHIFT)
#define SAMPLE_ADC_SAMPLE_SEL_OFST (0)
#define SAMPLE_ADC_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
#define SAMPLE_ADC_SAMPLE_0_VAL ((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_1_VAL ((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_2_VAL ((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_3_VAL ((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_4_VAL ((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_5_VAL ((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_6_VAL ((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_7_VAL ((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_SEL_OFST (0)
#define SAMPLE_ADC_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
#define SAMPLE_ADC_SAMPLE_0_VAL \
((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_1_VAL \
((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_2_VAL \
((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_3_VAL \
((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_4_VAL \
((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_5_VAL \
((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_6_VAL \
((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_7_VAL \
((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
// Decimation = ADF + 1
#define SAMPLE_ADC_DECMT_FACTOR_OFST (4)
#define SAMPLE_ADC_DECMT_FACTOR_MSK (0x00000007 << SAMPLE_ADC_DECMT_FACTOR_OFST)
#define SAMPLE_ADC_DECMT_FACTOR_0_VAL ((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_1_VAL ((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_2_VAL ((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_3_VAL ((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_4_VAL ((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_5_VAL ((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_6_VAL ((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_7_VAL ((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_OFST (4)
#define SAMPLE_ADC_DECMT_FACTOR_MSK (0x00000007 << SAMPLE_ADC_DECMT_FACTOR_OFST)
#define SAMPLE_ADC_DECMT_FACTOR_0_VAL \
((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_1_VAL \
((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_2_VAL \
((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_3_VAL \
((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_4_VAL \
((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_5_VAL \
((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_6_VAL \
((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_7_VAL \
((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_DGTL_SAMPLE_SEL_OFST (8)
#define SAMPLE_DGTL_SAMPLE_SEL_MSK (0x0000000F << SAMPLE_DGTL_SAMPLE_SEL_OFST)
#define SAMPLE_DGTL_SAMPLE_0_VAL ((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_1_VAL ((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_2_VAL ((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_3_VAL ((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_4_VAL ((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_5_VAL ((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_6_VAL ((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_7_VAL ((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_8_VAL ((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_9_VAL ((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_10_VAL ((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_11_VAL ((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_12_VAL ((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_13_VAL ((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_14_VAL ((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_15_VAL ((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_SEL_OFST (8)
#define SAMPLE_DGTL_SAMPLE_SEL_MSK (0x0000000F << SAMPLE_DGTL_SAMPLE_SEL_OFST)
#define SAMPLE_DGTL_SAMPLE_0_VAL \
((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_1_VAL \
((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_2_VAL \
((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_3_VAL \
((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_4_VAL \
((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_5_VAL \
((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_6_VAL \
((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_7_VAL \
((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_8_VAL \
((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_9_VAL \
((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_10_VAL \
((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_11_VAL \
((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_12_VAL \
((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_13_VAL \
((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_14_VAL \
((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_15_VAL \
((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_DECMT_FACTOR_OFST (12)
#define SAMPLE_DGTL_DECMT_FACTOR_MSK (0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
#define SAMPLE_DECMT_FACTOR_FULL_VAL ((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_HALF_VAL ((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_QUARTER_VAL ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DGTL_DECMT_FACTOR_OFST (12)
#define SAMPLE_DGTL_DECMT_FACTOR_MSK \
(0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
#define SAMPLE_DECMT_FACTOR_FULL_VAL \
((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_HALF_VAL \
((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_QUARTER_VAL \
((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
/** Vref Comp Mod Register */
#define EXT_DAQ_CTRL_REG (0x5C << MEM_MAP_SHIFT)
#define EXT_DAQ_CTRL_REG (0x5C << MEM_MAP_SHIFT)
#define EXT_DAQ_CTRL_VREF_COMP_OFST (0)
#define EXT_DAQ_CTRL_VREF_COMP_MSK (0x00000FFF << EXT_DAQ_CTRL_VREF_COMP_OFST)
#define EXT_DAQ_CTRL_CMP_LGC_ENBL_OFST (15)
#define EXT_DAQ_CTRL_CMP_LGC_ENBL_MSK (0x00000001 << EXT_DAQ_CTRL_CMP_LGC_ENBL_OFST)
#define EXT_DAQ_CTRL_INPT_DETECT_OFST (16)
#define EXT_DAQ_CTRL_INPT_DETECT_MSK (0x00000007 << EXT_DAQ_CTRL_INPT_DETECT_OFST)
#define EXT_DAQ_CTRL_CMP_LGC_ENBL_MSK \
(0x00000001 << EXT_DAQ_CTRL_CMP_LGC_ENBL_OFST)
#define EXT_DAQ_CTRL_INPT_DETECT_OFST (16)
#define EXT_DAQ_CTRL_INPT_DETECT_MSK \
(0x00000007 << EXT_DAQ_CTRL_INPT_DETECT_OFST)
#define EXT_DAQ_CTRL_INPT_DETECT_ENBL_OFST (19)
#define EXT_DAQ_CTRL_INPT_DETECT_ENBL_MSK (0x00000001 << EXT_DAQ_CTRL_INPT_DETECT_ENBL_OFST)
#define EXT_DAQ_CTRL_INPT_DETECT_ENBL_MSK \
(0x00000001 << EXT_DAQ_CTRL_INPT_DETECT_ENBL_OFST)
/** DAQ Register */
#define DAQ_REG (0x5D << MEM_MAP_SHIFT)
#define DAQ_REG (0x5D << MEM_MAP_SHIFT)
#define DAQ_SETTINGS_MSK (DAQ_HIGH_GAIN_MSK | DAQ_FIX_GAIN_MSK | DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_HIGH_GAIN_OFST (0)
#define DAQ_HIGH_GAIN_MSK (0x00000001 << DAQ_HIGH_GAIN_OFST)
#define DAQ_FIX_GAIN_DYNMC_VAL ((0x0 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
#define DAQ_FIX_GAIN_HIGHGAIN_VAL ((0x1 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
#define DAQ_FIX_GAIN_OFST (1)
#define DAQ_FIX_GAIN_MSK (0x00000003 << DAQ_FIX_GAIN_OFST)
#define DAQ_FIX_GAIN_STG_1_VAL ((0x1 << DAQ_FIX_GAIN_OFST) & DAQ_FIX_GAIN_MSK)
#define DAQ_FIX_GAIN_STG_2_VAL ((0x3 << DAQ_FIX_GAIN_OFST) & DAQ_FIX_GAIN_MSK)
#define DAQ_CMP_RST_OFST (4)
#define DAQ_CMP_RST_MSK (0x00000001 << DAQ_CMP_RST_OFST)
#define DAQ_STRG_CELL_SLCT_OFST (8)
#define DAQ_STRG_CELL_SLCT_MSK (0x0000000F << DAQ_STRG_CELL_SLCT_OFST)
#define DAQ_FRCE_SWTCH_GAIN_OFST (12)
#define DAQ_FRCE_SWTCH_GAIN_MSK (0x00000003 << DAQ_FRCE_SWTCH_GAIN_OFST)
#define DAQ_FRCE_GAIN_STG_1_VAL ((0x1 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_FRCE_GAIN_STG_2_VAL ((0x3 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_ELCTRN_CLLCTN_MDE_OFST (14)
#define DAQ_ELCTRN_CLLCTN_MDE_MSK (0x00000001 << DAQ_ELCTRN_CLLCTN_MDE_OFST)
#define DAQ_G2_CNNT_OFST (15)
#define DAQ_G2_CNNT_MSK (0x00000001 << DAQ_G2_CNNT_OFST)
#define DAQ_CRRNT_SRC_ENBL_OFST (16)
#define DAQ_CRRNT_SRC_ENBL_MSK (0x00000001 << DAQ_CRRNT_SRC_ENBL_OFST)
#define DAQ_CRRNT_SRC_CLMN_FIX_OFST (17)
#define DAQ_CRRNT_SRC_CLMN_FIX_MSK (0x00000001 << DAQ_CRRNT_SRC_CLMN_FIX_OFST)
#define DAQ_CRRNT_SRC_CLMN_SLCT_OFST (20)
#define DAQ_CRRNT_SRC_CLMN_SLCT_MSK (0x0000003F << DAQ_CRRNT_SRC_CLMN_SLCT_OFST)
#define DAQ_SETTINGS_MSK \
(DAQ_HIGH_GAIN_MSK | DAQ_FIX_GAIN_MSK | DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_HIGH_GAIN_OFST (0)
#define DAQ_HIGH_GAIN_MSK (0x00000001 << DAQ_HIGH_GAIN_OFST)
#define DAQ_FIX_GAIN_DYNMC_VAL ((0x0 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
#define DAQ_FIX_GAIN_HIGHGAIN_VAL \
((0x1 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
#define DAQ_FIX_GAIN_OFST (1)
#define DAQ_FIX_GAIN_MSK (0x00000003 << DAQ_FIX_GAIN_OFST)
#define DAQ_FIX_GAIN_STG_1_VAL ((0x1 << DAQ_FIX_GAIN_OFST) & DAQ_FIX_GAIN_MSK)
#define DAQ_FIX_GAIN_STG_2_VAL ((0x3 << DAQ_FIX_GAIN_OFST) & DAQ_FIX_GAIN_MSK)
#define DAQ_CMP_RST_OFST (4)
#define DAQ_CMP_RST_MSK (0x00000001 << DAQ_CMP_RST_OFST)
#define DAQ_STRG_CELL_SLCT_OFST (8)
#define DAQ_STRG_CELL_SLCT_MSK (0x0000000F << DAQ_STRG_CELL_SLCT_OFST)
#define DAQ_FRCE_SWTCH_GAIN_OFST (12)
#define DAQ_FRCE_SWTCH_GAIN_MSK (0x00000003 << DAQ_FRCE_SWTCH_GAIN_OFST)
#define DAQ_FRCE_GAIN_STG_1_VAL \
((0x1 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_FRCE_GAIN_STG_2_VAL \
((0x3 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_ELCTRN_CLLCTN_MDE_OFST (14)
#define DAQ_ELCTRN_CLLCTN_MDE_MSK (0x00000001 << DAQ_ELCTRN_CLLCTN_MDE_OFST)
#define DAQ_G2_CNNT_OFST (15)
#define DAQ_G2_CNNT_MSK (0x00000001 << DAQ_G2_CNNT_OFST)
#define DAQ_CRRNT_SRC_ENBL_OFST (16)
#define DAQ_CRRNT_SRC_ENBL_MSK (0x00000001 << DAQ_CRRNT_SRC_ENBL_OFST)
#define DAQ_CRRNT_SRC_CLMN_FIX_OFST (17)
#define DAQ_CRRNT_SRC_CLMN_FIX_MSK (0x00000001 << DAQ_CRRNT_SRC_CLMN_FIX_OFST)
#define DAQ_CRRNT_SRC_CLMN_SLCT_OFST (20)
#define DAQ_CRRNT_SRC_CLMN_SLCT_MSK (0x0000003F << DAQ_CRRNT_SRC_CLMN_SLCT_OFST)
/** Chip Power Register */
#define CHIP_POWER_REG (0x5E << MEM_MAP_SHIFT)
#define CHIP_POWER_ENABLE_OFST (0)
#define CHIP_POWER_ENABLE_MSK (0x00000001 << CHIP_POWER_ENABLE_OFST)
#define CHIP_POWER_STATUS_OFST (1)
#define CHIP_POWER_STATUS_MSK (0x00000001 << CHIP_POWER_STATUS_OFST)
#define CHIP_POWER_REG (0x5E << MEM_MAP_SHIFT)
#define CHIP_POWER_ENABLE_OFST (0)
#define CHIP_POWER_ENABLE_MSK (0x00000001 << CHIP_POWER_ENABLE_OFST)
#define CHIP_POWER_STATUS_OFST (1)
#define CHIP_POWER_STATUS_MSK (0x00000001 << CHIP_POWER_STATUS_OFST)
/** Temperature Control Register */
#define TEMP_CTRL_REG (0x5F << MEM_MAP_SHIFT)
#define TEMP_CTRL_REG (0x5F << MEM_MAP_SHIFT)
#define TEMP_CTRL_PROTCT_THRSHLD_OFST (0)
#define TEMP_CTRL_PROTCT_THRSHLD_MSK (0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
#define TEMP_CTRL_PROTCT_ENABLE_OFST (16)
#define TEMP_CTRL_PROTCT_ENABLE_MSK (0x00000001 << TEMP_CTRL_PROTCT_ENABLE_OFST)
#define TEMP_CTRL_PROTCT_THRSHLD_OFST (0)
#define TEMP_CTRL_PROTCT_THRSHLD_MSK \
(0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
#define TEMP_CTRL_PROTCT_ENABLE_OFST (16)
#define TEMP_CTRL_PROTCT_ENABLE_MSK (0x00000001 << TEMP_CTRL_PROTCT_ENABLE_OFST)
// set when temp higher than over threshold, write 1 to clear it
#define TEMP_CTRL_OVR_TMP_EVNT_OFST (31)
#define TEMP_CTRL_OVR_TMP_EVNT_MSK (0x00000001 << TEMP_CTRL_OVR_TMP_EVNT_OFST)
#define TEMP_CTRL_OVR_TMP_EVNT_OFST (31)
#define TEMP_CTRL_OVR_TMP_EVNT_MSK (0x00000001 << TEMP_CTRL_OVR_TMP_EVNT_OFST)
/* Set Delay 64 bit register */
#define SET_DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT) // different kind of delay
#define SET_DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT) // different kind of delay
#define SET_DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT) // different kind of delay
#define SET_DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT) // different kind of delay
/* Set Triggers 64 bit register */
#define SET_CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
#define SET_CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
#define SET_CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
#define SET_CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
/* Set Frames 64 bit register */
#define SET_FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
#define SET_FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
#define SET_FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
#define SET_FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
/* Set Period 64 bit register tT = T x 50 ns */
#define SET_PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
#define SET_PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
#define SET_PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
#define SET_PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
/* Set Exptime 64 bit register eEXP = Exp x 25 ns */
#define SET_EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT)
#define SET_EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT)
#define SET_EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT)
#define SET_EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT)
/* Starting Frame number 64 bit register */
#define FRAME_NUMBER_LSB_REG (0x6A << MEM_MAP_SHIFT)
#define FRAME_NUMBER_MSB_REG (0x6B << MEM_MAP_SHIFT)
#define FRAME_NUMBER_LSB_REG (0x6A << MEM_MAP_SHIFT)
#define FRAME_NUMBER_MSB_REG (0x6B << MEM_MAP_SHIFT)
/* Trigger Delay 32 bit register */
#define SET_TRIGGER_DELAY_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define SET_TRIGGER_DELAY_MSB_REG (0x71 << MEM_MAP_SHIFT)
#define SET_TRIGGER_DELAY_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define SET_TRIGGER_DELAY_MSB_REG (0x71 << MEM_MAP_SHIFT)
/** Module row coordinates */
#define COORD_ROW_REG (0x7C << MEM_MAP_SHIFT)
#define COORD_ROW_REG (0x7C << MEM_MAP_SHIFT)
#define COORD_ROW_OUTER_OFST (0)
#define COORD_ROW_OUTER_MSK (0x0000FFFF << COORD_ROW_OUTER_OFST)
#define COORD_ROW_INNER_OFST (16)
#define COORD_ROW_INNER_MSK (0x0000FFFF << COORD_ROW_INNER_OFST)
#define COORD_ROW_OUTER_OFST (0)
#define COORD_ROW_OUTER_MSK (0x0000FFFF << COORD_ROW_OUTER_OFST)
#define COORD_ROW_INNER_OFST (16)
#define COORD_ROW_INNER_MSK (0x0000FFFF << COORD_ROW_INNER_OFST)
/** Module column coordinates */
#define COORD_COL_REG (0x7D << MEM_MAP_SHIFT)
#define COORD_COL_OUTER_OFST (0)
#define COORD_COL_OUTER_MSK (0x0000FFFF << COORD_COL_OUTER_OFST)
#define COORD_COL_INNER_OFST (16)
#define COORD_COL_INNER_MSK (0x0000FFFF << COORD_COL_INNER_OFST)
#define COORD_COL_REG (0x7D << MEM_MAP_SHIFT)
#define COORD_COL_OUTER_OFST (0)
#define COORD_COL_OUTER_MSK (0x0000FFFF << COORD_COL_OUTER_OFST)
#define COORD_COL_INNER_OFST (16)
#define COORD_COL_INNER_MSK (0x0000FFFF << COORD_COL_INNER_OFST)
/** Module column coordinates */
#define COORD_RESERVED_REG (0x7E << MEM_MAP_SHIFT)
#define COORD_RESERVED_REG (0x7E << MEM_MAP_SHIFT)
#define COORD_RESERVED_OUTER_OFST (0)
#define COORD_RESERVED_OUTER_MSK (0x0000FFFF << COORD_RESERVED_OUTER_OFST)
#define COORD_RESERVED_INNER_OFST (16)
#define COORD_RESERVED_INNER_MSK (0x0000FFFF << COORD_RESERVED_INNER_OFST)
#define COORD_RESERVED_OUTER_OFST (0)
#define COORD_RESERVED_OUTER_MSK (0x0000FFFF << COORD_RESERVED_OUTER_OFST)
#define COORD_RESERVED_INNER_OFST (16)
#define COORD_RESERVED_INNER_MSK (0x0000FFFF << COORD_RESERVED_INNER_OFST)
/* ASIC Control Register */
#define ASIC_CTRL_REG (0x7F << MEM_MAP_SHIFT)
#define ASIC_CTRL_REG (0x7F << MEM_MAP_SHIFT)
// tPC = (PCT + 1) * 25ns
#define ASIC_CTRL_PRCHRG_TMR_OFST (0)
#define ASIC_CTRL_PRCHRG_TMR_MSK (0x000000FF << ASIC_CTRL_PRCHRG_TMR_OFST)
#define ASIC_CTRL_PRCHRG_TMR_VAL ((0x1F << ASIC_CTRL_PRCHRG_TMR_OFST) & ASIC_CTRL_PRCHRG_TMR_MSK)
#define ASIC_CTRL_PRCHRG_TMR_OFST (0)
#define ASIC_CTRL_PRCHRG_TMR_MSK (0x000000FF << ASIC_CTRL_PRCHRG_TMR_OFST)
#define ASIC_CTRL_PRCHRG_TMR_VAL \
((0x1F << ASIC_CTRL_PRCHRG_TMR_OFST) & ASIC_CTRL_PRCHRG_TMR_MSK)
// tDS = (DST + 1) * 25ns
#define ASIC_CTRL_DS_TMR_OFST (8)
#define ASIC_CTRL_DS_TMR_MSK (0x000000FF << ASIC_CTRL_DS_TMR_OFST)
#define ASIC_CTRL_DS_TMR_VAL ((0x1F << ASIC_CTRL_DS_TMR_OFST) & ASIC_CTRL_DS_TMR_MSK)
// tET = (ET + 1) * 25ns (increase timeout range between 2 consecutive storage cells)
#define ASIC_CTRL_EXPSRE_TMR_OFST (16)
#define ASIC_CTRL_EXPSRE_TMR_MSK (0x0000FFFF << ASIC_CTRL_EXPSRE_TMR_OFST)
#define ASIC_CTRL_EXPSRE_TMR_MAX_VAL (0x0000FFFF / (CLK_RUN * 1E-3))
#define ASIC_CTRL_DS_TMR_OFST (8)
#define ASIC_CTRL_DS_TMR_MSK (0x000000FF << ASIC_CTRL_DS_TMR_OFST)
#define ASIC_CTRL_DS_TMR_VAL \
((0x1F << ASIC_CTRL_DS_TMR_OFST) & ASIC_CTRL_DS_TMR_MSK)
// tET = (ET + 1) * 25ns (increase timeout range between 2 consecutive storage
// cells)
#define ASIC_CTRL_EXPSRE_TMR_OFST (16)
#define ASIC_CTRL_EXPSRE_TMR_MSK (0x0000FFFF << ASIC_CTRL_EXPSRE_TMR_OFST)
#define ASIC_CTRL_EXPSRE_TMR_MAX_VAL (0x0000FFFF / (CLK_RUN * 1E-3))
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_0_REG (0xF0 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST (31) /* Refresh alignment */
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST)
#define ADC_DSRLZR_0_REG (0xF0 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST (31) /* Refresh alignment */
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK \
(0x00000001 << ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_1_REG (0xF1 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_1_REG (0xF1 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST (31)
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST)
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK \
(0x00000001 << ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_2_REG (0xF2 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_2_REG (0xF2 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST (31)
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST)
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK \
(0x00000001 << ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_3_REG (0xF3 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_3_REG (0xF3 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST (31)
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST)
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK \
(0x00000001 << ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST)
/* Round Robin */
#define RXR_ENDPOINTS_MAX (64)
#define RXR_ENDPOINT_OUTER_START_REG (0x1000 << MEM_MAP_SHIFT)
#define RXR_ENDPOINT_INNER_START_REG (0x2000 << MEM_MAP_SHIFT)
#define RXR_ENDPOINT_OFST (0x10 << MEM_MAP_SHIFT)
#define RXR_ENDPOINTS_MAX (64)
#define RXR_ENDPOINT_OUTER_START_REG (0x1000 << MEM_MAP_SHIFT)
#define RXR_ENDPOINT_INNER_START_REG (0x2000 << MEM_MAP_SHIFT)
#define RXR_ENDPOINT_OFST (0x10 << MEM_MAP_SHIFT)

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slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
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@ -1,128 +1,144 @@
#pragma once
#include "sls_detector_defs.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x171220
#define REQRD_FRMWRE_VRSN_BOARD2 0x190716 // old
#define REQRD_FRMWRE_VRSN 0x200305 // new
#define MIN_REQRD_VRSN_T_RD_API 0x171220
#define REQRD_FRMWRE_VRSN_BOARD2 0x190716 // old
#define REQRD_FRMWRE_VRSN 0x200305 // new
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
/* Struct Definitions */
typedef struct udp_header_struct {
uint32_t udp_destmac_msb;
uint16_t udp_srcmac_msb;
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl: 4, ip_ver: 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
uint16_t ip_srcip_lsb;
uint16_t udp_srcport;
uint16_t ip_destip_lsb;
uint16_t udp_checksum;
uint16_t udp_destport;
uint32_t udp_destmac_msb;
uint16_t udp_srcmac_msb;
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl : 4, ip_ver : 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
uint16_t ip_srcip_lsb;
uint16_t udp_srcport;
uint16_t ip_destip_lsb;
uint16_t udp_checksum;
uint16_t udp_destport;
} udp_header;
#define IP_HEADER_SIZE (20)
#define UDP_IP_HEADER_LENGTH_BYTES (28)
#define IP_HEADER_SIZE (20)
#define UDP_IP_HEADER_LENGTH_BYTES (28)
/* Enums */
enum ADCINDEX {TEMP_FPGA, TEMP_ADC};
enum DACINDEX {J_VB_COMP, J_VDD_PROT, J_VIN_COM, J_VREF_PRECH, J_VB_PIXBUF, J_VB_DS, J_VREF_DS, J_VREF_COMP };
#define DEFAULT_DAC_VALS { 1220, /* J_VB_COMP */ \
3000, /* J_VDD_PROT */ \
1053, /* J_VIN_COM */ \
1450, /* J_VREF_PRECH */ \
750, /* J_VB_PIXBUF */ \
1000, /* J_VB_DS */ \
480, /* J_VREF_DS */ \
420 /* J_VREF_COMP */ \
};
enum NETWORKINDEX { TXN_FRAME, FLOWCTRL_10G };
enum CLKINDEX {RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS};
#define CLK_NAMES "run", "adc", "dbit"
enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
enum DACINDEX {
J_VB_COMP,
J_VDD_PROT,
J_VIN_COM,
J_VREF_PRECH,
J_VB_PIXBUF,
J_VB_DS,
J_VREF_DS,
J_VREF_COMP
};
#define DEFAULT_DAC_VALS \
{ \
1220, /* J_VB_COMP */ \
3000, /* J_VDD_PROT */ \
1053, /* J_VIN_COM */ \
1450, /* J_VREF_PRECH */ \
750, /* J_VB_PIXBUF */ \
1000, /* J_VB_DS */ \
480, /* J_VREF_DS */ \
420 /* J_VREF_COMP */ \
};
enum NETWORKINDEX { TXN_FRAME, FLOWCTRL_10G };
enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "dbit"
/* Hardware Definitions */
#define NCHAN (256 * 256)
#define NCHIP (8)
#define NDAC (8)
#define NDAC_OLDBOARD (16)
#define DYNAMIC_RANGE (16)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define DATA_BYTES (NCHIP * NCHAN * NUM_BYTES_PER_PIXEL)
#define CLK_RUN (40) /* MHz */
#define CLK_SYNC (20) /* MHz */
#define ADC_CLK_INDEX (1)
#define DBIT_CLK_INDEX (0)
#define NCHAN (256 * 256)
#define NCHIP (8)
#define NDAC (8)
#define NDAC_OLDBOARD (16)
#define DYNAMIC_RANGE (16)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define DATA_BYTES (NCHIP * NCHAN * NUM_BYTES_PER_PIXEL)
#define CLK_RUN (40) /* MHz */
#define CLK_SYNC (20) /* MHz */
#define ADC_CLK_INDEX (1)
#define DBIT_CLK_INDEX (0)
/** Default Parameters */
#define DEFAULT_NUM_FRAMES (100*1000*1000)
#define DEFAULT_NUM_FRAMES (100 * 1000 * 1000)
#define DEFAULT_STARTING_FRAME_NUMBER (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (10*1000) //ns
#define DEFAULT_PERIOD (2*1000*1000) //ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_TMP_THRSHLD (65*1000) //milli degree Celsius
#define DEFAULT_NUM_STRG_CLLS (0)
#define DEFAULT_STRG_CLL_STRT (0xf)
#define DEFAULT_STRG_CLL_DLY (0)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (10 * 1000) // ns
#define DEFAULT_PERIOD (2 * 1000 * 1000) // ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_TMP_THRSHLD (65 * 1000) // milli degree Celsius
#define DEFAULT_NUM_STRG_CLLS (0)
#define DEFAULT_STRG_CLL_STRT (0xf)
#define DEFAULT_STRG_CLL_DLY (0)
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200)
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200)
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
/* Defines in the Firmware */
#define MAX_TIMESLOT_VAL (0x1F)
#define MAX_THRESHOLD_TEMP_VAL (127999) //millidegrees
#define MAX_STORAGE_CELL_VAL (15) //0xF
#define MAX_STORAGE_CELL_DLY_NS_VAL (ASIC_CTRL_EXPSRE_TMR_MAX_VAL)
#define MAX_THRESHOLD_TEMP_VAL (127999) // millidegrees
#define MAX_STORAGE_CELL_VAL (15) // 0xF
#define MAX_STORAGE_CELL_DLY_NS_VAL (ASIC_CTRL_EXPSRE_TMR_MAX_VAL)
#define ACQ_TIME_MIN_CLOCK (2)
#define MAX_PHASE_SHIFTS (160)
#define BIT16_MASK (0xFFFF)
#define MAX_PHASE_SHIFTS (160)
#define BIT16_MASK (0xFFFF)
#define ADC_OFST_FULL_SPEED_VAL (0xf)
#define ADC_OFST_HALF_SPEED_VAL (0xb)
#define ADC_OFST_QUARTER_SPEED_VAL (0x7)
#define ADC_OFST_HALF_SPEED_BOARD2_VAL (0x13)
#define ADC_OFST_QUARTER_SPEED_BOARD2_VAL (0x0b)
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)
#define ADC_PORT_INVERT_BOARD2_VAL (0x453b2a9c)
#define ADC_OFST_FULL_SPEED_VAL (0xf)
#define ADC_OFST_HALF_SPEED_VAL (0xb)
#define ADC_OFST_QUARTER_SPEED_VAL (0x7)
#define ADC_OFST_HALF_SPEED_BOARD2_VAL (0x13)
#define ADC_OFST_QUARTER_SPEED_BOARD2_VAL (0x0b)
#define SAMPLE_ADC_FULL_SPEED \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
SAMPLE_DGTL_SAMPLE_2_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x200
#define SAMPLE_ADC_HALF_SPEED \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1310
#define SAMPLE_ADC_QUARTER_SPEED \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + \
SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2630
#define SAMPLE_ADC_HALF_SPEED_BOARD2 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1600
#define SAMPLE_ADC_QUARTER_SPEED_BOARD2 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
SAMPLE_DGTL_SAMPLE_11_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2b10
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)
#define ADC_PORT_INVERT_BOARD2_VAL (0x453b2a9c)
#define ADC_PHASE_FULL_SPEED (28)
#define ADC_PHASE_HALF_SPEED (35)
#define ADC_PHASE_QUARTER_SPEED (35)
#define ADC_PHASE_HALF_SPEED_BOARD2 (0x1E) // 30
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (0x1E) // 30
#define SAMPLE_ADC_FULL_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_2_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x200
#define SAMPLE_ADC_HALF_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1310
#define SAMPLE_ADC_QUARTER_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2630
#define SAMPLE_ADC_HALF_SPEED_BOARD2 (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1600
#define SAMPLE_ADC_QUARTER_SPEED_BOARD2 (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_11_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2b10
#define ADC_PHASE_FULL_SPEED (28)
#define ADC_PHASE_HALF_SPEED (35)
#define ADC_PHASE_QUARTER_SPEED (35)
#define ADC_PHASE_HALF_SPEED_BOARD2 (0x1E) //30
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (0x1E) //30
#define DBIT_PHASE_FULL_SPEED (37)
#define DBIT_PHASE_HALF_SPEED (37)
#define DBIT_PHASE_QUARTER_SPEED (37)
#define DBIT_PHASE_HALF_SPEED_BOARD2 (37)
#define DBIT_PHASE_QUARTER_SPEED_BOARD2 (37)
#define DBIT_PHASE_FULL_SPEED (37)
#define DBIT_PHASE_HALF_SPEED (37)
#define DBIT_PHASE_QUARTER_SPEED (37)
#define DBIT_PHASE_HALF_SPEED_BOARD2 (37)
#define DBIT_PHASE_QUARTER_SPEED_BOARD2 (37)

710
slsDetectorServers/moenchDetectorServer/RegisterDefs.h Executable file → Normal file
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@ -3,542 +3,570 @@
/* Definitions for FPGA */
#define MEM_MAP_SHIFT 1
/* FPGA Version RO register */
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
#define FPGA_VERSION_BRD_RVSN_OFST (0)
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_MOENCH_VAL ((0x5 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
#define FPGA_VERSION_BRD_RVSN_OFST (0)
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_MOENCH_VAL \
((0x5 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
/* Fix pattern RO register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
#define FIX_PATT_VAL (0xACDC2016)
#define FIX_PATT_VAL (0xACDC2016)
/* Status RO register */
#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
#define STATUS_RN_BSY_OFST (0)
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
#define STATUS_ANY_FF_FLL_OFST (2)
#define STATUS_ANY_FF_FLL_MSK (0x00000001 << STATUS_ANY_FF_FLL_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4)
#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
#define STATUS_DLY_AFTR_OFST (5)
#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
#define STATUS_EXPSNG_OFST (6)
#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
#define STATUS_CNT_ENBL_OFST (7)
#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
#define STATUS_SM_FF_FLL_OFST (11)
#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
#define STATUS_STPPD_OFST (15)
#define STATUS_STPPD_MSK (0x00000001 << STATUS_STPPD_OFST)
#define STATUS_ALL_FF_EMPTY_OFST (16)
#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
#define STATUS_CYCL_RN_BSY_OFST (17)
#define STATUS_CYCL_RN_BSY_MSK (0x00000001 << STATUS_CYCL_RN_BSY_OFST)
#define STATUS_FRM_RN_BSY_OFST (18)
#define STATUS_FRM_RN_BSY_MSK (0x00000001 << STATUS_FRM_RN_BSY_OFST)
#define STATUS_ADC_DESERON_OFST (19)
#define STATUS_ADC_DESERON_MSK (0x00000001 << STATUS_ADC_DESERON_OFST)
#define STATUS_PLL_RCNFG_BSY_OFST (20)
#define STATUS_PLL_RCNFG_BSY_MSK (0x00000001 << STATUS_PLL_RCNFG_BSY_OFST)
#define STATUS_DT_STRMNG_BSY_OFST (21)
#define STATUS_DT_STRMNG_BSY_MSK (0x00000001 << STATUS_DT_STRMNG_BSY_OFST)
#define STATUS_FRM_PCKR_BSY_OFST (22)
#define STATUS_FRM_PCKR_BSY_MSK (0x00000001 << STATUS_FRM_PCKR_BSY_OFST)
#define STATUS_PLL_PHS_DN_OFST (23)
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x677FF)
#define STATUS_RN_BSY_OFST (0)
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
#define STATUS_ANY_FF_FLL_OFST (2)
#define STATUS_ANY_FF_FLL_MSK (0x00000001 << STATUS_ANY_FF_FLL_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4)
#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
#define STATUS_DLY_AFTR_OFST (5)
#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
#define STATUS_EXPSNG_OFST (6)
#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
#define STATUS_CNT_ENBL_OFST (7)
#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
#define STATUS_SM_FF_FLL_OFST (11)
#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
#define STATUS_STPPD_OFST (15)
#define STATUS_STPPD_MSK (0x00000001 << STATUS_STPPD_OFST)
#define STATUS_ALL_FF_EMPTY_OFST (16)
#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
#define STATUS_CYCL_RN_BSY_OFST (17)
#define STATUS_CYCL_RN_BSY_MSK (0x00000001 << STATUS_CYCL_RN_BSY_OFST)
#define STATUS_FRM_RN_BSY_OFST (18)
#define STATUS_FRM_RN_BSY_MSK (0x00000001 << STATUS_FRM_RN_BSY_OFST)
#define STATUS_ADC_DESERON_OFST (19)
#define STATUS_ADC_DESERON_MSK (0x00000001 << STATUS_ADC_DESERON_OFST)
#define STATUS_PLL_RCNFG_BSY_OFST (20)
#define STATUS_PLL_RCNFG_BSY_MSK (0x00000001 << STATUS_PLL_RCNFG_BSY_OFST)
#define STATUS_DT_STRMNG_BSY_OFST (21)
#define STATUS_DT_STRMNG_BSY_MSK (0x00000001 << STATUS_DT_STRMNG_BSY_OFST)
#define STATUS_FRM_PCKR_BSY_OFST (22)
#define STATUS_FRM_PCKR_BSY_MSK (0x00000001 << STATUS_FRM_PCKR_BSY_OFST)
#define STATUS_PLL_PHS_DN_OFST (23)
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK \
(0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x677FF)
/* Look at me RO register TODO */
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
/* System Status RO register */
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK (0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK (0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK \
(0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as PLL_PARAM_REG 0x50 */
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as
* PLL_PARAM_REG 0x50 */
//#define PLL_PARAM_REG (0x05 << MEM_MAP_SHIFT)
/* FIFO Data RO register TODO */
#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK \
(0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
//#define FIFO_DATA_WRD_OFST (16)
//#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
/* FIFO Status RO register TODO */
#define FIFO_STATUS_REG (0x07 << MEM_MAP_SHIFT)
#define FIFO_STATUS_REG (0x07 << MEM_MAP_SHIFT)
/* FIFO Empty RO register TODO */
#define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT)
#define FIFO_EMPTY_ALL_EMPTY_MSK (0xFFFFFFFF)
#define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT)
#define FIFO_EMPTY_ALL_EMPTY_MSK (0xFFFFFFFF)
/* FIFO Full RO register TODO */
#define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT)
#define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT)
/* MCB Serial Number RO register */
#define MOD_SERIAL_NUMBER_REG (0x0A << MEM_MAP_SHIFT)
#define MOD_SERIAL_NUMBER_REG (0x0A << MEM_MAP_SHIFT)
#define MOD_SERIAL_NUMBER_OFST (0)
#define MOD_SERIAL_NUMBER_MSK (0x000000FF << MOD_SERIAL_NUMBER_OFST)
#define MOD_SERIAL_NUMBER_VRSN_OFST (16)
#define MOD_SERIAL_NUMBER_VRSN_MSK (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
#define MOD_SERIAL_NUMBER_OFST (0)
#define MOD_SERIAL_NUMBER_MSK (0x000000FF << MOD_SERIAL_NUMBER_OFST)
#define MOD_SERIAL_NUMBER_VRSN_OFST (16)
#define MOD_SERIAL_NUMBER_VRSN_MSK (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
/* API Version RO register */
#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DTCTR_TYP_OFST (24)
#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DTCTR_TYP_OFST (24)
#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
* CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
/* Delay Left 64 bit RO register. t = DLY x 50 ns. TODO */
#define DELAY_LEFT_LSB_REG (0x12 << MEM_MAP_SHIFT)
#define DELAY_LEFT_MSB_REG (0x13 << MEM_MAP_SHIFT)
#define DELAY_LEFT_LSB_REG (0x12 << MEM_MAP_SHIFT)
#define DELAY_LEFT_MSB_REG (0x13 << MEM_MAP_SHIFT)
/* Triggers Left 64 bit RO register TODO */
#define CYCLES_LEFT_LSB_REG (0x14 << MEM_MAP_SHIFT)
#define CYCLES_LEFT_MSB_REG (0x15 << MEM_MAP_SHIFT)
#define CYCLES_LEFT_LSB_REG (0x14 << MEM_MAP_SHIFT)
#define CYCLES_LEFT_MSB_REG (0x15 << MEM_MAP_SHIFT)
/* Frames Left 64 bit RO register TODO */
#define FRAMES_LEFT_LSB_REG (0x16 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_MSB_REG (0x17 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_LSB_REG (0x16 << MEM_MAP_SHIFT)
#define FRAMES_LEFT_MSB_REG (0x17 << MEM_MAP_SHIFT)
/* Period Left 64 bit RO register. t = T x 50 ns. TODO */
#define PERIOD_LEFT_LSB_REG (0x18 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_LSB_REG (0x18 << MEM_MAP_SHIFT)
#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
/* Exposure Time Left 64 bit RO register */
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
//used in FW #define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT)
//// Not used in FW
/* Gates Left 64 bit RO register */
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not
//used in FW #define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT)
//// Not used in FW
/* Data In 64 bit RO register TODO */
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
#define DATA_IN_MSB_REG (0x1F << MEM_MAP_SHIFT)
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
#define DATA_IN_MSB_REG (0x1F << MEM_MAP_SHIFT)
/* Pattern Out 64 bit RO register */
#define PATTERN_OUT_LSB_REG (0x20 << MEM_MAP_SHIFT)
#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
#define PATTERN_OUT_LSB_REG (0x20 << MEM_MAP_SHIFT)
#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
/* Frames From Start 64 bit RO register TODO */
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not
//used in FW #define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT)
//// Not used in FW
/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
* start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
/* Power Status RO register */
#define POWER_STATUS_REG (0x29 << MEM_MAP_SHIFT)
#define POWER_STATUS_REG (0x29 << MEM_MAP_SHIFT)
#define POWER_STATUS_ALRT_OFST (27)
#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
#define POWER_STATUS_ALRT_OFST (27)
#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
/* DAC Value Out RO register */
//#define DAC_VAL_OUT_REG (0x2A << MEM_MAP_SHIFT)
/* Slow ADC SPI Value RO register */
#define ADC_SPI_SLOW_VAL_REG (0x2B << MEM_MAP_SHIFT)
#define ADC_SPI_SLOW_VAL_REG (0x2B << MEM_MAP_SHIFT)
/* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK \
(0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK \
(0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
/* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
#define FIFO_DIN_MSB_REG (0x3D << MEM_MAP_SHIFT)
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
#define FIFO_DIN_MSB_REG (0x3D << MEM_MAP_SHIFT)
/* SPI (Serial Peripheral Interface) DAC, HV RW register */
#define SPI_REG (0x40 << MEM_MAP_SHIFT)
#define SPI_REG (0x40 << MEM_MAP_SHIFT)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_CS_OTPT_OFST (2)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_HV_SRL_DGTL_OTPT_OFST (8)
#define SPI_HV_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
#define SPI_HV_SRL_CLK_OTPT_OFST (9)
#define SPI_HV_SRL_CLK_OTPT_MSK (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
#define SPI_HV_SRL_CS_OTPT_OFST (10)
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_CS_OTPT_OFST (2)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_HV_SRL_DGTL_OTPT_OFST (8)
#define SPI_HV_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
#define SPI_HV_SRL_CLK_OTPT_OFST (9)
#define SPI_HV_SRL_CLK_OTPT_MSK (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
#define SPI_HV_SRL_CS_OTPT_OFST (10)
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
/* ADC SPI (Serial Peripheral Interface) RW register */
#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
#define ADC_SPI_SLOW_SRL_DT_OFST (8)
#define ADC_SPI_SLOW_SRL_DT_MSK (0x00000001 << ADC_SPI_SLOW_SRL_DT_OFST)
#define ADC_SPI_SLOW_SRL_CLK_OFST (9)
#define ADC_SPI_SLOW_SRL_CLK_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CLK_OFST)
#define ADC_SPI_SLOW_SRL_CNV_OFST (10)
#define ADC_SPI_SLOW_SRL_CNV_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CNV_OFST)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
#define ADC_SPI_SLOW_SRL_DT_OFST (8)
#define ADC_SPI_SLOW_SRL_DT_MSK (0x00000001 << ADC_SPI_SLOW_SRL_DT_OFST)
#define ADC_SPI_SLOW_SRL_CLK_OFST (9)
#define ADC_SPI_SLOW_SRL_CLK_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CLK_OFST)
#define ADC_SPI_SLOW_SRL_CNV_OFST (10)
#define ADC_SPI_SLOW_SRL_CNV_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CNV_OFST)
/* ADC Offset RW register */
#define ADC_OFFSET_REG (0x42 << MEM_MAP_SHIFT)
#define ADC_OFFSET_REG (0x42 << MEM_MAP_SHIFT)
#define ADC_OFFSET_ADC_PPLN_OFST (0)
#define ADC_OFFSET_ADC_PPLN_MSK (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
#define ADC_OFFSET_DBT_PPLN_OFST (16)
#define ADC_OFFSET_DBT_PPLN_MSK (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
#define ADC_OFFSET_ADC_PPLN_OFST (0)
#define ADC_OFFSET_ADC_PPLN_MSK (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
#define ADC_OFFSET_DBT_PPLN_OFST (16)
#define ADC_OFFSET_DBT_PPLN_MSK (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
/* ADC Port Invert RW register */
#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
#define ADC_PORT_INVERT_0_INPT_OFST (0)
#define ADC_PORT_INVERT_0_INPT_MSK (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
#define ADC_PORT_INVERT_1_INPT_OFST (8)
#define ADC_PORT_INVERT_1_INPT_MSK (0x000000FF << ADC_PORT_INVERT_1_INPT_OFST)
#define ADC_PORT_INVERT_2_INPT_OFST (16)
#define ADC_PORT_INVERT_2_INPT_MSK (0x000000FF << ADC_PORT_INVERT_2_INPT_OFST)
#define ADC_PORT_INVERT_3_INPT_OFST (24)
#define ADC_PORT_INVERT_3_INPT_MSK (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
#define ADC_PORT_INVERT_0_INPT_OFST (0)
#define ADC_PORT_INVERT_0_INPT_MSK (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
#define ADC_PORT_INVERT_1_INPT_OFST (8)
#define ADC_PORT_INVERT_1_INPT_MSK (0x000000FF << ADC_PORT_INVERT_1_INPT_OFST)
#define ADC_PORT_INVERT_2_INPT_OFST (16)
#define ADC_PORT_INVERT_2_INPT_MSK (0x000000FF << ADC_PORT_INVERT_2_INPT_OFST)
#define ADC_PORT_INVERT_3_INPT_OFST (24)
#define ADC_PORT_INVERT_3_INPT_MSK (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
/* Dummy RW register */
#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK \
(0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK \
(0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
/* Receiver IP Address RW register */
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
/* UDP Port RW register */
#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT)
#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT)
#define UDP_PORT_RX_OFST (0)
#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
#define UDP_PORT_TX_OFST (16)
#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
#define UDP_PORT_RX_OFST (0)
#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
#define UDP_PORT_TX_OFST (16)
#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
/* Receiver Mac Address 64 bit RW register */
#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT)
#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT)
#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT)
#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT)
#define RX_MAC_LSB_OFST (0)
#define RX_MAC_LSB_MSK (0xFFFFFFFF << RX_MAC_LSB_OFST)
#define RX_MAC_MSB_OFST (0)
#define RX_MAC_MSB_MSK (0x0000FFFF << RX_MAC_MSB_OFST)
#define RX_MAC_LSB_OFST (0)
#define RX_MAC_LSB_MSK (0xFFFFFFFF << RX_MAC_LSB_OFST)
#define RX_MAC_MSB_OFST (0)
#define RX_MAC_MSB_MSK (0x0000FFFF << RX_MAC_MSB_OFST)
/* Detector/ Transmitter Mac Address 64 bit RW register */
#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT)
#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT)
#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT)
#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT)
#define TX_MAC_LSB_OFST (0)
#define TX_MAC_LSB_MSK (0xFFFFFFFF << TX_MAC_LSB_OFST)
#define TX_MAC_MSB_OFST (0)
#define TX_MAC_MSB_MSK (0x0000FFFF << TX_MAC_MSB_OFST)
#define TX_MAC_LSB_OFST (0)
#define TX_MAC_LSB_MSK (0xFFFFFFFF << TX_MAC_LSB_OFST)
#define TX_MAC_MSB_OFST (0)
#define TX_MAC_MSB_MSK (0x0000FFFF << TX_MAC_MSB_OFST)
/* Detector/ Transmitter IP Address RW register */
#define TX_IP_REG (0x4B << MEM_MAP_SHIFT)
#define TX_IP_REG (0x4B << MEM_MAP_SHIFT)
/* Detector/ Transmitter IP Checksum RW register */
#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT)
#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT)
#define TX_IP_CHECKSUM_OFST (0)
#define TX_IP_CHECKSUM_MSK (0x0000FFFF << TX_IP_CHECKSUM_OFST)
#define TX_IP_CHECKSUM_OFST (0)
#define TX_IP_CHECKSUM_MSK (0x0000FFFF << TX_IP_CHECKSUM_OFST)
/* Configuration RW register */
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
#define CONFIG_LED_DSBL_OFST (0) // Not used in firmware or software
#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
#define CONFIG_DSBL_ANLG_OTPT_OFST (8)
#define CONFIG_DSBL_ANLG_OTPT_MSK (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
#define CONFIG_ENBLE_DGTL_OTPT_OFST (9)
#define CONFIG_ENBLE_DGTL_OTPT_MSK (0x00000001 << CONFIG_ENBLE_DGTL_OTPT_OFST)
#define CONFIG_GB10_SND_UDP_OFST (12)
#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
#define CONFIG_LED_DSBL_OFST (0) // Not used in firmware or software
#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
#define CONFIG_DSBL_ANLG_OTPT_OFST (8)
#define CONFIG_DSBL_ANLG_OTPT_MSK (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
#define CONFIG_ENBLE_DGTL_OTPT_OFST (9)
#define CONFIG_ENBLE_DGTL_OTPT_MSK (0x00000001 << CONFIG_ENBLE_DGTL_OTPT_OFST)
#define CONFIG_GB10_SND_UDP_OFST (12)
#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
/* External Signal RW register */
#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_AUTO_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_AUTO_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/* Control RW register */
#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
//#define CONTROL_STRT_FF_TST_OFST (2)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
//#define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
//#define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_RDT_OFST (5)
//#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 <<
//CONTROL_STRT_FF_TST_OFST) #define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 <<
//CONTROL_STP_FF_TST_OFST) #define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 <<
//CONTROL_STRT_RDT_OFST) #define CONTROL_STP_RDT_OFST (5) #define
//CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
//#define CONTROL_STP_EXPSR_OFST (7)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STRT_TRN_OFST (8)
//#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 <<
//CONTROL_STP_RDT_OFST) #define CONTROL_STRT_TRN_OFST (8) #define
//CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_TRN_OFST (9)
//#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_MMRY_RST_OFST (12)
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
//#define CONTROL_STP_TRN_MSK (0x00000001 <<
//CONTROL_STP_RDT_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_MMRY_RST_OFST (12)
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
//#define CONTROL_PLL_RCNFG_WR_OFST (13)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 << CONTROL_PLL_RCNFG_WR_OFST)
#define CONTROL_SND_10GB_PCKT_OFST (14)
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 <<
//CONTROL_PLL_RCNFG_WR_OFST)
#define CONTROL_SND_10GB_PCKT_OFST (14)
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
/* Reconfiguratble PLL Paramater RW register */
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
/* Reconfiguratble PLL Control RW regiser */
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
#define PLL_CNTRL_ADDR_OFST (16)
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
/* Pattern Control RW register */
#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
#define PATTERN_CNTRL_RD_OFST (1)
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
#define PATTERN_CNTRL_ADDR_OFST (16)
#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
#define PATTERN_CNTRL_WR_OFST (0)
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
#define PATTERN_CNTRL_RD_OFST (1)
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
#define PATTERN_CNTRL_ADDR_OFST (16)
#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
/* Pattern Limit RW regiser */
#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
/* Pattern Loop 0 Address RW regiser */
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
/* Pattern Loop 0 Iteration RW regiser */
#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
/* Pattern Loop 1 Address RW regiser */
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
/* Pattern Loop 1 Iteration RW regiser */
#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
/* Pattern Loop 2 Address RW regiser */
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern Loop 2 Iteration RW regiser */
#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
/* Pattern Wait 0 RW regiser */
#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
//FIXME: is mask 3FF
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
// FIXME: is mask 3FF
/* Pattern Wait 1 RW regiser */
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Wait 2 RW regiser */
#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
/* Samples RW register */
#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
#define SAMPLES_DIGITAL_OFST (0)
#define SAMPLES_DIGITAL_MSK (0x0000FFFF << SAMPLES_DIGITAL_OFST)
#define SAMPLES_ANALOG_OFST (16)
#define SAMPLES_ANALOG_MSK (0x0000FFFF << SAMPLES_ANALOG_OFST)
#define SAMPLES_DIGITAL_OFST (0)
#define SAMPLES_DIGITAL_MSK (0x0000FFFF << SAMPLES_DIGITAL_OFST)
#define SAMPLES_ANALOG_OFST (16)
#define SAMPLES_ANALOG_MSK (0x0000FFFF << SAMPLES_ANALOG_OFST)
/** Power RW register */
#define POWER_REG (0x5E << MEM_MAP_SHIFT)
#define POWER_REG (0x5E << MEM_MAP_SHIFT)
#define POWER_CHIP_OFST (16)
#define POWER_CHIP_MSK (0x00000001 << POWER_CHIP_OFST)
#define POWER_HV_INTERNAL_SLCT_OFST (31)
#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
#define POWER_CHIP_OFST (16)
#define POWER_CHIP_MSK (0x00000001 << POWER_CHIP_OFST)
#define POWER_HV_INTERNAL_SLCT_OFST (31)
#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
/* Number of Words RW register TODO */
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
/* Delay 64 bit RW register. t = DLY x 50 ns. */
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
/* Triggers 64 bit RW register */
#define CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
#define CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
#define CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
#define CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
/* Frames 64 bit RW register */
#define FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
#define FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
#define FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
#define FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
#define PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
#define PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
//Not used in FW #define EXPTIME_MSB_REG (0x69 <<
//MEM_MAP_SHIFT) // Not used in FW
/* Gates 64 bit RW register */
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used
//in FW #define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) //
//Not used in FW
/* Pattern IO Control 64 bit RW regiser
* Each bit configured as output(1)/ input(0) */
#define PATTERN_IO_CNTRL_LSB_REG (0x6C << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_MSB_REG (0x6D << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_LSB_REG (0x6C << MEM_MAP_SHIFT)
#define PATTERN_IO_CNTRL_MSB_REG (0x6D << MEM_MAP_SHIFT)
/* Pattern IO Clock Control 64 bit RW regiser
* When bit n enabled (1), clocked output for DIO[n] (T run clock)
* When bit n disabled (0), Dio[n] driven by its pattern output */
#define PATTERN_IO_CLK_CNTRL_LSB_REG (0x6E << MEM_MAP_SHIFT)
#define PATTERN_IO_CLK_CNTRL_MSB_REG (0x6F << MEM_MAP_SHIFT)
#define PATTERN_IO_CLK_CNTRL_LSB_REG (0x6E << MEM_MAP_SHIFT)
#define PATTERN_IO_CLK_CNTRL_MSB_REG (0x6F << MEM_MAP_SHIFT)
/* Pattern In 64 bit RW register */
#define PATTERN_IN_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define PATTERN_IN_MSB_REG (0x71 << MEM_MAP_SHIFT)
#define PATTERN_IN_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define PATTERN_IN_MSB_REG (0x71 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 0 64 bit RW register. t = PWT1 x T run clock */
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x73 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x73 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 1 64 bit RW register. t = PWT2 x T run clock */
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x75 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x75 << MEM_MAP_SHIFT)
/* Pattern Wait Timer 2 64 bit RW register. t = PWT3 x T run clock */
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
/* Readout enable RW register */
#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
#define READOUT_10G_ENABLE_ANLG_OFST (0)
#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
#define READOUT_10G_ENABLE_DGTL_OFST (8)
#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
#define READOUT_10G_ENABLE_ANLG_OFST (0)
#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
#define READOUT_10G_ENABLE_DGTL_OFST (8)
#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
/* Digital Bit External Trigger RW register */
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT) // Not used in firmware or software
#define DBIT_EXT_TRG_REG \
(0x7B << MEM_MAP_SHIFT) // Not used in firmware or software
#define DBIT_EXT_TRG_SRC_OFST (0)
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
#define DBIT_EXT_TRG_OPRTN_MD_OFST (16)
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
#define DBIT_EXT_TRG_SRC_OFST (0)
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
#define DBIT_EXT_TRG_OPRTN_MD_OFST (16)
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
/* Pin Delay 0 RW register */
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT) // Not used in firmware or software
#define OUTPUT_DELAY_0_REG \
(0x7C << MEM_MAP_SHIFT) // Not used in firmware or software
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST (0) //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK (0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL (1)
#define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST \
(0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK \
(0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay
// configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK \
(0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL (1)
#define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
/* Pin Delay 1 RW register
* Each bit configured as enable for dynamic output delay configuration */
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT) // Not used in firmware or software
#define PIN_DELAY_1_REG \
(0x7D << MEM_MAP_SHIFT) // Not used in firmware or software
/** Pattern Mask 64 bit RW regiser */
#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
#define PATTERN_MASK_MSB_REG (0x81 << MEM_MAP_SHIFT)
#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
#define PATTERN_MASK_MSB_REG (0x81 << MEM_MAP_SHIFT)
/** Pattern Set 64 bit RW regiser */
#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
/* Round Robin */
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)

211
slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
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@ -1,128 +1,143 @@
#pragma once
#include "sls_detector_defs.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x180314
#define REQRD_FRMWR_VRSN 0x200302
#define MIN_REQRD_VRSN_T_RD_API 0x180314
#define REQRD_FRMWR_VRSN 0x200302
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
/* Struct Definitions */
typedef struct udp_header_struct {
uint32_t udp_destmac_msb;
uint16_t udp_srcmac_msb;
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl: 4, ip_ver: 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
uint16_t ip_srcip_lsb;
uint16_t udp_srcport;
uint16_t ip_destip_lsb;
uint16_t udp_checksum;
uint16_t udp_destport;
uint32_t udp_destmac_msb;
uint16_t udp_srcmac_msb;
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl : 4, ip_ver : 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
uint16_t ip_srcip_lsb;
uint16_t udp_srcport;
uint16_t ip_destip_lsb;
uint16_t udp_checksum;
uint16_t udp_destport;
} udp_header;
#define IP_HEADER_SIZE (20)
#define UDP_IP_HEADER_LENGTH_BYTES (28)
#define IP_HEADER_SIZE (20)
#define UDP_IP_HEADER_LENGTH_BYTES (28)
/* Enums */
enum DACINDEX {MO_VBP_COLBUF, MO_VIPRE, MO_VIN_CM, MO_VB_SDA, MO_VCASC_SFP, MO_VOUT_CM, MO_VIPRE_CDS, MO_IBIAS_SFP};
#define DAC_NAMES "vbp_colbuf", "vipre", "vin_cm", "vb_sda", "vcasc_sfp", "vout_cm", "vipre_cds", "ibias_sfp"
#define DEFAULT_DAC_VALS { 1300, /* MO_VBP_COLBUF */ \
1000, /* MO_VIPRE */ \
1400, /* MO_VIN_CM */ \
680, /* MO_VB_SDA */ \
1428, /* MO_VCASC_SFP */ \
1200, /* MO_VOUT_CM */ \
800, /* MO_VIPRE_CDS */ \
900 /* MO_IBIAS_SFP */ \
};
enum DACINDEX {
MO_VBP_COLBUF,
MO_VIPRE,
MO_VIN_CM,
MO_VB_SDA,
MO_VCASC_SFP,
MO_VOUT_CM,
MO_VIPRE_CDS,
MO_IBIAS_SFP
};
#define DAC_NAMES \
"vbp_colbuf", "vipre", "vin_cm", "vb_sda", "vcasc_sfp", "vout_cm", \
"vipre_cds", "ibias_sfp"
#define DEFAULT_DAC_VALS \
{ \
1300, /* MO_VBP_COLBUF */ \
1000, /* MO_VIPRE */ \
1400, /* MO_VIN_CM */ \
680, /* MO_VB_SDA */ \
1428, /* MO_VCASC_SFP */ \
1200, /* MO_VOUT_CM */ \
800, /* MO_VIPRE_CDS */ \
900 /* MO_IBIAS_SFP */ \
};
enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
#define CLK_NAMES "run", "adc", "sync", "dbit"
enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "sync", "dbit"
/* Hardware Definitions */
#define NCHAN (32)
#define NCHIP (1)
#define NDAC (8)
#define DYNAMIC_RANGE (16)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define CLK_FREQ (156.25) /* MHz */
#define NSAMPLES_PER_ROW (25)
#define NCHANS_PER_ADC (25)
#define NCHAN (32)
#define NCHIP (1)
#define NDAC (8)
#define DYNAMIC_RANGE (16)
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
#define CLK_FREQ (156.25) /* MHz */
#define NSAMPLES_PER_ROW (25)
#define NCHANS_PER_ADC (25)
/** Default Parameters */
#define DEFAULT_PATTERN_FILE ("DefaultPattern.txt")
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define DEFAULT_NUM_SAMPLES (5000)
#define DEFAULT_EXPTIME (0)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_PERIOD (1 * 1000 * 1000) //ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_VLIMIT (-100)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_PATTERN_FILE ("DefaultPattern.txt")
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define DEFAULT_NUM_SAMPLES (5000)
#define DEFAULT_EXPTIME (0)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_PERIOD (1 * 1000 * 1000) // ns
#define DEFAULT_DELAY (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_VLIMIT (-100)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TX_UDP_PORT (0x7e9a)
#define DEFAULT_RUN_CLK_AT_STARTUP (200) // 40
#define DEFAULT_ADC_CLK_AT_STARTUP (40) // 20
#define DEFAULT_SYNC_CLK_AT_STARTUP (40) // 20
#define DEFAULT_ADC_CLK_AT_STARTUP (40) // 20
#define DEFAULT_SYNC_CLK_AT_STARTUP (40) // 20
#define DEFAULT_DBIT_CLK_AT_STARTUP (200)
#define DEFAULT_RUN_CLK (40)
#define DEFAULT_ADC_CLK (20)
#define DEFAULT_DBIT_CLK (40)
#define DEFAULT_ADC_PHASE_DEG (30)
#define DEFAULT_RUN_CLK (40)
#define DEFAULT_ADC_CLK (20)
#define DEFAULT_DBIT_CLK (40)
#define DEFAULT_ADC_PHASE_DEG (30)
#define DEFAULT_PIPELINE (15)
#define DEFAULT_SETTINGS (G4_HIGHGAIN)
#define DEFAULT_PIPELINE (15)
#define DEFAULT_SETTINGS (G4_HIGHGAIN)
// settings
#define DEFAULT_PATSETBIT (0x00000C800000800AULL)
#define G1_HIGHGAIN_PATMASK (0x00000C0000008008ULL)
#define G1_LOWGAIN_PATMASK (0x0000040000008000ULL)
#define G2_HIGHCAP_HIGHGAIN_PATMASK (0x0000080000000008ULL)
#define G2_HIGHCAP_LOWGAIN_PATMASK (0x0000000000000000ULL)
#define G2_LOWCAP_HIGHGAIN_PATMASK (0x00000C800000800AULL)
#define G2_LOWCAP_LOWGAIN_PATMASK (0x0000048000008002ULL)
#define G4_HIGHGAIN_PATMASK (0x000008800000000AULL)
#define G4_LOWGAIN_PATMASK (0x0000008000000002ULL)
#define DEFAULT_PATSETBIT (0x00000C800000800AULL)
#define G1_HIGHGAIN_PATMASK (0x00000C0000008008ULL)
#define G1_LOWGAIN_PATMASK (0x0000040000008000ULL)
#define G2_HIGHCAP_HIGHGAIN_PATMASK (0x0000080000000008ULL)
#define G2_HIGHCAP_LOWGAIN_PATMASK (0x0000000000000000ULL)
#define G2_LOWCAP_HIGHGAIN_PATMASK (0x00000C800000800AULL)
#define G2_LOWCAP_LOWGAIN_PATMASK (0x0000048000008002ULL)
#define G4_HIGHGAIN_PATMASK (0x000008800000000AULL)
#define G4_LOWGAIN_PATMASK (0x0000008000000002ULL)
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200) // min dac val
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
#define HIGHVOLTAGE_MIN (60)
#define HIGHVOLTAGE_MAX (200) // min dac val
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
/* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0x2000)
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_STEPS (8)
#define MAX_PATTERN_LENGTH (0x2000)
#define DIGITAL_IO_DELAY_MAXIMUM_PS \
((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_STEPS (8)
#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
#define WAIT_TIME_PATTERN_READ (10)
#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
#define WAIT_TME_US_FR_ACQDONE_REG \
(100) // wait time in us after acquisition done to ensure there is no data
// in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
#define WAIT_TIME_PATTERN_READ (10)
#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
/* MSB & LSB DEFINES */
#define MSB_OF_64_BIT_REG_OFST (32)
#define LSB_OF_64_BIT_REG_OFST (0)
#define BIT32_MSK (0xFFFFFFFF)
#define BIT16_MASK (0xFFFF)
#define ADC_PORT_INVERT_VAL (0x4a342593)
#define MAXIMUM_ADC_CLK (20)
#define PLL_VCO_FREQ_MHZ (800)
#define MSB_OF_64_BIT_REG_OFST (32)
#define LSB_OF_64_BIT_REG_OFST (0)
#define BIT32_MSK (0xFFFFFFFF)
#define BIT16_MASK (0xFFFF)
#define ADC_PORT_INVERT_VAL (0x4a342593)
#define MAXIMUM_ADC_CLK (20)
#define PLL_VCO_FREQ_MHZ (800)

365
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
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@ -1,315 +1,326 @@
#pragma once
#define REG_OFFSET (4)
#define REG_OFFSET (4)
/* Base addresses 0x1804 0000 ---------------------------------------------*/
/* Reconfiguration core for readout pll */
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
/* Reconfiguration core for system pll */
#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
#define BASE_SYSTEM_PLL (0x0800) // 0x1804_0800 - 0x1804_0FFF
/* Clock Generation */
#define BASE_CLK_GENERATION (0x1000) // 0x1804_1000 - 0x1804_XXXX //TODO
#define BASE_CLK_GENERATION (0x1000) // 0x1804_1000 - 0x1804_XXXX //TODO
/* Base addresses 0x1806 0000 ---------------------------------------------*/
/* General purpose control and status registers */
#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF
#define BASE_CONTROL (0x0000) // 0x1806_0000 - 0x1806_00FF
// https://git.psi.ch/sls_detectors_firmware/mythen_III_mcb/blob/master/code/hdl/ctrl/ctrl.vhd
/* ASIC Control */
#define BASE_ASIC (0x0100) // 0x1806_0100 - 0x1806_010F
#define BASE_ASIC (0x0100) // 0x1806_0100 - 0x1806_010F
/* ASIC Digital Interface. Data recovery core */
#define BASE_ADIF (0x0110) // 0x1806_0110 - 0x1806_011F
#define BASE_ADIF (0x0110) // 0x1806_0110 - 0x1806_011F
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/adif/adif_ctrl.vhd
/* Formatting of data core */
#define BASE_FMT (0x0120) // 0x1806_0120 - 0x1806_012F
#define BASE_FMT (0x0120) // 0x1806_0120 - 0x1806_012F
/* Packetizer */
#define BASE_PKT (0x0140) // 0x1806_0140 - 0x1806_014F
#define BASE_PKT (0x0140) // 0x1806_0140 - 0x1806_014F
// https://git.psi.ch/sls_detectors_firmware/mythen_III_mcb/blob/master/code/hdl/pkt/pkt_ctrl.vhd
/* Pattern control and status registers */
#define BASE_PATTERN_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
#define BASE_PATTERN_CONTROL (0x00200) // 0x1806_0200 - 0x1806_02FF
// https://git.psi.ch/sls_detectors_firmware/vhdl_library/blob/2e81ccbdbc5cb81813ba190fbdba43e8d6884eb9/pattern_flow/pattern_flow_ctrl.vhd
/* UDP datagram generator */
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
/* Pattern RAM. Pattern table */
#define BASE_PATTERN_RAM (0x10000) // 0x1807_0000 - 0x1807_FFFF
/* Clock Generation registers ------------------------------------------------------*/
#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
#define PLL_RESET_READOUT_OFST (0)
#define PLL_RESET_READOUT_MSK (0x00000001 << PLL_RESET_READOUT_OFST)
#define PLL_RESET_SYSTEM_OFST (1)
#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
#define BASE_PATTERN_RAM (0x10000) // 0x1807_0000 - 0x1807_FFFF
/* Clock Generation registers
* ------------------------------------------------------*/
#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
#define PLL_RESET_READOUT_OFST (0)
#define PLL_RESET_READOUT_MSK (0x00000001 << PLL_RESET_READOUT_OFST)
#define PLL_RESET_SYSTEM_OFST (1)
#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
/* Control registers --------------------------------------------------*/
/* Module Control Board Serial Number Register */
#define MCB_SERIAL_NO_REG (0x00 * REG_OFFSET + BASE_CONTROL)
#define MCB_SERIAL_NO_REG (0x00 * REG_OFFSET + BASE_CONTROL)
#define MCB_SERIAL_NO_VRSN_OFST (16)
#define MCB_SERIAL_NO_VRSN_MSK (0x0000001F << MCB_SERIAL_NO_VRSN_OFST)
#define MCB_SERIAL_NO_VRSN_OFST (16)
#define MCB_SERIAL_NO_VRSN_MSK (0x0000001F << MCB_SERIAL_NO_VRSN_OFST)
/* FPGA Version register */
#define FPGA_VERSION_REG (0x01 * REG_OFFSET + BASE_CONTROL)
#define FPGA_COMPILATION_DATE_OFST (0)
#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
#define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
#define FPGA_VERSION_REG (0x01 * REG_OFFSET + BASE_CONTROL)
#define FPGA_COMPILATION_DATE_OFST (0)
#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
#define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
/* API Version Register */
#define API_VERSION_REG (0x02 * REG_OFFSET + BASE_CONTROL)
#define API_VERSION_REG (0x02 * REG_OFFSET + BASE_CONTROL)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK \
(0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
/* Fix pattern register */
#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
#define FIX_PATT_VAL (0xACDC2019)
#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
#define FIX_PATT_VAL (0xACDC2019)
/* Status register */
#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL)
#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL)
/* Look at me register, read only */
#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL) //Not used in firmware or software, good to play with
#define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL) //Not used in software
#define LOOK_AT_ME_REG \
(0x05 * REG_OFFSET + \
BASE_CONTROL) // Not used in firmware or software, good to play with
#define SYSTEM_STATUS_REG \
(0x06 * REG_OFFSET + BASE_CONTROL) // Not used in software
/* Config RW regiseter */
#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL)
#define CONFIG_COUNTER_ENA_OFST (0)
#define CONFIG_COUNTER_ENA_MSK (0x00000003 << CONFIG_COUNTER_ENA_OFST)
#define CONFIG_COUNTER_ENA_DEFAULT_VAL ((0x0 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_1_VAL ((0x1 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_2_VAL ((0x2 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_ALL_VAL ((0x3 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_DYNAMIC_RANGE_OFST (4)
#define CONFIG_DYNAMIC_RANGE_MSK (0x00000003 << CONFIG_DYNAMIC_RANGE_OFST)
#define CONFIG_DYNAMIC_RANGE_1_VAL ((0x0 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_4_VAL ((0x1 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_16_VAL ((0x2 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_24_VAL ((0x3 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL)
#define CONFIG_COUNTER_ENA_OFST (0)
#define CONFIG_COUNTER_ENA_MSK (0x00000003 << CONFIG_COUNTER_ENA_OFST)
#define CONFIG_COUNTER_ENA_DEFAULT_VAL \
((0x0 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_1_VAL \
((0x1 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_2_VAL \
((0x2 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_ALL_VAL \
((0x3 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_DYNAMIC_RANGE_OFST (4)
#define CONFIG_DYNAMIC_RANGE_MSK (0x00000003 << CONFIG_DYNAMIC_RANGE_OFST)
#define CONFIG_DYNAMIC_RANGE_1_VAL \
((0x0 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_4_VAL \
((0x1 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_16_VAL \
((0x2 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_24_VAL \
((0x3 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
/* Control RW register */
#define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL)
#define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
#define CONTROL_PWR_CHIP_OFST (31)
#define CONTROL_PWR_CHIP_MSK (0x00000001 << CONTROL_PWR_CHIP_OFST)
#define CONTROL_STRT_ACQSTN_OFST (0)
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
#define CONTROL_PWR_CHIP_OFST (31)
#define CONTROL_PWR_CHIP_MSK (0x00000001 << CONTROL_PWR_CHIP_OFST)
/* Pattern IO Control 64 bit register */
#define PATTERN_IO_CTRL_LSB_REG (0x22 * REG_OFFSET + BASE_CONTROL)
#define PATTERN_IO_CTRL_MSB_REG (0x23 * REG_OFFSET + BASE_CONTROL)
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
#define PATTERN_IO_CTRL_LSB_REG (0x22 * REG_OFFSET + BASE_CONTROL)
#define PATTERN_IO_CTRL_MSB_REG (0x23 * REG_OFFSET + BASE_CONTROL)
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
/* Packetizer -------------------------------------------------------------*/
/* Packetizer Config Register */
#define PKT_CONFIG_REG (0x00 * REG_OFFSET + BASE_PKT)
#define PKT_CONFIG_REG (0x00 * REG_OFFSET + BASE_PKT)
#define PKT_CONFIG_NRXR_MAX_OFST (0)
#define PKT_CONFIG_NRXR_MAX_MSK (0x0000003F << PKT_CONFIG_NRXR_MAX_OFST)
#define PKT_CONFIG_RXR_START_ID_OFST (8)
#define PKT_CONFIG_RXR_START_ID_MSK (0x0000003F << PKT_CONFIG_RXR_START_ID_OFST)
#define PKT_CONFIG_NRXR_MAX_OFST (0)
#define PKT_CONFIG_NRXR_MAX_MSK (0x0000003F << PKT_CONFIG_NRXR_MAX_OFST)
#define PKT_CONFIG_RXR_START_ID_OFST (8)
#define PKT_CONFIG_RXR_START_ID_MSK (0x0000003F << PKT_CONFIG_RXR_START_ID_OFST)
/* Module Coordinates Register */
#define COORD_0_REG (0x02 * REG_OFFSET + BASE_PKT)
#define COORD_ROW_OFST (0)
#define COORD_ROW_MSK (0x0000FFFF << COORD_ROW_OFST)
#define COORD_COL_OFST (16)
#define COORD_COL_MSK (0x0000FFFF << COORD_COL_OFST)
#define COORD_0_REG (0x02 * REG_OFFSET + BASE_PKT)
#define COORD_ROW_OFST (0)
#define COORD_ROW_MSK (0x0000FFFF << COORD_ROW_OFST)
#define COORD_COL_OFST (16)
#define COORD_COL_MSK (0x0000FFFF << COORD_COL_OFST)
/* Module ID Register */
#define COORD_1_REG (0x03 * REG_OFFSET + BASE_PKT)
#define COORD_RESERVED_OFST (0)
#define COORD_RESERVED_MSK (0x0000FFFF << COORD_RESERVED_OFST)
#define COORD_ID_OFST (16) // Not connected in firmware TODO
#define COORD_ID_MSK (0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
#define COORD_1_REG (0x03 * REG_OFFSET + BASE_PKT)
#define COORD_RESERVED_OFST (0)
#define COORD_RESERVED_MSK (0x0000FFFF << COORD_RESERVED_OFST)
#define COORD_ID_OFST (16) // Not connected in firmware TODO
#define COORD_ID_MSK \
(0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
/* Pattern Control registers --------------------------------------------------*/
/* Pattern Control registers
* --------------------------------------------------*/
/* Pattern status Register*/
#define PAT_STATUS_REG (0x00 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PAT_STATUS_RUN_BUSY_OFST (0)
#define PAT_STATUS_RUN_BUSY_MSK (0x00000001 << PAT_STATUS_RUN_BUSY_OFST)
#define PAT_STATUS_WAIT_FOR_TRGGR_OFST (3)
#define PAT_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << PAT_STATUS_WAIT_FOR_TRGGR_OFST)
#define PAT_STATUS_DLY_BFRE_TRGGR_OFST (4)
#define PAT_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_BFRE_TRGGR_OFST)
#define PAT_STATUS_FIFO_FULL_OFST (5)
#define PAT_STATUS_FIFO_FULL_MSK (0x00000001 << PAT_STATUS_FIFO_FULL_OFST)
#define PAT_STATUS_DLY_AFTR_TRGGR_OFST (15)
#define PAT_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_AFTR_TRGGR_OFST)
#define PAT_STATUS_CSM_BUSY_OFST (17)
#define PAT_STATUS_CSM_BUSY_MSK (0x00000001 << PAT_STATUS_CSM_BUSY_OFST)
#define PAT_STATUS_REG (0x00 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PAT_STATUS_RUN_BUSY_OFST (0)
#define PAT_STATUS_RUN_BUSY_MSK (0x00000001 << PAT_STATUS_RUN_BUSY_OFST)
#define PAT_STATUS_WAIT_FOR_TRGGR_OFST (3)
#define PAT_STATUS_WAIT_FOR_TRGGR_MSK \
(0x00000001 << PAT_STATUS_WAIT_FOR_TRGGR_OFST)
#define PAT_STATUS_DLY_BFRE_TRGGR_OFST (4)
#define PAT_STATUS_DLY_BFRE_TRGGR_MSK \
(0x00000001 << PAT_STATUS_DLY_BFRE_TRGGR_OFST)
#define PAT_STATUS_FIFO_FULL_OFST (5)
#define PAT_STATUS_FIFO_FULL_MSK (0x00000001 << PAT_STATUS_FIFO_FULL_OFST)
#define PAT_STATUS_DLY_AFTR_TRGGR_OFST (15)
#define PAT_STATUS_DLY_AFTR_TRGGR_MSK \
(0x00000001 << PAT_STATUS_DLY_AFTR_TRGGR_OFST)
#define PAT_STATUS_CSM_BUSY_OFST (17)
#define PAT_STATUS_CSM_BUSY_MSK (0x00000001 << PAT_STATUS_CSM_BUSY_OFST)
/* Delay left 64bit Register */
#define GET_DELAY_LSB_REG (0x02 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_DELAY_MSB_REG (0x03 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_DELAY_LSB_REG (0x02 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_DELAY_MSB_REG (0x03 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Triggers left 64bit Register */
#define GET_CYCLES_LSB_REG (0x04 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_CYCLES_MSB_REG (0x05 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_CYCLES_LSB_REG (0x04 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_CYCLES_MSB_REG (0x05 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Frames left 64bit Register */
#define GET_FRAMES_LSB_REG (0x06 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_FRAMES_MSB_REG (0x07 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_FRAMES_LSB_REG (0x06 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_FRAMES_MSB_REG (0x07 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Period left 64bit Register */
#define GET_PERIOD_LSB_REG (0x08 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_PERIOD_MSB_REG (0x09 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_PERIOD_LSB_REG (0x08 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define GET_PERIOD_MSB_REG (0x09 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Time from Start 64 bit register */
#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_PATTERN_CONTROL)
#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_PATTERN_CONTROL)
#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_PATTERN_CONTROL)
#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_PATTERN_CONTROL)
#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Get Frames from Start 64 bit register (frames from last reset using
* CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_PATTERN_CONTROL)
#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Measurement Time 64 bit register (timestamp at a frame start until reset)*/
#define START_FRAME_TIME_LSB_REG (0x0E * REG_OFFSET + BASE_PATTERN_CONTROL)
#define START_FRAME_TIME_MSB_REG (0x0F * REG_OFFSET + BASE_PATTERN_CONTROL)
#define START_FRAME_TIME_LSB_REG (0x0E * REG_OFFSET + BASE_PATTERN_CONTROL)
#define START_FRAME_TIME_MSB_REG (0x0F * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Delay 64bit Write-register */
#define SET_DELAY_LSB_REG (0x22 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_DELAY_MSB_REG (0x23 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_DELAY_LSB_REG (0x22 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_DELAY_MSB_REG (0x23 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Cylces 64bit Write-register */
#define SET_CYCLES_LSB_REG (0x24 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_CYCLES_MSB_REG (0x25 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_CYCLES_LSB_REG (0x24 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_CYCLES_MSB_REG (0x25 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Frames 64bit Write-register */
#define SET_FRAMES_LSB_REG (0x26 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_FRAMES_MSB_REG (0x27 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_FRAMES_LSB_REG (0x26 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_FRAMES_MSB_REG (0x27 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Period 64bit Write-register */
#define SET_PERIOD_LSB_REG (0x28 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_PERIOD_MSB_REG (0x29 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_PERIOD_LSB_REG (0x28 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_PERIOD_MSB_REG (0x29 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* External Signal register */
#define EXT_SIGNAL_REG (0x30 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define EXT_SIGNAL_REG (0x30 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
/* Trigger Delay 64 bit register */
#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_TRIGGER_DELAY_MSB_REG (0x33 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_TRIGGER_DELAY_LSB_REG (0x32 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define SET_TRIGGER_DELAY_MSB_REG (0x33 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Limit RW Register */
#define PATTERN_LIMIT_REG (0x40 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LIMIT_REG (0x40 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
#define PATTERN_LIMIT_STRT_OFST (0)
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
#define PATTERN_LIMIT_STP_OFST (16)
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
/** Pattern Mask 64 bit RW regiser */
#define PATTERN_MASK_LSB_REG (0x42 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_MASK_MSB_REG (0x43 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_MASK_LSB_REG (0x42 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_MASK_MSB_REG (0x43 * REG_OFFSET + BASE_PATTERN_CONTROL)
/** Pattern Set 64 bit RW regiser */
#define PATTERN_SET_LSB_REG (0x44 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_SET_MSB_REG (0x45 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_SET_LSB_REG (0x44 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_SET_MSB_REG (0x45 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Wait Timer 0 64bit RW Register */
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x60 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x61 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x60 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x61 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Wait 0 RW Register*/
#define PATTERN_WAIT_0_ADDR_REG (0x62 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_0_ADDR_REG (0x62 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
#define PATTERN_WAIT_0_ADDR_OFST (0)
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
/* Pattern Loop 0 Iteration RW Register */
#define PATTERN_LOOP_0_ITERATION_REG (0x63 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_0_ITERATION_REG (0x63 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Loop 0 Address RW Register */
#define PATTERN_LOOP_0_ADDR_REG (0x64 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_0_ADDR_REG (0x64 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
/* Pattern Wait Timer 1 64bit RW Register */
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x65 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x66 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x65 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x66 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Wait 1 RW Register*/
#define PATTERN_WAIT_1_ADDR_REG (0x67 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_1_ADDR_REG (0x67 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
#define PATTERN_WAIT_1_ADDR_OFST (0)
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
/* Pattern Loop 1 Iteration RW Register */
#define PATTERN_LOOP_1_ITERATION_REG (0x68 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_1_ITERATION_REG (0x68 * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Loop 1 Address RW Register */
#define PATTERN_LOOP_1_ADDR_REG (0x69 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_1_ADDR_REG (0x69 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
/* Pattern Wait Timer 2 64bit RW Register */
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x6A * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x6B * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x6A * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x6B * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Wait 2 RW Register*/
#define PATTERN_WAIT_2_ADDR_REG (0x6C * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_2_ADDR_REG (0x6C * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
#define PATTERN_WAIT_2_ADDR_OFST (0)
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
/* Pattern Loop 2 Iteration RW Register */
#define PATTERN_LOOP_2_ITERATION_REG (0x6D * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_2_ITERATION_REG (0x6D * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Pattern Loop 0 Address RW Register */
#define PATTERN_LOOP_2_ADDR_REG (0x6E * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
#define PATTERN_LOOP_2_ADDR_REG (0x6E * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern RAM registers --------------------------------------------------*/
/* Register of first word */
#define PATTERN_STEP0_LSB_REG (0x0 * REG_OFFSET + BASE_PATTERN_RAM)
#define PATTERN_STEP0_MSB_REG (0x1 * REG_OFFSET + BASE_PATTERN_RAM)
#define PATTERN_STEP0_LSB_REG (0x0 * REG_OFFSET + BASE_PATTERN_RAM)
#define PATTERN_STEP0_MSB_REG (0x1 * REG_OFFSET + BASE_PATTERN_RAM)

178
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
View File

@ -1,100 +1,128 @@
#pragma once
#include "sls_detector_defs.h"
#define REQRD_FRMWRE_VRSN 0x190000
#define REQRD_FRMWRE_VRSN 0x190000
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
/* Hardware Definitions */
#define NCOUNTERS (3)
#define MAX_COUNTER_MSK (0x7)
#define NCHAN_1_COUNTER (128)
#define NCHAN (128 * NCOUNTERS)
#define NCHIP (10)
#define NDAC (16)
#define NCOUNTERS (3)
#define MAX_COUNTER_MSK (0x7)
#define NCHAN_1_COUNTER (128)
#define NCHAN (128 * NCOUNTERS)
#define NCHIP (10)
#define NDAC (16)
#define HV_SOFT_MAX_VOLTAGE (200)
#define HV_HARD_MAX_VOLTAGE (530)
#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
#define DAC_DRIVER_FILE_NAME ("/etc/devlinks/dac")
#define TYPE_FILE_NAME ("/etc/devlinks/type")
#define TYPE_FILE_NAME ("/etc/devlinks/type")
#define DAC_MAX_MV (2048)
#define TYPE_MYTHEN3_MODULE_VAL (93)
#define TYPE_TOLERANCE (10)
#define TYPE_NO_MODULE_STARTING_VAL (800)
#define TYPE_MYTHEN3_MODULE_VAL (93)
#define TYPE_TOLERANCE (10)
#define TYPE_NO_MODULE_STARTING_VAL (800)
/** Default Parameters */
#define DEFAULT_DYNAMIC_RANGE (24)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (100*1000*1000) //ns
#define DEFAULT_PERIOD (2*1000*1000) //ns
#define DEFAULT_DYNAMIC_RANGE (24)
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (100 * 1000 * 1000) // ns
#define DEFAULT_PERIOD (2 * 1000 * 1000) // ns
#define DEFAULT_DELAY_AFTER_TRIGGER (0)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_READOUT_C0 (10)//(125000000) // rdo_clk, 125 MHz
#define DEFAULT_READOUT_C1 (10)//(125000000) // rdo_x2_clk, 125 MHz
#define DEFAULT_SYSTEM_C0 (5)//(250000000) // run_clk, 250 MHz
#define DEFAULT_SYSTEM_C1 (10)//(125000000) // chip_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (10)//(125000000) // sync_clk, 125 MHz
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_READOUT_C0 (10) //(125000000) // rdo_clk, 125 MHz
#define DEFAULT_READOUT_C1 (10) //(125000000) // rdo_x2_clk, 125 MHz
#define DEFAULT_SYSTEM_C0 (5) //(250000000) // run_clk, 250 MHz
#define DEFAULT_SYSTEM_C1 (10) //(125000000) // chip_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (10) //(125000000) // sync_clk, 125 MHz
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
#define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
#define SYSTEM_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
#define READOUT_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
#define SYSTEM_PLL_VCO_FREQ_HZ (1250000000) // 1.25GHz
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
/** Other Definitions */
#define BIT16_MASK (0xFFFF)
#define BIT16_MASK (0xFFFF)
/* Enums */
enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3, M_VTH1, M_VICIN, M_CAS, M_VRF, M_VPL, M_VIPRE, M_VIINSH, M_VPH, M_VTRIM, M_VDCSH};
#define DAC_NAMES "vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1", "vicin", "vcas", "vpreamp", "vpl", "vipre", "viinsh", "vph", "vtrim", "vdcsh"
#define DEFAULT_DAC_VALS {1200, /* casSh */ \
2800, /* Vth2 */ \
1280, /* VrfSh */ \
2800, /* VrfShNpol */ \
1220, /* vIpreOut */ \
2800, /* Vth3 */ \
2800, /* Vth1 */ \
1708, /* vIcin */ \
1800, /* cas */ \
1100, /* Vrf */ \
1100, /* VPL */ \
2624, /* vIpre */ \
1708, /* vIinSh */ \
1712, /* VPH */ \
2800, /* vTrim */ \
800 /* VdcSh */ \
};
enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, NUM_CLOCKS};
#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
enum PLLINDEX {READOUT_PLL, SYSTEM_PLL};
enum DACINDEX {
M_CASSH,
M_VTH2,
M_VRFSH,
M_VRFSHNPOL,
M_VIPRE_OUT,
M_VTH3,
M_VTH1,
M_VICIN,
M_CAS,
M_VRF,
M_VPL,
M_VIPRE,
M_VIINSH,
M_VPH,
M_VTRIM,
M_VDCSH
};
#define DAC_NAMES \
"vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1", \
"vicin", "vcas", "vpreamp", "vpl", "vipre", "viinsh", "vph", "vtrim", \
"vdcsh"
#define DEFAULT_DAC_VALS \
{ \
1200, /* casSh */ \
2800, /* Vth2 */ \
1280, /* VrfSh */ \
2800, /* VrfShNpol */ \
1220, /* vIpreOut */ \
2800, /* Vth3 */ \
2800, /* Vth1 */ \
1708, /* vIcin */ \
1800, /* cas */ \
1100, /* Vrf */ \
1100, /* VPL */ \
2624, /* vIpre */ \
1708, /* vIinSh */ \
1712, /* VPH */ \
2800, /* vTrim */ \
800 /* VdcSh */ \
};
enum CLKINDEX {
READOUT_C0,
READOUT_C1,
SYSTEM_C0,
SYSTEM_C1,
SYSTEM_C2,
NUM_CLOCKS
};
#define CLK_NAMES \
"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
/* Struct Definitions */
typedef struct udp_header_struct {
uint32_t udp_destmac_msb;
uint16_t udp_srcmac_msb;
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl: 4, ip_ver: 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
uint16_t ip_srcip_lsb;
uint16_t udp_srcport;
uint16_t ip_destip_lsb;
uint16_t udp_checksum;
uint16_t udp_destport;
uint32_t udp_destmac_msb;
uint16_t udp_srcmac_msb;
uint16_t udp_destmac_lsb;
uint32_t udp_srcmac_lsb;
uint8_t ip_tos;
uint8_t ip_ihl : 4, ip_ver : 4;
uint16_t udp_ethertype;
uint16_t ip_identification;
uint16_t ip_totallength;
uint8_t ip_protocol;
uint8_t ip_ttl;
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
uint16_t ip_srcip_msb;
uint16_t ip_checksum;
uint16_t ip_destip_msb;
uint16_t ip_srcip_lsb;
uint16_t udp_srcport;
uint16_t ip_destip_lsb;
uint16_t udp_checksum;
uint16_t udp_destport;
} udp_header;
#define UDP_IP_HEADER_LENGTH_BYTES (28)
#define PACKETS_PER_FRAME (2)
#define UDP_IP_HEADER_LENGTH_BYTES (28)
#define PACKETS_PER_FRAME (2)

3
slsDetectorServers/slsDetectorServer/include/AD7689.h Executable file → Normal file
View File

@ -11,7 +11,8 @@
* @param dmsk digital output mask
* @param dofst digital output offset
*/
void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst);
void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk,
uint32_t clkmsk, uint32_t dmsk, int dofst);
/**
* Disable SPI

3
slsDetectorServers/slsDetectorServer/include/AD9252.h Executable file → Normal file
View File

@ -10,7 +10,8 @@
* @param dmsk digital output mask
* @param dofst digital output offset
*/
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst);
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst);
/**
* Disable SPI

8
slsDetectorServers/slsDetectorServer/include/AD9257.h Executable file → Normal file
View File

@ -10,12 +10,13 @@
* @param dmsk digital output mask
* @param dofst digital output offset
*/
void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst);
void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst);
/**
* Disable SPI
*/
void AD9257_Disable() ;
void AD9257_Disable();
/**
* Get vref voltage
@ -24,7 +25,8 @@ int AD9257_GetVrefVoltage(int mV);
/**
* Set vref voltage
* @param val voltage to be set (0 for 1.0V, 1 for 1.14V, 2 for 1.33V, 3 for 1.6V, 4 for 2.0V
* @param val voltage to be set (0 for 1.0V, 1 for 1.14V, 2 for 1.33V, 3
* for 1.6V, 4 for 2.0V
* @returns ok or fail
*/
int AD9257_SetVrefVoltage(int val, int mV);

21
slsDetectorServers/slsDetectorServer/include/ALTERA_PLL.h Executable file → Normal file
View File

@ -15,7 +15,9 @@
* @param wd2msk write parameter mask for pll for dbit clock (Jungfrau only)
* @param clk2Index clkIndex of second pll (Jungfrau only)
*/
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst, uint32_t wd2msk, int clk2Index);
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst, uint32_t wd2msk, int clk2Index);
#else
/**
* Set Defines
@ -27,26 +29,30 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32
* @param amsk address mask
* @param aofst address offset
*/
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst);
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst);
#endif
/**
* Reset only PLL
*/
void ALTERA_PLL_ResetPLL ();
void ALTERA_PLL_ResetPLL();
/**
* Reset PLL Reconfiguration and PLL
*/
void ALTERA_PLL_ResetPLLAndReconfiguration ();
void ALTERA_PLL_ResetPLLAndReconfiguration();
/**
* Set PLL Reconfig register
* @param reg register
* @param val value
* @param useDefaultWRMask only jungfrau for dbit clk (clkindex1, use second WR mask)
* @param useDefaultWRMask only jungfrau for dbit clk (clkindex1, use second WR
* mask)
*/
void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val, int useSecondWRMask);
void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
int useSecondWRMask);
/**
* Write Phase Shift
@ -67,5 +73,4 @@ void ALTERA_PLL_SetModePolling();
* @param value frequency to set to
* @param frequency set
*/
int ALTERA_PLL_SetOuputFrequency (int clkIndex, int pllVCOFreqMhz, int value);
int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value);

13
slsDetectorServers/slsDetectorServer/include/ALTERA_PLL_CYCLONE10.h Executable file → Normal file
View File

@ -14,7 +14,10 @@
* @param vcofreq0 vco frequency of pll 0
* @param vcofreq1 vco frequency of pll 1
*/
void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0, uint32_t baseaddr1, uint32_t resetreg0, uint32_t resetreg1, uint32_t resetmsk0, uint32_t resetmsk1, int vcofreq0, int vcofreq1);
void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0,
uint32_t baseaddr1, uint32_t resetreg0,
uint32_t resetreg1, uint32_t resetmsk0,
uint32_t resetmsk1, int vcofreq0, int vcofreq1);
/**
* Get Max Clock Divider
@ -44,7 +47,7 @@ void ALTERA_PLL_C10_Reconfigure(int pllIndex);
* Reset pll
* @param pllIndex pll index
*/
void ALTERA_PLL_C10_ResetPLL (int pllIndex);
void ALTERA_PLL_C10_ResetPLL(int pllIndex);
/**
* Set Phase Shift
@ -53,7 +56,8 @@ void ALTERA_PLL_C10_ResetPLL (int pllIndex);
* @param phase phase shift
* @param pos 1 if up down direction of shift is positive, else 0
*/
void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos);
void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase,
int pos);
/**
* Calculate and write output frequency
@ -61,5 +65,4 @@ void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos
* @param clkIndex clock index
* @param value clock divider to set to
*/
void ALTERA_PLL_C10_SetOuputClockDivider (int pllIndex, int clkIndex, int value);
void ALTERA_PLL_C10_SetOuputClockDivider(int pllIndex, int clkIndex, int value);

4
slsDetectorServers/slsDetectorServer/include/ASIC_Driver.h Executable file → Normal file
View File

@ -6,7 +6,7 @@
* Set Defines
* @param driverfname driver file name
*/
void ASIC_Driver_SetDefines(char* driverfname);
void ASIC_Driver_SetDefines(char *driverfname);
/**
* Set value
@ -15,4 +15,4 @@ void ASIC_Driver_SetDefines(char* driverfname);
* @param buffer buffer
* @return OK or FAIL
*/
int ASIC_Driver_Set(int index, int length, char* buffer);
int ASIC_Driver_Set(int index, int length, char *buffer);

7
slsDetectorServers/slsDetectorServer/include/DAC6571.h Executable file → Normal file
View File

@ -7,14 +7,11 @@
* @param hardMaxV maximum hardware limit
* @param driverfname driver file name
*/
void DAC6571_SetDefines(int hardMaxV, char* driverfname);
void DAC6571_SetDefines(int hardMaxV, char *driverfname);
/**
* Set value
* @param val value to set
* @return OK or FAIL
*/
int DAC6571_Set (int val) ;
int DAC6571_Set(int val);

8
slsDetectorServers/slsDetectorServer/include/I2C.h Executable file → Normal file
View File

@ -15,9 +15,9 @@
* @param sdreg sda hold register (defined in RegisterDefs.h)
* @param treg transfer command fifo register (defined in RegisterDefs.h)
*/
void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg,
uint32_t rreg, uint32_t rlvlreg,
uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg);
void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg, uint32_t rreg,
uint32_t rlvlreg, uint32_t slreg, uint32_t shreg,
uint32_t sdreg, uint32_t treg);
/**
* Read register
@ -34,5 +34,3 @@ uint32_t I2C_Read(uint32_t devId, uint32_t addr);
* @param data data to be written (16 bit)
*/
void I2C_Write(uint32_t devId, uint32_t addr, uint16_t data);

7
slsDetectorServers/slsDetectorServer/include/INA226.h Executable file → Normal file
View File

@ -4,7 +4,8 @@
/**
* Configure the I2C core and Enable core
* @param rOhm shunt resister value in Ohms (defined in slsDetectorServer_defs.h)
* @param rOhm shunt resister value in Ohms (defined in
* slsDetectorServer_defs.h)
* @param creg control register (defined in RegisterDefs.h)
* @param sreg status register (defined in RegisterDefs.h)
* @param rreg rx data fifo register (defined in RegisterDefs.h)
@ -15,8 +16,8 @@
* @param treg transfer command fifo register (defined in RegisterDefs.h)
*/
void INA226_ConfigureI2CCore(double rOhm, uint32_t creg, uint32_t sreg,
uint32_t rreg, uint32_t rlvlreg,
uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg);
uint32_t rreg, uint32_t rlvlreg, uint32_t slreg,
uint32_t shreg, uint32_t sdreg, uint32_t treg);
/**
* Calibrate resolution of current register

19
slsDetectorServers/slsDetectorServer/include/LTC2620.h Executable file → Normal file
View File

@ -9,11 +9,13 @@
* @param clkmsk clock output mask
* @param dmsk digital output mask
* @param dofst digital output offset
* @param nd total number of dacs for this board (for dac channel and daisy chain chip id)
* @param nd total number of dacs for this board (for dac channel and daisy
* chain chip id)
* @param minMV minimum voltage determined by hardware
* @param maxMV maximum voltage determined by hardware
*/
void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst, int nd, int minMV, int maxMV);
void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst, int nd, int minMV, int maxMV);
/**
* Disable SPI
@ -46,7 +48,7 @@ int LTC2620_GetMaxNumSteps();
* @param dacval pointer to value converted to dac units
* @returns FAIL when voltage outside limits, OK if conversion successful
*/
int LTC2620_VoltageToDac(int voltage, int* dacval);
int LTC2620_VoltageToDac(int voltage, int *dacval);
/**
* Convert dac units to voltage
@ -54,7 +56,7 @@ int LTC2620_VoltageToDac(int voltage, int* dacval);
* @param voltage pointer to value converted to mV
* @returns FAIL when voltage outside limits, OK if conversion successful
*/
int LTC2620_DacToVoltage(int dacval, int* voltage);
int LTC2620_DacToVoltage(int dacval, int *voltage);
/**
* Set a single chip (all non ctb detectors use this)
@ -70,7 +72,7 @@ void LTC2620_SetSingle(int cmd, int data, int dacaddr);
* @param valw current value of register while bit banging
* @param val data to be sent (data, dac addr and command)
*/
void LTC2620_SendDaisyData(uint32_t* valw, uint32_t val);
void LTC2620_SendDaisyData(uint32_t *valw, uint32_t val);
/**
* Set a single chip (all non ctb detectors use this)
@ -84,7 +86,8 @@ void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex);
/**
* Sets a single chip (LTC2620_SetSingle) or multiple chip (LTC2620_SetDaisy)
* multiple chip is only for ctb where the multiple chips are connected in daisy fashion
* multiple chip is only for ctb where the multiple chips are connected in daisy
* fashion
* @param cmd command to send
* @param data dac value to be set
* @param dacaddr dac channel number for the chip
@ -102,7 +105,7 @@ void LTC2620_Configure();
* @param dacnum dac number
* @param data dac value to set
*/
void LTC2620_SetDAC (int dacnum, int data);
void LTC2620_SetDAC(int dacnum, int data);
/**
* Set dac in dac units or mV
@ -112,4 +115,4 @@ void LTC2620_SetDAC (int dacnum, int data);
* @param dacval pointer to value in dac units
* @returns OK or FAIL for success of operation
*/
int LTC2620_SetDACValue (int dacnum, int val, int mV, int* dacval);
int LTC2620_SetDACValue(int dacnum, int val, int mV, int *dacval);

10
slsDetectorServers/slsDetectorServer/include/LTC2620_Driver.h Executable file → Normal file
View File

@ -8,8 +8,7 @@
* @param driverfname driver file name
* @param numdacs number of dacs
*/
void LTC2620_D_SetDefines(int hardMaxV, char* driverfname, int numdacs);
void LTC2620_D_SetDefines(int hardMaxV, char *driverfname, int numdacs);
/**
* Get max number of steps
@ -22,7 +21,7 @@ int LTC2620_D_GetMaxNumSteps();
* @param dacval pointer to value converted to dac units
* @returns FAIL when voltage outside limits, OK if conversion successful
*/
int LTC2620_D_VoltageToDac(int voltage, int* dacval);
int LTC2620_D_VoltageToDac(int voltage, int *dacval);
/**
* Convert dac units to voltage
@ -30,7 +29,7 @@ int LTC2620_D_VoltageToDac(int voltage, int* dacval);
* @param voltage pointer to value converted to mV
* @returns FAIL when voltage outside limits, OK if conversion successful
*/
int LTC2620_D_DacToVoltage(int dacval, int* voltage);
int LTC2620_D_DacToVoltage(int dacval, int *voltage);
/**
* Set value
@ -41,4 +40,5 @@ int LTC2620_D_DacToVoltage(int dacval, int* voltage);
* @param dacval pointer to dac value
* @return OK or FAIL
*/
int LTC2620_D_SetDACValue(int dacnum, int val, int mV, char* dacname, int *dacval);
int LTC2620_D_SetDACValue(int dacnum, int val, int mV, char *dacname,
int *dacval);

9
slsDetectorServers/slsDetectorServer/include/MAX1932.h Executable file → Normal file
View File

@ -12,8 +12,8 @@
* @param minMV minimum voltage determined by hardware
* @param maxMV maximum voltage determined by hardware
*/
void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst,
int minMV, int maxMV);
void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst, int minMV, int maxMV);
/**
* Disable SPI
@ -25,7 +25,4 @@ void MAX1932_Disable();
* @param val pointer to value to set
* @return OK or FAIL
*/
int MAX1932_Set (int* val) ;
int MAX1932_Set(int *val);

4
slsDetectorServers/slsDetectorServer/include/UDPPacketHeaderGenerator.h Executable file → Normal file
View File

@ -17,10 +17,10 @@ uint64_t getUDPFrameNumber();
* @param buffer pointer to header
* @param id module id
*/
void createUDPPacketHeader(char* buffer, uint16_t id);
void createUDPPacketHeader(char *buffer, uint16_t id);
/**
* fill up the udp packet with data till its full
* @param buffer pointer to memory
*/
int fillUDPPacket(char* buffer);
int fillUDPPacket(char *buffer);

6
slsDetectorServers/slsDetectorServer/include/blackfin.h Executable file → Normal file
View File

@ -1,10 +1,10 @@
#pragma once
#include <sys/types.h>
#include <inttypes.h>
#include <sys/types.h>
/** I2C defines */
#define I2C_CLOCK_MHZ (131.25)
#define I2C_CLOCK_MHZ (131.25)
/**
* Write into a 16 bit register
@ -98,7 +98,7 @@ u_int32_t writeRegister16(u_int32_t offset, u_int32_t data);
/**
* Get base address for memory copy
*/
uint32_t* Blackfin_getBaseAddress();
uint32_t *Blackfin_getBaseAddress();
/**
* Map FPGA
*/

116
slsDetectorServers/slsDetectorServer/include/clogger.h Executable file → Normal file
View File

@ -2,10 +2,9 @@
#include "ansi.h"
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdlib.h>
#ifdef FIFODEBUG
#define FILELOG_MAX_LEVEL logDEBUG5
@ -21,48 +20,85 @@
#define FILELOG_MAX_LEVEL logINFO
#endif
enum TLogLevel{
logERROR, logWARNING, logINFOBLUE, logINFOGREEN, logINFORED, logINFO,
logDEBUG, logDEBUG1, logDEBUG2, logDEBUG3, logDEBUG4, logDEBUG5
enum TLogLevel {
logERROR,
logWARNING,
logINFOBLUE,
logINFOGREEN,
logINFORED,
logINFO,
logDEBUG,
logDEBUG1,
logDEBUG2,
logDEBUG3,
logDEBUG4,
logDEBUG5
};
#define ERROR_MSG_LENGTH 1000
#define LOG(lvl, fmt, ...) \
if (lvl > FILELOG_MAX_LEVEL); \
else {char* temp = FILELOG_BuildLog fmt; FILELOG_PrintLog(lvl, temp);free(temp);}
#define LOG(lvl, fmt, ...) \
if (lvl > FILELOG_MAX_LEVEL) \
; \
else { \
char *temp = FILELOG_BuildLog fmt; \
FILELOG_PrintLog(lvl, temp); \
free(temp); \
}
static inline void FILELOG_PrintLog(enum TLogLevel level, char* m) {
switch(level) {
case logERROR: cprintf(RED BOLD, "ERROR: %s", m); break;
case logWARNING: cprintf(YELLOW BOLD, "WARNING: %s", m); break;
case logINFOBLUE: cprintf(BLUE, "INFO: %s", m); break;
case logINFOGREEN: cprintf(GREEN, "INFO: %s", m); break;
case logINFORED: cprintf(RED, "INFO: %s", m); break;
case logINFO: cprintf(RESET, "INFO: %s", m); break;
case logDEBUG: cprintf(MAGENTA, "DEBUG: %s", m); break;
case logDEBUG1: cprintf(MAGENTA, "DEBUG1: %s", m); break;
case logDEBUG2: cprintf(MAGENTA, "DEBUG2: %s", m); break;
case logDEBUG3: cprintf(MAGENTA, "DEBUG3: %s", m); break;
case logDEBUG4: cprintf(MAGENTA, "DEBUG4: %s", m); break;
case logDEBUG5: cprintf(MAGENTA, "DEBUG5: %s", m); break;
}
fflush(stdout);
static inline void FILELOG_PrintLog(enum TLogLevel level, char *m) {
switch (level) {
case logERROR:
cprintf(RED BOLD, "ERROR: %s", m);
break;
case logWARNING:
cprintf(YELLOW BOLD, "WARNING: %s", m);
break;
case logINFOBLUE:
cprintf(BLUE, "INFO: %s", m);
break;
case logINFOGREEN:
cprintf(GREEN, "INFO: %s", m);
break;
case logINFORED:
cprintf(RED, "INFO: %s", m);
break;
case logINFO:
cprintf(RESET, "INFO: %s", m);
break;
case logDEBUG:
cprintf(MAGENTA, "DEBUG: %s", m);
break;
case logDEBUG1:
cprintf(MAGENTA, "DEBUG1: %s", m);
break;
case logDEBUG2:
cprintf(MAGENTA, "DEBUG2: %s", m);
break;
case logDEBUG3:
cprintf(MAGENTA, "DEBUG3: %s", m);
break;
case logDEBUG4:
cprintf(MAGENTA, "DEBUG4: %s", m);
break;
case logDEBUG5:
cprintf(MAGENTA, "DEBUG5: %s", m);
break;
}
fflush(stdout);
}
static inline char* FILELOG_BuildLog(const char* fmt, ...) {
char* p;
va_list ap;
p = malloc(ERROR_MSG_LENGTH);
va_start(ap, fmt);
int ret = vsnprintf(p, ERROR_MSG_LENGTH, fmt, ap);
va_end(ap);
if (ret < 0 || ret >= ERROR_MSG_LENGTH) {
FILELOG_PrintLog(logERROR, ("Could not print the "
"complete error message in the next print.\n"));
}
return p;
static inline char *FILELOG_BuildLog(const char *fmt, ...) {
char *p;
va_list ap;
p = malloc(ERROR_MSG_LENGTH);
va_start(ap, fmt);
int ret = vsnprintf(p, ERROR_MSG_LENGTH, fmt, ap);
va_end(ap);
if (ret < 0 || ret >= ERROR_MSG_LENGTH) {
FILELOG_PrintLog(logERROR,
("Could not print the "
"complete error message in the next print.\n"));
}
return p;
};

7
slsDetectorServers/slsDetectorServer/include/common.h Executable file → Normal file
View File

@ -1,7 +1,8 @@
#pragma once
/**
* Convert a value from a range to a different range (eg voltage to dac or vice versa)
* Convert a value from a range to a different range (eg voltage to dac or vice
* versa)
* @param inputMin input minimum
* @param inputMax input maximum
* @param outputMin output minimum
@ -10,5 +11,5 @@
* @param outputValue pointer to output value
* @returns FAIL if input value is out of bounds, else OK
*/
int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin, int outputMax,
int inputValue, int* outputValue);
int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin,
int outputMax, int inputValue, int *outputValue);

21
slsDetectorServers/slsDetectorServer/include/commonServerFunctions.h Executable file → Normal file
View File

@ -2,14 +2,23 @@
#include <inttypes.h>
void SPIChipSelect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask, int convBit);
void SPIChipSelect(uint32_t *valw, uint32_t addr, uint32_t csmask,
uint32_t clkmask, uint32_t digoutmask, int convBit);
void SPIChipDeselect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask, int convBit);
void SPIChipDeselect(uint32_t *valw, uint32_t addr, uint32_t csmask,
uint32_t clkmask, uint32_t digoutmask, int convBit);
void sendDataToSPI (uint32_t* valw, uint32_t addr, uint32_t val, int numbitstosend, uint32_t clkmask, uint32_t digoutmask, int digofset);
void sendDataToSPI(uint32_t *valw, uint32_t addr, uint32_t val,
int numbitstosend, uint32_t clkmask, uint32_t digoutmask,
int digofset);
uint32_t receiveDataFromSPI (uint32_t* valw, uint32_t addr, int numbitstoreceive, uint32_t clkmask, uint32_t readaddr) ;
uint32_t receiveDataFromSPI(uint32_t *valw, uint32_t addr, int numbitstoreceive,
uint32_t clkmask, uint32_t readaddr);
void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask, int numbitstosend, uint32_t clkmask, uint32_t digoutmask, int digofset, int convBit);
void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask,
int numbitstosend, uint32_t clkmask, uint32_t digoutmask,
int digofset, int convBit);
uint32_t serializeFromSPI(uint32_t addr, uint32_t csmask, int numbitstoreceive, uint32_t clkmask, uint32_t digoutmask, uint32_t readaddr, int convBit);
uint32_t serializeFromSPI(uint32_t addr, uint32_t csmask, int numbitstoreceive,
uint32_t clkmask, uint32_t digoutmask,
uint32_t readaddr, int convBit);

42
slsDetectorServers/slsDetectorServer/include/communication_funcs.h Executable file → Normal file
View File

@ -1,22 +1,16 @@
#ifndef COMMUNICATION_FUNCS_H
#define COMMUNICATION_FUNCS_H
#include "sls_detector_defs.h"
typedef enum{
INT16,
INT32,
INT64,
OTHER
}intType;
typedef enum { INT16, INT32, INT64, OTHER } intType;
// communciate with stop server
#ifdef VIRTUAL
#define FILE_STATUS "/tmp/Sls_virtual_server_status_"
#define FILE_STOP "/tmp/Sls_virtual_server_stop_"
#define FD_STATUS 0
#define FD_STOP 1
#define FILE_STOP "/tmp/Sls_virtual_server_stop_"
#define FD_STATUS 0
#define FD_STOP 1
#endif
int bindSocket(unsigned short int port_number);
@ -24,14 +18,14 @@ int acceptConnection(int socketDescriptor);
void closeConnection(int file_Des);
void exitServer(int socketDescriptor);
void swapData(void* val,int length,intType itype);
int sendData(int file_des, void* buf,int length, intType itype);
int receiveData(int file_des, void* buf,int length, intType itype);
int sendDataOnly(int file_des, void* buf,int length);
int receiveDataOnly(int file_des, void* buf,int length);
void swapData(void *val, int length, intType itype);
int sendData(int file_des, void *buf, int length, intType itype);
int receiveData(int file_des, void *buf, int length, intType itype);
int sendDataOnly(int file_des, void *buf, int length);
int receiveDataOnly(int file_des, void *buf, int length);
int sendModule(int file_des, sls_detector_module *myMod);
int receiveModule(int file_des, sls_detector_module* myMod);
int receiveModule(int file_des, sls_detector_module *myMod);
/**
* Servers sets and prints error message for locked server
@ -39,7 +33,6 @@ int receiveModule(int file_des, sls_detector_module* myMod);
*/
void Server_LockedError();
/**
* Server verifies if it is unlocked,
* sets and prints appropriate message if it is locked and different clients
@ -47,16 +40,17 @@ void Server_LockedError();
*/
int Server_VerifyLock();
/**
* Server sends result to client (also set ret to force_update if different clients)
* Server sends result to client (also set ret to force_update if different
* clients)
* @param fileDes file descriptor for the socket
* @param itype 32 or 64 or others to determine to swap data from big endian to little endian
* @param itype 32 or 64 or others to determine to swap data from big endian to
* little endian
* @param retval pointer to result
* @param retvalSize size of result
* @returns result of operation
*/
int Server_SendResult(int fileDes, intType itype, void* retval, int retvalSize);
int Server_SendResult(int fileDes, intType itype, void *retval, int retvalSize);
/**
* Convert mac address from integer to char array
@ -64,20 +58,20 @@ int Server_SendResult(int fileDes, intType itype, void* retval, int retvalSize);
* @param size size of char array result
* @param mac mac address as an integer
*/
void getMacAddressinString(char* cmac, int size, uint64_t mac);
void getMacAddressinString(char *cmac, int size, uint64_t mac);
/**
* Convert ip address from integer to char array
* @param cip char arrary result
* @param ip ip address as an integer
*/
void getIpAddressinString(char* cip, uint32_t ip);
void getIpAddressinString(char *cip, uint32_t ip);
/**
* Convert string to ip address
* @param cip string source
* @param ip result
*/
void getIpAddressFromString(char* cip, uint32_t* ip);
void getIpAddressFromString(char *cip, uint32_t *ip);
#endif

5
slsDetectorServers/slsDetectorServer/include/communication_funcs_UDP.h Executable file → Normal file
View File

@ -11,7 +11,8 @@ int getUdPSocketDescriptor(int index);
* @param ip udp destination ip
* @param port udp destination port
*/
int setUDPDestinationDetails(int index, const char* ip, unsigned short int port);
int setUDPDestinationDetails(int index, const char *ip,
unsigned short int port);
/**
* Create udp socket
@ -25,7 +26,7 @@ int createUDPSocket(int index);
* @param buf pointer to memory to write
* @param length length of buffer to write to socket
*/
int sendUDPPacket(int index, const char* buf, int length);
int sendUDPPacket(int index, const char *buf, int length);
/**
* Close udp socket

6
slsDetectorServers/slsDetectorServer/include/communication_virtual.h Executable file → Normal file
View File

@ -8,7 +8,9 @@ void ComVirtual_setStatus(int value);
int ComVirtual_getStatus();
void ComVirtual_setStop(int value);
int ComVirtual_getStop();
int ComVirtual_writeToFile(int value, const char* fname, const char* serverName);
int ComVirtual_readFromFile(int* value, const char* fname, const char* serverName);
int ComVirtual_writeToFile(int value, const char *fname,
const char *serverName);
int ComVirtual_readFromFile(int *value, const char *fname,
const char *serverName);
#endif

4
slsDetectorServers/slsDetectorServer/include/nios.h Executable file → Normal file
View File

@ -1,7 +1,7 @@
#pragma once
#include <sys/types.h>
#include <inttypes.h>
#include <sys/types.h>
/**
* Write into a 32 bit register for cspbase 1
@ -86,4 +86,4 @@ int mapCSP0(void);
/**
* Get Nios base address
*/
u_int32_t* Nios_getBaseAddress();
u_int32_t *Nios_getBaseAddress();

8
slsDetectorServers/slsDetectorServer/include/programFpgaBlackfin.h Executable file → Normal file
View File

@ -1,7 +1,7 @@
#pragma once
#include <stdio.h>
#include <stdint.h>
#include <stdio.h>
/**
* Define GPIO pins if not defined
@ -34,14 +34,14 @@ void eraseFlash();
* @param filefp pointer to flash
* @return 0 for success, 1 for fail (cannot open file for writing program)
*/
int startWritingFPGAprogram(FILE** filefp);
int startWritingFPGAprogram(FILE **filefp);
/**
* When done writing the program, close file pointer and
* notify FPGA to pick up the program from flash
* @param filefp pointer to flash
*/
void stopWritingFPGAprogram(FILE* filefp);
void stopWritingFPGAprogram(FILE *filefp);
/**
* Write FPGA Program to flash
@ -50,4 +50,4 @@ void stopWritingFPGAprogram(FILE* filefp);
* @param filefp pointer to flash
* @return 0 for success, 1 for fail (cannot write)
*/
int writeFPGAProgram(char* fpgasrc, uint64_t fsize, FILE* filefp);
int writeFPGAProgram(char *fpgasrc, uint64_t fsize, FILE *filefp);

13
slsDetectorServers/slsDetectorServer/include/programFpgaNios.h Executable file → Normal file
View File

@ -1,14 +1,15 @@
#pragma once
#include <stdio.h>
#include <stdint.h>
#include <stdio.h>
#define NIOS_MAX_APP_IMAGE_SIZE (0x00580000)
/** Notify microcontroller of successful server start up */
void NotifyServerStartSuccess();
/** create notification file to notify watchdog of critical tasks (to not shutdown) */
/** create notification file to notify watchdog of critical tasks (to not
* shutdown) */
void CreateNotificationForCriticalTasks();
/** write 1 to notification file to postpone shut down process if requested*/
@ -23,8 +24,8 @@ void rebootControllerAndFPGA();
/** finds the right mtd drive
* @param mess error message
* @returns ok or fail
*/
int findFlash(char* mess);
*/
int findFlash(char *mess);
/** erase flash */
void eraseFlash();
@ -35,7 +36,7 @@ void eraseFlash();
* @param fsize file size
* @returns ok or fail
*/
int eraseAndWriteToFlash(char* mess, char* fpgasrc, uint64_t fsize);
int eraseAndWriteToFlash(char *mess, char *fpgasrc, uint64_t fsize);
/**
* Write FPGA Program to flash
@ -45,4 +46,4 @@ int eraseAndWriteToFlash(char* mess, char* fpgasrc, uint64_t fsize);
* @param filefp pointer to flash
* @return ok or fail
*/
int writeFPGAProgram(char* mess, char* fpgasrc, uint64_t fsize, FILE* filefp);
int writeFPGAProgram(char *mess, char *fpgasrc, uint64_t fsize, FILE *filefp);

22
slsDetectorServers/slsDetectorServer/include/readDefaultPattern.h Executable file → Normal file
View File

@ -1,22 +1,24 @@
#pragma once
#include <sys/types.h>
#include <inttypes.h>
#include <sys/types.h>
int loadDefaultPattern(char* fname);
int loadDefaultPattern(char *fname);
int default_writePatternWord(char* line, uint32_t addr, uint64_t word);
int default_writePatternWord(char *line, uint32_t addr, uint64_t word);
int default_writePatternIOControl(char* line, uint64_t arg);
int default_writePatternIOControl(char *line, uint64_t arg);
int default_writePatternClkControl(char* line, uint64_t arg);
int default_writePatternClkControl(char *line, uint64_t arg);
int default_setPatternLoopLimits(char* line, uint32_t startAddr, uint32_t stopAddr);
int default_setPatternLoopLimits(char *line, uint32_t startAddr,
uint32_t stopAddr);
int default_setPatternLoopAddresses(char* line, int level, uint32_t startAddr, uint32_t stopAddr);
int default_setPatternLoopAddresses(char *line, int level, uint32_t startAddr,
uint32_t stopAddr);
int default_setPatternLoopCycles(char* line, int level, int numLoops);
int default_setPatternLoopCycles(char *line, int level, int numLoops);
int default_setPatternWaitAddresses(char* line, int level, uint32_t addr);
int default_setPatternWaitAddresses(char *line, int level, uint32_t addr);
int default_setPatternWaitTime(char* line, int level, uint64_t waittime);
int default_setPatternWaitTime(char *line, int level, uint64_t waittime);

700
slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h Executable file → Normal file
View File

@ -1,11 +1,12 @@
#include "sls_detector_defs.h"
#include "slsDetectorServer_defs.h" // DAC_INDEX, ADC_INDEX, also include RegisterDefs.h
#include "sls_detector_defs.h"
#ifdef GOTTHARDD
#include "clogger.h" // runState(enum TLogLevel)
#include "AD9252.h" // old board compatibility
#include "AD9252.h" // old board compatibility
#include "clogger.h" // runState(enum TLogLevel)
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
#include "AD9257.h" // commonServerFunctions.h, blackfin.h, ansi.h
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD)
#include "AD9257.h" // commonServerFunctions.h, blackfin.h, ansi.h
#endif
#ifdef MOENCHD
#include "readDefaultPattern.h"
@ -19,533 +20,528 @@
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
#include "nios.h"
#elif defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
#elif defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD)
#include "blackfin.h"
#endif
#include <stdio.h> // FILE
#include <stdlib.h>
#include <stdio.h> // FILE
#include <sys/types.h>
/****************************************************
This functions are used by the slsDetectroServer_funcs interface.
Here are the definitions, but the actual implementation should be done for each single detector.
Here are the definitions, but the actual implementation should be done for each
single detector.
****************************************************/
enum interfaceType {OUTER, INNER};
enum interfaceType { OUTER, INNER };
typedef struct udpStruct_s {
int srcport;
int srcport2;
int dstport;
int dstport2;
uint64_t srcmac;
uint64_t srcmac2;
uint64_t dstmac;
uint64_t dstmac2;
uint32_t srcip;
uint32_t srcip2;
uint32_t dstip;
uint32_t dstip2;
}udpStruct;
int srcport;
int srcport2;
int dstport;
int dstport2;
uint64_t srcmac;
uint64_t srcmac2;
uint64_t dstmac;
uint64_t dstmac2;
uint32_t srcip;
uint32_t srcip2;
uint32_t dstip;
uint32_t dstip2;
} udpStruct;
// basic tests
int isInitCheckDone();
int getInitResult(char** mess);
void basictests();
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
int checkType();
int testFpga();
int testBus();
int isInitCheckDone();
int getInitResult(char **mess);
void basictests();
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
int checkType();
int testFpga();
int testBus();
#endif
#if defined(GOTTHARDD) || ((defined(EIGERD) || defined(JUNGFRAUD)) && defined(VIRTUAL))
void setTestImageMode(int ival);
int getTestImageMode();
#if defined(GOTTHARDD) || \
((defined(EIGERD) || defined(JUNGFRAUD)) && defined(VIRTUAL))
void setTestImageMode(int ival);
int getTestImageMode();
#endif
// Ids
u_int64_t getServerVersion();
u_int64_t getClientServerAPIVersion();
u_int64_t getFirmwareVersion();
u_int64_t getFirmwareAPIVersion();
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
u_int16_t getHardwareVersionNumber();
u_int64_t getServerVersion();
u_int64_t getClientServerAPIVersion();
u_int64_t getFirmwareVersion();
u_int64_t getFirmwareAPIVersion();
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D)
u_int16_t getHardwareVersionNumber();
#endif
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
u_int16_t getHardwareSerialNumber();
u_int16_t getHardwareSerialNumber();
#endif
#ifdef JUNGFRAUD
int isHardwareVersion2();
int isHardwareVersion2();
#endif
u_int32_t getDetectorNumber();
u_int64_t getDetectorMAC();
u_int32_t getDetectorIP();
u_int32_t getDetectorNumber();
u_int64_t getDetectorMAC();
u_int32_t getDetectorIP();
#ifdef GOTTHARDD
u_int32_t getBoardRevision();
u_int32_t getBoardRevision();
#endif
// initialization
void initControlServer();
void initStopServer();
void initControlServer();
void initStopServer();
#ifdef EIGERD
void getModuleConfiguration();
void getModuleConfiguration();
#endif
// set up detector
#ifdef EIGERD
void allocateDetectorStructureMemory();
void allocateDetectorStructureMemory();
#endif
void setupDetector();
void setupDetector();
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
int updateDatabytesandAllocateRAM();
void updateDataBytes();
int updateDatabytesandAllocateRAM();
void updateDataBytes();
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D) || defined(MOENCHD)
int setDefaultDacs();
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D) || \
defined(MOENCHD)
int setDefaultDacs();
#endif
#ifdef GOTTHARD2D
int readConfigFile();
int readConfigFile();
#endif
// advanced read/write reg
#ifdef EIGERD
int writeRegister(uint32_t offset, uint32_t data);
int readRegister(uint32_t offset, uint32_t* retval);
int writeRegister(uint32_t offset, uint32_t data);
int readRegister(uint32_t offset, uint32_t *retval);
#elif GOTTHARDD
uint32_t writeRegister16And32(uint32_t offset, uint32_t data); //FIXME its not there in ctb or moench?
uint32_t readRegister16And32(uint32_t offset);
uint32_t
writeRegister16And32(uint32_t offset,
uint32_t data); // FIXME its not there in ctb or moench?
uint32_t readRegister16And32(uint32_t offset);
#endif
// firmware functions (resets)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
void cleanFifos();
void resetCore();
void resetPeripheral();
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D)
void cleanFifos();
void resetCore();
void resetPeripheral();
#elif GOTTHARDD
void setPhaseShiftOnce();
void setPhaseShift(int numphaseshift);
void cleanFifos();
void setADCSyncRegister();
void setDAQRegister();
void setChipOfInterestRegister(int adc);
void setROIADC(int adc);
void setGbitReadout();
int readConfigFile();
void setMasterSlaveConfiguration();
void setPhaseShiftOnce();
void setPhaseShift(int numphaseshift);
void cleanFifos();
void setADCSyncRegister();
void setDAQRegister();
void setChipOfInterestRegister(int adc);
void setROIADC(int adc);
void setGbitReadout();
int readConfigFile();
void setMasterSlaveConfiguration();
#endif
// parameters - dr, roi
int setDynamicRange(int dr);
int setDynamicRange(int dr);
#ifdef GOTTHARDD
int setROI(ROI arg);
ROI getROI();
int setROI(ROI arg);
ROI getROI();
#endif
#ifdef JUNGFRAUD
void setADCInvertRegister(uint32_t val);
uint32_t getADCInvertRegister();
void setADCInvertRegister(uint32_t val);
uint32_t getADCInvertRegister();
#endif
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
int setADCEnableMask(uint32_t mask);
uint32_t getADCEnableMask();
void setADCEnableMask_10G(uint32_t mask);
uint32_t getADCEnableMask_10G();
void setADCInvertRegister(uint32_t val);
uint32_t getADCInvertRegister();
int setADCEnableMask(uint32_t mask);
uint32_t getADCEnableMask();
void setADCEnableMask_10G(uint32_t mask);
uint32_t getADCEnableMask_10G();
void setADCInvertRegister(uint32_t val);
uint32_t getADCInvertRegister();
#endif
#if defined(CHIPTESTBOARDD)
int setExternalSamplingSource(int val);
int setExternalSampling(int val);
int setExternalSamplingSource(int val);
int setExternalSampling(int val);
#endif
// parameters - readout
#ifdef EIGERD
int setParallelMode(int mode);
int getParallelMode();
int setOverFlowMode(int mode);
int getOverFlowMode();
void setStoreInRamMode(int mode);
int getStoreInRamMode();
int setParallelMode(int mode);
int getParallelMode();
int setOverFlowMode(int mode);
int getOverFlowMode();
void setStoreInRamMode(int mode);
int getStoreInRamMode();
#endif
#ifdef CHIPTESTBOARDD
int setReadoutMode(enum readoutMode mode);
int getReadoutMode();
int setReadoutMode(enum readoutMode mode);
int getReadoutMode();
#endif
// parameters - timer
#ifdef JUNGFRAUD
int selectStoragecellStart(int pos);
int selectStoragecellStart(int pos);
#endif
#if defined(JUNGFRAUD) || defined(EIGERD)
int setStartingFrameNumber(uint64_t value);
int getStartingFrameNumber(uint64_t* value);
int setStartingFrameNumber(uint64_t value);
int getStartingFrameNumber(uint64_t *value);
#endif
void setNumFrames(int64_t val);
int64_t getNumFrames();
void setNumTriggers(int64_t val);
int64_t getNumTriggers();
int setExpTime(int64_t val);
int64_t getExpTime();
int setPeriod(int64_t val);
int64_t getPeriod();
void setNumFrames(int64_t val);
int64_t getNumFrames();
void setNumTriggers(int64_t val);
int64_t getNumTriggers();
int setExpTime(int64_t val);
int64_t getExpTime();
int setPeriod(int64_t val);
int64_t getPeriod();
#ifdef GOTTHARD2D
void setNumBursts(int64_t val);
int64_t getNumBursts();
int setBurstPeriod(int64_t val);
int64_t getBurstPeriod();
void setNumBursts(int64_t val);
int64_t getNumBursts();
int setBurstPeriod(int64_t val);
int64_t getBurstPeriod();
#endif
#ifdef EIGERD
int setSubExpTime(int64_t val);
int64_t getSubExpTime();
int setSubDeadTime(int64_t val);
int64_t getSubDeadTime();
int64_t getMeasuredPeriod();
int64_t getMeasuredSubPeriod();
int setSubExpTime(int64_t val);
int64_t getSubExpTime();
int setSubDeadTime(int64_t val);
int64_t getSubDeadTime();
int64_t getMeasuredPeriod();
int64_t getMeasuredSubPeriod();
#endif
#ifdef JUNGFRAUD
void setNumAdditionalStorageCells(int val);
int getNumAdditionalStorageCells();
int setStorageCellDelay(int64_t val);
int64_t getStorageCellDelay();
void setNumAdditionalStorageCells(int val);
int getNumAdditionalStorageCells();
int setStorageCellDelay(int64_t val);
int64_t getStorageCellDelay();
#endif
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
int setNumAnalogSamples(int val);
int getNumAnalogSamples();
int setNumAnalogSamples(int val);
int getNumAnalogSamples();
#endif
#ifdef CHIPTESTBOARDD
int setNumDigitalSamples(int val);
int getNumDigitalSamples();
int setNumDigitalSamples(int val);
int getNumDigitalSamples();
#endif
#ifdef MYTHEN3D
void setCounterMask(uint32_t arg);
uint32_t getCounterMask();
void setCounterMask(uint32_t arg);
uint32_t getCounterMask();
#endif
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
int setDelayAfterTrigger(int64_t val);
int64_t getDelayAfterTrigger();
int64_t getNumFramesLeft();
int64_t getNumTriggersLeft();
int64_t getDelayAfterTriggerLeft();
int64_t getPeriodLeft();
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
int setDelayAfterTrigger(int64_t val);
int64_t getDelayAfterTrigger();
int64_t getNumFramesLeft();
int64_t getNumTriggersLeft();
int64_t getDelayAfterTriggerLeft();
int64_t getPeriodLeft();
#endif
#ifdef GOTTHARDD
int64_t getExpTimeLeft();
int64_t getExpTimeLeft();
#endif
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
int64_t getFramesFromStart();
int64_t getActualTime();
int64_t getMeasurementTime();
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D)
int64_t getFramesFromStart();
int64_t getActualTime();
int64_t getMeasurementTime();
#endif
// parameters - module, settings
#if (!defined(CHIPTESTBOARDD)) && (!defined(MOENCHD)) && (!defined(MYTHEN3D)) && (!defined(GOTTHARD2D))
int setModule(sls_detector_module myMod, char* mess);
int getModule(sls_detector_module *myMod);
#if (!defined(CHIPTESTBOARDD)) && (!defined(MOENCHD)) && \
(!defined(MYTHEN3D)) && (!defined(GOTTHARD2D))
int setModule(sls_detector_module myMod, char *mess);
int getModule(sls_detector_module *myMod);
#endif
#if (!defined(CHIPTESTBOARDD)) && (!defined(MYTHEN3D))
enum detectorSettings setSettings(enum detectorSettings sett);
enum detectorSettings setSettings(enum detectorSettings sett);
#endif
#if !defined(MYTHEN3D)
enum detectorSettings getSettings();
enum detectorSettings getSettings();
#endif
// parameters - threshold
#ifdef EIGERD
int getThresholdEnergy();
int setThresholdEnergy(int ev);
int getThresholdEnergy();
int setThresholdEnergy(int ev);
#endif
// parameters - dac, adc, hv
#ifdef GOTTHARD2D
int setOnChipDAC(enum ONCHIP_DACINDEX ind, int chipIndex, int val);
int getOnChipDAC(enum ONCHIP_DACINDEX ind, int chipIndex);
int setOnChipDAC(enum ONCHIP_DACINDEX ind, int chipIndex, int val);
int getOnChipDAC(enum ONCHIP_DACINDEX ind, int chipIndex);
#endif
void setDAC(enum DACINDEX ind, int val, int mV);
int getDAC(enum DACINDEX ind, int mV);
int getMaxDacSteps();
void setDAC(enum DACINDEX ind, int val, int mV);
int getDAC(enum DACINDEX ind, int mV);
int getMaxDacSteps();
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
int dacToVoltage(int dac);
int checkVLimitCompliant(int mV);
int checkVLimitDacCompliant(int dac);
int getVLimit();
void setVLimit(int l);
int dacToVoltage(int dac);
int checkVLimitCompliant(int mV);
int checkVLimitDacCompliant(int dac);
int getVLimit();
void setVLimit(int l);
#endif
#ifdef CHIPTESTBOARDD
int isVchipValid(int val);
int getVchip();
void setVchip(int val);
int getVChipToSet(enum DACINDEX ind, int val);
int getDACIndexFromADCIndex(enum ADCINDEX ind);
int getADCIndexFromDACIndex(enum DACINDEX ind);
int isPowerValid(enum DACINDEX ind, int val);
int getPower();
void setPower(enum DACINDEX ind, int val);
void powerOff();
int isVchipValid(int val);
int getVchip();
void setVchip(int val);
int getVChipToSet(enum DACINDEX ind, int val);
int getDACIndexFromADCIndex(enum ADCINDEX ind);
int getADCIndexFromDACIndex(enum DACINDEX ind);
int isPowerValid(enum DACINDEX ind, int val);
int getPower();
void setPower(enum DACINDEX ind, int val);
void powerOff();
#endif
#if !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
int getADC(enum ADCINDEX ind);
#if !defined(MOENCHD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D)
int getADC(enum ADCINDEX ind);
#endif
int setHighVoltage(int val);
int setHighVoltage(int val);
// parameters - timing, extsig
void setTiming( enum timingMode arg);
enum timingMode getTiming();
void setTiming(enum timingMode arg);
enum timingMode getTiming();
#ifdef GOTTHARDD
void setExtSignal(enum externalSignalFlag mode);
int getExtSignal();
void setExtSignal(enum externalSignalFlag mode);
int getExtSignal();
#endif
// configure mac
#ifdef GOTTHARDD
void calcChecksum(mac_conf* mac, int sourceip, int destip);
void calcChecksum(mac_conf *mac, int sourceip, int destip);
#elif JUNGFRAUD
void setNumberofUDPInterfaces(int val);
int getNumberofUDPInterfaces();
void selectPrimaryInterface(int val);
int getPrimaryInterface();
void setupHeader(int iRxEntry, enum interfaceType type, uint32_t destip, uint64_t destmac, uint32_t destport, uint64_t sourcemac, uint32_t sourceip, uint32_t sourceport);
void setNumberofUDPInterfaces(int val);
int getNumberofUDPInterfaces();
void selectPrimaryInterface(int val);
int getPrimaryInterface();
void setupHeader(int iRxEntry, enum interfaceType type, uint32_t destip,
uint64_t destmac, uint32_t destport, uint64_t sourcemac,
uint32_t sourceip, uint32_t sourceport);
#endif
#if defined(JUNGFRAUD) || defined(GOTTHARD2D) || defined(MYTHEN3D) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
void calcChecksum(udp_header* udp);
#if defined(JUNGFRAUD) || defined(GOTTHARD2D) || defined(MYTHEN3D) || \
defined(CHIPTESTBOARDD) || defined(MOENCHD)
void calcChecksum(udp_header *udp);
#endif
#ifdef GOTTHARDD
int getAdcConfigured();
int getAdcConfigured();
#endif
int configureMAC();
int setDetectorPosition(int pos[]);
int* getDetectorPosition();
int configureMAC();
int setDetectorPosition(int pos[]);
int *getDetectorPosition();
#ifdef EIGERD
int setQuad(int value);
int getQuad();
int setInterruptSubframe(int value);
int getInterruptSubframe();
int setReadNLines(int value);
int getReadNLines();
int setQuad(int value);
int getQuad();
int setInterruptSubframe(int value);
int getInterruptSubframe();
int setReadNLines(int value);
int getReadNLines();
#endif
#if defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(EIGERD)
int enableTenGigabitEthernet(int val);
int enableTenGigabitEthernet(int val);
#endif
// very detector specific
// moench specific - powerchip
#ifdef MOENCHD
int powerChip (int on);
int setAnalogOnlyReadout();
int powerChip(int on);
int setAnalogOnlyReadout();
#endif
// chip test board or moench specific - configure frequency, phase, pll, flashing firmware
// chip test board or moench specific - configure frequency, phase, pll,
// flashing firmware
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
int setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
void configureSyncFrequency(enum CLKINDEX ind);
void setPipeline(enum CLKINDEX ind, int val);
int getPipeline(enum CLKINDEX ind);
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
int setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
void configureSyncFrequency(enum CLKINDEX ind);
void setPipeline(enum CLKINDEX ind, int val);
int getPipeline(enum CLKINDEX ind);
// patterns
uint64_t writePatternIOControl(uint64_t word);
uint64_t writePatternClkControl(uint64_t word);
uint64_t readPatternWord(int addr);
uint64_t writePatternWord(int addr, uint64_t word);
int setPatternWaitAddress(int level, int addr);
uint64_t setPatternWaitTime(int level, uint64_t t);
void setPatternLoop(int level, int *startAddr, int *stopAddr, int *nLoop);
uint64_t writePatternIOControl(uint64_t word);
uint64_t writePatternClkControl(uint64_t word);
uint64_t readPatternWord(int addr);
uint64_t writePatternWord(int addr, uint64_t word);
int setPatternWaitAddress(int level, int addr);
uint64_t setPatternWaitTime(int level, uint64_t t);
void setPatternLoop(int level, int *startAddr, int *stopAddr, int *nLoop);
#ifdef CHIPTESTBOARDD
int setLEDEnable(int enable);
void setDigitalIODelay(uint64_t pinMask, int delay);
int setLEDEnable(int enable);
void setDigitalIODelay(uint64_t pinMask, int delay);
#endif
void setPatternMask(uint64_t mask);
uint64_t getPatternMask();
void setPatternBitMask(uint64_t mask);
uint64_t getPatternBitMask();
void setPatternMask(uint64_t mask);
uint64_t getPatternMask();
void setPatternBitMask(uint64_t mask);
uint64_t getPatternBitMask();
#endif
// jungfrau specific - powerchip, autocompdisable, clockdiv, asictimer, clock, pll, flashing firmware
// jungfrau specific - powerchip, autocompdisable, clockdiv, asictimer, clock,
// pll, flashing firmware
#ifdef JUNGFRAUD
void initReadoutConfiguration();
int powerChip (int on);
int autoCompDisable(int on);
void configureASICTimer();
int setClockDivider(enum CLKINDEX ind, int val);
int getClockDivider(enum CLKINDEX ind);
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
int setThresholdTemperature(int val);
int setTemperatureControl(int val);
int setTemperatureEvent(int val);
void alignDeserializer();
void initReadoutConfiguration();
int powerChip(int on);
int autoCompDisable(int on);
void configureASICTimer();
int setClockDivider(enum CLKINDEX ind, int val);
int getClockDivider(enum CLKINDEX ind);
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
int setThresholdTemperature(int val);
int setTemperatureControl(int val);
int setTemperatureEvent(int val);
void alignDeserializer();
// eiger specific - iodelay, pulse, rate, temp, activate, delay nw parameter
#elif EIGERD
int setClockDivider(enum CLKINDEX ind, int val);
int getClockDivider(enum CLKINDEX ind);
int setIODelay(int val);
int setCounterBit(int val);
int pulsePixel(int n, int x, int y);
int pulsePixelNMove(int n, int x, int y);
int pulseChip(int n);
int updateRateCorrection(char* mess);
int validateAndSetRateCorrection(int64_t tau_ns, char* mess);
int setRateCorrection(int64_t custom_tau_in_nsec);
int getRateCorrectionEnable();
int getDefaultSettingsTau_in_nsec();
void setDefaultSettingsTau_in_nsec(int t);
int64_t getCurrentTau();
void setExternalGating(int enable[]);
int setAllTrimbits(int val);
int getAllTrimbits();
int getBebFPGATemp();
int activate(int enable);
int setClockDivider(enum CLKINDEX ind, int val);
int getClockDivider(enum CLKINDEX ind);
int setIODelay(int val);
int setCounterBit(int val);
int pulsePixel(int n, int x, int y);
int pulsePixelNMove(int n, int x, int y);
int pulseChip(int n);
int updateRateCorrection(char *mess);
int validateAndSetRateCorrection(int64_t tau_ns, char *mess);
int setRateCorrection(int64_t custom_tau_in_nsec);
int getRateCorrectionEnable();
int getDefaultSettingsTau_in_nsec();
void setDefaultSettingsTau_in_nsec(int t);
int64_t getCurrentTau();
void setExternalGating(int enable[]);
int setAllTrimbits(int val);
int getAllTrimbits();
int getBebFPGATemp();
int activate(int enable);
// gotthard specific - adc phase
#elif GOTTHARDD
int setPhase(enum CLKINDEX ind, int val, int degrees);
int setPhase(enum CLKINDEX ind, int val, int degrees);
#elif MYTHEN3D
uint64_t readPatternWord(int addr);
uint64_t writePatternWord(int addr, uint64_t word);
int setPatternWaitAddress(int level, int addr);
uint64_t setPatternWaitTime(int level, uint64_t t);
void setPatternLoop(int level, int *startAddr, int *stopAddr, int *nLoop);
void setPatternMask(uint64_t mask);
uint64_t getPatternMask();
void setPatternBitMask(uint64_t mask);
uint64_t getPatternBitMask();
int checkDetectorType();
int powerChip (int on);
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
//void setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
int getVCOFrequency(enum CLKINDEX ind);
int getMaxClockDivider();
int setClockDivider(enum CLKINDEX ind, int val);
int getClockDivider(enum CLKINDEX ind);
uint64_t readPatternWord(int addr);
uint64_t writePatternWord(int addr, uint64_t word);
int setPatternWaitAddress(int level, int addr);
uint64_t setPatternWaitTime(int level, uint64_t t);
void setPatternLoop(int level, int *startAddr, int *stopAddr, int *nLoop);
void setPatternMask(uint64_t mask);
uint64_t getPatternMask();
void setPatternBitMask(uint64_t mask);
uint64_t getPatternBitMask();
int checkDetectorType();
int powerChip(int on);
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
// void setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
int getVCOFrequency(enum CLKINDEX ind);
int getMaxClockDivider();
int setClockDivider(enum CLKINDEX ind, int val);
int getClockDivider(enum CLKINDEX ind);
#elif GOTTHARD2D
int checkDetectorType();
int powerChip (int on);
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
//void setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
int getVCOFrequency(enum CLKINDEX ind);
int getMaxClockDivider();
int setClockDivider(enum CLKINDEX ind, int val);
int getClockDivider(enum CLKINDEX ind);
int setInjectChannel(int offset, int increment);
void getInjectedChannels(int* offset, int* increment);
int setVetoReference(int gainIndex, int value);
int setVetoPhoton(int chipIndex, int gainIndex, int* values);
int getVetoPhoton(int chipIndex, int* retvals);
int configureSingleADCDriver(int chipIndex);
int configureADC();
int setBurstModeinFPGA(enum burstMode value);
int setBurstMode(enum burstMode burst);
enum burstMode getBurstMode();
void setCurrentSource(int value);
int getCurrentSource();
void setTimingSource(enum timingSourceType value);
enum timingSourceType getTimingSource();
int checkDetectorType();
int powerChip(int on);
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
int getMaxPhase(enum CLKINDEX ind);
int validatePhaseinDegrees(enum CLKINDEX ind, int val, int retval);
// void setFrequency(enum CLKINDEX ind, int val);
int getFrequency(enum CLKINDEX ind);
int getVCOFrequency(enum CLKINDEX ind);
int getMaxClockDivider();
int setClockDivider(enum CLKINDEX ind, int val);
int getClockDivider(enum CLKINDEX ind);
int setInjectChannel(int offset, int increment);
void getInjectedChannels(int *offset, int *increment);
int setVetoReference(int gainIndex, int value);
int setVetoPhoton(int chipIndex, int gainIndex, int *values);
int getVetoPhoton(int chipIndex, int *retvals);
int configureSingleADCDriver(int chipIndex);
int configureADC();
int setBurstModeinFPGA(enum burstMode value);
int setBurstMode(enum burstMode burst);
enum burstMode getBurstMode();
void setCurrentSource(int value);
int getCurrentSource();
void setTimingSource(enum timingSourceType value);
enum timingSourceType getTimingSource();
#endif
#if defined(JUNGFRAUD) || defined(EIGERD)
int getTenGigaFlowControl();
int setTenGigaFlowControl(int value);
int getTransmissionDelayFrame();
int setTransmissionDelayFrame(int value);
int getTenGigaFlowControl();
int setTenGigaFlowControl(int value);
int getTransmissionDelayFrame();
int setTransmissionDelayFrame(int value);
#endif
#ifdef EIGERD
int getTransmissionDelayLeft();
int setTransmissionDelayLeft(int value);
int getTransmissionDelayRight();
int setTransmissionDelayRight(int value);
int getTransmissionDelayLeft();
int setTransmissionDelayLeft(int value);
int getTransmissionDelayRight();
int setTransmissionDelayRight(int value);
#endif
// aquisition
#ifdef EIGERD
int prepareAcquisition();
int prepareAcquisition();
#endif
int startStateMachine();
int startStateMachine();
#ifdef VIRTUAL
void* start_timer(void* arg);
void *start_timer(void *arg);
#endif
int stopStateMachine();
int stopStateMachine();
#ifdef EIGERD
int softwareTrigger();
int softwareTrigger();
#endif
#ifdef EIGERD
int startReadOut();
int startReadOut();
#endif
enum runStatus getRunStatus();
void readFrame(int *ret, char *mess);
enum runStatus getRunStatus();
void readFrame(int *ret, char *mess);
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
void readandSendUDPFrames(int *ret, char *mess);
void unsetFifoReadStrobes();
void readSample(int ns);
uint32_t checkDataInFifo();
int checkFifoForEndOfAcquisition();
int readFrameFromFifo();
void readandSendUDPFrames(int *ret, char *mess);
void unsetFifoReadStrobes();
void readSample(int ns);
uint32_t checkDataInFifo();
int checkFifoForEndOfAcquisition();
int readFrameFromFifo();
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
u_int32_t runBusy();
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
u_int32_t runBusy();
#endif
#ifdef GOTTHARDD
u_int32_t runState(enum TLogLevel lev);
u_int32_t runState(enum TLogLevel lev);
#endif
//common
// common
#ifdef EIGERD
int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod);
int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod);
#endif
int calculateDataBytes();
int getTotalNumberOfChannels();
int calculateDataBytes();
int getTotalNumberOfChannels();
#if defined(MOENCHD) || defined(CHIPTESTBOARDD)
void getNumberOfChannels(int* nchanx, int* nchany);
void getNumberOfChannels(int *nchanx, int *nchany);
#endif
int getNumberOfChips();
int getNumberOfDACs();
int getNumberOfChannelsPerChip();
int getNumberOfChips();
int getNumberOfDACs();
int getNumberOfChannelsPerChip();

22
slsDetectorServers/slsDetectorServer/include/slsDetectorServer_funcs.h Executable file → Normal file
View File

@ -1,23 +1,24 @@
#pragma once
#include "sls_detector_defs.h"
#include "clogger.h"
#include "sls_detector_defs.h"
enum numberMode {DEC, HEX};
#define GOODBYE (-200)
#define REBOOT (-400)
enum numberMode { DEC, HEX };
#define GOODBYE (-200)
#define REBOOT (-400)
// initialization functions
int printSocketReadError();
void init_detector();
int decode_function(int);
const char* getRetName();
const char* getFunctionName(enum detFuncs func);
const char *getRetName();
const char *getFunctionName(enum detFuncs func);
void function_table();
void functionNotImplemented();
void modeNotImplemented(char* modename, int mode);
void validate(int arg, int retval, char* modename, enum numberMode nummode);
void validate64(int64_t arg, int64_t retval, char* modename, enum numberMode nummode);
int executeCommand(char* command, char* result, enum TLogLevel level);
void modeNotImplemented(char *modename, int mode);
void validate(int arg, int retval, char *modename, enum numberMode nummode);
void validate64(int64_t arg, int64_t retval, char *modename,
enum numberMode nummode);
int executeCommand(char *command, char *result, enum TLogLevel level);
int M_nofunc(int);
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
void rebootNiosControllerAndFPGA();
@ -217,4 +218,3 @@ int set_timing_source(int);
int get_num_channels(int);
int update_rate_correction(int);
int get_receiver_parameters(int);