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format slsdetectorservers

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This commit is contained in:
maliakal_d 2020-05-05 15:23:11 +02:00
parent 31ec3c8cf7
commit 671cf45fd7
49 changed files with 3750 additions and 3409 deletions
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1
CMakeLists.txt
View File

@ -50,7 +50,6 @@ option(SLS_TUNE_LOCAL "tune to local machine" OFF)
set(ClangFormat_EXCLUDE_PATTERNS "build/"
"libs/"
"slsDetectorCalibration/"
"slsDetectorServers/"
"ctbGui/"
"manual/"
"python/"

122
slsDetectorServers/ctbDetectorServer/RegisterDefs.h Executable file → Normal file
View File

@ -10,7 +10,8 @@
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_CTB_VAL ((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
#define FPGA_VERSION_DTCTR_TYP_CTB_VAL \
((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
/* Fix pattern RO register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
@ -57,7 +58,8 @@
#define STATUS_PLL_PHS_DN_OFST (23)
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_MSK \
(0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x677FF)
/* Look at me RO register TODO */
@ -67,24 +69,30 @@
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK (0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK (0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK \
(0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as PLL_PARAM_REG 0x50 */
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as
* PLL_PARAM_REG 0x50 */
//#define PLL_PARAM_REG (0x05 << MEM_MAP_SHIFT)
/* FIFO Data RO register TODO */
#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK \
(0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
//#define FIFO_DATA_WRD_OFST (16)
//#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
@ -114,7 +122,8 @@
#define API_VERSION_DTCTR_TYP_OFST (24)
#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using CONTROL_CRST. TODO */
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
* CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
@ -135,12 +144,14 @@
#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
/* Exposure Time Left 64 bit RO register */
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
//used in FW #define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT)
//// Not used in FW
/* Gates Left 64 bit RO register */
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not
//used in FW #define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT)
//// Not used in FW
/* Data In 64 bit RO register TODO */
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
@ -151,14 +162,16 @@
#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
/* Frames From Start 64 bit RO register TODO */
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not
//used in FW #define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT)
//// Not used in FW
/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame start until reset) TODO */
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
* start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
@ -177,9 +190,11 @@
/* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK \
(0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK \
(0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
/* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
@ -243,9 +258,11 @@
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK \
(0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK \
(0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
/* Receiver IP Address RW register */
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
@ -313,21 +330,22 @@
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
//#define CONTROL_STRT_FF_TST_OFST (2)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
//#define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
//#define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_RDT_OFST (5)
//#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 <<
//CONTROL_STRT_FF_TST_OFST) #define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 <<
//CONTROL_STP_FF_TST_OFST) #define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 <<
//CONTROL_STRT_RDT_OFST) #define CONTROL_STP_RDT_OFST (5) #define
//CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
//#define CONTROL_STP_EXPSR_OFST (7)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STRT_TRN_OFST (8)
//#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 <<
//CONTROL_STP_RDT_OFST) #define CONTROL_STRT_TRN_OFST (8) #define
//CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_TRN_OFST (9)
//#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STP_TRN_MSK (0x00000001 <<
//CONTROL_STP_RDT_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
@ -335,7 +353,8 @@
#define CONTROL_MMRY_RST_OFST (12)
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
//#define CONTROL_PLL_RCNFG_WR_OFST (13)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 << CONTROL_PLL_RCNFG_WR_OFST)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 <<
//CONTROL_PLL_RCNFG_WR_OFST)
#define CONTROL_SND_10GB_PCKT_OFST (14)
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
@ -348,7 +367,8 @@
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
@ -378,7 +398,8 @@
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
@ -389,7 +410,8 @@
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
@ -400,7 +422,8 @@
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
@ -445,7 +468,6 @@
/* Number of Words RW register TODO */
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
/* Delay 64 bit RW register. t = DLY x 50 ns. */
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
@ -463,12 +485,14 @@
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
//Not used in FW #define EXPTIME_MSB_REG (0x69 <<
//MEM_MAP_SHIFT) // Not used in FW
/* Gates 64 bit RW register */
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used
//in FW #define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) //
//Not used in FW
/* Pattern IO Control 64 bit RW regiser
* Each bit configured as output(1)/ input(0) */
@ -505,7 +529,6 @@
#define READOUT_10G_ENABLE_DGTL_OFST (8)
#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
/* Digital Bit External Trigger RW register */
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
@ -517,11 +540,15 @@
/* Pin Delay 0 RW register */
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST (0) //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST \
(0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK \
(0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay
// configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK (0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK \
(0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL (1)
#define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
@ -550,6 +577,3 @@
/* Round Robin */
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)

66
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
View File

@ -1,7 +1,6 @@
#pragma once
#include "sls_detector_defs.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x181130
#define REQRD_FRMWR_VRSN 0x191127
@ -36,10 +35,53 @@ typedef struct udp_header_struct {
#define UDP_IP_HEADER_LENGTH_BYTES (28)
/* Enums */
enum ADCINDEX {V_PWR_IO, V_PWR_A, V_PWR_B, V_PWR_C, V_PWR_D, I_PWR_IO, I_PWR_A, I_PWR_B, I_PWR_C, I_PWR_D, S_ADC0, S_ADC1, S_ADC2, S_ADC3, S_ADC4, S_ADC5, S_ADC6, S_ADC7, S_TMP};
enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
D10, D11, D12, D13, D14, D15, D16, D17,
D_PWR_D, D_PWR_CHIP, D_PWR_C, D_PWR_B, D_PWR_A, D_PWR_IO};
enum ADCINDEX {
V_PWR_IO,
V_PWR_A,
V_PWR_B,
V_PWR_C,
V_PWR_D,
I_PWR_IO,
I_PWR_A,
I_PWR_B,
I_PWR_C,
I_PWR_D,
S_ADC0,
S_ADC1,
S_ADC2,
S_ADC3,
S_ADC4,
S_ADC5,
S_ADC6,
S_ADC7,
S_TMP
};
enum DACINDEX {
D0,
D1,
D2,
D3,
D4,
D5,
D6,
D7,
D8,
D9,
D10,
D11,
D12,
D13,
D14,
D15,
D16,
D17,
D_PWR_D,
D_PWR_CHIP,
D_PWR_C,
D_PWR_B,
D_PWR_A,
D_PWR_IO
};
enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
#define CLK_NAMES "run", "adc", "sync", "dbit"
@ -85,16 +127,21 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
#define VCHIP_MIN_MV (1673)
#define VCHIP_MAX_MV (2668) // min dac val
#define POWER_RGLTR_MIN (636)
#define POWER_RGLTR_MAX (2638) // min dac val (not vchip-max) because of dac conversions
#define POWER_RGLTR_MAX \
(2638) // min dac val (not vchip-max) because of dac conversions
#define VCHIP_POWER_INCRMNT (200)
#define VIO_MIN_MV (1200) // for fpga to function
/* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0x2000)
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define DIGITAL_IO_DELAY_MAXIMUM_PS \
((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_STEPS (8)
#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TME_US_FR_ACQDONE_REG \
(100) // wait time in us after acquisition done to ensure there is no data
// in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
@ -109,4 +156,3 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
#define MAXIMUM_ADC_CLK (65)
#define PLL_VCO_FREQ_MHZ (800)

43
slsDetectorServers/eigerDetectorServer/Beb.h Executable file → Normal file
View File

@ -1,10 +1,8 @@
#pragma once
#include "LocalLinkInterface.h"
#include "slsDetectorServer_defs.h"
struct BebInfo {
unsigned int beb_number;
unsigned int serial_address;
@ -16,11 +14,13 @@ struct BebInfo{
unsigned int src_port_10GbE;
};
void BebInfo_BebInfo(struct BebInfo *bebInfo, unsigned int beb_num);
void BebInfo_BebDstInfo(struct BebInfo *bebInfo, unsigned int beb_num);
int BebInfo_SetSerialAddress(struct BebInfo *bebInfo, unsigned int add);
int BebInfo_SetHeaderInfo(struct BebInfo* bebInfo, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);//src_port fixed 42000+beb_number or 52000 + beb_number);
int BebInfo_SetHeaderInfo(
struct BebInfo *bebInfo, int ten_gig, char *src_mac, char *src_ip,
unsigned int
src_port); // src_port fixed 42000+beb_number or 52000 + beb_number);
unsigned int BebInfo_GetBebNumber(struct BebInfo *bebInfo);
unsigned int BebInfo_GetSerialAddress(struct BebInfo *bebInfo);
char *BebInfo_GetSrcMAC(struct BebInfo *bebInfo, int ten_gig);
@ -32,7 +32,6 @@ int Beb_InitBebInfos();
int Beb_CheckSourceStuffBebInfo();
unsigned int Beb_GetBebInfoIndex(unsigned int beb_numb);
void Beb_GetModuleConfiguration(int *master, int *top, int *normal);
int Beb_IsTransmitting(int *retval, int tengiga, int waitForDelay);
@ -61,22 +60,38 @@ int Beb_SetIP(char* ip, uint8_t* dst_ptr);
int Beb_SetPortNumber(unsigned int port_number, uint8_t *dst_ptr);
void Beb_AdjustIPChecksum(struct udp_header_type *ip);
int Beb_SetHeaderData(unsigned int beb_number, int ten_gig, char* dst_mac, char* dst_ip, unsigned int dst_port);
int Beb_SetHeaderData1(char* src_mac, char* src_ip, unsigned int src_port, char* dst_mac, char* dst_ip, unsigned int dst_port);
int Beb_SetHeaderData(unsigned int beb_number, int ten_gig, char *dst_mac,
char *dst_ip, unsigned int dst_port);
int Beb_SetHeaderData1(char *src_mac, char *src_ip, unsigned int src_port,
char *dst_mac, char *dst_ip, unsigned int dst_port);
void Beb_SwapDataFun(int little_endian, unsigned int n, unsigned int *d);
int Beb_SetByteOrder();
void Beb_Beb();
int Beb_SetBebSrcHeaderInfos(unsigned int beb_number, int ten_gig, char* src_mac, char* src_ip, unsigned int src_port);
int Beb_SetUpUDPHeader(unsigned int beb_number, int ten_gig, unsigned int header_number, char* dst_mac, char* dst_ip, unsigned int dst_port);
int Beb_SetBebSrcHeaderInfos(unsigned int beb_number, int ten_gig,
char *src_mac, char *src_ip,
unsigned int src_port);
int Beb_SetUpUDPHeader(unsigned int beb_number, int ten_gig,
unsigned int header_number, char *dst_mac, char *dst_ip,
unsigned int dst_port);
/*int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty=1);*/
int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int npackets, unsigned int packet_size, int stop_read_when_fifo_empty);
/*int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int
* left_right, int ten_gig, unsigned int dst_number, unsigned int npackets,
* unsigned int packet_size, int stop_read_when_fifo_empty=1);*/
int Beb_SendMultiReadRequest(unsigned int beb_number, unsigned int left_right,
int ten_gig, unsigned int dst_number,
unsigned int npackets, unsigned int packet_size,
int stop_read_when_fifo_empty);
int Beb_StopAcquisition();
int Beb_SetUpTransferParameters(short the_bit_mode);
/*int Beb_RequestNImages(unsigned int beb_number, unsigned int left_right, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait=0); //all images go to the same destination!*/
int Beb_RequestNImages(unsigned int beb_number, int ten_gig, unsigned int dst_number, unsigned int nimages, int test_just_send_out_packets_no_wait);
/*int Beb_RequestNImages(unsigned int beb_number, unsigned int left_right, int
* ten_gig, unsigned int dst_number, unsigned int nimages, int
* test_just_send_out_packets_no_wait=0); //all images go to the same
* destination!*/
int Beb_RequestNImages(unsigned int beb_number, int ten_gig,
unsigned int dst_number, unsigned int nimages,
int test_just_send_out_packets_no_wait);
int Beb_Test(unsigned int beb_number);
@ -97,5 +112,3 @@ int Beb_open(u_int32_t** csp0base, u_int32_t offset);
u_int32_t Beb_Read32(u_int32_t *baseaddr, u_int32_t offset);
u_int32_t Beb_Write32(u_int32_t *baseaddr, u_int32_t offset, u_int32_t data);
void Beb_close(int fd, u_int32_t *csp0base);

67
slsDetectorServers/eigerDetectorServer/FebControl.h Executable file → Normal file
View File

@ -2,7 +2,6 @@
#include "FebInterface.h"
#include <netinet/in.h>
struct Module {
unsigned int module_number;
int top_address_valid;
@ -19,10 +18,12 @@ struct Module{
int *bottom_dac;
};
void Module_Module(struct Module* mod,unsigned int number, unsigned int address_top);
void Module_ModuleBottom(struct Module* mod,unsigned int number, unsigned int address_bottom);
void Module_Module1(struct Module* mod,unsigned int number, unsigned int address_top, unsigned int address_bottom);
void Module_Module(struct Module *mod, unsigned int number,
unsigned int address_top);
void Module_ModuleBottom(struct Module *mod, unsigned int number,
unsigned int address_bottom);
void Module_Module1(struct Module *mod, unsigned int number,
unsigned int address_top, unsigned int address_bottom);
unsigned int Module_GetModuleNumber(struct Module *mod);
int Module_TopAddressIsValid(struct Module *mod);
unsigned int Module_GetTopBaseAddress(struct Module *mod);
@ -32,9 +33,11 @@ unsigned int Module_GetBottomBaseAddress(struct Module* mod);
int Module_BottomAddressIsValid(struct Module *mod);
unsigned int Module_GetBottomLeftAddress(struct Module *mod);
unsigned int Module_GetBottomRightAddress(struct Module *mod);
unsigned int Module_SetTopIDelay(struct Module* mod,unsigned int chip,unsigned int value);
unsigned int Module_SetTopIDelay(struct Module *mod, unsigned int chip,
unsigned int value);
unsigned int Module_GetTopIDelay(struct Module *mod, unsigned int chip);
unsigned int Module_SetBottomIDelay(struct Module* mod,unsigned int chip,unsigned int value);
unsigned int Module_SetBottomIDelay(struct Module *mod, unsigned int chip,
unsigned int value);
unsigned int Module_GetBottomIDelay(struct Module *mod, unsigned int chip);
float Module_SetHighVoltage(struct Module *mod, float value);
@ -45,29 +48,36 @@ int Module_GetTopDACValue(struct Module* mod,unsigned int i);
int Module_SetBottomDACValue(struct Module *mod, unsigned int i, int value);
int Module_GetBottomDACValue(struct Module *mod, unsigned int i);
void Feb_Control_activate(int activate);
int Feb_Control_IsBottomModule();
int Feb_Control_GetModuleNumber();
void Feb_Control_PrintModuleList();
int Feb_Control_GetModuleIndex(unsigned int module_number, unsigned int* module_index);
int Feb_Control_GetModuleIndex(unsigned int module_number,
unsigned int *module_index);
int Feb_Control_CheckModuleAddresses(struct Module *m);
int Feb_Control_AddModule(unsigned int module_number, unsigned int top_address);
int Feb_Control_AddModule1(unsigned int module_number, int top_enable, unsigned int top_address, unsigned int bottom_address, int half_module);
int Feb_Control_AddModule1(unsigned int module_number, int top_enable,
unsigned int top_address,
unsigned int bottom_address, int half_module);
int Feb_Control_GetDACNumber(char *s, unsigned int *n);
int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch, unsigned int* value);
int Feb_Control_VoltageToDAC(float value, unsigned int* digital, unsigned int nsteps, float vmin, float vmax);
float Feb_Control_DACToVoltage(unsigned int digital,unsigned int nsteps,float vmin,float vmax);
int Feb_Control_SendIDelays(unsigned int dst_num, int chip_lr, unsigned int channels, unsigned int ndelay_units);
int Feb_Control_SendDACValue(unsigned int dst_num, unsigned int ch,
unsigned int *value);
int Feb_Control_VoltageToDAC(float value, unsigned int *digital,
unsigned int nsteps, float vmin, float vmax);
float Feb_Control_DACToVoltage(unsigned int digital, unsigned int nsteps,
float vmin, float vmax);
int Feb_Control_SendIDelays(unsigned int dst_num, int chip_lr,
unsigned int channels, unsigned int ndelay_units);
int Feb_Control_SetStaticBits();
int Feb_Control_SetStaticBits1(unsigned int the_static_bits);
int Feb_Control_SendBitModeToBebServer();
unsigned int Feb_Control_ConvertTimeToRegister(float time_in_sec);
unsigned int Feb_Control_AddressToAll();
int Feb_Control_SetCommandRegister(unsigned int cmd);
int Feb_Control_GetDAQStatusRegister(unsigned int dst_address, unsigned int* ret_status);
int Feb_Control_GetDAQStatusRegister(unsigned int dst_address,
unsigned int *ret_status);
int Feb_Control_StartDAQOnlyNWaitForFinish(int sleep_time_us);
int Feb_Control_ResetChipCompletely();
int Feb_Control_ResetChipPartially();
@ -86,14 +96,17 @@ int Feb_Control_SendHighVoltage(int dacvalue);
int Feb_Control_ReceiveHighVoltage(unsigned int *value);
int Feb_Control_SetIDelays(unsigned int module_num, unsigned int ndelay_units);
int Feb_Control_SetIDelays1(unsigned int module_num, unsigned int chip_pos, unsigned int ndelay_units);
int Feb_Control_SetIDelays1(unsigned int module_num, unsigned int chip_pos,
unsigned int ndelay_units);
int Feb_Control_DecodeDACString(char* dac_str, unsigned int* module_index, int* top, int* bottom, unsigned int* dac_ch);
int Feb_Control_DecodeDACString(char *dac_str, unsigned int *module_index,
int *top, int *bottom, unsigned int *dac_ch);
int Feb_Control_SetDAC(char *s, int value, int is_a_voltage_mv);
int Feb_Control_GetDAC(char *s, int *ret_value, int voltage_mv);
int Feb_Control_GetDACName(unsigned int dac_num, char *s);
int Feb_Control_SetTrimbits(unsigned int module_num, unsigned int* trimbits, int top);
int Feb_Control_SetTrimbits(unsigned int module_num, unsigned int *trimbits,
int top);
unsigned int *Feb_Control_GetTrimbits();
int Feb_Control_SaveAllTrimbitsTo(int value, int top);
int Feb_Control_Reset();
@ -111,7 +124,8 @@ unsigned int Feb_Control_GetNExposures();
int Feb_Control_SetExposureTime(double the_exposure_time_in_sec);
double Feb_Control_GetExposureTime();
int64_t Feb_Control_GetExposureTime_in_nsec();
int Feb_Control_SetSubFrameExposureTime(int64_t the_subframe_exposure_time_in_10nsec);
int Feb_Control_SetSubFrameExposureTime(
int64_t the_subframe_exposure_time_in_10nsec);
int64_t Feb_Control_GetSubFrameExposureTime();
int Feb_Control_SetSubFramePeriod(int64_t the_subframe_period_in_10nsec);
int64_t Feb_Control_GetSubFramePeriod();
@ -119,10 +133,16 @@ int Feb_Control_SetExposurePeriod(double the_exposure_period_in_sec);
double Feb_Control_GetExposurePeriod();
int Feb_Control_SetDynamicRange(unsigned int four_eight_sixteen_or_thirtytwo);
unsigned int Feb_Control_GetDynamicRange();
int Feb_Control_SetReadoutSpeed(unsigned int readout_speed); //0 was default, 0->full,1->half,2->quarter or 3->super_slow
int Feb_Control_SetReadoutMode(unsigned int readout_mode); ///0 was default,0->parallel,1->non-parallel,2-> safe_mode
int Feb_Control_SetTriggerMode(unsigned int trigger_mode, int polarity);//0 and 1 was default,
int Feb_Control_SetExternalEnableMode(int use_external_enable, int polarity);//0 and 1 was default,
int Feb_Control_SetReadoutSpeed(
unsigned int readout_speed); // 0 was default, 0->full,1->half,2->quarter or
// 3->super_slow
int Feb_Control_SetReadoutMode(unsigned int readout_mode); /// 0 was
/// default,0->parallel,1->non-parallel,2->
/// safe_mode
int Feb_Control_SetTriggerMode(unsigned int trigger_mode,
int polarity); // 0 and 1 was default,
int Feb_Control_SetExternalEnableMode(int use_external_enable,
int polarity); // 0 and 1 was default,
int Feb_Control_SetInTestModeVariable(int on);
int Feb_Control_GetTestModeVariable();
@ -159,4 +179,3 @@ int Feb_Control_GetReadNLines();
int Feb_Control_WriteRegister(uint32_t offset, uint32_t data);
int Feb_Control_ReadRegister(uint32_t offset, uint32_t *retval);

26
slsDetectorServers/eigerDetectorServer/FebInterface.h Executable file → Normal file
View File

@ -5,10 +5,22 @@ int Feb_Interface_ReadFrom(unsigned int ch, unsigned int ntrys);
void Feb_Interface_FebInterface();
void Feb_Interface_SendCompleteList(unsigned int n, unsigned int *list);
int Feb_Interface_SetByteOrder();
int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,unsigned int* value_read);
int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads, unsigned int* reg_nums,unsigned int* values_read);
int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,unsigned int value, int wait_on, unsigned int wait_on_address);
int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites, unsigned int* reg_nums, unsigned int* values, int* wait_ons, unsigned int* wait_on_addresses);
int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num, unsigned int start_address, unsigned int nwrites, unsigned int *values);
int Feb_Interface_ReadRegister(unsigned int sub_num, unsigned int reg_num,
unsigned int *value_read);
int Feb_Interface_ReadRegisters(unsigned int sub_num, unsigned int nreads,
unsigned int *reg_nums,
unsigned int *values_read);
int Feb_Interface_WriteRegister(unsigned int sub_num, unsigned int reg_num,
unsigned int value, int wait_on,
unsigned int wait_on_address);
int Feb_Interface_WriteRegisters(unsigned int sub_num, unsigned int nwrites,
unsigned int *reg_nums, unsigned int *values,
int *wait_ons,
unsigned int *wait_on_addresses);
int Feb_Interface_WriteMemoryInLoops(unsigned int sub_num, unsigned int mem_num,
unsigned int start_address,
unsigned int nwrites,
unsigned int *values);
int Feb_Interface_WriteMemory(unsigned int sub_num, unsigned int mem_num,
unsigned int start_address, unsigned int nwrites,
unsigned int *values);

70
slsDetectorServers/eigerDetectorServer/FebRegisterDefs.h Executable file → Normal file
View File

@ -22,16 +22,16 @@
#define DAQ_REG_HRDWRE_TOP_OFST (1)
#define DAQ_REG_HRDWRE_TOP_MSK (0x00000001 << DAQ_REG_HRDWRE_TOP_OFST)
#define DAQ_REG_HRDWRE_INTRRPT_SF_OFST (2)
#define DAQ_REG_HRDWRE_INTRRPT_SF_MSK (0x00000001 << DAQ_REG_HRDWRE_INTRRPT_SF_OFST)
#define DAQ_REG_HRDWRE_INTRRPT_SF_MSK \
(0x00000001 << DAQ_REG_HRDWRE_INTRRPT_SF_OFST)
#define DAQ_REG_RO_OFFSET 20
#define DAQ_REG_STATUS (DAQ_REG_RO_OFFSET + 0) //also pg and fifo status register
#define DAQ_REG_STATUS \
(DAQ_REG_RO_OFFSET + 0) // also pg and fifo status register
#define FEB_REG_STATUS (DAQ_REG_RO_OFFSET + 3)
#define MEAS_SUBPERIOD_REG (DAQ_REG_RO_OFFSET + 4)
#define MEAS_PERIOD_REG (DAQ_REG_RO_OFFSET + 5)
#define DAQ_CTRL_RESET 0x80000000
#define DAQ_CTRL_START 0x40000000
#define ACQ_CTRL_START 0x50000000 // this is 0x10000000 (acq) | 0x40000000 (daq)
@ -54,7 +54,8 @@
#define DAQ_IGNORE_INITIAL_CRAP 0x00000400 // crap before readout
#define DAQ_READOUT_NROWS 0x00000800
#define DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START 0x00001000 //last 4 bit of data in the last frame
#define DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START \
0x00001000 // last 4 bit of data in the last frame
#define DAQ_RELEASE_IMAGE_STORE_AFTER_READOUT 0x00002000
#define DAQ_RESET_PIXEL_COUNTERS_AFTER_READOUT 0x00004000
@ -63,52 +64,62 @@
#define DAQ_CLK_MAIN_CLK_TO_SELECT_NEXT_PIXEL 0x00010000
#define DAQ_SEND_N_TEST_PULSES 0x00020000
#define DAQ_CHIP_CONTROLLER_HALF_SPEED 0x00040000 //everything at 100 MHz (50MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_QUARTER_SPEED 0x00080000 //everything at 50 MHz (25MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED 0x000c0000 //everything at ~200 kHz (200 kHz MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_HALF_SPEED \
0x00040000 // everything at 100 MHz (50MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_QUARTER_SPEED \
0x00080000 // everything at 50 MHz (25MHz ddr readout)
#define DAQ_CHIP_CONTROLLER_SUPER_SLOW_SPEED \
0x000c0000 // everything at ~200 kHz (200 kHz MHz ddr readout)
//#define DAQ_FIFO_ENABLE 0x00100000 commented out as it is not used anywhere
//#define DAQ_FIFO_ENABLE 0x00100000 commented out as it
//is not used anywhere
#define DAQ_REG_CHIP_CMDS_INT_TRIGGER 0x00100000
// direct chip commands to the DAQ_REG_CHIP_CMDS register
#define DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE 0x00200000 //row clk is before main clk readout sequence
#define DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE 0x00400000 //expose ->readout ->expose -> ..., with store is always closed
#define DAQ_NEXPOSURERS_SAFEST_MODE_ROW_CLK_BEFORE_MODE \
0x00200000 // row clk is before main clk readout sequence
#define DAQ_NEXPOSURERS_NORMAL_NONPARALLEL_MODE \
0x00400000 // expose ->readout ->expose -> ..., with store is always closed
#define DAQ_NEXPOSURERS_PARALLEL_MODE 0x00600000 // parallel acquire/read mode
//DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES is old now hard-wired in the firmware that every image comes with a header
//#define DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES 0x00800000 //DAQ_IGNORE_INITIAL_CRAP and DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START
// DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES is old now hard-wired in the firmware
// that every image comes with a header #define
//DAQ_NEXPOSURERS_READOUT_COMPLETE_IMAGES 0x00800000
////DAQ_IGNORE_INITIAL_CRAP and DAQ_CLKOUT_LAST_4_BITS_AND_RETURN_TO_START
#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING 0x01000000
#define DAQ_NEXPOSURERS_EXTERNAL_ENABLING_POLARITY 0x02000000
#define DAQ_NEXPOSURERS_EXTERNAL_TRIGGER_POLARITY 0x04000000
#define DAQ_NEXPOSURERS_INTERNAL_ACQUISITION 0x00000000 // internally controlled
#define DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START 0x08000000 //external acquisition start
#define DAQ_NEXPOSURERS_EXTERNAL_ACQUISITION_START \
0x08000000 // external acquisition start
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START 0x10000000 // external image start
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP 0x18000000 //externally controlly, external image start and stop
#define DAQ_NEXPOSURERS_EXTERNAL_IMAGE_START_AND_STOP \
0x18000000 // externally controlly, external image start and stop
#define DAQ_NEXPOSURERS_ACTIVATE_AUTO_SUBIMAGING 0x20000000
#define DAQ_NEXPOSURERS_ACTIVATE_RATE_CORRECTION 0x40000000
//#define DAQ_MASTER_HALF_MODULE 0x80000000 currently not used
//#define DAQ_MASTER_HALF_MODULE 0x80000000 currently not
//used
// chips static bits
#define DAQ_STATIC_BIT_PROGRAM 0x00000001
#define DAQ_STATIC_BIT_M4 0x00000002 // these are the status bits, not bit mode
#define DAQ_STATIC_BIT_M8 0x00000004 // these are the status bits, not bit mode
#define DAQ_STATIC_BIT_M12 0x00000000 //these are the status bits, not bit mode, ie. "00" is 12 bit mode
#define DAQ_STATIC_BIT_M12 \
0x00000000 // these are the status bits, not bit mode, ie. "00" is 12 bit
// mode
#define DAQ_STATIC_BIT_CHIP_TEST 0x00000008
#define DAQ_STATIC_BIT_ROTEST 0x00000010
#define DAQ_CS_BAR_LEFT 0x00000020
#define DAQ_CS_BAR_RIGHT 0x00000040
// status flags
#define DAQ_STATUS_DAQ_RUNNING 0x01
#define DAQ_DATA_COLLISION_ERROR 0x02
#define DAQ_STATUS_CURRENT_M4 0x04
#define DAQ_STATUS_CURRENT_M8 0x08
#define DAQ_STATUS_CURRENT_M12 0x00 // in 12 bit mode both are cleared
@ -146,7 +157,8 @@
#define FLOW_REG_OFFSET 0x140
#define FLOW_REG_TXM_FLOW_CNTRL_10G_OFST (0)
#define FLOW_REG_TXM_FLOW_CNTRL_10G_MSK (0x1 << FLOW_REG_TXM_FLOW_CNTRL_10G_OFST)
#define FLOW_REG_TXM_FLOW_CNTRL_10G_MSK \
(0x1 << FLOW_REG_TXM_FLOW_CNTRL_10G_OFST)
#define FLOW_REG_OVERFLOW_32_BIT_OFST (2)
#define FLOW_REG_OVERFLOW_32_BIT_MSK (0x1 << FLOW_REG_OVERFLOW_32_BIT_OFST)
@ -210,19 +222,3 @@
#define UDP_HEADER_Z_MSK (0xFFFF << UDP_HEADER_Z_OFST)
#define UDP_HEADER_Y_OFST (16)
#define UDP_HEADER_Y_MSK (0xFFFF << UDP_HEADER_Y_OFST)

3
slsDetectorServers/eigerDetectorServer/HardwareIO.h Executable file → Normal file
View File

@ -4,8 +4,6 @@
#include "xfs_types.h"
xfs_u8 HWIO_xfs_in8(xfs_u32 InAddress);
xfs_u16 HWIO_xfs_in16(xfs_u32 InAddress);
xfs_u32 HWIO_xfs_in32(xfs_u32 InAddress);
@ -13,4 +11,3 @@
void HWIO_xfs_out8(xfs_u32 OutAddress, xfs_u8 Value);
void HWIO_xfs_out16(xfs_u32 OutAddress, xfs_u16 Value);
void HWIO_xfs_out32(xfs_u32 OutAddress, xfs_u32 Value);

7
slsDetectorServers/eigerDetectorServer/HardwareMMappingDefs.h Executable file → Normal file
View File

@ -5,7 +5,6 @@
#ifndef __PLB_LL_FIFO_H__
#define __PLB_LL_FIFO_H__
/******************************************************************************/
/* definitions */
/******************************************************************************/
@ -20,7 +19,6 @@
#define PLB_LL_FIFO_CTRL_LL_SOF 0x10000000
#define PLB_LL_FIFO_CTRL_LL_MASK 0xF0000000
#define PLB_LL_FIFO_CTRL_TX_RESET 0x08000000
#define PLB_LL_FIFO_CTRL_RX_RESET 0x04000000
@ -38,10 +36,8 @@
// reset Rx and Tx Fifo and set User Reset
#define PLB_LL_FIFO_CTRL_RESET_FIFO 0x0C400000
#define PLB_LL_FIFO_CTRL_CONFIG_VECTOR 0x000FFFFF
#define PLB_LL_FIFO_STATUS_LL_REM_SHIFT 30
#define PLB_LL_FIFO_STATUS_LL_REM 0xC0000000
#define PLB_LL_FIFO_STATUS_LL_EOF 0x20000000
@ -56,7 +52,4 @@
#define PLB_LL_FIFO_ALMOST_FULL_THRESHOLD_WORDS 100
#endif // __PLB_LL_FIFO_H__

17
slsDetectorServers/eigerDetectorServer/LocalLinkInterface.h Executable file → Normal file
View File

@ -2,7 +2,6 @@
#include "HardwareIO.h"
struct LocalLinkInterface {
xfs_u32 ll_fifo_base;
unsigned int ll_fifo_ctrl_reg;
@ -10,12 +9,16 @@ struct LocalLinkInterface{
int Local_Init(struct LocalLinkInterface *ll, unsigned int ll_fifo_badr);
int Local_Reset1(struct LocalLinkInterface *ll, unsigned int rst_mask);
int Local_ctrl_reg_write_mask(struct LocalLinkInterface* ll,unsigned int mask, unsigned int val);
void Local_LocalLinkInterface1(struct LocalLinkInterface* ll,unsigned int ll_fifo_badr);
int Local_ctrl_reg_write_mask(struct LocalLinkInterface *ll, unsigned int mask,
unsigned int val);
void Local_LocalLinkInterface1(struct LocalLinkInterface *ll,
unsigned int ll_fifo_badr);
unsigned int Local_StatusVector(struct LocalLinkInterface *ll);
int Local_Reset(struct LocalLinkInterface *ll);
int Local_Write(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
int Local_Read(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
int Local_Test(struct LocalLinkInterface* ll,unsigned int buffer_len, void *buffer);
int Local_Write(struct LocalLinkInterface *ll, unsigned int buffer_len,
void *buffer);
int Local_Read(struct LocalLinkInterface *ll, unsigned int buffer_len,
void *buffer);
int Local_Test(struct LocalLinkInterface *ll, unsigned int buffer_len,
void *buffer);
void Local_LocalLinkInterface(struct LocalLinkInterface *ll);

46
slsDetectorServers/eigerDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
View File

@ -10,8 +10,27 @@
#define STATUS_ERROR 2
/* Enums */
enum DACINDEX {E_SVP,E_VTR,E_VRF,E_VRS,E_SVN,E_VTGSTV,E_VCMP_LL,E_VCMP_LR,E_CAL,E_VCMP_RL,E_RXB_RB,E_RXB_LB,E_VCMP_RR,E_VCP,E_VCN,E_VIS,E_VTHRESHOLD};
#define DEFAULT_DAC_VALS { \
enum DACINDEX {
E_SVP,
E_VTR,
E_VRF,
E_VRS,
E_SVN,
E_VTGSTV,
E_VCMP_LL,
E_VCMP_LR,
E_CAL,
E_VCMP_RL,
E_RXB_RB,
E_RXB_LB,
E_VCMP_RR,
E_VCP,
E_VCN,
E_VIS,
E_VTHRESHOLD
};
#define DEFAULT_DAC_VALS \
{ \
0, /* SvP */ \
2480, /* Vtr */ \
3300, /* Vrf */ \
@ -29,7 +48,16 @@ enum DACINDEX {E_SVP,E_VTR,E_VRF,E_VRS,E_SVN,E_VTGSTV,E_VCMP_LL,E_VCMP_L
2000, /* Vcn */ \
1550 /* Vis */ \
};
enum ADCINDEX {TEMP_FPGAEXT, TEMP_10GE, TEMP_DCDC, TEMP_SODL, TEMP_SODR, TEMP_FPGA, TEMP_FPGAFEBL, TEMP_FPGAFEBR};
enum ADCINDEX {
TEMP_FPGAEXT,
TEMP_10GE,
TEMP_DCDC,
TEMP_SODL,
TEMP_SODR,
TEMP_FPGA,
TEMP_FPGAFEBL,
TEMP_FPGAFEBR
};
enum NETWORKINDEX { TXN_LEFT, TXN_RIGHT, TXN_FRAME, FLOWCTRL_10G };
enum ROINDEX { E_PARALLEL, E_NON_PARALLEL };
enum CLKINDEX { RUN_CLK, NUM_CLOCKS };
@ -40,13 +68,13 @@ enum CLKINDEX {RUN_CLK, NUM_CLOCKS};
#define NCHIP (4)
#define NDAC (16)
#define TEN_GIGA_BUFFER_SIZE (4112)
#define ONE_GIGA_BUFFER_SIZE (1040)
#define TEN_GIGA_CONSTANT (4)
#define ONE_GIGA_CONSTANT (16)
#define NORMAL_HIGHVOLTAGE_INPUTPORT "/sys/class/hwmon/hwmon5/device/in0_input"
#define NORMAL_HIGHVOLTAGE_OUTPUTPORT "/sys/class/hwmon/hwmon5/device/out0_output"
#define NORMAL_HIGHVOLTAGE_OUTPUTPORT \
"/sys/class/hwmon/hwmon5/device/out0_output"
#define SPECIAL9M_HIGHVOLTAGE_PORT "/dev/ttyS1"
#define SPECIAL9M_HIGHVOLTAGE_BUFFERSIZE (16)
#define DEFAULT_UDP_SOURCE_PORT (0xE185)
@ -86,12 +114,14 @@ enum CLKINDEX {RUN_CLK, NUM_CLOCKS};
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2048)
#define LTC2620_MIN_VAL (0) // including LTC defines instead of LTC262.h (includes bit banging and blackfin read and write)
#define LTC2620_MIN_VAL \
(0) // including LTC defines instead of LTC262.h (includes bit banging and
// blackfin read and write)
#define LTC2620_MAX_VAL (4095) // 12 bits
#define DAC_MAX_STEPS (4096)
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS (0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
#define MAX_SUBFRAME_EXPOSURE_VAL_IN_10NS \
(0x1FFFFFFF) /** 29 bit register for max subframe exposure value */
#define SLAVE_HIGH_VOLTAGE_READ_VAL (-999)
#define HIGH_VOLTAGE_TOLERANCE (5)

8
slsDetectorServers/eigerDetectorServer/xfs_types.h Executable file → Normal file
View File

@ -14,10 +14,8 @@ typedef signed int xfs_i32;
typedef signed short xfs_i16;
typedef signed char xfs_i8;
// UDP Header
struct udp_header_type
{
struct udp_header_type {
// ethternet frame (14 byte)
uint8_t dst_mac[6];
uint8_t src_mac[6];
@ -41,8 +39,4 @@ struct udp_header_type
uint8_t dst_port[2];
uint8_t udp_message_len[2];
uint8_t udp_checksum[2];
};

62
slsDetectorServers/eigerDetectorServer/xparameters.h Executable file → Normal file
View File

@ -1,4 +1,5 @@
/* ONLY THOSE ARE USED IN THIS SOFTWARE. If one of those is modified in xilinx compilation, this file should be replaced with updated values
/* ONLY THOSE ARE USED IN THIS SOFTWARE. If one of those is modified in xilinx
compilation, this file should be replaced with updated values
XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR
XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR
XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR
@ -24,27 +25,22 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
/******************************************************************/
/* Definitions for peripheral BB_IO_SHIFT_REG_PPC440 */
#define XPAR_BB_IO_SHIFT_REG_PPC440_BASEADDR 0xD3000000
#define XPAR_BB_IO_SHIFT_REG_PPC440_HIGHADDR 0xD300FFFF
/* Definitions for peripheral EIGER_BEB_SYNCH_IO_PPC440 */
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_BASEADDR 0xD3100000
#define XPAR_EIGER_BEB_SYNCH_IO_PPC440_HIGHADDR 0xD310FFFF
/* Definitions for peripheral PLB_BRAM_10G */
#define XPAR_PLB_BRAM_10G_MEM0_BASEADDR 0xD4100000
#define XPAR_PLB_BRAM_10G_MEM0_HIGHADDR 0xD410FFFF
/* Definitions for peripheral PLB_BRAM_TEMAC */
#define XPAR_PLB_BRAM_TEMAC_MEM0_BASEADDR 0xD4000000
#define XPAR_PLB_BRAM_TEMAC_MEM0_HIGHADDR 0xD400FFFF
/* Definitions for peripheral PLB_GPIO_SYS */
#define XPAR_PLB_GPIO_SYS_BASEADDR 0xD1000000
#define XPAR_PLB_GPIO_SYS_HIGHADDR 0xD100FFFF
@ -52,12 +48,9 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
/** Command Generator */
#define XPAR_CMD_GENERATOR 0xC5000000
/** Version Numbers */
#define XPAR_VERSION 0xc6000000
/* Definitions for peripheral PLB_GPIO_TEST */
#define XPAR_PLB_GPIO_TEST_BASEADDR 0xD1010000
#define XPAR_PLB_GPIO_TEST_HIGHADDR 0xD101FFFF
@ -66,9 +59,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define UDP_HEADER_FRAME_NUMBER_LSB_OFST (0x0140)
#define UDP_HEADER_FRAME_NUMBER_MSB_OFST (0x0160)
/* Definitions for packet, frame and delay down counters */
#define XPAR_COUNTER_BASEADDR 0xD1020000
#define XPAR_COUNTER_HIGHADDR 0xD102FFFF
@ -83,8 +73,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define UDP_HEADER_GET_FNUM_10G_RIGHT_LSB_OFST (0x00C4)
#define UDP_HEADER_GET_FNUM_10G_RIGHT_MSB_OFST (0x00E4)
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT */
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR 0xC4100000
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_HIGHADDR 0xC410FFFF
@ -92,46 +80,37 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
/* Definitions for a new memory */
//#define XPAR_PLB_LL_NEW_MEMORY 0xD1000000//0xD1000084//0xC4200000
/* Definitions for peripheral PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT */
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_BASEADDR 0xC4110000
#define XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_RIGHT_HIGHADDR 0xC411FFFF
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_LEFT */
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_BASEADDR 0xC4120000
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_LEFT_HIGHADDR 0xC412FFFF
/* Definitions for peripheral PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT */
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_BASEADDR 0xC4130000
#define XPAR_PLB_LL_FIFO_AURORA_RX4_TX1_RIGHT_HIGHADDR 0xC413FFFF
/* Definitions for peripheral PLB_LL_FIFO_XAUI_10G */
#define XPAR_PLB_LL_FIFO_XAUI_10G_BASEADDR 0xC4140000
#define XPAR_PLB_LL_FIFO_XAUI_10G_HIGHADDR 0xC414FFFF
/* Definitions for peripheral PLB_V46_CPU_TO_PLB_V46_BRIDGED */
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_BASEADDR 0xCFFF0000
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_BRIDGE_HIGHADDR 0xCFFFFFFF
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_BASEADDR 0xD0000000
#define XPAR_PLB_V46_CPU_TO_PLB_V46_BRIDGED_RNG0_HIGHADDR 0xDFFFFFFF
/* Definitions for peripheral PPC_SRAM */
#define XPAR_PPC_SRAM_BASEADDR 0x00000000
#define XPAR_PPC_SRAM_HIGHADDR 0x01FFFFFF
/******************************************************************/
/* Definitions for peripheral PFLASH */
#define XPAR_PFLASH_NUM_BANKS_MEM 1
/******************************************************************/
/* Definitions for peripheral PFLASH */
@ -155,13 +134,11 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_PLB_SHT1X_IF_CH1_BASEADDR 0xD2200000
#define XPAR_PLB_SHT1X_IF_CH1_HIGHADDR 0xD220FFFF
/* Definitions for peripheral PLB_SHT1X_IF_CH2 */
#define XPAR_PLB_SHT1X_IF_CH2_DEVICE_ID 1
#define XPAR_PLB_SHT1X_IF_CH2_BASEADDR 0xD2210000
#define XPAR_PLB_SHT1X_IF_CH2_HIGHADDR 0xD221FFFF
/******************************************************************/
/* Definitions for driver UARTLITE */
@ -176,10 +153,8 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_RS232_ODD_PARITY 0
#define XPAR_RS232_DATA_BITS 8
/******************************************************************/
/* Canonical definitions for peripheral RS232 */
#define XPAR_UARTLITE_0_DEVICE_ID XPAR_RS232_DEVICE_ID
#define XPAR_UARTLITE_0_BASEADDR 0xC0000000
@ -190,7 +165,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_UARTLITE_0_DATA_BITS 8
#define XPAR_UARTLITE_0_SIO_CHAN 1
/******************************************************************/
/* Definitions for driver SPI */
@ -205,7 +179,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_SPI_FLASH_NUM_SS_BITS 1
#define XPAR_SPI_FLASH_NUM_TRANSFER_BITS 8
/* Definitions for peripheral XPS_SPI_FEB_CFG */
#define XPAR_XPS_SPI_FEB_CFG_DEVICE_ID 1
#define XPAR_XPS_SPI_FEB_CFG_BASEADDR 0xD2010000
@ -215,10 +188,8 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XPS_SPI_FEB_CFG_NUM_SS_BITS 2
#define XPAR_XPS_SPI_FEB_CFG_NUM_TRANSFER_BITS 8
/******************************************************************/
/* Canonical definitions for peripheral SPI_FLASH */
#define XPAR_SPI_0_DEVICE_ID XPAR_SPI_FLASH_DEVICE_ID
#define XPAR_SPI_0_BASEADDR 0xD2000000
@ -228,7 +199,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_SPI_0_NUM_SS_BITS 1
#define XPAR_SPI_0_NUM_TRANSFER_BITS 8
/* Canonical definitions for peripheral XPS_SPI_FEB_CFG */
#define XPAR_SPI_1_DEVICE_ID XPAR_XPS_SPI_FEB_CFG_DEVICE_ID
#define XPAR_SPI_1_BASEADDR 0xD2010000
@ -238,7 +208,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_SPI_1_NUM_SS_BITS 2
#define XPAR_SPI_1_NUM_TRANSFER_BITS 8
/******************************************************************/
/* Definitions for driver LLTEMAC */
@ -275,23 +244,18 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_LLTEMAC_0_MCAST_EXTEND 0
#define XPAR_LLTEMAC_0_INTR 1
/* LocalLink TYPE Enumerations */
#define XPAR_LL_FIFO 1
#define XPAR_LL_DMA 2
/* Canonical LocalLink parameters for TEMAC_INST */
/******************************************************************/
/* Definitions for peripheral XPS_BRAM_IF_CNTLR_PPC440 */
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_BASEADDR 0xFFFC0000
#define XPAR_XPS_BRAM_IF_CNTLR_PPC440_HIGHADDR 0xFFFFFFFF
/******************************************************************/
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 5
@ -306,7 +270,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XPS_INTC_PPC440_HIGHADDR 0xC100FFFF
#define XPAR_XPS_INTC_PPC440_KIND_OF_INTR 0xFFFFFFF4
/******************************************************************/
#define XPAR_INTC_SINGLE_BASEADDR 0xC1000000
@ -331,10 +294,14 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_INTC_0_HIGHADDR 0xC100FFFF
#define XPAR_INTC_0_KIND_OF_INTR 0xFFFFFFF4
#define XPAR_INTC_0_LLFIFO_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_LLTEMAC_0_VEC_ID XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
#define XPAR_INTC_0_TMRCTR_0_VEC_ID XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
#define XPAR_INTC_0_SPI_0_VEC_ID XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_LLFIFO_0_VEC_ID \
XPAR_XPS_INTC_PPC440_XPS_LL_FIFO_TEMAC_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_LLTEMAC_0_VEC_ID \
XPAR_XPS_INTC_PPC440_TEMAC_INST_TEMACINTC0_IRPT_INTR
#define XPAR_INTC_0_TMRCTR_0_VEC_ID \
XPAR_XPS_INTC_PPC440_XPS_TIMER_PPC440_INTERRUPT_INTR
#define XPAR_INTC_0_SPI_0_VEC_ID \
XPAR_XPS_INTC_PPC440_SPI_FLASH_IP2INTC_IRPT_INTR
#define XPAR_INTC_0_UARTLITE_0_VEC_ID XPAR_XPS_INTC_PPC440_RS232_INTERRUPT_INTR
/******************************************************************/
@ -347,7 +314,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XPS_LL_FIFO_TEMAC_BASEADDR 0xC4000000
#define XPAR_XPS_LL_FIFO_TEMAC_HIGHADDR 0xC400FFFF
/******************************************************************/
/* Canonical definitions for peripheral XPS_LL_FIFO_TEMAC */
@ -355,7 +321,6 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_LLFIFO_0_BASEADDR 0xC4000000
#define XPAR_LLFIFO_0_HIGHADDR 0xC400FFFF
/******************************************************************/
/* Definitions for driver SYSMON */
@ -367,17 +332,14 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XPS_SYSMON_ADC_PPC440_HIGHADDR 0xD001FFFF
#define XPAR_XPS_SYSMON_ADC_PPC440_INCLUDE_INTR 1
/******************************************************************/
/* Canonical definitions for peripheral XPS_SYSMON_ADC_PPC440 */
#define XPAR_SYSMON_0_DEVICE_ID XPAR_XPS_SYSMON_ADC_PPC440_DEVICE_ID
#define XPAR_SYSMON_0_BASEADDR 0xD0010000
#define XPAR_SYSMON_0_HIGHADDR 0xD001FFFF
#define XPAR_SYSMON_0_INCLUDE_INTR 1
/******************************************************************/
/* Definitions for driver TMRCTR */
@ -388,16 +350,13 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_XPS_TIMER_PPC440_BASEADDR 0xC2000000
#define XPAR_XPS_TIMER_PPC440_HIGHADDR 0xC200FFFF
/******************************************************************/
/* Canonical definitions for peripheral XPS_TIMER_PPC440 */
#define XPAR_TMRCTR_0_DEVICE_ID XPAR_XPS_TIMER_PPC440_DEVICE_ID
#define XPAR_TMRCTR_0_BASEADDR 0xC2000000
#define XPAR_TMRCTR_0_HIGHADDR 0xC200FFFF
/******************************************************************/
/* Definitions for bus frequencies */
@ -553,4 +512,3 @@ XPAR_PLB_LL_FIFO_AURORA_DUAL_CTRL_FEB_LEFT_BASEADDR
#define XPAR_PPC440_VIRTEX5_HW_VER "1.01.a"
/******************************************************************/

59
slsDetectorServers/gotthard2DetectorServer/RegisterDefs.h
View File

@ -1,9 +1,7 @@
#pragma once
#define REG_OFFSET (4)
/* Base addresses 0x1804 0000 ---------------------------------------------*/
/* Reconfiguration core for readout pll */
#define BASE_READOUT_PLL (0x0000) // 0x1804_0000 - 0x1804_07FF
@ -39,9 +37,8 @@
/* UDP datagram generator */
#define BASE_UDP_RAM (0x01000) // 0x1806_1000 - 0x1806_1FFF
/* Clock Generation registers ------------------------------------------------------*/
/* Clock Generation registers
* ------------------------------------------------------*/
#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
#define PLL_RESET_READOUT_OFST (0)
@ -49,8 +46,6 @@
#define PLL_RESET_SYSTEM_OFST (1)
#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
/* Control registers --------------------------------------------------*/
/* Module Control Board Serial Number register */
@ -73,7 +68,8 @@
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK \
(0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
/* Fix pattern register */
#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
@ -105,15 +101,14 @@
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
#define CONTROL_TIMING_SOURCE_EXT_OFST (17)
#define CONTROL_TIMING_SOURCE_EXT_MSK (0x00000001 << CONTROL_TIMING_SOURCE_EXT_OFST)
#define CONTROL_TIMING_SOURCE_EXT_MSK \
(0x00000001 << CONTROL_TIMING_SOURCE_EXT_OFST)
#define CONTROL_PWR_CHIP_OFST (31)
#define CONTROL_PWR_CHIP_MSK (0x00000001 << CONTROL_PWR_CHIP_OFST)
/** DTA Offset Register */
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
/* ASIC registers --------------------------------------------------*/
/* ASIC Config register */
@ -121,17 +116,25 @@
#define ASIC_CONFIG_RUN_MODE_OFST (0)
#define ASIC_CONFIG_RUN_MODE_MSK (0x00000003 << ASIC_CONFIG_RUN_MODE_OFST)
#define ASIC_CONFIG_RUN_MODE_INT_BURST_VAL ((0x1 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_CONT_VAL ((0x2 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL ((0x3 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_INT_BURST_VAL \
((0x1 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_CONT_VAL \
((0x2 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_RUN_MODE_EXT_BURST_VAL \
((0x3 << ASIC_CONFIG_RUN_MODE_OFST) & ASIC_CONFIG_RUN_MODE_MSK)
#define ASIC_CONFIG_GAIN_OFST (4)
#define ASIC_CONFIG_GAIN_MSK (0x00000003 << ASIC_CONFIG_GAIN_OFST)
#define ASIC_CONFIG_DYNAMIC_GAIN_VAL ((0x0 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_1_VAL ((0x1 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_2_VAL ((0x2 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_RESERVED_VAL ((0x3 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_DYNAMIC_GAIN_VAL \
((0x0 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_1_VAL \
((0x1 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_FIX_GAIN_2_VAL \
((0x2 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_RESERVED_VAL \
((0x3 << ASIC_CONFIG_GAIN_OFST) & ASIC_CONFIG_GAIN_MSK)
#define ASIC_CONFIG_CURRENT_SRC_EN_OFST (7)
#define ASIC_CONFIG_CURRENT_SRC_EN_MSK (0x00000001 << ASIC_CONFIG_CURRENT_SRC_EN_OFST)
#define ASIC_CONFIG_CURRENT_SRC_EN_MSK \
(0x00000001 << ASIC_CONFIG_CURRENT_SRC_EN_OFST)
#define ASIC_CONFIG_RST_DAC_OFST (15)
#define ASIC_CONFIG_RST_DAC_MSK (0x00000001 << ASIC_CONFIG_RST_DAC_OFST)
#define ASIC_CONFIG_DONE_OFST (31)
@ -151,8 +154,6 @@
#define ASIC_INT_EXPTIME_LSB_REG (0x04 * REG_OFFSET + BASE_ASIC)
#define ASIC_INT_EXPTIME_MSB_REG (0x05 * REG_OFFSET + BASE_ASIC)
/* Packetizer -------------------------------------------------------------*/
/* Packetizer Config Register */
@ -175,8 +176,8 @@
#define COORD_RESERVED_OFST (0)
#define COORD_RESERVED_MSK (0x0000FFFF << COORD_RESERVED_OFST)
#define COORD_ID_OFST (16) // Not connected in firmware TODO
#define COORD_ID_MSK (0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
#define COORD_ID_MSK \
(0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
/* Flow control registers --------------------------------------------------*/
@ -186,13 +187,16 @@
#define FLOW_STATUS_RUN_BUSY_OFST (0)
#define FLOW_STATUS_RUN_BUSY_MSK (0x00000001 << FLOW_STATUS_RUN_BUSY_OFST)
#define FLOW_STATUS_WAIT_FOR_TRGGR_OFST (3)
#define FLOW_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << FLOW_STATUS_WAIT_FOR_TRGGR_OFST)
#define FLOW_STATUS_WAIT_FOR_TRGGR_MSK \
(0x00000001 << FLOW_STATUS_WAIT_FOR_TRGGR_OFST)
#define FLOW_STATUS_DLY_BFRE_TRGGR_OFST (4)
#define FLOW_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << FLOW_STATUS_DLY_BFRE_TRGGR_OFST)
#define FLOW_STATUS_DLY_BFRE_TRGGR_MSK \
(0x00000001 << FLOW_STATUS_DLY_BFRE_TRGGR_OFST)
#define FLOW_STATUS_FIFO_FULL_OFST (5)
#define FLOW_STATUS_FIFO_FULL_MSK (0x00000001 << FLOW_STATUS_FIFO_FULL_OFST)
#define FLOW_STATUS_DLY_AFTR_TRGGR_OFST (15)
#define FLOW_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << FLOW_STATUS_DLY_AFTR_TRGGR_OFST)
#define FLOW_STATUS_DLY_AFTR_TRGGR_MSK \
(0x00000001 << FLOW_STATUS_DLY_AFTR_TRGGR_OFST)
#define FLOW_STATUS_CSM_BUSY_OFST (17)
#define FLOW_STATUS_CSM_BUSY_MSK (0x00000001 << FLOW_STATUS_CSM_BUSY_OFST)
@ -216,7 +220,8 @@
#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_FLOW_CONTROL)
#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_FLOW_CONTROL)
/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
/* Get Frames from Start 64 bit register (frames from last reset using
* CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_FLOW_CONTROL)
#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_FLOW_CONTROL)

74
slsDetectorServers/gotthard2DetectorServer/slsDetectorServer_defs.h
View File

@ -62,42 +62,58 @@
#define BIT16_MASK (0xFFFF)
/* Enums */
enum DACINDEX {G2_VREF_H_ADC, /* 0 */ \
G2_DAC_UNUSED, /* 1 */ \
G2_VB_COMP_FE, /* 2 */ \
G2_VB_COMP_ADC, /* 3 */ \
G2_VCOM_CDS, /* 4 */ \
G2_VREF_RSTORE,/* 5 */ \
G2_VB_OPA_1ST, /* 6 */ \
G2_VREF_COMP_FE,/* 7 */ \
G2_VCOM_ADC1, /* 8 */ \
G2_VREF_PRECH, /* 9 */ \
G2_VREF_L_ADC, /* 10 */ \
G2_VREF_CDS, /* 11 */ \
G2_VB_CS, /* 12 */ \
G2_VB_OPA_FD, /* 13 */ \
G2_DAC_UNUSED2, /* 14 */ \
G2_VCOM_ADC2 /* 15*/ \
enum DACINDEX {
G2_VREF_H_ADC, /* 0 */
G2_DAC_UNUSED, /* 1 */
G2_VB_COMP_FE, /* 2 */
G2_VB_COMP_ADC, /* 3 */
G2_VCOM_CDS, /* 4 */
G2_VREF_RSTORE, /* 5 */
G2_VB_OPA_1ST, /* 6 */
G2_VREF_COMP_FE, /* 7 */
G2_VCOM_ADC1, /* 8 */
G2_VREF_PRECH, /* 9 */
G2_VREF_L_ADC, /* 10 */
G2_VREF_CDS, /* 11 */
G2_VB_CS, /* 12 */
G2_VB_OPA_FD, /* 13 */
G2_DAC_UNUSED2, /* 14 */
G2_VCOM_ADC2 /* 15*/
};
#define DAC_NAMES "vref_h_adc", "dac_unused", "vb_comp_fe", "vb_comp_adc", "vcom_cds", "vref_rstore", "vb_opa_1st", "vref_comp_fe", "vcom_adc1", "vref_prech", "vref_l_adc", "vref_cds", "vb_cs", "vb_opa_fd", "dac_unused2", "vcom_adc2"
#define DAC_NAMES \
"vref_h_adc", "dac_unused", "vb_comp_fe", "vb_comp_adc", "vcom_cds", \
"vref_rstore", "vb_opa_1st", "vref_comp_fe", "vcom_adc1", \
"vref_prech", "vref_l_adc", "vref_cds", "vb_cs", "vb_opa_fd", \
"dac_unused2", "vcom_adc2"
enum ONCHIP_DACINDEX {G2_VCHIP_COMP_FE, /* 0 */ \
G2_VCHIP_OPA_1ST, /* 1 */ \
G2_VCHIP_OPA_FD, /* 2 */ \
G2_VCHIP_COMP_ADC, /* 3 */ \
G2_VCHIP_UNUSED, /* 4 */ \
G2_VCHIP_REF_COMP_FE, /* 5 */ \
G2_VCHIP_CS /* 6 */ \
enum ONCHIP_DACINDEX {
G2_VCHIP_COMP_FE, /* 0 */
G2_VCHIP_OPA_1ST, /* 1 */
G2_VCHIP_OPA_FD, /* 2 */
G2_VCHIP_COMP_ADC, /* 3 */
G2_VCHIP_UNUSED, /* 4 */
G2_VCHIP_REF_COMP_FE, /* 5 */
G2_VCHIP_CS /* 6 */
};
#define ONCHIP_DAC_NAMES "vchip_comp_fe", "vchip_opa_1st", "vchip_opa_fd", "vchip_comp_adc", "vchip_unused", "vchip_ref_comp_fe", "vchip_cs"
#define ONCHIP_DAC_NAMES \
"vchip_comp_fe", "vchip_opa_1st", "vchip_opa_fd", "vchip_comp_adc", \
"vchip_unused", "vchip_ref_comp_fe", "vchip_cs"
enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, SYSTEM_C3, NUM_CLOCKS};
#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", "SYSTEM_C3"
enum CLKINDEX {
READOUT_C0,
READOUT_C1,
SYSTEM_C0,
SYSTEM_C1,
SYSTEM_C2,
SYSTEM_C3,
NUM_CLOCKS
};
#define CLK_NAMES \
"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2", \
"SYSTEM_C3"
enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
/** Chip Definitions */
#define ASIC_ADDR_MAX_BITS (4)
#define ASIC_CURRENT_INJECT_ADDR (0x9)

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@ -8,11 +8,16 @@
#define GAIN_CONFGAIN_OFST (0)
#define GAIN_CONFGAIN_MSK (0x000000FF << GAIN_CONFGAIN_OFST)
#define GAIN_CONFGAIN_HGH_GAIN_VAL ((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_DYNMC_GAIN_VAL ((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_LW_GAIN_VAL ((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_MDM_GAIN_VAL ((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL ((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_HGH_GAIN_VAL \
((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_DYNMC_GAIN_VAL \
((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_LW_GAIN_VAL \
((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_MDM_GAIN_VAL \
((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL \
((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
/** Flow Control register */
//#define FLOW_CONTROL_REG (0x11 << MEM_MAP_SHIFT)
@ -60,12 +65,16 @@
#define DAQ_TKN_TMNG_OFST (0)
#define DAQ_TKN_TMNG_MSK (0x0000FFFF << DAQ_TKN_TMNG_OFST)
#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL ((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL ((0x1f10 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL \
((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL \
((0x1f10 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_PCKT_LNGTH_OFST (16)
#define DAQ_PCKT_LNGTH_MSK (0x0000FFFF << DAQ_PCKT_LNGTH_OFST)
#define DAQ_PCKT_LNGTH_NO_ROI_VAL ((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
#define DAQ_PCKT_LNGTH_ROI_VAL ((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
#define DAQ_PCKT_LNGTH_NO_ROI_VAL \
((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
#define DAQ_PCKT_LNGTH_ROI_VAL \
((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
/** Time From Start register */
//#define TIME_FROM_START_REG (0x16 << MEM_MAP_SHIFT)
@ -95,27 +104,37 @@
#define ADC_SYNC_ENET_STRT_DLY_OFST (0)
#define ADC_SYNC_ENET_STRT_DLY_MSK (0x0000000F << ADC_SYNC_ENET_STRT_DLY_OFST)
#define ADC_SYNC_ENET_STRT_DLY_VAL ((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
#define ADC_SYNC_ENET_STRT_DLY_VAL \
((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
#define ADC_SYNC_TKN1_HGH_DLY_OFST (4)
#define ADC_SYNC_TKN1_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_HGH_DLY_OFST)
#define ADC_SYNC_TKN1_HGH_DLY_VAL ((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
#define ADC_SYNC_TKN1_HGH_DLY_VAL \
((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
#define ADC_SYNC_TKN2_HGH_DLY_OFST (8)
#define ADC_SYNC_TKN2_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_HGH_DLY_OFST)
#define ADC_SYNC_TKN2_HGH_DLY_VAL ((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
#define ADC_SYNC_TKN2_HGH_DLY_VAL \
((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
#define ADC_SYNC_TKN1_LOW_DLY_OFST (12)
#define ADC_SYNC_TKN1_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_LOW_DLY_OFST)
#define ADC_SYNC_TKN1_LOW_DLY_VAL ((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
#define ADC_SYNC_TKN1_LOW_DLY_VAL \
((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
#define ADC_SYNC_TKN2_LOW_DLY_OFST (16)
#define ADC_SYNC_TKN2_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_LOW_DLY_OFST)
#define ADC_SYNC_TKN2_LOW_DLY_VAL ((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
#define ADC_SYNC_TKN2_LOW_DLY_VAL \
((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
// 0x32214
#define ADC_SYNC_TKN_VAL (ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL | ADC_SYNC_TKN2_LOW_DLY_VAL)
#define ADC_SYNC_TKN_VAL \
(ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | \
ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL | \
ADC_SYNC_TKN2_LOW_DLY_VAL)
#define ADC_SYNC_CLEAN_FIFOS_OFST (20)
#define ADC_SYNC_CLEAN_FIFOS_MSK (0x00000001 << ADC_SYNC_CLEAN_FIFOS_OFST)
#define ADC_SYNC_ENET_DELAY_OFST (24)
#define ADC_SYNC_ENET_DELAY_MSK (0x000000FF << ADC_SYNC_ENET_DELAY_OFST)
#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL ((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_ROI_VAL ((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL \
((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_ROI_VAL \
((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
/** Time From Start register */
//#define MU_TIME_REG (0x1a << MEM_MAP_SHIFT)
@ -131,7 +150,9 @@
#define TEMP_SPI_IN_T2_CLK_MSK (0x00000001 << TEMP_SPI_IN_T2_CLK_OFST)
#define TEMP_SPI_IN_T2_CS_OFST (3)
#define TEMP_SPI_IN_T2_CS_MSK (0x00000001 << TEMP_SPI_IN_T2_CS_OFST)
#define TEMP_SPI_IN_IDLE_MSK (TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CS_MSK | TEMP_SPI_IN_T1_CLK_MSK | TEMP_SPI_IN_T2_CLK_MSK)
#define TEMP_SPI_IN_IDLE_MSK \
(TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CS_MSK | TEMP_SPI_IN_T1_CLK_MSK | \
TEMP_SPI_IN_T2_CLK_MSK)
/** Temperatre SPI Out register */
#define TEMP_SPI_OUT_REG (0x1c << MEM_MAP_SHIFT)
@ -171,7 +192,8 @@
#define FPGA_VERSION_REG (0x22 << MEM_MAP_SHIFT)
#define FPGA_VERSION_OFST (0)
#define FPGA_VERSION_MSK (0x00FFFFFF << FPGA_VERSION_OFST) // to get in format yymmdd
#define FPGA_VERSION_MSK \
(0x00FFFFFF << FPGA_VERSION_OFST) // to get in format yymmdd
/* Fix Pattern register */
#define FIX_PATT_REG (0x23 << MEM_MAP_SHIFT)
@ -260,7 +282,8 @@
#define EXT_SIGNAL_MSK (0x00000007 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_OFF_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_RSNG_VAL ((0x3 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL ((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL \
((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/** Look at me register */
//#define LOOK_AT_ME_REG (0x28 << MEM_MAP_SHIFT)
@ -274,7 +297,8 @@
#define CHIP_OF_INTRST_ADC_SEL_OFST (0)
#define CHIP_OF_INTRST_ADC_SEL_MSK (0x0000001F << CHIP_OF_INTRST_ADC_SEL_OFST)
#define CHIP_OF_INTRST_NUM_CHNNLS_OFST (16)
#define CHIP_OF_INTRST_NUM_CHNNLS_MSK (0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
#define CHIP_OF_INTRST_NUM_CHNNLS_MSK \
(0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
/** Out MUX register */
//#define OUT_MUX_REG (0x2b << MEM_MAP_SHIFT)
@ -366,4 +390,3 @@
/* Counter Block Memory starting address */
#define COUNTER_MEMORY_REG (0x85 << MEM_MAP_SHIFT)

21
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
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@ -4,11 +4,21 @@
/* Enums */
enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
enum DACINDEX {G_VREF_DS, G_VCASCN_PB, G_VCASCP_PB, G_VOUT_CM, G_VCASC_OUT, G_VIN_CM, G_VREF_COMP, G_IB_TESTC};
enum DACINDEX {
G_VREF_DS,
G_VCASCN_PB,
G_VCASCP_PB,
G_VOUT_CM,
G_VCASC_OUT,
G_VIN_CM,
G_VREF_COMP,
G_IB_TESTC
};
enum CLKINDEX { ADC_CLK, NUM_CLOCKS };
#define CLK_NAMES "adc"
#define DEFAULT_DAC_VALS { \
#define DEFAULT_DAC_VALS \
{ \
660, /* G_VREF_DS */ \
650, /* G_VCASCN_PB */ \
1480, /* G_VCASCP_PB */ \
@ -34,10 +44,12 @@ enum CLKINDEX {ADC_CLK, NUM_CLOCKS};
#define CLK_FREQ (32007729) /* Hz */
/** Firmware Definitions */
#define IP_PACKET_SIZE_NO_ROI (NCHIP * (NCHAN / 2) * 2 + 14 + 20) // 2 packets, so divide by 2
#define IP_PACKET_SIZE_NO_ROI \
(NCHIP * (NCHAN / 2) * 2 + 14 + 20) // 2 packets, so divide by 2
#define IP_PACKET_SIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20)
#define UDP_PACKETSIZE_NO_ROI (NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2) // 2 packets, so divide by 2
#define UDP_PACKETSIZE_NO_ROI \
(NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2) // 2 packets, so divide by 2
#define UDP_PACKETSIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2)
/** Default Parameters */
@ -124,4 +136,3 @@ typedef struct tse_conf_struct{
u_int32_t mdio_addr0; // 0xF
u_int32_t mdio_addr1;
} tse_conf;

238
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@ -11,8 +11,6 @@
#define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
/* Fix pattern register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
@ -34,27 +32,30 @@
#define RUNMACHINE_BUSY_OFST (17)
#define RUNMACHINE_BUSY_MSK (0x00000001 << RUNMACHINE_BUSY_OFST)
/* Look at me register */
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT) //Not used in firmware or software
#define LOOK_AT_ME_REG \
(0x03 << MEM_MAP_SHIFT) // Not used in firmware or software
/* System Status register */
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT) // Not used in software
#define DDR3_CAL_DONE_OFST (0) // Not used in software
#define DDR3_CAL_DONE_MSK (0x00000001 << DDR3_CAL_DONE_OFST) //Not used in software
#define DDR3_CAL_DONE_MSK \
(0x00000001 << DDR3_CAL_DONE_OFST) // Not used in software
#define DDR3_CAL_FAIL_OFST (1) // Not used in software
#define DDR3_CAL_FAIL_MSK (0x00000001 << DDR3_CAL_FAIL_OFST) //Not used in software
#define DDR3_CAL_FAIL_MSK \
(0x00000001 << DDR3_CAL_FAIL_OFST) // Not used in software
#define DDR3_INIT_DONE_OFST (2) // Not used in software
#define DDR3_INIT_DONE_MSK (0x00000001 << DDR3_INIT_DONE_OFST) //Not used in software
#define DDR3_INIT_DONE_MSK \
(0x00000001 << DDR3_INIT_DONE_OFST) // Not used in software
#define RECONFIG_PLL_LCK_OFST (3) // Not used in software
#define RECONFIG_PLL_LCK_MSK (0x00000001 << RECONFIG_PLL_LCK_OFST) //Not used in software
#define RECONFIG_PLL_LCK_MSK \
(0x00000001 << RECONFIG_PLL_LCK_OFST) // Not used in software
#define PLL_A_LCK_OFST (4) // Not used in software
#define PLL_A_LCK_MSK (0x00000001 << PLL_A_LCK_OFST) // Not used in software
#define DD3_PLL_LCK_OFST (5) // Not used in software
#define DD3_PLL_LCK_MSK (0x00000001 << DD3_PLL_LCK_OFST) // Not used in software
/* Module Control Board Serial Number Register */
#define MOD_SERIAL_NUM_REG (0x0A << MEM_MAP_SHIFT)
@ -62,8 +63,8 @@
#define HARDWARE_SERIAL_NUM_MSK (0x000000FF << HARDWARE_SERIAL_NUM_OFST)
#define HARDWARE_VERSION_NUM_OFST (16)
#define HARDWARE_VERSION_NUM_MSK (0x0000003F << HARDWARE_VERSION_NUM_OFST)
#define HARDWARE_VERSION_2_VAL ((0x2 << HARDWARE_VERSION_NUM_OFST) & HARDWARE_VERSION_NUM_MSK)
#define HARDWARE_VERSION_2_VAL \
((0x2 << HARDWARE_VERSION_NUM_OFST) & HARDWARE_VERSION_NUM_MSK)
/* API Version Register */
#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
@ -71,7 +72,8 @@
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK \
(0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
/* Time from Start 64 bit register */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
@ -94,14 +96,17 @@
#define GET_PERIOD_MSB_REG (0x19 << MEM_MAP_SHIFT)
/** Get Temperature Carlos, incorrectl as get gates */
#define GET_TEMPERATURE_TMP112_REG (0x1c << MEM_MAP_SHIFT) // (after multiplying by 625) in 10ths of millidegrees of TMP112
#define GET_TEMPERATURE_TMP112_REG \
(0x1c << MEM_MAP_SHIFT) // (after multiplying by 625) in 10ths of
// millidegrees of TMP112
#define TEMPERATURE_VALUE_BIT (0)
#define TEMPERATURE_VALUE_MSK (0x000007FF << TEMPERATURE_VALUE_BIT)
#define TEMPERATURE_POLARITY_BIT (11)
#define TEMPERATURE_POLARITY_MSK (0x00000001 << TEMPERATURE_POLARITY_BIT)
/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
/* Get Frames from Start 64 bit register (frames from last reset using
* CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT)
@ -157,19 +162,25 @@
/* Configuration Register */
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
// readout timer (from chip) to stabilize (esp in burst acquisition mode) tRDT = (RDT + 1) * 25ns
// readout timer (from chip) to stabilize (esp in burst acquisition mode) tRDT =
// (RDT + 1) * 25ns
#define CONFIG_RDT_TMR_OFST (0)
#define CONFIG_RDT_TMR_MSK (0x0000FFFF << CONFIG_RDT_TMR_OFST)
#define CONFIG_OPRTN_MDE_2_X_10GbE_OFST (16)
#define CONFIG_OPRTN_MDE_2_X_10GbE_MSK (0x00000001 << CONFIG_OPRTN_MDE_2_X_10GbE_OFST)
#define CONFIG_OPRTN_MDE_2_X_10GbE_MSK \
(0x00000001 << CONFIG_OPRTN_MDE_2_X_10GbE_OFST)
// if 0, outer is the primary interface
#define CONFIG_INNR_PRIMRY_INTRFCE_OFST (17)
#define CONFIG_INNR_PRIMRY_INTRFCE_MSK (0x00000001 << CONFIG_INNR_PRIMRY_INTRFCE_OFST)
#define CONFIG_INNR_PRIMRY_INTRFCE_MSK \
(0x00000001 << CONFIG_INNR_PRIMRY_INTRFCE_OFST)
#define CONFIG_READOUT_SPEED_OFST (20)
#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST)
#define CONFIG_QUARTER_SPEED_10MHZ_VAL ((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_HALF_SPEED_20MHZ_VAL ((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_FULL_SPEED_40MHZ_VAL ((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_QUARTER_SPEED_10MHZ_VAL \
((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_HALF_SPEED_20MHZ_VAL \
((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_FULL_SPEED_40MHZ_VAL \
((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
#define CONFIG_TDMA_ENABLE_OFST (24)
#define CONFIG_TDMA_ENABLE_MSK (0x00000001 << CONFIG_TDMA_ENABLE_OFST)
#define CONFIG_TDMA_TIMESLOT_OFST (25) // 1ms
@ -193,20 +204,24 @@
#define CONTROL_CORE_RST_OFST (10)
#define CONTROL_CORE_RST_MSK (0x00000001 << CONTROL_CORE_RST_OFST)
#define CONTROL_PERIPHERAL_RST_OFST (11) // DDR3 HMem Ctrlr, GBE, Temp
#define CONTROL_PERIPHERAL_RST_MSK (0x00000001 << CONTROL_PERIPHERAL_RST_OFST) //DDR3 HMem Ctrlr, GBE, Temp
#define CONTROL_DDR3_MEM_RST_OFST (12) //only PHY, not DDR3 PLL ,Not used in software
#define CONTROL_DDR3_MEM_RST_MSK (0x00000001 << CONTROL_DDR3_MEM_RST_OFST) //only PHY, not DDR3 PLL ,Not used in software
#define CONTROL_PERIPHERAL_RST_MSK \
(0x00000001 << CONTROL_PERIPHERAL_RST_OFST) // DDR3 HMem Ctrlr, GBE, Temp
#define CONTROL_DDR3_MEM_RST_OFST \
(12) // only PHY, not DDR3 PLL ,Not used in software
#define CONTROL_DDR3_MEM_RST_MSK \
(0x00000001 << CONTROL_DDR3_MEM_RST_OFST) // only PHY, not DDR3 PLL ,Not
// used in software
#define CONTROL_ACQ_FIFO_CLR_OFST (14)
#define CONTROL_ACQ_FIFO_CLR_MSK (0x00000001 << CONTROL_ACQ_FIFO_CLR_OFST)
#define CONTROL_STORAGE_CELL_NUM_OFST (16)
#define CONTROL_STORAGE_CELL_NUM_MSK (0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
#define CONTROL_STORAGE_CELL_NUM_MSK \
(0x0000000F << CONTROL_STORAGE_CELL_NUM_OFST)
#define CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST (20)
#define CONTROL_RX_ADDTNL_ENDPTS_NUM_MSK (0x0000003F << CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST)
#define CONTROL_RX_ADDTNL_ENDPTS_NUM_MSK \
(0x0000003F << CONTROL_RX_ADDTNL_ENDPTS_NUM_OFST)
#define CONTROL_RX_ENDPTS_START_OFST (26)
#define CONTROL_RX_ENDPTS_START_MSK (0x0000003F << CONTROL_RX_ENDPTS_START_OFST)
/* Reconfiguratble PLL Paramater Register */
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
@ -214,7 +229,8 @@
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0) // parameter reset
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST) //parameter reset
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST) // parameter reset
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
@ -229,50 +245,86 @@
#define SAMPLE_ADC_SAMPLE_SEL_OFST (0)
#define SAMPLE_ADC_SAMPLE_SEL_MSK (0x00000007 << SAMPLE_ADC_SAMPLE_SEL_OFST)
#define SAMPLE_ADC_SAMPLE_0_VAL ((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_1_VAL ((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_2_VAL ((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_3_VAL ((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_4_VAL ((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_5_VAL ((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_6_VAL ((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_7_VAL ((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_0_VAL \
((0x0 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_1_VAL \
((0x1 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_2_VAL \
((0x2 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_3_VAL \
((0x3 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_4_VAL \
((0x4 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_5_VAL \
((0x5 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_6_VAL \
((0x6 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
#define SAMPLE_ADC_SAMPLE_7_VAL \
((0x7 << SAMPLE_ADC_SAMPLE_SEL_OFST) & SAMPLE_ADC_SAMPLE_SEL_MSK)
// Decimation = ADF + 1
#define SAMPLE_ADC_DECMT_FACTOR_OFST (4)
#define SAMPLE_ADC_DECMT_FACTOR_MSK (0x00000007 << SAMPLE_ADC_DECMT_FACTOR_OFST)
#define SAMPLE_ADC_DECMT_FACTOR_0_VAL ((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_1_VAL ((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_2_VAL ((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_3_VAL ((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_4_VAL ((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_5_VAL ((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_6_VAL ((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_7_VAL ((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_0_VAL \
((0x0 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_1_VAL \
((0x1 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_2_VAL \
((0x2 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_3_VAL \
((0x3 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_4_VAL \
((0x4 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_5_VAL \
((0x5 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_6_VAL \
((0x6 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_ADC_DECMT_FACTOR_7_VAL \
((0x7 << SAMPLE_ADC_DECMT_FACTOR_OFST) & SAMPLE_ADC_DECMT_FACTOR_MSK)
#define SAMPLE_DGTL_SAMPLE_SEL_OFST (8)
#define SAMPLE_DGTL_SAMPLE_SEL_MSK (0x0000000F << SAMPLE_DGTL_SAMPLE_SEL_OFST)
#define SAMPLE_DGTL_SAMPLE_0_VAL ((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_1_VAL ((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_2_VAL ((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_3_VAL ((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_4_VAL ((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_5_VAL ((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_6_VAL ((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_7_VAL ((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_8_VAL ((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_9_VAL ((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_10_VAL ((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_11_VAL ((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_12_VAL ((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_13_VAL ((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_14_VAL ((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_15_VAL ((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_0_VAL \
((0x0 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_1_VAL \
((0x1 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_2_VAL \
((0x2 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_3_VAL \
((0x3 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_4_VAL \
((0x4 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_5_VAL \
((0x5 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_6_VAL \
((0x6 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_7_VAL \
((0x7 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_8_VAL \
((0x8 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_9_VAL \
((0x9 << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_10_VAL \
((0xa << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_11_VAL \
((0xb << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_12_VAL \
((0xc << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_13_VAL \
((0xd << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_14_VAL \
((0xe << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_SAMPLE_15_VAL \
((0xf << SAMPLE_DGTL_SAMPLE_SEL_OFST) & SAMPLE_DGTL_SAMPLE_SEL_MSK)
#define SAMPLE_DGTL_DECMT_FACTOR_OFST (12)
#define SAMPLE_DGTL_DECMT_FACTOR_MSK (0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
#define SAMPLE_DECMT_FACTOR_FULL_VAL ((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_HALF_VAL ((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_QUARTER_VAL ((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DGTL_DECMT_FACTOR_MSK \
(0x00000003 << SAMPLE_DGTL_DECMT_FACTOR_OFST)
#define SAMPLE_DECMT_FACTOR_FULL_VAL \
((0x0 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_HALF_VAL \
((0x1 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
#define SAMPLE_DECMT_FACTOR_QUARTER_VAL \
((0x2 << SAMPLE_DGTL_DECMT_FACTOR_OFST) & SAMPLE_DGTL_DECMT_FACTOR_MSK)
/** Vref Comp Mod Register */
#define EXT_DAQ_CTRL_REG (0x5C << MEM_MAP_SHIFT)
@ -280,21 +332,25 @@
#define EXT_DAQ_CTRL_VREF_COMP_OFST (0)
#define EXT_DAQ_CTRL_VREF_COMP_MSK (0x00000FFF << EXT_DAQ_CTRL_VREF_COMP_OFST)
#define EXT_DAQ_CTRL_CMP_LGC_ENBL_OFST (15)
#define EXT_DAQ_CTRL_CMP_LGC_ENBL_MSK (0x00000001 << EXT_DAQ_CTRL_CMP_LGC_ENBL_OFST)
#define EXT_DAQ_CTRL_CMP_LGC_ENBL_MSK \
(0x00000001 << EXT_DAQ_CTRL_CMP_LGC_ENBL_OFST)
#define EXT_DAQ_CTRL_INPT_DETECT_OFST (16)
#define EXT_DAQ_CTRL_INPT_DETECT_MSK (0x00000007 << EXT_DAQ_CTRL_INPT_DETECT_OFST)
#define EXT_DAQ_CTRL_INPT_DETECT_MSK \
(0x00000007 << EXT_DAQ_CTRL_INPT_DETECT_OFST)
#define EXT_DAQ_CTRL_INPT_DETECT_ENBL_OFST (19)
#define EXT_DAQ_CTRL_INPT_DETECT_ENBL_MSK (0x00000001 << EXT_DAQ_CTRL_INPT_DETECT_ENBL_OFST)
#define EXT_DAQ_CTRL_INPT_DETECT_ENBL_MSK \
(0x00000001 << EXT_DAQ_CTRL_INPT_DETECT_ENBL_OFST)
/** DAQ Register */
#define DAQ_REG (0x5D << MEM_MAP_SHIFT)
#define DAQ_SETTINGS_MSK (DAQ_HIGH_GAIN_MSK | DAQ_FIX_GAIN_MSK | DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_SETTINGS_MSK \
(DAQ_HIGH_GAIN_MSK | DAQ_FIX_GAIN_MSK | DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_HIGH_GAIN_OFST (0)
#define DAQ_HIGH_GAIN_MSK (0x00000001 << DAQ_HIGH_GAIN_OFST)
#define DAQ_FIX_GAIN_DYNMC_VAL ((0x0 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
#define DAQ_FIX_GAIN_HIGHGAIN_VAL ((0x1 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
#define DAQ_FIX_GAIN_HIGHGAIN_VAL \
((0x1 << DAQ_HIGH_GAIN_OFST) & DAQ_HIGH_GAIN_MSK)
#define DAQ_FIX_GAIN_OFST (1)
#define DAQ_FIX_GAIN_MSK (0x00000003 << DAQ_FIX_GAIN_OFST)
#define DAQ_FIX_GAIN_STG_1_VAL ((0x1 << DAQ_FIX_GAIN_OFST) & DAQ_FIX_GAIN_MSK)
@ -305,8 +361,10 @@
#define DAQ_STRG_CELL_SLCT_MSK (0x0000000F << DAQ_STRG_CELL_SLCT_OFST)
#define DAQ_FRCE_SWTCH_GAIN_OFST (12)
#define DAQ_FRCE_SWTCH_GAIN_MSK (0x00000003 << DAQ_FRCE_SWTCH_GAIN_OFST)
#define DAQ_FRCE_GAIN_STG_1_VAL ((0x1 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_FRCE_GAIN_STG_2_VAL ((0x3 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_FRCE_GAIN_STG_1_VAL \
((0x1 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_FRCE_GAIN_STG_2_VAL \
((0x3 << DAQ_FRCE_SWTCH_GAIN_OFST) & DAQ_FRCE_SWTCH_GAIN_MSK)
#define DAQ_ELCTRN_CLLCTN_MDE_OFST (14)
#define DAQ_ELCTRN_CLLCTN_MDE_MSK (0x00000001 << DAQ_ELCTRN_CLLCTN_MDE_OFST)
#define DAQ_G2_CNNT_OFST (15)
@ -326,19 +384,18 @@
#define CHIP_POWER_STATUS_OFST (1)
#define CHIP_POWER_STATUS_MSK (0x00000001 << CHIP_POWER_STATUS_OFST)
/** Temperature Control Register */
#define TEMP_CTRL_REG (0x5F << MEM_MAP_SHIFT)
#define TEMP_CTRL_PROTCT_THRSHLD_OFST (0)
#define TEMP_CTRL_PROTCT_THRSHLD_MSK (0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
#define TEMP_CTRL_PROTCT_THRSHLD_MSK \
(0x000007FF << TEMP_CTRL_PROTCT_THRSHLD_OFST)
#define TEMP_CTRL_PROTCT_ENABLE_OFST (16)
#define TEMP_CTRL_PROTCT_ENABLE_MSK (0x00000001 << TEMP_CTRL_PROTCT_ENABLE_OFST)
// set when temp higher than over threshold, write 1 to clear it
#define TEMP_CTRL_OVR_TMP_EVNT_OFST (31)
#define TEMP_CTRL_OVR_TMP_EVNT_MSK (0x00000001 << TEMP_CTRL_OVR_TMP_EVNT_OFST)
/* Set Delay 64 bit register */
#define SET_DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT) // different kind of delay
#define SET_DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT) // different kind of delay
@ -383,7 +440,6 @@
#define COORD_COL_INNER_OFST (16)
#define COORD_COL_INNER_MSK (0x0000FFFF << COORD_COL_INNER_OFST)
/** Module column coordinates */
#define COORD_RESERVED_REG (0x7E << MEM_MAP_SHIFT)
@ -397,39 +453,42 @@
// tPC = (PCT + 1) * 25ns
#define ASIC_CTRL_PRCHRG_TMR_OFST (0)
#define ASIC_CTRL_PRCHRG_TMR_MSK (0x000000FF << ASIC_CTRL_PRCHRG_TMR_OFST)
#define ASIC_CTRL_PRCHRG_TMR_VAL ((0x1F << ASIC_CTRL_PRCHRG_TMR_OFST) & ASIC_CTRL_PRCHRG_TMR_MSK)
#define ASIC_CTRL_PRCHRG_TMR_VAL \
((0x1F << ASIC_CTRL_PRCHRG_TMR_OFST) & ASIC_CTRL_PRCHRG_TMR_MSK)
// tDS = (DST + 1) * 25ns
#define ASIC_CTRL_DS_TMR_OFST (8)
#define ASIC_CTRL_DS_TMR_MSK (0x000000FF << ASIC_CTRL_DS_TMR_OFST)
#define ASIC_CTRL_DS_TMR_VAL ((0x1F << ASIC_CTRL_DS_TMR_OFST) & ASIC_CTRL_DS_TMR_MSK)
// tET = (ET + 1) * 25ns (increase timeout range between 2 consecutive storage cells)
#define ASIC_CTRL_DS_TMR_VAL \
((0x1F << ASIC_CTRL_DS_TMR_OFST) & ASIC_CTRL_DS_TMR_MSK)
// tET = (ET + 1) * 25ns (increase timeout range between 2 consecutive storage
// cells)
#define ASIC_CTRL_EXPSRE_TMR_OFST (16)
#define ASIC_CTRL_EXPSRE_TMR_MSK (0x0000FFFF << ASIC_CTRL_EXPSRE_TMR_OFST)
#define ASIC_CTRL_EXPSRE_TMR_MAX_VAL (0x0000FFFF / (CLK_RUN * 1E-3))
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_0_REG (0xF0 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST (31) /* Refresh alignment */
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST)
#define ADC_DSRLZR_0_RFRSH_ALGNMNT_MSK \
(0x00000001 << ADC_DSRLZR_0_RFRSH_ALGNMNT_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_1_REG (0xF1 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST (31)
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST)
#define ADC_DSRLZR_1_RFRSH_ALGNMNT_MSK \
(0x00000001 << ADC_DSRLZR_1_RFRSH_ALGNMNT_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_2_REG (0xF2 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST (31)
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST)
#define ADC_DSRLZR_2_RFRSH_ALGNMNT_MSK \
(0x00000001 << ADC_DSRLZR_2_RFRSH_ALGNMNT_OFST)
/* ADC 0 Deserializer Control */
#define ADC_DSRLZR_3_REG (0xF3 << MEM_MAP_SHIFT)
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST (31)
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK (0x00000001 << ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST)
#define ADC_DSRLZR_3_RFRSH_ALGNMNT_MSK \
(0x00000001 << ADC_DSRLZR_3_RFRSH_ALGNMNT_OFST)
/* Round Robin */
#define RXR_ENDPOINTS_MAX (64)
@ -437,8 +496,3 @@
#define RXR_ENDPOINT_INNER_START_REG (0x2000 << MEM_MAP_SHIFT)
#define RXR_ENDPOINT_OFST (0x10 << MEM_MAP_SHIFT)

42
slsDetectorServers/jungfrauDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
View File

@ -1,7 +1,6 @@
#pragma once
#include "sls_detector_defs.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x171220
#define REQRD_FRMWRE_VRSN_BOARD2 0x190716 // old
@ -36,11 +35,21 @@ typedef struct udp_header_struct {
#define IP_HEADER_SIZE (20)
#define UDP_IP_HEADER_LENGTH_BYTES (28)
/* Enums */
enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
enum DACINDEX {J_VB_COMP, J_VDD_PROT, J_VIN_COM, J_VREF_PRECH, J_VB_PIXBUF, J_VB_DS, J_VREF_DS, J_VREF_COMP };
#define DEFAULT_DAC_VALS { 1220, /* J_VB_COMP */ \
enum DACINDEX {
J_VB_COMP,
J_VDD_PROT,
J_VIN_COM,
J_VREF_PRECH,
J_VB_PIXBUF,
J_VB_DS,
J_VREF_DS,
J_VREF_COMP
};
#define DEFAULT_DAC_VALS \
{ \
1220, /* J_VB_COMP */ \
3000, /* J_VDD_PROT */ \
1053, /* J_VIN_COM */ \
1450, /* J_VREF_PRECH */ \
@ -97,8 +106,6 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS};
#define MAX_PHASE_SHIFTS (160)
#define BIT16_MASK (0xFFFF)
#define ADC_OFST_FULL_SPEED_VAL (0xf)
#define ADC_OFST_HALF_SPEED_VAL (0xb)
#define ADC_OFST_QUARTER_SPEED_VAL (0x7)
@ -108,11 +115,21 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS};
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)
#define ADC_PORT_INVERT_BOARD2_VAL (0x453b2a9c)
#define SAMPLE_ADC_FULL_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_2_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x200
#define SAMPLE_ADC_HALF_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1310
#define SAMPLE_ADC_QUARTER_SPEED (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2630
#define SAMPLE_ADC_HALF_SPEED_BOARD2 (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1600
#define SAMPLE_ADC_QUARTER_SPEED_BOARD2 (SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + SAMPLE_DGTL_SAMPLE_11_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2b10
#define SAMPLE_ADC_FULL_SPEED \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
SAMPLE_DGTL_SAMPLE_2_VAL + SAMPLE_DECMT_FACTOR_FULL_VAL) // 0x200
#define SAMPLE_ADC_HALF_SPEED \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
SAMPLE_DGTL_SAMPLE_3_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1310
#define SAMPLE_ADC_QUARTER_SPEED \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_3_VAL + \
SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2630
#define SAMPLE_ADC_HALF_SPEED_BOARD2 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_0_VAL + \
SAMPLE_DGTL_SAMPLE_6_VAL + SAMPLE_DECMT_FACTOR_HALF_VAL) // 0x1600
#define SAMPLE_ADC_QUARTER_SPEED_BOARD2 \
(SAMPLE_ADC_SAMPLE_0_VAL + SAMPLE_ADC_DECMT_FACTOR_1_VAL + \
SAMPLE_DGTL_SAMPLE_11_VAL + SAMPLE_DECMT_FACTOR_QUARTER_VAL) // 0x2b10
#define ADC_PHASE_FULL_SPEED (28)
#define ADC_PHASE_HALF_SPEED (35)
@ -120,7 +137,6 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS};
#define ADC_PHASE_HALF_SPEED_BOARD2 (0x1E) // 30
#define ADC_PHASE_QUARTER_SPEED_BOARD2 (0x1E) // 30
#define DBIT_PHASE_FULL_SPEED (37)
#define DBIT_PHASE_HALF_SPEED (37)
#define DBIT_PHASE_QUARTER_SPEED (37)

130
slsDetectorServers/moenchDetectorServer/RegisterDefs.h Executable file → Normal file
View File

@ -3,7 +3,6 @@
/* Definitions for FPGA */
#define MEM_MAP_SHIFT 1
/* FPGA Version RO register */
#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
@ -11,7 +10,8 @@
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_MOENCH_VAL ((0x5 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
#define FPGA_VERSION_DTCTR_TYP_MOENCH_VAL \
((0x5 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
/* Fix pattern RO register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
@ -58,7 +58,8 @@
#define STATUS_PLL_PHS_DN_OFST (23)
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_MSK \
(0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x677FF)
/* Look at me RO register TODO */
@ -68,24 +69,30 @@
#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK (0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_DDR3_INT_DN_MSK \
(0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK (0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK \
(0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as PLL_PARAM_REG 0x50 */
/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as
* PLL_PARAM_REG 0x50 */
//#define PLL_PARAM_REG (0x05 << MEM_MAP_SHIFT)
/* FIFO Data RO register TODO */
#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
#define FIFO_DATA_HRDWR_SRL_NMBR_MSK \
(0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
//#define FIFO_DATA_WRD_OFST (16)
//#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
@ -115,7 +122,8 @@
#define API_VERSION_DTCTR_TYP_OFST (24)
#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using CONTROL_CRST. TODO */
/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
* CONTROL_CRST. TODO */
#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
@ -136,12 +144,14 @@
#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
/* Exposure Time Left 64 bit RO register */
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
//used in FW #define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT)
//// Not used in FW
/* Gates Left 64 bit RO register */
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not
//used in FW #define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT)
//// Not used in FW
/* Data In 64 bit RO register TODO */
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
@ -152,14 +162,16 @@
#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
/* Frames From Start 64 bit RO register TODO */
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT) // Not used in FW
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not
//used in FW #define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT)
//// Not used in FW
/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame start until reset) TODO */
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
* start until reset) TODO */
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
@ -178,9 +190,11 @@
/* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK \
(0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK \
(0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
/* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
@ -244,9 +258,11 @@
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK \
(0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK \
(0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
/* Receiver IP Address RW register */
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
@ -314,21 +330,22 @@
#define CONTROL_STP_ACQSTN_OFST (1)
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
//#define CONTROL_STRT_FF_TST_OFST (2)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
//#define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
//#define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_RDT_OFST (5)
//#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 <<
//CONTROL_STRT_FF_TST_OFST) #define CONTROL_STP_FF_TST_OFST (3)
//#define CONTROL_STP_FF_TST_MSK (0x00000001 <<
//CONTROL_STP_FF_TST_OFST) #define CONTROL_STRT_RDT_OFST (4)
//#define CONTROL_STRT_RDT_MSK (0x00000001 <<
//CONTROL_STRT_RDT_OFST) #define CONTROL_STP_RDT_OFST (5) #define
//CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
//#define CONTROL_STP_EXPSR_OFST (7)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STRT_TRN_OFST (8)
//#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_EXPSR_MSK (0x00000001 <<
//CONTROL_STP_RDT_OFST) #define CONTROL_STRT_TRN_OFST (8) #define
//CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
//#define CONTROL_STP_TRN_OFST (9)
//#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
//#define CONTROL_STP_TRN_MSK (0x00000001 <<
//CONTROL_STP_RDT_OFST)
#define CONTROL_CRE_RST_OFST (10)
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
@ -336,7 +353,8 @@
#define CONTROL_MMRY_RST_OFST (12)
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
//#define CONTROL_PLL_RCNFG_WR_OFST (13)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 << CONTROL_PLL_RCNFG_WR_OFST)
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 <<
//CONTROL_PLL_RCNFG_WR_OFST)
#define CONTROL_SND_10GB_PCKT_OFST (14)
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
@ -349,7 +367,8 @@
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
#define PLL_CNTRL_WR_PRMTR_OFST (2)
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
#define PLL_CNTRL_PLL_RST_OFST (3)
@ -379,7 +398,8 @@
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
@ -390,7 +410,8 @@
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
@ -401,7 +422,8 @@
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
@ -446,7 +468,6 @@
/* Number of Words RW register TODO */
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
/* Delay 64 bit RW register. t = DLY x 50 ns. */
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
@ -464,12 +485,14 @@
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
/* Period 64 bit RW register */
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT) // Not used in FW
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
//Not used in FW #define EXPTIME_MSB_REG (0x69 <<
//MEM_MAP_SHIFT) // Not used in FW
/* Gates 64 bit RW register */
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) // Not used in FW
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used
//in FW #define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) //
//Not used in FW
/* Pattern IO Control 64 bit RW regiser
* Each bit configured as output(1)/ input(0) */
@ -507,7 +530,8 @@
#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
/* Digital Bit External Trigger RW register */
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT) // Not used in firmware or software
#define DBIT_EXT_TRG_REG \
(0x7B << MEM_MAP_SHIFT) // Not used in firmware or software
#define DBIT_EXT_TRG_SRC_OFST (0)
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
@ -515,20 +539,26 @@
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
/* Pin Delay 0 RW register */
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT) // Not used in firmware or software
#define OUTPUT_DELAY_0_REG \
(0x7C << MEM_MAP_SHIFT) // Not used in firmware or software
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST (0) //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST \
(0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK \
(0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
// 1: load dynamic output settings, 0: trigger start of dynamic output delay
// configuration pn falling edge of ODT (output delay trigger) bit
#define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK (0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK \
(0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
#define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL (1)
#define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
/* Pin Delay 1 RW register
* Each bit configured as enable for dynamic output delay configuration */
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT) // Not used in firmware or software
#define PIN_DELAY_1_REG \
(0x7D << MEM_MAP_SHIFT) // Not used in firmware or software
/** Pattern Mask 64 bit RW regiser */
#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
@ -540,5 +570,3 @@
/* Round Robin */
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)

31
slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h Executable file → Normal file
View File

@ -1,7 +1,6 @@
#pragma once
#include "sls_detector_defs.h"
#include "RegisterDefs.h"
#include "sls_detector_defs.h"
#define MIN_REQRD_VRSN_T_RD_API 0x180314
#define REQRD_FRMWR_VRSN 0x200302
@ -36,9 +35,22 @@ typedef struct udp_header_struct {
#define UDP_IP_HEADER_LENGTH_BYTES (28)
/* Enums */
enum DACINDEX {MO_VBP_COLBUF, MO_VIPRE, MO_VIN_CM, MO_VB_SDA, MO_VCASC_SFP, MO_VOUT_CM, MO_VIPRE_CDS, MO_IBIAS_SFP};
#define DAC_NAMES "vbp_colbuf", "vipre", "vin_cm", "vb_sda", "vcasc_sfp", "vout_cm", "vipre_cds", "ibias_sfp"
#define DEFAULT_DAC_VALS { 1300, /* MO_VBP_COLBUF */ \
enum DACINDEX {
MO_VBP_COLBUF,
MO_VIPRE,
MO_VIN_CM,
MO_VB_SDA,
MO_VCASC_SFP,
MO_VOUT_CM,
MO_VIPRE_CDS,
MO_IBIAS_SFP
};
#define DAC_NAMES \
"vbp_colbuf", "vipre", "vin_cm", "vb_sda", "vcasc_sfp", "vout_cm", \
"vipre_cds", "ibias_sfp"
#define DEFAULT_DAC_VALS \
{ \
1300, /* MO_VBP_COLBUF */ \
1000, /* MO_VIPRE */ \
1400, /* MO_VIN_CM */ \
680, /* MO_VB_SDA */ \
@ -106,10 +118,14 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
/* Defines in the Firmware */
#define MAX_PATTERN_LENGTH (0x2000)
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define DIGITAL_IO_DELAY_MAXIMUM_PS \
((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define MAX_PHASE_SHIFTS_STEPS (8)
#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TME_US_FR_ACQDONE_REG \
(100) // wait time in us after acquisition done to ensure there is no data
// in fifo
#define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
@ -125,4 +141,3 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
#define ADC_PORT_INVERT_VAL (0x4a342593)
#define MAXIMUM_ADC_CLK (20)
#define PLL_VCO_FREQ_MHZ (800)

75
slsDetectorServers/mythen3DetectorServer/RegisterDefs.h
View File

@ -1,6 +1,5 @@
#pragma once
#define REG_OFFSET (4)
/* Base addresses 0x1804 0000 ---------------------------------------------*/
@ -43,9 +42,8 @@
/* Pattern RAM. Pattern table */
#define BASE_PATTERN_RAM (0x10000) // 0x1807_0000 - 0x1807_FFFF
/* Clock Generation registers ------------------------------------------------------*/
/* Clock Generation registers
* ------------------------------------------------------*/
#define PLL_RESET_REG (0x00 * REG_OFFSET + BASE_CLK_GENERATION)
#define PLL_RESET_READOUT_OFST (0)
@ -53,8 +51,6 @@
#define PLL_RESET_SYSTEM_OFST (1)
#define PLL_RESET_SYSTEM_MSK (0x00000001 << PLL_RESET_SYSTEM_OFST)
/* Control registers --------------------------------------------------*/
/* Module Control Board Serial Number Register */
@ -71,14 +67,14 @@
#define DETECTOR_TYPE_OFST (24)
#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
/* API Version Register */
#define API_VERSION_REG (0x02 * REG_OFFSET + BASE_CONTROL)
#define API_VERSION_OFST (0)
#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
#define API_VERSION_DETECTOR_TYPE_OFST (24) // Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
#define API_VERSION_DETECTOR_TYPE_MSK \
(0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) // Not used in software
/* Fix pattern register */
#define FIX_PATT_REG (0x03 * REG_OFFSET + BASE_CONTROL)
@ -88,25 +84,35 @@
#define STATUS_REG (0x04 * REG_OFFSET + BASE_CONTROL)
/* Look at me register, read only */
#define LOOK_AT_ME_REG (0x05 * REG_OFFSET + BASE_CONTROL) //Not used in firmware or software, good to play with
#define SYSTEM_STATUS_REG (0x06 * REG_OFFSET + BASE_CONTROL) //Not used in software
#define LOOK_AT_ME_REG \
(0x05 * REG_OFFSET + \
BASE_CONTROL) // Not used in firmware or software, good to play with
#define SYSTEM_STATUS_REG \
(0x06 * REG_OFFSET + BASE_CONTROL) // Not used in software
/* Config RW regiseter */
#define CONFIG_REG (0x20 * REG_OFFSET + BASE_CONTROL)
#define CONFIG_COUNTER_ENA_OFST (0)
#define CONFIG_COUNTER_ENA_MSK (0x00000003 << CONFIG_COUNTER_ENA_OFST)
#define CONFIG_COUNTER_ENA_DEFAULT_VAL ((0x0 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_1_VAL ((0x1 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_2_VAL ((0x2 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_ALL_VAL ((0x3 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_DEFAULT_VAL \
((0x0 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_1_VAL \
((0x1 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_2_VAL \
((0x2 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_COUNTER_ENA_ALL_VAL \
((0x3 << CONFIG_COUNTER_ENA_OFST) & CONFIG_COUNTER_ENA_MSK)
#define CONFIG_DYNAMIC_RANGE_OFST (4)
#define CONFIG_DYNAMIC_RANGE_MSK (0x00000003 << CONFIG_DYNAMIC_RANGE_OFST)
#define CONFIG_DYNAMIC_RANGE_1_VAL ((0x0 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_4_VAL ((0x1 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_16_VAL ((0x2 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_24_VAL ((0x3 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_1_VAL \
((0x0 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_4_VAL \
((0x1 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_16_VAL \
((0x2 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
#define CONFIG_DYNAMIC_RANGE_24_VAL \
((0x3 << CONFIG_DYNAMIC_RANGE_OFST) & CONFIG_DYNAMIC_RANGE_MSK)
/* Control RW register */
#define CONTROL_REG (0x21 * REG_OFFSET + BASE_CONTROL)
@ -130,8 +136,6 @@
#define DTA_OFFSET_REG (0x24 * REG_OFFSET + BASE_CONTROL)
/* Packetizer -------------------------------------------------------------*/
/* Packetizer Config Register */
@ -154,23 +158,27 @@
#define COORD_RESERVED_OFST (0)
#define COORD_RESERVED_MSK (0x0000FFFF << COORD_RESERVED_OFST)
#define COORD_ID_OFST (16) // Not connected in firmware TODO
#define COORD_ID_MSK (0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
#define COORD_ID_MSK \
(0x0000FFFF << COORD_ID_OFST) // Not connected in firmware TODO
/* Pattern Control registers --------------------------------------------------*/
/* Pattern Control registers
* --------------------------------------------------*/
/* Pattern status Register*/
#define PAT_STATUS_REG (0x00 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PAT_STATUS_RUN_BUSY_OFST (0)
#define PAT_STATUS_RUN_BUSY_MSK (0x00000001 << PAT_STATUS_RUN_BUSY_OFST)
#define PAT_STATUS_WAIT_FOR_TRGGR_OFST (3)
#define PAT_STATUS_WAIT_FOR_TRGGR_MSK (0x00000001 << PAT_STATUS_WAIT_FOR_TRGGR_OFST)
#define PAT_STATUS_WAIT_FOR_TRGGR_MSK \
(0x00000001 << PAT_STATUS_WAIT_FOR_TRGGR_OFST)
#define PAT_STATUS_DLY_BFRE_TRGGR_OFST (4)
#define PAT_STATUS_DLY_BFRE_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_BFRE_TRGGR_OFST)
#define PAT_STATUS_DLY_BFRE_TRGGR_MSK \
(0x00000001 << PAT_STATUS_DLY_BFRE_TRGGR_OFST)
#define PAT_STATUS_FIFO_FULL_OFST (5)
#define PAT_STATUS_FIFO_FULL_MSK (0x00000001 << PAT_STATUS_FIFO_FULL_OFST)
#define PAT_STATUS_DLY_AFTR_TRGGR_OFST (15)
#define PAT_STATUS_DLY_AFTR_TRGGR_MSK (0x00000001 << PAT_STATUS_DLY_AFTR_TRGGR_OFST)
#define PAT_STATUS_DLY_AFTR_TRGGR_MSK \
(0x00000001 << PAT_STATUS_DLY_AFTR_TRGGR_OFST)
#define PAT_STATUS_CSM_BUSY_OFST (17)
#define PAT_STATUS_CSM_BUSY_MSK (0x00000001 << PAT_STATUS_CSM_BUSY_OFST)
@ -194,7 +202,8 @@
#define TIME_FROM_START_LSB_REG (0x0A * REG_OFFSET + BASE_PATTERN_CONTROL)
#define TIME_FROM_START_MSB_REG (0x0B * REG_OFFSET + BASE_PATTERN_CONTROL)
/* Get Frames from Start 64 bit register (frames from last reset using CONTROL_CRST) */
/* Get Frames from Start 64 bit register (frames from last reset using
* CONTROL_CRST) */
#define FRAMES_FROM_START_LSB_REG (0x0C * REG_OFFSET + BASE_PATTERN_CONTROL)
#define FRAMES_FROM_START_MSB_REG (0x0D * REG_OFFSET + BASE_PATTERN_CONTROL)
@ -261,7 +270,8 @@
#define PATTERN_LOOP_0_ADDR_REG (0x64 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
@ -282,7 +292,8 @@
#define PATTERN_LOOP_1_ADDR_REG (0x69 * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
@ -303,11 +314,11 @@
#define PATTERN_LOOP_2_ADDR_REG (0x6E * REG_OFFSET + BASE_PATTERN_CONTROL)
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
(0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
/* Pattern RAM registers --------------------------------------------------*/
/* Register of first word */

42
slsDetectorServers/mythen3DetectorServer/slsDetectorServer_defs.h
View File

@ -22,7 +22,6 @@
#define TYPE_TOLERANCE (10)
#define TYPE_NO_MODULE_STARTING_VAL (800)
/** Default Parameters */
#define DEFAULT_DYNAMIC_RANGE (24)
#define DEFAULT_NUM_FRAMES (1)
@ -38,7 +37,6 @@
#define DEFAULT_SYSTEM_C1 (10) //(125000000) // chip_clk, 125 MHz
#define DEFAULT_SYSTEM_C2 (10) //(125000000) // sync_clk, 125 MHz
/* Firmware Definitions */
#define IP_HEADER_SIZE (20)
#define FIXED_PLL_FREQUENCY (020000000) // 20MHz
@ -50,9 +48,31 @@
#define BIT16_MASK (0xFFFF)
/* Enums */
enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3, M_VTH1, M_VICIN, M_CAS, M_VRF, M_VPL, M_VIPRE, M_VIINSH, M_VPH, M_VTRIM, M_VDCSH};
#define DAC_NAMES "vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1", "vicin", "vcas", "vpreamp", "vpl", "vipre", "viinsh", "vph", "vtrim", "vdcsh"
#define DEFAULT_DAC_VALS {1200, /* casSh */ \
enum DACINDEX {
M_CASSH,
M_VTH2,
M_VRFSH,
M_VRFSHNPOL,
M_VIPRE_OUT,
M_VTH3,
M_VTH1,
M_VICIN,
M_CAS,
M_VRF,
M_VPL,
M_VIPRE,
M_VIINSH,
M_VPH,
M_VTRIM,
M_VDCSH
};
#define DAC_NAMES \
"vcassh", "vth2", "vshaper", "vshaperneg", "vipre_out", "vth3", "vth1", \
"vicin", "vcas", "vpreamp", "vpl", "vipre", "viinsh", "vph", "vtrim", \
"vdcsh"
#define DEFAULT_DAC_VALS \
{ \
1200, /* casSh */ \
2800, /* Vth2 */ \
1280, /* VrfSh */ \
2800, /* VrfShNpol */ \
@ -69,8 +89,16 @@ enum DACINDEX {M_CASSH, M_VTH2, M_VRFSH, M_VRFSHNPOL, M_VIPRE_OUT, M_VTH3
2800, /* vTrim */ \
800 /* VdcSh */ \
};
enum CLKINDEX {READOUT_C0, READOUT_C1, SYSTEM_C0, SYSTEM_C1, SYSTEM_C2, NUM_CLOCKS};
#define CLK_NAMES "READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
enum CLKINDEX {
READOUT_C0,
READOUT_C1,
SYSTEM_C0,
SYSTEM_C1,
SYSTEM_C2,
NUM_CLOCKS
};
#define CLK_NAMES \
"READOUT_C0", "READOUT_C1", "SYSTEM_C0", "SYSTEM_C1", "SYSTEM_C2"
enum PLLINDEX { READOUT_PLL, SYSTEM_PLL };
/* Struct Definitions */

3
slsDetectorServers/slsDetectorServer/include/AD7689.h Executable file → Normal file
View File

@ -11,7 +11,8 @@
* @param dmsk digital output mask
* @param dofst digital output offset
*/
void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst);
void AD7689_SetDefines(uint32_t reg, uint32_t roreg, uint32_t cmsk,
uint32_t clkmsk, uint32_t dmsk, int dofst);
/**
* Disable SPI

3
slsDetectorServers/slsDetectorServer/include/AD9252.h Executable file → Normal file
View File

@ -10,7 +10,8 @@
* @param dmsk digital output mask
* @param dofst digital output offset
*/
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst);
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst);
/**
* Disable SPI

6
slsDetectorServers/slsDetectorServer/include/AD9257.h Executable file → Normal file
View File

@ -10,7 +10,8 @@
* @param dmsk digital output mask
* @param dofst digital output offset
*/
void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst);
void AD9257_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst);
/**
* Disable SPI
@ -24,7 +25,8 @@ int AD9257_GetVrefVoltage(int mV);
/**
* Set vref voltage
* @param val voltage to be set (0 for 1.0V, 1 for 1.14V, 2 for 1.33V, 3 for 1.6V, 4 for 2.0V
* @param val voltage to be set (0 for 1.0V, 1 for 1.14V, 2 for 1.33V, 3
* for 1.6V, 4 for 2.0V
* @returns ok or fail
*/
int AD9257_SetVrefVoltage(int val, int mV);

15
slsDetectorServers/slsDetectorServer/include/ALTERA_PLL.h Executable file → Normal file
View File

@ -15,7 +15,9 @@
* @param wd2msk write parameter mask for pll for dbit clock (Jungfrau only)
* @param clk2Index clkIndex of second pll (Jungfrau only)
*/
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst, uint32_t wd2msk, int clk2Index);
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst, uint32_t wd2msk, int clk2Index);
#else
/**
* Set Defines
@ -27,7 +29,9 @@ void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32
* @param amsk address mask
* @param aofst address offset
*/
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk, uint32_t wpmsk, uint32_t prmsk, uint32_t amsk, int aofst);
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst);
#endif
/**
@ -44,9 +48,11 @@ void ALTERA_PLL_ResetPLLAndReconfiguration ();
* Set PLL Reconfig register
* @param reg register
* @param val value
* @param useDefaultWRMask only jungfrau for dbit clk (clkindex1, use second WR mask)
* @param useDefaultWRMask only jungfrau for dbit clk (clkindex1, use second WR
* mask)
*/
void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val, int useSecondWRMask);
void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
int useSecondWRMask);
/**
* Write Phase Shift
@ -68,4 +74,3 @@ void ALTERA_PLL_SetModePolling();
* @param frequency set
*/
int ALTERA_PLL_SetOuputFrequency(int clkIndex, int pllVCOFreqMhz, int value);

9
slsDetectorServers/slsDetectorServer/include/ALTERA_PLL_CYCLONE10.h Executable file → Normal file
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@ -14,7 +14,10 @@
* @param vcofreq0 vco frequency of pll 0
* @param vcofreq1 vco frequency of pll 1
*/
void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0, uint32_t baseaddr1, uint32_t resetreg0, uint32_t resetreg1, uint32_t resetmsk0, uint32_t resetmsk1, int vcofreq0, int vcofreq1);
void ALTERA_PLL_C10_SetDefines(int regofst, uint32_t baseaddr0,
uint32_t baseaddr1, uint32_t resetreg0,
uint32_t resetreg1, uint32_t resetmsk0,
uint32_t resetmsk1, int vcofreq0, int vcofreq1);
/**
* Get Max Clock Divider
@ -53,7 +56,8 @@ void ALTERA_PLL_C10_ResetPLL (int pllIndex);
* @param phase phase shift
* @param pos 1 if up down direction of shift is positive, else 0
*/
void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos);
void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase,
int pos);
/**
* Calculate and write output frequency
@ -62,4 +66,3 @@ void ALTERA_PLL_C10_SetPhaseShift(int pllIndex, int clkIndex, int phase, int pos
* @param value clock divider to set to
*/
void ALTERA_PLL_C10_SetOuputClockDivider(int pllIndex, int clkIndex, int value);

0
slsDetectorServers/slsDetectorServer/include/ASIC_Driver.h Executable file → Normal file
View File

3
slsDetectorServers/slsDetectorServer/include/DAC6571.h Executable file → Normal file
View File

@ -15,6 +15,3 @@ void DAC6571_SetDefines(int hardMaxV, char* driverfname);
* @return OK or FAIL
*/
int DAC6571_Set(int val);

8
slsDetectorServers/slsDetectorServer/include/I2C.h Executable file → Normal file
View File

@ -15,9 +15,9 @@
* @param sdreg sda hold register (defined in RegisterDefs.h)
* @param treg transfer command fifo register (defined in RegisterDefs.h)
*/
void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg,
uint32_t rreg, uint32_t rlvlreg,
uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg);
void I2C_ConfigureI2CCore(uint32_t creg, uint32_t sreg, uint32_t rreg,
uint32_t rlvlreg, uint32_t slreg, uint32_t shreg,
uint32_t sdreg, uint32_t treg);
/**
* Read register
@ -34,5 +34,3 @@ uint32_t I2C_Read(uint32_t devId, uint32_t addr);
* @param data data to be written (16 bit)
*/
void I2C_Write(uint32_t devId, uint32_t addr, uint16_t data);

7
slsDetectorServers/slsDetectorServer/include/INA226.h Executable file → Normal file
View File

@ -4,7 +4,8 @@
/**
* Configure the I2C core and Enable core
* @param rOhm shunt resister value in Ohms (defined in slsDetectorServer_defs.h)
* @param rOhm shunt resister value in Ohms (defined in
* slsDetectorServer_defs.h)
* @param creg control register (defined in RegisterDefs.h)
* @param sreg status register (defined in RegisterDefs.h)
* @param rreg rx data fifo register (defined in RegisterDefs.h)
@ -15,8 +16,8 @@
* @param treg transfer command fifo register (defined in RegisterDefs.h)
*/
void INA226_ConfigureI2CCore(double rOhm, uint32_t creg, uint32_t sreg,
uint32_t rreg, uint32_t rlvlreg,
uint32_t slreg, uint32_t shreg, uint32_t sdreg, uint32_t treg);
uint32_t rreg, uint32_t rlvlreg, uint32_t slreg,
uint32_t shreg, uint32_t sdreg, uint32_t treg);
/**
* Calibrate resolution of current register

9
slsDetectorServers/slsDetectorServer/include/LTC2620.h Executable file → Normal file
View File

@ -9,11 +9,13 @@
* @param clkmsk clock output mask
* @param dmsk digital output mask
* @param dofst digital output offset
* @param nd total number of dacs for this board (for dac channel and daisy chain chip id)
* @param nd total number of dacs for this board (for dac channel and daisy
* chain chip id)
* @param minMV minimum voltage determined by hardware
* @param maxMV maximum voltage determined by hardware
*/
void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst, int nd, int minMV, int maxMV);
void LTC2620_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst, int nd, int minMV, int maxMV);
/**
* Disable SPI
@ -84,7 +86,8 @@ void LTC2620_SetDaisy(int cmd, int data, int dacaddr, int chipIndex);
/**
* Sets a single chip (LTC2620_SetSingle) or multiple chip (LTC2620_SetDaisy)
* multiple chip is only for ctb where the multiple chips are connected in daisy fashion
* multiple chip is only for ctb where the multiple chips are connected in daisy
* fashion
* @param cmd command to send
* @param data dac value to be set
* @param dacaddr dac channel number for the chip

4
slsDetectorServers/slsDetectorServer/include/LTC2620_Driver.h Executable file → Normal file
View File

@ -10,7 +10,6 @@
*/
void LTC2620_D_SetDefines(int hardMaxV, char *driverfname, int numdacs);
/**
* Get max number of steps
*/
@ -41,4 +40,5 @@ int LTC2620_D_DacToVoltage(int dacval, int* voltage);
* @param dacval pointer to dac value
* @return OK or FAIL
*/
int LTC2620_D_SetDACValue(int dacnum, int val, int mV, char* dacname, int *dacval);
int LTC2620_D_SetDACValue(int dacnum, int val, int mV, char *dacname,
int *dacval);

7
slsDetectorServers/slsDetectorServer/include/MAX1932.h Executable file → Normal file
View File

@ -12,8 +12,8 @@
* @param minMV minimum voltage determined by hardware
* @param maxMV maximum voltage determined by hardware
*/
void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk, uint32_t dmsk, int dofst,
int minMV, int maxMV);
void MAX1932_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst, int minMV, int maxMV);
/**
* Disable SPI
@ -26,6 +26,3 @@ void MAX1932_Disable();
* @return OK or FAIL
*/
int MAX1932_Set(int *val);

0
slsDetectorServers/slsDetectorServer/include/UDPPacketHeaderGenerator.h Executable file → Normal file
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2
slsDetectorServers/slsDetectorServer/include/blackfin.h Executable file → Normal file
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@ -1,7 +1,7 @@
#pragma once
#include <sys/types.h>
#include <inttypes.h>
#include <sys/types.h>
/** I2C defines */
#define I2C_CLOCK_MHZ (131.25)

82
slsDetectorServers/slsDetectorServer/include/clogger.h Executable file → Normal file
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@ -2,10 +2,9 @@
#include "ansi.h"
#include <stdlib.h>
#include <stdio.h>
#include <stdarg.h>
#include <stdio.h>
#include <stdlib.h>
#ifdef FIFODEBUG
#define FILELOG_MAX_LEVEL logDEBUG5
@ -22,30 +21,69 @@
#endif
enum TLogLevel {
logERROR, logWARNING, logINFOBLUE, logINFOGREEN, logINFORED, logINFO,
logDEBUG, logDEBUG1, logDEBUG2, logDEBUG3, logDEBUG4, logDEBUG5
logERROR,
logWARNING,
logINFOBLUE,
logINFOGREEN,
logINFORED,
logINFO,
logDEBUG,
logDEBUG1,
logDEBUG2,
logDEBUG3,
logDEBUG4,
logDEBUG5
};
#define ERROR_MSG_LENGTH 1000
#define LOG(lvl, fmt, ...) \
if (lvl > FILELOG_MAX_LEVEL); \
else {char* temp = FILELOG_BuildLog fmt; FILELOG_PrintLog(lvl, temp);free(temp);}
if (lvl > FILELOG_MAX_LEVEL) \
; \
else { \
char *temp = FILELOG_BuildLog fmt; \
FILELOG_PrintLog(lvl, temp); \
free(temp); \
}
static inline void FILELOG_PrintLog(enum TLogLevel level, char *m) {
switch (level) {
case logERROR: cprintf(RED BOLD, "ERROR: %s", m); break;
case logWARNING: cprintf(YELLOW BOLD, "WARNING: %s", m); break;
case logINFOBLUE: cprintf(BLUE, "INFO: %s", m); break;
case logINFOGREEN: cprintf(GREEN, "INFO: %s", m); break;
case logINFORED: cprintf(RED, "INFO: %s", m); break;
case logINFO: cprintf(RESET, "INFO: %s", m); break;
case logDEBUG: cprintf(MAGENTA, "DEBUG: %s", m); break;
case logDEBUG1: cprintf(MAGENTA, "DEBUG1: %s", m); break;
case logDEBUG2: cprintf(MAGENTA, "DEBUG2: %s", m); break;
case logDEBUG3: cprintf(MAGENTA, "DEBUG3: %s", m); break;
case logDEBUG4: cprintf(MAGENTA, "DEBUG4: %s", m); break;
case logDEBUG5: cprintf(MAGENTA, "DEBUG5: %s", m); break;
case logERROR:
cprintf(RED BOLD, "ERROR: %s", m);
break;
case logWARNING:
cprintf(YELLOW BOLD, "WARNING: %s", m);
break;
case logINFOBLUE:
cprintf(BLUE, "INFO: %s", m);
break;
case logINFOGREEN:
cprintf(GREEN, "INFO: %s", m);
break;
case logINFORED:
cprintf(RED, "INFO: %s", m);
break;
case logINFO:
cprintf(RESET, "INFO: %s", m);
break;
case logDEBUG:
cprintf(MAGENTA, "DEBUG: %s", m);
break;
case logDEBUG1:
cprintf(MAGENTA, "DEBUG1: %s", m);
break;
case logDEBUG2:
cprintf(MAGENTA, "DEBUG2: %s", m);
break;
case logDEBUG3:
cprintf(MAGENTA, "DEBUG3: %s", m);
break;
case logDEBUG4:
cprintf(MAGENTA, "DEBUG4: %s", m);
break;
case logDEBUG5:
cprintf(MAGENTA, "DEBUG5: %s", m);
break;
}
fflush(stdout);
}
@ -58,11 +96,9 @@ static inline char* FILELOG_BuildLog(const char* fmt, ...) {
int ret = vsnprintf(p, ERROR_MSG_LENGTH, fmt, ap);
va_end(ap);
if (ret < 0 || ret >= ERROR_MSG_LENGTH) {
FILELOG_PrintLog(logERROR, ("Could not print the "
FILELOG_PrintLog(logERROR,
("Could not print the "
"complete error message in the next print.\n"));
}
return p;
};

7
slsDetectorServers/slsDetectorServer/include/common.h Executable file → Normal file
View File

@ -1,7 +1,8 @@
#pragma once
/**
* Convert a value from a range to a different range (eg voltage to dac or vice versa)
* Convert a value from a range to a different range (eg voltage to dac or vice
* versa)
* @param inputMin input minimum
* @param inputMax input maximum
* @param outputMin output minimum
@ -10,5 +11,5 @@
* @param outputValue pointer to output value
* @returns FAIL if input value is out of bounds, else OK
*/
int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin, int outputMax,
int inputValue, int* outputValue);
int ConvertToDifferentRange(int inputMin, int inputMax, int outputMin,
int outputMax, int inputValue, int *outputValue);

21
slsDetectorServers/slsDetectorServer/include/commonServerFunctions.h Executable file → Normal file
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@ -2,14 +2,23 @@
#include <inttypes.h>
void SPIChipSelect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask, int convBit);
void SPIChipSelect(uint32_t *valw, uint32_t addr, uint32_t csmask,
uint32_t clkmask, uint32_t digoutmask, int convBit);
void SPIChipDeselect (uint32_t* valw, uint32_t addr, uint32_t csmask, uint32_t clkmask, uint32_t digoutmask, int convBit);
void SPIChipDeselect(uint32_t *valw, uint32_t addr, uint32_t csmask,
uint32_t clkmask, uint32_t digoutmask, int convBit);
void sendDataToSPI (uint32_t* valw, uint32_t addr, uint32_t val, int numbitstosend, uint32_t clkmask, uint32_t digoutmask, int digofset);
void sendDataToSPI(uint32_t *valw, uint32_t addr, uint32_t val,
int numbitstosend, uint32_t clkmask, uint32_t digoutmask,
int digofset);
uint32_t receiveDataFromSPI (uint32_t* valw, uint32_t addr, int numbitstoreceive, uint32_t clkmask, uint32_t readaddr) ;
uint32_t receiveDataFromSPI(uint32_t *valw, uint32_t addr, int numbitstoreceive,
uint32_t clkmask, uint32_t readaddr);
void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask, int numbitstosend, uint32_t clkmask, uint32_t digoutmask, int digofset, int convBit);
void serializeToSPI(uint32_t addr, uint32_t val, uint32_t csmask,
int numbitstosend, uint32_t clkmask, uint32_t digoutmask,
int digofset, int convBit);
uint32_t serializeFromSPI(uint32_t addr, uint32_t csmask, int numbitstoreceive, uint32_t clkmask, uint32_t digoutmask, uint32_t readaddr, int convBit);
uint32_t serializeFromSPI(uint32_t addr, uint32_t csmask, int numbitstoreceive,
uint32_t clkmask, uint32_t digoutmask,
uint32_t readaddr, int convBit);

16
slsDetectorServers/slsDetectorServer/include/communication_funcs.h Executable file → Normal file
View File

@ -1,15 +1,9 @@
#ifndef COMMUNICATION_FUNCS_H
#define COMMUNICATION_FUNCS_H
#include "sls_detector_defs.h"
typedef enum{
INT16,
INT32,
INT64,
OTHER
}intType;
typedef enum { INT16, INT32, INT64, OTHER } intType;
// communciate with stop server
#ifdef VIRTUAL
@ -39,7 +33,6 @@ int receiveModule(int file_des, sls_detector_module* myMod);
*/
void Server_LockedError();
/**
* Server verifies if it is unlocked,
* sets and prints appropriate message if it is locked and different clients
@ -47,11 +40,12 @@ void Server_LockedError();
*/
int Server_VerifyLock();
/**
* Server sends result to client (also set ret to force_update if different clients)
* Server sends result to client (also set ret to force_update if different
* clients)
* @param fileDes file descriptor for the socket
* @param itype 32 or 64 or others to determine to swap data from big endian to little endian
* @param itype 32 or 64 or others to determine to swap data from big endian to
* little endian
* @param retval pointer to result
* @param retvalSize size of result
* @returns result of operation

3
slsDetectorServers/slsDetectorServer/include/communication_funcs_UDP.h Executable file → Normal file
View File

@ -11,7 +11,8 @@ int getUdPSocketDescriptor(int index);
* @param ip udp destination ip
* @param port udp destination port
*/
int setUDPDestinationDetails(int index, const char* ip, unsigned short int port);
int setUDPDestinationDetails(int index, const char *ip,
unsigned short int port);
/**
* Create udp socket

6
slsDetectorServers/slsDetectorServer/include/communication_virtual.h Executable file → Normal file
View File

@ -8,7 +8,9 @@ void ComVirtual_setStatus(int value);
int ComVirtual_getStatus();
void ComVirtual_setStop(int value);
int ComVirtual_getStop();
int ComVirtual_writeToFile(int value, const char* fname, const char* serverName);
int ComVirtual_readFromFile(int* value, const char* fname, const char* serverName);
int ComVirtual_writeToFile(int value, const char *fname,
const char *serverName);
int ComVirtual_readFromFile(int *value, const char *fname,
const char *serverName);
#endif

2
slsDetectorServers/slsDetectorServer/include/nios.h Executable file → Normal file
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@ -1,7 +1,7 @@
#pragma once
#include <sys/types.h>
#include <inttypes.h>
#include <sys/types.h>
/**
* Write into a 32 bit register for cspbase 1

2
slsDetectorServers/slsDetectorServer/include/programFpgaBlackfin.h Executable file → Normal file
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@ -1,7 +1,7 @@
#pragma once
#include <stdio.h>
#include <stdint.h>
#include <stdio.h>
/**
* Define GPIO pins if not defined

5
slsDetectorServers/slsDetectorServer/include/programFpgaNios.h Executable file → Normal file
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@ -1,14 +1,15 @@
#pragma once
#include <stdio.h>
#include <stdint.h>
#include <stdio.h>
#define NIOS_MAX_APP_IMAGE_SIZE (0x00580000)
/** Notify microcontroller of successful server start up */
void NotifyServerStartSuccess();
/** create notification file to notify watchdog of critical tasks (to not shutdown) */
/** create notification file to notify watchdog of critical tasks (to not
* shutdown) */
void CreateNotificationForCriticalTasks();
/** write 1 to notification file to postpone shut down process if requested*/

8
slsDetectorServers/slsDetectorServer/include/readDefaultPattern.h Executable file → Normal file
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@ -1,7 +1,7 @@
#pragma once
#include <sys/types.h>
#include <inttypes.h>
#include <sys/types.h>
int loadDefaultPattern(char *fname);
@ -11,9 +11,11 @@ int default_writePatternIOControl(char* line, uint64_t arg);
int default_writePatternClkControl(char *line, uint64_t arg);
int default_setPatternLoopLimits(char* line, uint32_t startAddr, uint32_t stopAddr);
int default_setPatternLoopLimits(char *line, uint32_t startAddr,
uint32_t stopAddr);
int default_setPatternLoopAddresses(char* line, int level, uint32_t startAddr, uint32_t stopAddr);
int default_setPatternLoopAddresses(char *line, int level, uint32_t startAddr,
uint32_t stopAddr);
int default_setPatternLoopCycles(char *line, int level, int numLoops);

82
slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h Executable file → Normal file
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@ -1,10 +1,11 @@
#include "sls_detector_defs.h"
#include "slsDetectorServer_defs.h" // DAC_INDEX, ADC_INDEX, also include RegisterDefs.h
#include "sls_detector_defs.h"
#ifdef GOTTHARDD
#include "clogger.h" // runState(enum TLogLevel)
#include "AD9252.h" // old board compatibility
#include "clogger.h" // runState(enum TLogLevel)
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD)
#include "AD9257.h" // commonServerFunctions.h, blackfin.h, ansi.h
#endif
#ifdef MOENCHD
@ -19,18 +20,19 @@
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
#include "nios.h"
#elif defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
#elif defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD)
#include "blackfin.h"
#endif
#include <stdlib.h>
#include <stdio.h> // FILE
#include <stdlib.h>
#include <sys/types.h>
/****************************************************
This functions are used by the slsDetectroServer_funcs interface.
Here are the definitions, but the actual implementation should be done for each single detector.
Here are the definitions, but the actual implementation should be done for each
single detector.
****************************************************/
@ -50,18 +52,19 @@ typedef struct udpStruct_s {
uint32_t dstip2;
} udpStruct;
// basic tests
int isInitCheckDone();
int getInitResult(char **mess);
void basictests();
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
int checkType();
int testFpga();
int testBus();
#endif
#if defined(GOTTHARDD) || ((defined(EIGERD) || defined(JUNGFRAUD)) && defined(VIRTUAL))
#if defined(GOTTHARDD) || \
((defined(EIGERD) || defined(JUNGFRAUD)) && defined(VIRTUAL))
void setTestImageMode(int ival);
int getTestImageMode();
#endif
@ -71,7 +74,8 @@ u_int64_t getServerVersion();
u_int64_t getClientServerAPIVersion();
u_int64_t getFirmwareVersion();
u_int64_t getFirmwareAPIVersion();
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D)
u_int16_t getHardwareVersionNumber();
#endif
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
@ -87,7 +91,6 @@ u_int32_t getDetectorIP();
u_int32_t getBoardRevision();
#endif
// initialization
void initControlServer();
void initStopServer();
@ -105,26 +108,28 @@ int updateDatabytesandAllocateRAM();
void updateDataBytes();
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D) || defined(MOENCHD)
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MYTHEN3D) || \
defined(MOENCHD)
int setDefaultDacs();
#endif
#ifdef GOTTHARD2D
int readConfigFile();
#endif
// advanced read/write reg
#ifdef EIGERD
int writeRegister(uint32_t offset, uint32_t data);
int readRegister(uint32_t offset, uint32_t *retval);
#elif GOTTHARDD
uint32_t writeRegister16And32(uint32_t offset, uint32_t data); //FIXME its not there in ctb or moench?
uint32_t
writeRegister16And32(uint32_t offset,
uint32_t data); // FIXME its not there in ctb or moench?
uint32_t readRegister16And32(uint32_t offset);
#endif
// firmware functions (resets)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D)
void cleanFifos();
void resetCore();
void resetPeripheral();
@ -141,7 +146,6 @@ int readConfigFile();
void setMasterSlaveConfiguration();
#endif
// parameters - dr, roi
int setDynamicRange(int dr);
#ifdef GOTTHARDD
@ -179,8 +183,6 @@ int setReadoutMode(enum readoutMode mode);
int getReadoutMode();
#endif
// parameters - timer
#ifdef JUNGFRAUD
int selectStoragecellStart(int pos);
@ -230,7 +232,8 @@ void setCounterMask(uint32_t arg);
uint32_t getCounterMask();
#endif
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(JUNGFRAUD) || defined(GOTTHARDD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
int setDelayAfterTrigger(int64_t val);
int64_t getDelayAfterTrigger();
int64_t getNumFramesLeft();
@ -241,16 +244,16 @@ int64_t getPeriodLeft();
#ifdef GOTTHARDD
int64_t getExpTimeLeft();
#endif
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D)
int64_t getFramesFromStart();
int64_t getActualTime();
int64_t getMeasurementTime();
#endif
// parameters - module, settings
#if (!defined(CHIPTESTBOARDD)) && (!defined(MOENCHD)) && (!defined(MYTHEN3D)) && (!defined(GOTTHARD2D))
#if (!defined(CHIPTESTBOARDD)) && (!defined(MOENCHD)) && \
(!defined(MYTHEN3D)) && (!defined(GOTTHARD2D))
int setModule(sls_detector_module myMod, char *mess);
int getModule(sls_detector_module *myMod);
#endif
@ -303,8 +306,6 @@ int getADC(enum ADCINDEX ind);
int setHighVoltage(int val);
// parameters - timing, extsig
void setTiming(enum timingMode arg);
enum timingMode getTiming();
@ -321,22 +322,22 @@ void setNumberofUDPInterfaces(int val);
int getNumberofUDPInterfaces();
void selectPrimaryInterface(int val);
int getPrimaryInterface();
void setupHeader(int iRxEntry, enum interfaceType type, uint32_t destip, uint64_t destmac, uint32_t destport, uint64_t sourcemac, uint32_t sourceip, uint32_t sourceport);
void setupHeader(int iRxEntry, enum interfaceType type, uint32_t destip,
uint64_t destmac, uint32_t destport, uint64_t sourcemac,
uint32_t sourceip, uint32_t sourceport);
#endif
#if defined(JUNGFRAUD) || defined(GOTTHARD2D) || defined(MYTHEN3D) || defined(CHIPTESTBOARDD) || defined(MOENCHD)
#if defined(JUNGFRAUD) || defined(GOTTHARD2D) || defined(MYTHEN3D) || \
defined(CHIPTESTBOARDD) || defined(MOENCHD)
void calcChecksum(udp_header *udp);
#endif
#ifdef GOTTHARDD
int getAdcConfigured();
#endif
int configureMAC();
int setDetectorPosition(int pos[]);
int *getDetectorPosition();
#ifdef EIGERD
int setQuad(int value);
int getQuad();
@ -349,7 +350,6 @@ int getReadNLines();
int enableTenGigabitEthernet(int val);
#endif
// very detector specific
// moench specific - powerchip
@ -358,7 +358,8 @@ int powerChip (int on);
int setAnalogOnlyReadout();
#endif
// chip test board or moench specific - configure frequency, phase, pll, flashing firmware
// chip test board or moench specific - configure frequency, phase, pll,
// flashing firmware
#if defined(CHIPTESTBOARDD) || defined(MOENCHD)
int setPhase(enum CLKINDEX ind, int val, int degrees);
int getPhase(enum CLKINDEX ind, int degrees);
@ -387,7 +388,8 @@ void setPatternBitMask(uint64_t mask);
uint64_t getPatternBitMask();
#endif
// jungfrau specific - powerchip, autocompdisable, clockdiv, asictimer, clock, pll, flashing firmware
// jungfrau specific - powerchip, autocompdisable, clockdiv, asictimer, clock,
// pll, flashing firmware
#ifdef JUNGFRAUD
void initReadoutConfiguration();
int powerChip(int on);
@ -495,9 +497,6 @@ int getTransmissionDelayRight();
int setTransmissionDelayRight(int value);
#endif
// aquisition
#ifdef EIGERD
int prepareAcquisition();
@ -525,7 +524,8 @@ int checkFifoForEndOfAcquisition();
int readFrameFromFifo();
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(CHIPTESTBOARDD) || \
defined(MOENCHD) || defined(MYTHEN3D) || defined(GOTTHARD2D)
u_int32_t runBusy();
#endif
@ -533,7 +533,6 @@ u_int32_t runBusy();
u_int32_t runState(enum TLogLevel lev);
#endif
// common
#ifdef EIGERD
int copyModule(sls_detector_module *destMod, sls_detector_module *srcMod);
@ -546,6 +545,3 @@ void getNumberOfChannels(int* nchanx, int* nchany);
int getNumberOfChips();
int getNumberOfDACs();
int getNumberOfChannelsPerChip();

6
slsDetectorServers/slsDetectorServer/include/slsDetectorServer_funcs.h Executable file → Normal file
View File

@ -1,6 +1,6 @@
#pragma once
#include "sls_detector_defs.h"
#include "clogger.h"
#include "sls_detector_defs.h"
enum numberMode { DEC, HEX };
#define GOODBYE (-200)
@ -16,7 +16,8 @@ void function_table();
void functionNotImplemented();
void modeNotImplemented(char *modename, int mode);
void validate(int arg, int retval, char *modename, enum numberMode nummode);
void validate64(int64_t arg, int64_t retval, char* modename, enum numberMode nummode);
void validate64(int64_t arg, int64_t retval, char *modename,
enum numberMode nummode);
int executeCommand(char *command, char *result, enum TLogLevel level);
int M_nofunc(int);
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
@ -217,4 +218,3 @@ int set_timing_source(int);
int get_num_channels(int);
int update_rate_correction(int);
int get_receiver_parameters(int);