mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2026-01-16 00:49:22 +01:00
format slsdetectorservers
This commit is contained in:
211
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h
Executable file → Normal file
211
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h
Executable file → Normal file
@@ -3,125 +3,136 @@
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#include <stdlib.h>
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/* Enums */
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enum ADCINDEX {TEMP_FPGA, TEMP_ADC};
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enum DACINDEX {G_VREF_DS, G_VCASCN_PB, G_VCASCP_PB, G_VOUT_CM, G_VCASC_OUT, G_VIN_CM, G_VREF_COMP, G_IB_TESTC};
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enum CLKINDEX {ADC_CLK, NUM_CLOCKS};
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#define CLK_NAMES "adc"
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enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
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enum DACINDEX {
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G_VREF_DS,
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G_VCASCN_PB,
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G_VCASCP_PB,
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G_VOUT_CM,
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G_VCASC_OUT,
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G_VIN_CM,
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G_VREF_COMP,
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G_IB_TESTC
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};
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enum CLKINDEX { ADC_CLK, NUM_CLOCKS };
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#define CLK_NAMES "adc"
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#define DEFAULT_DAC_VALS { \
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660, /* G_VREF_DS */ \
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650, /* G_VCASCN_PB */ \
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1480, /* G_VCASCP_PB */ \
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1520, /* G_VOUT_CM */ \
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1320, /* G_VCASC_OUT */ \
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1350, /* G_VIN_CM */ \
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350, /* G_VREF_COMP */ \
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2001 /* G_IB_TESTC */ \
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};
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#define DEFAULT_DAC_VALS \
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{ \
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660, /* G_VREF_DS */ \
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650, /* G_VCASCN_PB */ \
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1480, /* G_VCASCP_PB */ \
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1520, /* G_VOUT_CM */ \
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1320, /* G_VCASC_OUT */ \
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1350, /* G_VIN_CM */ \
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350, /* G_VREF_COMP */ \
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2001 /* G_IB_TESTC */ \
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};
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/* for 25 um */
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#define CONFIG_FILE "config.txt"
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#define CONFIG_FILE "config.txt"
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/* Hardware Definitions */
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#define NCHAN (128)
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#define NCHIP (10)
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#define NDAC (8)
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#define NCHIPS_PER_ADC (2)
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#define NCHAN_PER_ADC (256)
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#define DYNAMIC_RANGE (16)
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#define NUM_BITS_PER_PIXEL (DYNAMIC_RANGE / 8)
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#define DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
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#define CLK_FREQ (32007729) /* Hz */
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#define NCHAN (128)
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#define NCHIP (10)
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#define NDAC (8)
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#define NCHIPS_PER_ADC (2)
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#define NCHAN_PER_ADC (256)
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#define DYNAMIC_RANGE (16)
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#define NUM_BITS_PER_PIXEL (DYNAMIC_RANGE / 8)
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#define DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
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#define CLK_FREQ (32007729) /* Hz */
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/** Firmware Definitions */
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#define IP_PACKET_SIZE_NO_ROI (NCHIP * (NCHAN / 2) * 2 + 14 + 20) // 2 packets, so divide by 2
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#define IP_PACKET_SIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20)
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#define IP_PACKET_SIZE_NO_ROI \
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(NCHIP * (NCHAN / 2) * 2 + 14 + 20) // 2 packets, so divide by 2
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#define IP_PACKET_SIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20)
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#define UDP_PACKETSIZE_NO_ROI (NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2) // 2 packets, so divide by 2
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#define UDP_PACKETSIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2)
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#define UDP_PACKETSIZE_NO_ROI \
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(NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2) // 2 packets, so divide by 2
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#define UDP_PACKETSIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2)
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/** Default Parameters */
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_EXPTIME (1 * 1000 * 1000) // 1 ms
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#define DEFAULT_PERIOD (1 * 1000 * 1000 * 1000) // 1 s
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#define DEFAULT_DELAY (0)
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#define DEFAULT_SETTINGS (DYNAMICGAIN)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_TRIGGER_MODE (TRIGGER_IN_RISING_EDGE)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_PHASE_SHIFT (120)
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#define DEFAULT_TX_UDP_PORT (0xE185)
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#define DEFAULT_NUM_FRAMES (1)
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#define DEFAULT_NUM_CYCLES (1)
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#define DEFAULT_EXPTIME (1 * 1000 * 1000) // 1 ms
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#define DEFAULT_PERIOD (1 * 1000 * 1000 * 1000) // 1 s
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#define DEFAULT_DELAY (0)
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#define DEFAULT_SETTINGS (DYNAMICGAIN)
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#define DEFAULT_TIMING_MODE (AUTO_TIMING)
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#define DEFAULT_TRIGGER_MODE (TRIGGER_IN_RISING_EDGE)
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#define DEFAULT_HIGH_VOLTAGE (0)
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#define DEFAULT_PHASE_SHIFT (120)
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#define DEFAULT_TX_UDP_PORT (0xE185)
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2500)
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#define DAC_MIN_MV (0)
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#define DAC_MAX_MV (2500)
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/** ENEt conf structs */
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typedef struct mac_header_struct{
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u_int8_t mac_dest_mac2;
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u_int8_t mac_dest_mac1;
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u_int8_t mac_dummy1;
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u_int8_t mac_dummy2;
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u_int8_t mac_dest_mac6;
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u_int8_t mac_dest_mac5;
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u_int8_t mac_dest_mac4;
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u_int8_t mac_dest_mac3;
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u_int8_t mac_src_mac4;
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u_int8_t mac_src_mac3;
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u_int8_t mac_src_mac2;
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u_int8_t mac_src_mac1;
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u_int16_t mac_ether_type;
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u_int8_t mac_src_mac6;
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u_int8_t mac_src_mac5;
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typedef struct mac_header_struct {
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u_int8_t mac_dest_mac2;
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u_int8_t mac_dest_mac1;
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u_int8_t mac_dummy1;
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u_int8_t mac_dummy2;
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u_int8_t mac_dest_mac6;
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u_int8_t mac_dest_mac5;
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u_int8_t mac_dest_mac4;
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u_int8_t mac_dest_mac3;
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u_int8_t mac_src_mac4;
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u_int8_t mac_src_mac3;
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u_int8_t mac_src_mac2;
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u_int8_t mac_src_mac1;
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u_int16_t mac_ether_type;
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u_int8_t mac_src_mac6;
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u_int8_t mac_src_mac5;
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} mac_header;
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typedef struct ip_header_struct {
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u_int16_t ip_len;
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u_int8_t ip_tos;
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u_int8_t ip_ihl:4 ,ip_ver:4;
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u_int16_t ip_offset:13,ip_flag:3;
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u_int16_t ip_ident;
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u_int16_t ip_chksum;
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u_int8_t ip_protocol;
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u_int8_t ip_ttl;
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u_int32_t ip_sourceip;
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u_int32_t ip_destip;
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u_int16_t ip_len;
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u_int8_t ip_tos;
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u_int8_t ip_ihl : 4, ip_ver : 4;
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u_int16_t ip_offset : 13, ip_flag : 3;
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u_int16_t ip_ident;
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u_int16_t ip_chksum;
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u_int8_t ip_protocol;
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u_int8_t ip_ttl;
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u_int32_t ip_sourceip;
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u_int32_t ip_destip;
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} ip_header;
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typedef struct udp_header_struct{
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u_int16_t udp_destport;
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u_int16_t udp_srcport;
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u_int16_t udp_chksum;
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u_int16_t udp_len;
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typedef struct udp_header_struct {
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u_int16_t udp_destport;
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u_int16_t udp_srcport;
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u_int16_t udp_chksum;
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u_int16_t udp_len;
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} udp_header;
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typedef struct mac_conf_struct{
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mac_header mac;
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ip_header ip;
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udp_header udp;
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u_int32_t npack;
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u_int32_t lpack;
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u_int32_t npad;
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u_int32_t cdone;
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typedef struct mac_conf_struct {
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mac_header mac;
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ip_header ip;
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udp_header udp;
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u_int32_t npack;
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u_int32_t lpack;
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u_int32_t npad;
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u_int32_t cdone;
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} mac_conf;
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typedef struct tse_conf_struct{
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u_int32_t rev; //0x0
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u_int32_t scratch;
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u_int32_t command_config;
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u_int32_t mac_0; //0x3
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u_int32_t mac_1;
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u_int32_t frm_length;
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u_int32_t pause_quant;
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u_int32_t rx_section_empty; //0x7
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u_int32_t rx_section_full;
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u_int32_t tx_section_empty;
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u_int32_t tx_section_full;
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u_int32_t rx_almost_empty; //0xB
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u_int32_t rx_almost_full;
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u_int32_t tx_almost_empty;
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u_int32_t tx_almost_full;
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u_int32_t mdio_addr0; //0xF
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u_int32_t mdio_addr1;
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}tse_conf;
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typedef struct tse_conf_struct {
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u_int32_t rev; // 0x0
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u_int32_t scratch;
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u_int32_t command_config;
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u_int32_t mac_0; // 0x3
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u_int32_t mac_1;
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u_int32_t frm_length;
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u_int32_t pause_quant;
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u_int32_t rx_section_empty; // 0x7
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u_int32_t rx_section_full;
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u_int32_t tx_section_empty;
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u_int32_t tx_section_full;
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u_int32_t rx_almost_empty; // 0xB
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u_int32_t rx_almost_full;
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u_int32_t tx_almost_empty;
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u_int32_t tx_almost_full;
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u_int32_t mdio_addr0; // 0xF
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u_int32_t mdio_addr1;
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} tse_conf;
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