mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-12 21:07:13 +02:00
format slsdetectorservers
This commit is contained in:
726
slsDetectorServers/ctbDetectorServer/RegisterDefs.h
Executable file → Normal file
726
slsDetectorServers/ctbDetectorServer/RegisterDefs.h
Executable file → Normal file
@ -4,552 +4,576 @@
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#define MEM_MAP_SHIFT 1
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/* FPGA Version RO register */
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#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
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#define FPGA_VERSION_REG (0x00 << MEM_MAP_SHIFT)
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#define FPGA_VERSION_BRD_RVSN_OFST (0)
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#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
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#define FPGA_VERSION_DTCTR_TYP_OFST (24)
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#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
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#define FPGA_VERSION_DTCTR_TYP_CTB_VAL ((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
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#define FPGA_VERSION_BRD_RVSN_OFST (0)
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#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
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#define FPGA_VERSION_DTCTR_TYP_OFST (24)
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#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
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#define FPGA_VERSION_DTCTR_TYP_CTB_VAL \
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((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
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/* Fix pattern RO register */
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#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
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#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
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#define FIX_PATT_VAL (0xACDC2016)
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#define FIX_PATT_VAL (0xACDC2016)
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/* Status RO register */
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#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
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#define STATUS_REG (0x02 << MEM_MAP_SHIFT)
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#define STATUS_RN_BSY_OFST (0)
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#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
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#define STATUS_RDT_BSY_OFST (1)
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#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
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#define STATUS_ANY_FF_FLL_OFST (2)
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#define STATUS_ANY_FF_FLL_MSK (0x00000001 << STATUS_ANY_FF_FLL_OFST)
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#define STATUS_WTNG_FR_TRGGR_OFST (3)
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#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
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#define STATUS_DLY_BFR_OFST (4)
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#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
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#define STATUS_DLY_AFTR_OFST (5)
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#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
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#define STATUS_EXPSNG_OFST (6)
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#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
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#define STATUS_CNT_ENBL_OFST (7)
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#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
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#define STATUS_SM_FF_FLL_OFST (11)
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#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
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#define STATUS_STPPD_OFST (15)
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#define STATUS_STPPD_MSK (0x00000001 << STATUS_STPPD_OFST)
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#define STATUS_ALL_FF_EMPTY_OFST (16)
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#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
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#define STATUS_CYCL_RN_BSY_OFST (17)
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#define STATUS_CYCL_RN_BSY_MSK (0x00000001 << STATUS_CYCL_RN_BSY_OFST)
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#define STATUS_FRM_RN_BSY_OFST (18)
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#define STATUS_FRM_RN_BSY_MSK (0x00000001 << STATUS_FRM_RN_BSY_OFST)
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#define STATUS_ADC_DESERON_OFST (19)
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#define STATUS_ADC_DESERON_MSK (0x00000001 << STATUS_ADC_DESERON_OFST)
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#define STATUS_PLL_RCNFG_BSY_OFST (20)
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#define STATUS_PLL_RCNFG_BSY_MSK (0x00000001 << STATUS_PLL_RCNFG_BSY_OFST)
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#define STATUS_DT_STRMNG_BSY_OFST (21)
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#define STATUS_DT_STRMNG_BSY_MSK (0x00000001 << STATUS_DT_STRMNG_BSY_OFST)
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#define STATUS_FRM_PCKR_BSY_OFST (22)
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#define STATUS_FRM_PCKR_BSY_MSK (0x00000001 << STATUS_FRM_PCKR_BSY_OFST)
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#define STATUS_PLL_PHS_DN_OFST (23)
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#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
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#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
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#define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
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#define STATUS_IDLE_MSK (0x677FF)
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#define STATUS_RN_BSY_OFST (0)
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#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
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#define STATUS_RDT_BSY_OFST (1)
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#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
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#define STATUS_ANY_FF_FLL_OFST (2)
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#define STATUS_ANY_FF_FLL_MSK (0x00000001 << STATUS_ANY_FF_FLL_OFST)
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#define STATUS_WTNG_FR_TRGGR_OFST (3)
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#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
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#define STATUS_DLY_BFR_OFST (4)
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#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
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#define STATUS_DLY_AFTR_OFST (5)
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#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
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#define STATUS_EXPSNG_OFST (6)
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#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
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#define STATUS_CNT_ENBL_OFST (7)
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#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
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#define STATUS_SM_FF_FLL_OFST (11)
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#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
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#define STATUS_STPPD_OFST (15)
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#define STATUS_STPPD_MSK (0x00000001 << STATUS_STPPD_OFST)
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#define STATUS_ALL_FF_EMPTY_OFST (16)
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#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
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#define STATUS_CYCL_RN_BSY_OFST (17)
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#define STATUS_CYCL_RN_BSY_MSK (0x00000001 << STATUS_CYCL_RN_BSY_OFST)
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#define STATUS_FRM_RN_BSY_OFST (18)
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#define STATUS_FRM_RN_BSY_MSK (0x00000001 << STATUS_FRM_RN_BSY_OFST)
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#define STATUS_ADC_DESERON_OFST (19)
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#define STATUS_ADC_DESERON_MSK (0x00000001 << STATUS_ADC_DESERON_OFST)
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#define STATUS_PLL_RCNFG_BSY_OFST (20)
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#define STATUS_PLL_RCNFG_BSY_MSK (0x00000001 << STATUS_PLL_RCNFG_BSY_OFST)
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#define STATUS_DT_STRMNG_BSY_OFST (21)
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#define STATUS_DT_STRMNG_BSY_MSK (0x00000001 << STATUS_DT_STRMNG_BSY_OFST)
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#define STATUS_FRM_PCKR_BSY_OFST (22)
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#define STATUS_FRM_PCKR_BSY_MSK (0x00000001 << STATUS_FRM_PCKR_BSY_OFST)
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#define STATUS_PLL_PHS_DN_OFST (23)
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#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
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#define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
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#define STATUS_PT_CNTRL_STTS_OFF_MSK \
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(0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
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#define STATUS_IDLE_MSK (0x677FF)
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/* Look at me RO register TODO */
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#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
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#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
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/* System Status RO register */
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#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
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#define SYSTEM_STATUS_REG (0x04 << MEM_MAP_SHIFT)
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#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
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#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
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#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
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#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK (0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
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#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
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#define SYSTEM_STATUS_DDR3_INT_DN_MSK (0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
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#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
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#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK (0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
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#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
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#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
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#define SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST (0)
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#define SYSTEM_STATUS_DDR3_CLBRTN_OK_MSK \
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(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_OK_OFST)
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#define SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST (1)
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#define SYSTEM_STATUS_DDR3_CLBRTN_FL_MSK \
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(0x00000001 << SYSTEM_STATUS_DDR3_CLBRTN_FL_OFST)
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#define SYSTEM_STATUS_DDR3_INT_DN_OFST (2)
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#define SYSTEM_STATUS_DDR3_INT_DN_MSK \
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(0x00000001 << SYSTEM_STATUS_DDR3_INT_DN_OFST)
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#define SYSTEM_STATUS_RCNFG_PLL_LCK_OFST (3)
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#define SYSTEM_STATUS_RCNFG_PLL_LCK_MSK \
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(0x00000001 << SYSTEM_STATUS_RCNFG_PLL_LCK_OFST)
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#define SYSTEM_STATUS_PLL_A_LCK_OFST (4)
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#define SYSTEM_STATUS_PLL_A_LCK_MSK (0x00000001 << SYSTEM_STATUS_PLL_A_LCK_OFST)
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/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as PLL_PARAM_REG 0x50 */
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/* PLL Param (Reconfiguratble PLL Parameter) RO register TODO FIXME: Same as
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* PLL_PARAM_REG 0x50 */
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//#define PLL_PARAM_REG (0x05 << MEM_MAP_SHIFT)
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/* FIFO Data RO register TODO */
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#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
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#define FIFO_DATA_REG (0x06 << MEM_MAP_SHIFT)
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#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
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#define FIFO_DATA_HRDWR_SRL_NMBR_MSK (0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
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#define FIFO_DATA_HRDWR_SRL_NMBR_OFST (0)
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#define FIFO_DATA_HRDWR_SRL_NMBR_MSK \
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(0x0000FFFF << FIFO_DATA_HRDWR_SRL_NMBR_OFST)
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//#define FIFO_DATA_WRD_OFST (16)
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//#define FIFO_DATA_WRD_MSK (0x0000FFFF << FIFO_DATA_WRD_OFST)
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/* FIFO Status RO register TODO */
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#define FIFO_STATUS_REG (0x07 << MEM_MAP_SHIFT)
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#define FIFO_STATUS_REG (0x07 << MEM_MAP_SHIFT)
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/* FIFO Empty RO register TODO */
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#define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT)
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#define FIFO_EMPTY_ALL_EMPTY_MSK (0xFFFFFFFF)
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#define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT)
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#define FIFO_EMPTY_ALL_EMPTY_MSK (0xFFFFFFFF)
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/* FIFO Full RO register TODO */
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#define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT)
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#define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT)
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/* MCB Serial Number RO register */
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#define MOD_SERIAL_NUMBER_REG (0x0A << MEM_MAP_SHIFT)
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#define MOD_SERIAL_NUMBER_REG (0x0A << MEM_MAP_SHIFT)
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#define MOD_SERIAL_NUMBER_OFST (0)
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#define MOD_SERIAL_NUMBER_MSK (0x000000FF << MOD_SERIAL_NUMBER_OFST)
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#define MOD_SERIAL_NUMBER_VRSN_OFST (16)
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#define MOD_SERIAL_NUMBER_VRSN_MSK (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
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#define MOD_SERIAL_NUMBER_OFST (0)
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#define MOD_SERIAL_NUMBER_MSK (0x000000FF << MOD_SERIAL_NUMBER_OFST)
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#define MOD_SERIAL_NUMBER_VRSN_OFST (16)
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#define MOD_SERIAL_NUMBER_VRSN_MSK (0x0000003F << MOD_SERIAL_NUMBER_VRSN_OFST)
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/* API Version RO register */
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#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
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#define API_VERSION_REG (0x0F << MEM_MAP_SHIFT)
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#define API_VERSION_OFST (0)
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#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
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#define API_VERSION_DTCTR_TYP_OFST (24)
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#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
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#define API_VERSION_OFST (0)
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#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
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#define API_VERSION_DTCTR_TYP_OFST (24)
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#define API_VERSION_DTCTR_TYP_MSK (0x000000FF << API_VERSION_DTCTR_TYP_OFST)
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/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using CONTROL_CRST. TODO */
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#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
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#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
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/* Time from Start 64 bit RO register. t = GCLK x 50 ns. Reset using
|
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* CONTROL_CRST. TODO */
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#define TIME_FROM_START_LSB_REG (0x10 << MEM_MAP_SHIFT)
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#define TIME_FROM_START_MSB_REG (0x11 << MEM_MAP_SHIFT)
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/* Delay Left 64 bit RO register. t = DLY x 50 ns. TODO */
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#define DELAY_LEFT_LSB_REG (0x12 << MEM_MAP_SHIFT)
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#define DELAY_LEFT_MSB_REG (0x13 << MEM_MAP_SHIFT)
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#define DELAY_LEFT_LSB_REG (0x12 << MEM_MAP_SHIFT)
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#define DELAY_LEFT_MSB_REG (0x13 << MEM_MAP_SHIFT)
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/* Triggers Left 64 bit RO register TODO */
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#define CYCLES_LEFT_LSB_REG (0x14 << MEM_MAP_SHIFT)
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#define CYCLES_LEFT_MSB_REG (0x15 << MEM_MAP_SHIFT)
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#define CYCLES_LEFT_LSB_REG (0x14 << MEM_MAP_SHIFT)
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#define CYCLES_LEFT_MSB_REG (0x15 << MEM_MAP_SHIFT)
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/* Frames Left 64 bit RO register TODO */
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#define FRAMES_LEFT_LSB_REG (0x16 << MEM_MAP_SHIFT)
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#define FRAMES_LEFT_MSB_REG (0x17 << MEM_MAP_SHIFT)
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#define FRAMES_LEFT_LSB_REG (0x16 << MEM_MAP_SHIFT)
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#define FRAMES_LEFT_MSB_REG (0x17 << MEM_MAP_SHIFT)
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/* Period Left 64 bit RO register. t = T x 50 ns. TODO */
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#define PERIOD_LEFT_LSB_REG (0x18 << MEM_MAP_SHIFT)
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#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
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#define PERIOD_LEFT_LSB_REG (0x18 << MEM_MAP_SHIFT)
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#define PERIOD_LEFT_MSB_REG (0x19 << MEM_MAP_SHIFT)
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||||
/* Exposure Time Left 64 bit RO register */
|
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//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not used in FW
|
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//#define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT) // Not used in FW
|
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//#define EXPTIME_LEFT_LSB_REG (0x1A << MEM_MAP_SHIFT) // Not
|
||||
//used in FW #define EXPTIME_LEFT_MSB_REG (0x1B << MEM_MAP_SHIFT)
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//// Not used in FW
|
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|
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/* Gates Left 64 bit RO register */
|
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//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not used in FW
|
||||
//#define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT) // Not used in FW
|
||||
//#define GATES_LEFT_LSB_REG (0x1C << MEM_MAP_SHIFT) // Not
|
||||
//used in FW #define GATES_LEFT_MSB_REG (0x1D << MEM_MAP_SHIFT)
|
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//// Not used in FW
|
||||
|
||||
/* Data In 64 bit RO register TODO */
|
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#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
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#define DATA_IN_MSB_REG (0x1F << MEM_MAP_SHIFT)
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||||
#define DATA_IN_LSB_REG (0x1E << MEM_MAP_SHIFT)
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#define DATA_IN_MSB_REG (0x1F << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Out 64 bit RO register */
|
||||
#define PATTERN_OUT_LSB_REG (0x20 << MEM_MAP_SHIFT)
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#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
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#define PATTERN_OUT_LSB_REG (0x20 << MEM_MAP_SHIFT)
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#define PATTERN_OUT_MSB_REG (0x21 << MEM_MAP_SHIFT)
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/* Frames From Start 64 bit RO register TODO */
|
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//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not used in FW
|
||||
//#define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT) // Not used in FW
|
||||
//#define FRAMES_FROM_START_LSB_REG (0x22 << MEM_MAP_SHIFT) // Not
|
||||
//used in FW #define FRAMES_FROM_START_MSB_REG (0x23 << MEM_MAP_SHIFT)
|
||||
//// Not used in FW
|
||||
|
||||
/* Frames From Start PG 64 bit RO register. Reset using CONTROL_CRST. TODO */
|
||||
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
|
||||
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
|
||||
#define FRAMES_FROM_START_PG_LSB_REG (0x24 << MEM_MAP_SHIFT)
|
||||
#define FRAMES_FROM_START_PG_MSB_REG (0x25 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame start until reset) TODO */
|
||||
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
|
||||
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
|
||||
/* Start Frame Time (Measurement Time) 64 bit register (timestamp at a frame
|
||||
* start until reset) TODO */
|
||||
#define START_FRAME_TIME_LSB_REG (0x26 << MEM_MAP_SHIFT)
|
||||
#define START_FRAME_TIME_MSB_REG (0x27 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Power Status RO register */
|
||||
#define POWER_STATUS_REG (0x29 << MEM_MAP_SHIFT)
|
||||
#define POWER_STATUS_REG (0x29 << MEM_MAP_SHIFT)
|
||||
|
||||
#define POWER_STATUS_ALRT_OFST (27)
|
||||
#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
|
||||
#define POWER_STATUS_ALRT_OFST (27)
|
||||
#define POWER_STATUS_ALRT_MSK (0x0000001F << POWER_STATUS_ALRT_OFST)
|
||||
|
||||
/* DAC Value Out RO register */
|
||||
//#define DAC_VAL_OUT_REG (0x2A << MEM_MAP_SHIFT)
|
||||
|
||||
/* Slow ADC SPI Value RO register */
|
||||
#define ADC_SPI_SLOW_VAL_REG (0x2B << MEM_MAP_SHIFT)
|
||||
#define ADC_SPI_SLOW_VAL_REG (0x2B << MEM_MAP_SHIFT)
|
||||
|
||||
/* FIFO Digital In Status RO register */
|
||||
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
|
||||
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
|
||||
#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
|
||||
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
|
||||
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
|
||||
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
|
||||
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
|
||||
#define FIFO_DIN_STATUS_FIFO_FULL_MSK \
|
||||
(0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
|
||||
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
|
||||
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK \
|
||||
(0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
|
||||
|
||||
/* FIFO Digital In 64 bit RO register */
|
||||
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
|
||||
#define FIFO_DIN_MSB_REG (0x3D << MEM_MAP_SHIFT)
|
||||
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)
|
||||
#define FIFO_DIN_MSB_REG (0x3D << MEM_MAP_SHIFT)
|
||||
|
||||
/* SPI (Serial Peripheral Interface) DAC, HV RW register */
|
||||
#define SPI_REG (0x40 << MEM_MAP_SHIFT)
|
||||
#define SPI_REG (0x40 << MEM_MAP_SHIFT)
|
||||
|
||||
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
|
||||
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
|
||||
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
|
||||
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
|
||||
#define SPI_DAC_SRL_CS_OTPT_OFST (2)
|
||||
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
|
||||
#define SPI_HV_SRL_DGTL_OTPT_OFST (8)
|
||||
#define SPI_HV_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
|
||||
#define SPI_HV_SRL_CLK_OTPT_OFST (9)
|
||||
#define SPI_HV_SRL_CLK_OTPT_MSK (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
|
||||
#define SPI_HV_SRL_CS_OTPT_OFST (10)
|
||||
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
|
||||
#define SPI_DAC_SRL_DGTL_OTPT_OFST (0)
|
||||
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
|
||||
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
|
||||
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
|
||||
#define SPI_DAC_SRL_CS_OTPT_OFST (2)
|
||||
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
|
||||
#define SPI_HV_SRL_DGTL_OTPT_OFST (8)
|
||||
#define SPI_HV_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_HV_SRL_DGTL_OTPT_OFST)
|
||||
#define SPI_HV_SRL_CLK_OTPT_OFST (9)
|
||||
#define SPI_HV_SRL_CLK_OTPT_MSK (0x00000001 << SPI_HV_SRL_CLK_OTPT_OFST)
|
||||
#define SPI_HV_SRL_CS_OTPT_OFST (10)
|
||||
#define SPI_HV_SRL_CS_OTPT_MSK (0x00000001 << SPI_HV_SRL_CS_OTPT_OFST)
|
||||
|
||||
/* ADC SPI (Serial Peripheral Interface) RW register */
|
||||
#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
|
||||
#define ADC_SPI_REG (0x41 << MEM_MAP_SHIFT)
|
||||
|
||||
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
|
||||
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
|
||||
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
|
||||
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
|
||||
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
|
||||
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
|
||||
#define ADC_SPI_SLOW_SRL_DT_OFST (8)
|
||||
#define ADC_SPI_SLOW_SRL_DT_MSK (0x00000001 << ADC_SPI_SLOW_SRL_DT_OFST)
|
||||
#define ADC_SPI_SLOW_SRL_CLK_OFST (9)
|
||||
#define ADC_SPI_SLOW_SRL_CLK_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CLK_OFST)
|
||||
#define ADC_SPI_SLOW_SRL_CNV_OFST (10)
|
||||
#define ADC_SPI_SLOW_SRL_CNV_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CNV_OFST)
|
||||
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
|
||||
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
|
||||
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
|
||||
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
|
||||
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
|
||||
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000000F << ADC_SPI_SRL_CS_OTPT_OFST)
|
||||
#define ADC_SPI_SLOW_SRL_DT_OFST (8)
|
||||
#define ADC_SPI_SLOW_SRL_DT_MSK (0x00000001 << ADC_SPI_SLOW_SRL_DT_OFST)
|
||||
#define ADC_SPI_SLOW_SRL_CLK_OFST (9)
|
||||
#define ADC_SPI_SLOW_SRL_CLK_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CLK_OFST)
|
||||
#define ADC_SPI_SLOW_SRL_CNV_OFST (10)
|
||||
#define ADC_SPI_SLOW_SRL_CNV_MSK (0x00000001 << ADC_SPI_SLOW_SRL_CNV_OFST)
|
||||
|
||||
/* ADC Offset RW register */
|
||||
#define ADC_OFFSET_REG (0x42 << MEM_MAP_SHIFT)
|
||||
#define ADC_OFFSET_REG (0x42 << MEM_MAP_SHIFT)
|
||||
|
||||
#define ADC_OFFSET_ADC_PPLN_OFST (0)
|
||||
#define ADC_OFFSET_ADC_PPLN_MSK (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
|
||||
#define ADC_OFFSET_DBT_PPLN_OFST (16)
|
||||
#define ADC_OFFSET_DBT_PPLN_MSK (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
|
||||
#define ADC_OFFSET_ADC_PPLN_OFST (0)
|
||||
#define ADC_OFFSET_ADC_PPLN_MSK (0x000000FF << ADC_OFFSET_ADC_PPLN_OFST)
|
||||
#define ADC_OFFSET_DBT_PPLN_OFST (16)
|
||||
#define ADC_OFFSET_DBT_PPLN_MSK (0x000000FF << ADC_OFFSET_DBT_PPLN_OFST)
|
||||
|
||||
/* ADC Port Invert RW register */
|
||||
#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
|
||||
#define ADC_PORT_INVERT_REG (0x43 << MEM_MAP_SHIFT)
|
||||
|
||||
#define ADC_PORT_INVERT_0_INPT_OFST (0)
|
||||
#define ADC_PORT_INVERT_0_INPT_MSK (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
|
||||
#define ADC_PORT_INVERT_1_INPT_OFST (8)
|
||||
#define ADC_PORT_INVERT_1_INPT_MSK (0x000000FF << ADC_PORT_INVERT_1_INPT_OFST)
|
||||
#define ADC_PORT_INVERT_2_INPT_OFST (16)
|
||||
#define ADC_PORT_INVERT_2_INPT_MSK (0x000000FF << ADC_PORT_INVERT_2_INPT_OFST)
|
||||
#define ADC_PORT_INVERT_3_INPT_OFST (24)
|
||||
#define ADC_PORT_INVERT_3_INPT_MSK (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
|
||||
#define ADC_PORT_INVERT_0_INPT_OFST (0)
|
||||
#define ADC_PORT_INVERT_0_INPT_MSK (0x000000FF << ADC_PORT_INVERT_0_INPT_OFST)
|
||||
#define ADC_PORT_INVERT_1_INPT_OFST (8)
|
||||
#define ADC_PORT_INVERT_1_INPT_MSK (0x000000FF << ADC_PORT_INVERT_1_INPT_OFST)
|
||||
#define ADC_PORT_INVERT_2_INPT_OFST (16)
|
||||
#define ADC_PORT_INVERT_2_INPT_MSK (0x000000FF << ADC_PORT_INVERT_2_INPT_OFST)
|
||||
#define ADC_PORT_INVERT_3_INPT_OFST (24)
|
||||
#define ADC_PORT_INVERT_3_INPT_MSK (0x000000FF << ADC_PORT_INVERT_3_INPT_OFST)
|
||||
|
||||
/* Dummy RW register */
|
||||
#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
|
||||
#define DUMMY_REG (0x44 << MEM_MAP_SHIFT)
|
||||
|
||||
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
|
||||
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
|
||||
#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
|
||||
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
|
||||
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
|
||||
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK (0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
|
||||
#define DUMMY_FIFO_CHNNL_SLCT_OFST (0)
|
||||
#define DUMMY_FIFO_CHNNL_SLCT_MSK (0x0000003F << DUMMY_FIFO_CHNNL_SLCT_OFST)
|
||||
#define DUMMY_ANLG_FIFO_RD_STRBE_OFST (8)
|
||||
#define DUMMY_ANLG_FIFO_RD_STRBE_MSK \
|
||||
(0x00000001 << DUMMY_ANLG_FIFO_RD_STRBE_OFST)
|
||||
#define DUMMY_DGTL_FIFO_RD_STRBE_OFST (9)
|
||||
#define DUMMY_DGTL_FIFO_RD_STRBE_MSK \
|
||||
(0x00000001 << DUMMY_DGTL_FIFO_RD_STRBE_OFST)
|
||||
|
||||
/* Receiver IP Address RW register */
|
||||
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
|
||||
#define RX_IP_REG (0x45 << MEM_MAP_SHIFT)
|
||||
|
||||
/* UDP Port RW register */
|
||||
#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT)
|
||||
#define UDP_PORT_REG (0x46 << MEM_MAP_SHIFT)
|
||||
|
||||
#define UDP_PORT_RX_OFST (0)
|
||||
#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
|
||||
#define UDP_PORT_TX_OFST (16)
|
||||
#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
|
||||
#define UDP_PORT_RX_OFST (0)
|
||||
#define UDP_PORT_RX_MSK (0x0000FFFF << UDP_PORT_RX_OFST)
|
||||
#define UDP_PORT_TX_OFST (16)
|
||||
#define UDP_PORT_TX_MSK (0x0000FFFF << UDP_PORT_TX_OFST)
|
||||
|
||||
/* Receiver Mac Address 64 bit RW register */
|
||||
#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT)
|
||||
#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT)
|
||||
#define RX_MAC_LSB_REG (0x47 << MEM_MAP_SHIFT)
|
||||
#define RX_MAC_MSB_REG (0x48 << MEM_MAP_SHIFT)
|
||||
|
||||
#define RX_MAC_LSB_OFST (0)
|
||||
#define RX_MAC_LSB_MSK (0xFFFFFFFF << RX_MAC_LSB_OFST)
|
||||
#define RX_MAC_MSB_OFST (0)
|
||||
#define RX_MAC_MSB_MSK (0x0000FFFF << RX_MAC_MSB_OFST)
|
||||
#define RX_MAC_LSB_OFST (0)
|
||||
#define RX_MAC_LSB_MSK (0xFFFFFFFF << RX_MAC_LSB_OFST)
|
||||
#define RX_MAC_MSB_OFST (0)
|
||||
#define RX_MAC_MSB_MSK (0x0000FFFF << RX_MAC_MSB_OFST)
|
||||
|
||||
/* Detector/ Transmitter Mac Address 64 bit RW register */
|
||||
#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT)
|
||||
#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT)
|
||||
#define TX_MAC_LSB_REG (0x49 << MEM_MAP_SHIFT)
|
||||
#define TX_MAC_MSB_REG (0x4A << MEM_MAP_SHIFT)
|
||||
|
||||
#define TX_MAC_LSB_OFST (0)
|
||||
#define TX_MAC_LSB_MSK (0xFFFFFFFF << TX_MAC_LSB_OFST)
|
||||
#define TX_MAC_MSB_OFST (0)
|
||||
#define TX_MAC_MSB_MSK (0x0000FFFF << TX_MAC_MSB_OFST)
|
||||
#define TX_MAC_LSB_OFST (0)
|
||||
#define TX_MAC_LSB_MSK (0xFFFFFFFF << TX_MAC_LSB_OFST)
|
||||
#define TX_MAC_MSB_OFST (0)
|
||||
#define TX_MAC_MSB_MSK (0x0000FFFF << TX_MAC_MSB_OFST)
|
||||
|
||||
/* Detector/ Transmitter IP Address RW register */
|
||||
#define TX_IP_REG (0x4B << MEM_MAP_SHIFT)
|
||||
#define TX_IP_REG (0x4B << MEM_MAP_SHIFT)
|
||||
|
||||
/* Detector/ Transmitter IP Checksum RW register */
|
||||
#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT)
|
||||
#define TX_IP_CHECKSUM_REG (0x4C << MEM_MAP_SHIFT)
|
||||
|
||||
#define TX_IP_CHECKSUM_OFST (0)
|
||||
#define TX_IP_CHECKSUM_MSK (0x0000FFFF << TX_IP_CHECKSUM_OFST)
|
||||
#define TX_IP_CHECKSUM_OFST (0)
|
||||
#define TX_IP_CHECKSUM_MSK (0x0000FFFF << TX_IP_CHECKSUM_OFST)
|
||||
|
||||
/* Configuration RW register */
|
||||
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
|
||||
#define CONFIG_REG (0x4D << MEM_MAP_SHIFT)
|
||||
|
||||
#define CONFIG_LED_DSBL_OFST (0)
|
||||
#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
|
||||
#define CONFIG_DSBL_ANLG_OTPT_OFST (8)
|
||||
#define CONFIG_DSBL_ANLG_OTPT_MSK (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
|
||||
#define CONFIG_ENBLE_DGTL_OTPT_OFST (9)
|
||||
#define CONFIG_ENBLE_DGTL_OTPT_MSK (0x00000001 << CONFIG_ENBLE_DGTL_OTPT_OFST)
|
||||
#define CONFIG_GB10_SND_UDP_OFST (12)
|
||||
#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
|
||||
#define CONFIG_LED_DSBL_OFST (0)
|
||||
#define CONFIG_LED_DSBL_MSK (0x00000001 << CONFIG_LED_DSBL_OFST)
|
||||
#define CONFIG_DSBL_ANLG_OTPT_OFST (8)
|
||||
#define CONFIG_DSBL_ANLG_OTPT_MSK (0x00000001 << CONFIG_DSBL_ANLG_OTPT_OFST)
|
||||
#define CONFIG_ENBLE_DGTL_OTPT_OFST (9)
|
||||
#define CONFIG_ENBLE_DGTL_OTPT_MSK (0x00000001 << CONFIG_ENBLE_DGTL_OTPT_OFST)
|
||||
#define CONFIG_GB10_SND_UDP_OFST (12)
|
||||
#define CONFIG_GB10_SND_UDP_MSK (0x00000001 << CONFIG_GB10_SND_UDP_OFST)
|
||||
|
||||
/* External Signal RW register */
|
||||
#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
|
||||
#define EXT_SIGNAL_REG (0x4E << MEM_MAP_SHIFT)
|
||||
|
||||
#define EXT_SIGNAL_OFST (0)
|
||||
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
|
||||
#define EXT_SIGNAL_AUTO_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
|
||||
#define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
|
||||
#define EXT_SIGNAL_OFST (0)
|
||||
#define EXT_SIGNAL_MSK (0x00000001 << EXT_SIGNAL_OFST)
|
||||
#define EXT_SIGNAL_AUTO_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
|
||||
#define EXT_SIGNAL_TRGGR_VAL ((0x1 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
|
||||
|
||||
/* Control RW register */
|
||||
#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
|
||||
#define CONTROL_REG (0x4F << MEM_MAP_SHIFT)
|
||||
|
||||
#define CONTROL_STRT_ACQSTN_OFST (0)
|
||||
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
|
||||
#define CONTROL_STP_ACQSTN_OFST (1)
|
||||
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
|
||||
#define CONTROL_STRT_ACQSTN_OFST (0)
|
||||
#define CONTROL_STRT_ACQSTN_MSK (0x00000001 << CONTROL_STRT_ACQSTN_OFST)
|
||||
#define CONTROL_STP_ACQSTN_OFST (1)
|
||||
#define CONTROL_STP_ACQSTN_MSK (0x00000001 << CONTROL_STP_ACQSTN_OFST)
|
||||
//#define CONTROL_STRT_FF_TST_OFST (2)
|
||||
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
|
||||
//#define CONTROL_STP_FF_TST_OFST (3)
|
||||
//#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
|
||||
//#define CONTROL_STRT_RDT_OFST (4)
|
||||
//#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
|
||||
//#define CONTROL_STP_RDT_OFST (5)
|
||||
//#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
|
||||
#define CONTROL_STRT_EXPSR_OFST (6)
|
||||
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
|
||||
//#define CONTROL_STRT_FF_TST_MSK (0x00000001 <<
|
||||
//CONTROL_STRT_FF_TST_OFST) #define CONTROL_STP_FF_TST_OFST (3)
|
||||
//#define CONTROL_STP_FF_TST_MSK (0x00000001 <<
|
||||
//CONTROL_STP_FF_TST_OFST) #define CONTROL_STRT_RDT_OFST (4)
|
||||
//#define CONTROL_STRT_RDT_MSK (0x00000001 <<
|
||||
//CONTROL_STRT_RDT_OFST) #define CONTROL_STP_RDT_OFST (5) #define
|
||||
//CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
|
||||
#define CONTROL_STRT_EXPSR_OFST (6)
|
||||
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
|
||||
//#define CONTROL_STP_EXPSR_OFST (7)
|
||||
//#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
|
||||
//#define CONTROL_STRT_TRN_OFST (8)
|
||||
//#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
|
||||
//#define CONTROL_STP_EXPSR_MSK (0x00000001 <<
|
||||
//CONTROL_STP_RDT_OFST) #define CONTROL_STRT_TRN_OFST (8) #define
|
||||
//CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
|
||||
//#define CONTROL_STP_TRN_OFST (9)
|
||||
//#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
|
||||
#define CONTROL_CRE_RST_OFST (10)
|
||||
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
|
||||
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
|
||||
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
|
||||
#define CONTROL_MMRY_RST_OFST (12)
|
||||
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
|
||||
//#define CONTROL_STP_TRN_MSK (0x00000001 <<
|
||||
//CONTROL_STP_RDT_OFST)
|
||||
#define CONTROL_CRE_RST_OFST (10)
|
||||
#define CONTROL_CRE_RST_MSK (0x00000001 << CONTROL_CRE_RST_OFST)
|
||||
#define CONTROL_PRPHRL_RST_OFST (11) // Only GBE10?
|
||||
#define CONTROL_PRPHRL_RST_MSK (0x00000001 << CONTROL_PRPHRL_RST_OFST)
|
||||
#define CONTROL_MMRY_RST_OFST (12)
|
||||
#define CONTROL_MMRY_RST_MSK (0x00000001 << CONTROL_MMRY_RST_OFST)
|
||||
//#define CONTROL_PLL_RCNFG_WR_OFST (13)
|
||||
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 << CONTROL_PLL_RCNFG_WR_OFST)
|
||||
#define CONTROL_SND_10GB_PCKT_OFST (14)
|
||||
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
|
||||
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
|
||||
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
|
||||
//#define CONTROL_PLL_RCNFG_WR_MSK (0x00000001 <<
|
||||
//CONTROL_PLL_RCNFG_WR_OFST)
|
||||
#define CONTROL_SND_10GB_PCKT_OFST (14)
|
||||
#define CONTROL_SND_10GB_PCKT_MSK (0x00000001 << CONTROL_SND_10GB_PCKT_OFST)
|
||||
#define CONTROL_CLR_ACQSTN_FIFO_OFST (15)
|
||||
#define CONTROL_CLR_ACQSTN_FIFO_MSK (0x00000001 << CONTROL_CLR_ACQSTN_FIFO_OFST)
|
||||
|
||||
/* Reconfiguratble PLL Paramater RW register */
|
||||
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
|
||||
#define PLL_PARAM_REG (0x50 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Reconfiguratble PLL Control RW regiser */
|
||||
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
|
||||
#define PLL_CNTRL_REG (0x51 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
|
||||
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK (0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
|
||||
#define PLL_CNTRL_WR_PRMTR_OFST (2)
|
||||
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
|
||||
#define PLL_CNTRL_PLL_RST_OFST (3)
|
||||
#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
|
||||
#define PLL_CNTRL_ADDR_OFST (16)
|
||||
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
|
||||
#define PLL_CNTRL_RCNFG_PRMTR_RST_OFST (0)
|
||||
#define PLL_CNTRL_RCNFG_PRMTR_RST_MSK \
|
||||
(0x00000001 << PLL_CNTRL_RCNFG_PRMTR_RST_OFST)
|
||||
#define PLL_CNTRL_WR_PRMTR_OFST (2)
|
||||
#define PLL_CNTRL_WR_PRMTR_MSK (0x00000001 << PLL_CNTRL_WR_PRMTR_OFST)
|
||||
#define PLL_CNTRL_PLL_RST_OFST (3)
|
||||
#define PLL_CNTRL_PLL_RST_MSK (0x00000001 << PLL_CNTRL_PLL_RST_OFST)
|
||||
#define PLL_CNTRL_ADDR_OFST (16)
|
||||
#define PLL_CNTRL_ADDR_MSK (0x0000003F << PLL_CNTRL_ADDR_OFST)
|
||||
|
||||
/* Pattern Control RW register */
|
||||
#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_CNTRL_REG (0x52 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_CNTRL_WR_OFST (0)
|
||||
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
|
||||
#define PATTERN_CNTRL_RD_OFST (1)
|
||||
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
|
||||
#define PATTERN_CNTRL_ADDR_OFST (16)
|
||||
#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
|
||||
#define PATTERN_CNTRL_WR_OFST (0)
|
||||
#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST)
|
||||
#define PATTERN_CNTRL_RD_OFST (1)
|
||||
#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST)
|
||||
#define PATTERN_CNTRL_ADDR_OFST (16)
|
||||
#define PATTERN_CNTRL_ADDR_MSK (0x00001FFF << PATTERN_CNTRL_ADDR_OFST)
|
||||
|
||||
/* Pattern Limit RW regiser */
|
||||
#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LIMIT_REG (0x53 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_LIMIT_STRT_OFST (0)
|
||||
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
|
||||
#define PATTERN_LIMIT_STP_OFST (16)
|
||||
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
|
||||
#define PATTERN_LIMIT_STRT_OFST (0)
|
||||
#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
|
||||
#define PATTERN_LIMIT_STP_OFST (16)
|
||||
#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
|
||||
|
||||
/* Pattern Loop 0 Address RW regiser */
|
||||
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LOOP_0_ADDR_REG (0x54 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
|
||||
#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_0_ADDR_STRT_MSK \
|
||||
(0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
|
||||
|
||||
/* Pattern Loop 0 Iteration RW regiser */
|
||||
#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LOOP_0_ITERATION_REG (0x55 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Loop 1 Address RW regiser */
|
||||
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LOOP_1_ADDR_REG (0x56 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
|
||||
#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_1_ADDR_STRT_MSK \
|
||||
(0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
|
||||
|
||||
/* Pattern Loop 1 Iteration RW regiser */
|
||||
#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LOOP_1_ITERATION_REG (0x57 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Loop 2 Address RW regiser */
|
||||
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LOOP_2_ADDR_REG (0x58 << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
|
||||
#define PATTERN_LOOP_2_ADDR_STRT_MSK \
|
||||
(0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
|
||||
#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
|
||||
|
||||
/* Pattern Loop 2 Iteration RW regiser */
|
||||
#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_LOOP_2_ITERATION_REG (0x59 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Wait 0 RW regiser */
|
||||
#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_0_ADDR_REG (0x5A << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_WAIT_0_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
|
||||
//FIXME: is mask 3FF
|
||||
#define PATTERN_WAIT_0_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
|
||||
// FIXME: is mask 3FF
|
||||
|
||||
/* Pattern Wait 1 RW regiser */
|
||||
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_1_ADDR_REG (0x5B << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_WAIT_1_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
|
||||
#define PATTERN_WAIT_1_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
|
||||
|
||||
/* Pattern Wait 2 RW regiser */
|
||||
#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_2_ADDR_REG (0x5C << MEM_MAP_SHIFT)
|
||||
|
||||
#define PATTERN_WAIT_2_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
|
||||
#define PATTERN_WAIT_2_ADDR_OFST (0)
|
||||
#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
|
||||
|
||||
/* Samples RW register */
|
||||
#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
|
||||
#define SAMPLES_REG (0x5D << MEM_MAP_SHIFT)
|
||||
|
||||
#define SAMPLES_DIGITAL_OFST (0)
|
||||
#define SAMPLES_DIGITAL_MSK (0x0000FFFF << SAMPLES_DIGITAL_OFST)
|
||||
#define SAMPLES_ANALOG_OFST (16)
|
||||
#define SAMPLES_ANALOG_MSK (0x0000FFFF << SAMPLES_ANALOG_OFST)
|
||||
#define SAMPLES_DIGITAL_OFST (0)
|
||||
#define SAMPLES_DIGITAL_MSK (0x0000FFFF << SAMPLES_DIGITAL_OFST)
|
||||
#define SAMPLES_ANALOG_OFST (16)
|
||||
#define SAMPLES_ANALOG_MSK (0x0000FFFF << SAMPLES_ANALOG_OFST)
|
||||
|
||||
/** Power RW register */
|
||||
#define POWER_REG (0x5E << MEM_MAP_SHIFT)
|
||||
#define POWER_REG (0x5E << MEM_MAP_SHIFT)
|
||||
|
||||
#define POWER_ENBL_VLTG_RGLTR_OFST (16)
|
||||
#define POWER_ENBL_VLTG_RGLTR_MSK (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
|
||||
#define POWER_HV_INTERNAL_SLCT_OFST (31)
|
||||
#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
|
||||
#define POWER_ENBL_VLTG_RGLTR_OFST (16)
|
||||
#define POWER_ENBL_VLTG_RGLTR_MSK (0x0000001F << POWER_ENBL_VLTG_RGLTR_OFST)
|
||||
#define POWER_HV_INTERNAL_SLCT_OFST (31)
|
||||
#define POWER_HV_INTERNAL_SLCT_MSK (0x00000001 << POWER_HV_INTERNAL_SLCT_OFST)
|
||||
|
||||
/* Number of Words RW register TODO */
|
||||
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
|
||||
|
||||
#define NUMBER_OF_WORDS_REG (0x5F << MEM_MAP_SHIFT)
|
||||
|
||||
/* Delay 64 bit RW register. t = DLY x 50 ns. */
|
||||
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
|
||||
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
|
||||
#define DELAY_LSB_REG (0x60 << MEM_MAP_SHIFT)
|
||||
#define DELAY_MSB_REG (0x61 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Triggers 64 bit RW register */
|
||||
#define CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
|
||||
#define CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
|
||||
#define CYCLES_LSB_REG (0x62 << MEM_MAP_SHIFT)
|
||||
#define CYCLES_MSB_REG (0x63 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Frames 64 bit RW register */
|
||||
#define FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
|
||||
#define FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
|
||||
#define FRAMES_LSB_REG (0x64 << MEM_MAP_SHIFT)
|
||||
#define FRAMES_MSB_REG (0x65 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Period 64 bit RW register */
|
||||
#define PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
|
||||
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
|
||||
#define PERIOD_LSB_REG (0x66 << MEM_MAP_SHIFT)
|
||||
#define PERIOD_MSB_REG (0x67 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Period 64 bit RW register */
|
||||
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) // Not used in FW
|
||||
//#define EXPTIME_MSB_REG (0x69 << MEM_MAP_SHIFT) // Not used in FW
|
||||
//#define EXPTIME_LSB_REG (0x68 << MEM_MAP_SHIFT) //
|
||||
//Not used in FW #define EXPTIME_MSB_REG (0x69 <<
|
||||
//MEM_MAP_SHIFT) // Not used in FW
|
||||
|
||||
/* Gates 64 bit RW register */
|
||||
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used in FW
|
||||
//#define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) // Not used in FW
|
||||
//#define GATES_LSB_REG (0x6A << MEM_MAP_SHIFT) // Not used
|
||||
//in FW #define GATES_MSB_REG (0x6B << MEM_MAP_SHIFT) //
|
||||
//Not used in FW
|
||||
|
||||
/* Pattern IO Control 64 bit RW regiser
|
||||
* Each bit configured as output(1)/ input(0) */
|
||||
#define PATTERN_IO_CNTRL_LSB_REG (0x6C << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IO_CNTRL_MSB_REG (0x6D << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IO_CNTRL_LSB_REG (0x6C << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IO_CNTRL_MSB_REG (0x6D << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern IO Clock Control 64 bit RW regiser
|
||||
* When bit n enabled (1), clocked output for DIO[n] (T run clock)
|
||||
* When bit n disabled (0), Dio[n] driven by its pattern output */
|
||||
#define PATTERN_IO_CLK_CNTRL_LSB_REG (0x6E << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IO_CLK_CNTRL_MSB_REG (0x6F << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IO_CLK_CNTRL_LSB_REG (0x6E << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IO_CLK_CNTRL_MSB_REG (0x6F << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern In 64 bit RW register */
|
||||
#define PATTERN_IN_LSB_REG (0x70 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IN_MSB_REG (0x71 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IN_LSB_REG (0x70 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_IN_MSB_REG (0x71 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Wait Timer 0 64 bit RW register. t = PWT1 x T run clock */
|
||||
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x72 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x73 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_0_LSB_REG (0x72 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_0_MSB_REG (0x73 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Wait Timer 1 64 bit RW register. t = PWT2 x T run clock */
|
||||
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x74 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x75 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_1_LSB_REG (0x74 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_1_MSB_REG (0x75 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Pattern Wait Timer 2 64 bit RW register. t = PWT3 x T run clock */
|
||||
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_2_LSB_REG (0x76 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_WAIT_TIMER_2_MSB_REG (0x77 << MEM_MAP_SHIFT)
|
||||
|
||||
/* Readout enable RW register */
|
||||
#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
|
||||
|
||||
#define READOUT_10G_ENABLE_ANLG_OFST (0)
|
||||
#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
|
||||
#define READOUT_10G_ENABLE_DGTL_OFST (8)
|
||||
#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
|
||||
#define READOUT_10G_ENABLE_REG (0x79 << MEM_MAP_SHIFT)
|
||||
|
||||
#define READOUT_10G_ENABLE_ANLG_OFST (0)
|
||||
#define READOUT_10G_ENABLE_ANLG_MSK (0x000000FF << READOUT_10G_ENABLE_ANLG_OFST)
|
||||
#define READOUT_10G_ENABLE_DGTL_OFST (8)
|
||||
#define READOUT_10G_ENABLE_DGTL_MSK (0x00000001 << READOUT_10G_ENABLE_DGTL_OFST)
|
||||
|
||||
/* Digital Bit External Trigger RW register */
|
||||
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
|
||||
#define DBIT_EXT_TRG_REG (0x7B << MEM_MAP_SHIFT)
|
||||
|
||||
#define DBIT_EXT_TRG_SRC_OFST (0)
|
||||
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
|
||||
#define DBIT_EXT_TRG_OPRTN_MD_OFST (16)
|
||||
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
|
||||
#define DBIT_EXT_TRG_SRC_OFST (0)
|
||||
#define DBIT_EXT_TRG_SRC_MSK (0x0000003F << DBIT_EXT_TRG_SRC_OFST)
|
||||
#define DBIT_EXT_TRG_OPRTN_MD_OFST (16)
|
||||
#define DBIT_EXT_TRG_OPRTN_MD_MSK (0x00000001 << DBIT_EXT_TRG_OPRTN_MD_OFST)
|
||||
|
||||
/* Pin Delay 0 RW register */
|
||||
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
|
||||
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
|
||||
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST (0) //t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
|
||||
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK (0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
|
||||
// 1: load dynamic output settings, 0: trigger start of dynamic output delay configuration pn falling edge of ODT (output delay trigger) bit
|
||||
#define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
|
||||
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK (0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
|
||||
#define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL (1)
|
||||
#define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
|
||||
#define OUTPUT_DELAY_0_REG (0x7C << MEM_MAP_SHIFT)
|
||||
#define OUTPUT_DELAY_0_OTPT_STTNG_STEPS (25)
|
||||
#define OUTPUT_DELAY_0_OTPT_STTNG_OFST \
|
||||
(0) // t = OTPT_STTNG * 25 ps, max for Cyclone V = 775 ps
|
||||
#define OUTPUT_DELAY_0_OTPT_STTNG_MSK \
|
||||
(0x0000001F << OUTPUT_DELAY_0_OTPT_STTNG_OFST)
|
||||
// 1: load dynamic output settings, 0: trigger start of dynamic output delay
|
||||
// configuration pn falling edge of ODT (output delay trigger) bit
|
||||
#define OUTPUT_DELAY_0_OTPT_TRGGR_OFST (31)
|
||||
#define OUTPUT_DELAY_0_OTPT_TRGGR_MSK \
|
||||
(0x00000001 << OUTPUT_DELAY_0_OTPT_TRGGR_OFST)
|
||||
#define OUTPUT_DELAY_0_OTPT_TRGGR_LD_VAL (1)
|
||||
#define OUTPUT_DELAY_0_OTPT_TRGGR_STRT_VAL (0)
|
||||
|
||||
/* Pin Delay 1 RW register
|
||||
* Each bit configured as enable for dynamic output delay configuration */
|
||||
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
|
||||
#define PIN_DELAY_1_REG (0x7D << MEM_MAP_SHIFT)
|
||||
|
||||
/** Pattern Mask 64 bit RW regiser */
|
||||
#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_MASK_MSB_REG (0x81 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_MASK_LSB_REG (0x80 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_MASK_MSB_REG (0x81 << MEM_MAP_SHIFT)
|
||||
|
||||
/** Pattern Set 64 bit RW regiser */
|
||||
#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_SET_LSB_REG (0x82 << MEM_MAP_SHIFT)
|
||||
#define PATTERN_SET_MSB_REG (0x83 << MEM_MAP_SHIFT)
|
||||
|
||||
/** I2C Control register */
|
||||
#define I2C_TRANSFER_COMMAND_FIFO_REG (0x100 << MEM_MAP_SHIFT)
|
||||
#define I2C_RX_DATA_FIFO_REG (0x101 << MEM_MAP_SHIFT)
|
||||
#define I2C_CONTROL_REG (0x102 << MEM_MAP_SHIFT)
|
||||
#define I2C_STATUS_REG (0x105 << MEM_MAP_SHIFT)
|
||||
#define I2C_RX_DATA_FIFO_LEVEL_REG (0x107 << MEM_MAP_SHIFT)
|
||||
#define I2C_SCL_LOW_COUNT_REG (0x108 << MEM_MAP_SHIFT)
|
||||
#define I2C_SCL_HIGH_COUNT_REG (0x109 << MEM_MAP_SHIFT)
|
||||
#define I2C_SDA_HOLD_REG (0x10A << MEM_MAP_SHIFT)
|
||||
//fixme: upto 0x10f
|
||||
#define I2C_TRANSFER_COMMAND_FIFO_REG (0x100 << MEM_MAP_SHIFT)
|
||||
#define I2C_RX_DATA_FIFO_REG (0x101 << MEM_MAP_SHIFT)
|
||||
#define I2C_CONTROL_REG (0x102 << MEM_MAP_SHIFT)
|
||||
#define I2C_STATUS_REG (0x105 << MEM_MAP_SHIFT)
|
||||
#define I2C_RX_DATA_FIFO_LEVEL_REG (0x107 << MEM_MAP_SHIFT)
|
||||
#define I2C_SCL_LOW_COUNT_REG (0x108 << MEM_MAP_SHIFT)
|
||||
#define I2C_SCL_HIGH_COUNT_REG (0x109 << MEM_MAP_SHIFT)
|
||||
#define I2C_SDA_HOLD_REG (0x10A << MEM_MAP_SHIFT)
|
||||
// fixme: upto 0x10f
|
||||
|
||||
/* Round Robin */
|
||||
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)
|
||||
|
||||
|
||||
|
||||
#define RXR_ENDPOINT_START_REG (0x1000 << MEM_MAP_SHIFT)
|
||||
|
||||
226
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
Executable file → Normal file
226
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
Executable file → Normal file
@ -1,112 +1,158 @@
|
||||
#pragma once
|
||||
#include "sls_detector_defs.h"
|
||||
#include "RegisterDefs.h"
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#define MIN_REQRD_VRSN_T_RD_API 0x181130
|
||||
#define REQRD_FRMWR_VRSN 0x191127
|
||||
|
||||
#define MIN_REQRD_VRSN_T_RD_API 0x181130
|
||||
#define REQRD_FRMWR_VRSN 0x191127
|
||||
|
||||
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
|
||||
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
|
||||
|
||||
/* Struct Definitions */
|
||||
typedef struct udp_header_struct {
|
||||
uint32_t udp_destmac_msb;
|
||||
uint16_t udp_srcmac_msb;
|
||||
uint16_t udp_destmac_lsb;
|
||||
uint32_t udp_srcmac_lsb;
|
||||
uint8_t ip_tos;
|
||||
uint8_t ip_ihl: 4, ip_ver: 4;
|
||||
uint16_t udp_ethertype;
|
||||
uint16_t ip_identification;
|
||||
uint16_t ip_totallength;
|
||||
uint8_t ip_protocol;
|
||||
uint8_t ip_ttl;
|
||||
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
|
||||
uint16_t ip_srcip_msb;
|
||||
uint16_t ip_checksum;
|
||||
uint16_t ip_destip_msb;
|
||||
uint16_t ip_srcip_lsb;
|
||||
uint16_t udp_srcport;
|
||||
uint16_t ip_destip_lsb;
|
||||
uint16_t udp_checksum;
|
||||
uint16_t udp_destport;
|
||||
uint32_t udp_destmac_msb;
|
||||
uint16_t udp_srcmac_msb;
|
||||
uint16_t udp_destmac_lsb;
|
||||
uint32_t udp_srcmac_lsb;
|
||||
uint8_t ip_tos;
|
||||
uint8_t ip_ihl : 4, ip_ver : 4;
|
||||
uint16_t udp_ethertype;
|
||||
uint16_t ip_identification;
|
||||
uint16_t ip_totallength;
|
||||
uint8_t ip_protocol;
|
||||
uint8_t ip_ttl;
|
||||
uint16_t ip_fragmentoffset : 13, ip_flags : 3;
|
||||
uint16_t ip_srcip_msb;
|
||||
uint16_t ip_checksum;
|
||||
uint16_t ip_destip_msb;
|
||||
uint16_t ip_srcip_lsb;
|
||||
uint16_t udp_srcport;
|
||||
uint16_t ip_destip_lsb;
|
||||
uint16_t udp_checksum;
|
||||
uint16_t udp_destport;
|
||||
} udp_header;
|
||||
|
||||
#define IP_HEADER_SIZE (20)
|
||||
#define UDP_IP_HEADER_LENGTH_BYTES (28)
|
||||
#define IP_HEADER_SIZE (20)
|
||||
#define UDP_IP_HEADER_LENGTH_BYTES (28)
|
||||
|
||||
/* Enums */
|
||||
enum ADCINDEX {V_PWR_IO, V_PWR_A, V_PWR_B, V_PWR_C, V_PWR_D, I_PWR_IO, I_PWR_A, I_PWR_B, I_PWR_C, I_PWR_D, S_ADC0, S_ADC1, S_ADC2, S_ADC3, S_ADC4, S_ADC5, S_ADC6, S_ADC7, S_TMP};
|
||||
enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
|
||||
D10, D11, D12, D13, D14, D15, D16, D17,
|
||||
D_PWR_D, D_PWR_CHIP, D_PWR_C, D_PWR_B, D_PWR_A, D_PWR_IO};
|
||||
enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
|
||||
#define CLK_NAMES "run", "adc", "sync", "dbit"
|
||||
enum ADCINDEX {
|
||||
V_PWR_IO,
|
||||
V_PWR_A,
|
||||
V_PWR_B,
|
||||
V_PWR_C,
|
||||
V_PWR_D,
|
||||
I_PWR_IO,
|
||||
I_PWR_A,
|
||||
I_PWR_B,
|
||||
I_PWR_C,
|
||||
I_PWR_D,
|
||||
S_ADC0,
|
||||
S_ADC1,
|
||||
S_ADC2,
|
||||
S_ADC3,
|
||||
S_ADC4,
|
||||
S_ADC5,
|
||||
S_ADC6,
|
||||
S_ADC7,
|
||||
S_TMP
|
||||
};
|
||||
enum DACINDEX {
|
||||
D0,
|
||||
D1,
|
||||
D2,
|
||||
D3,
|
||||
D4,
|
||||
D5,
|
||||
D6,
|
||||
D7,
|
||||
D8,
|
||||
D9,
|
||||
D10,
|
||||
D11,
|
||||
D12,
|
||||
D13,
|
||||
D14,
|
||||
D15,
|
||||
D16,
|
||||
D17,
|
||||
D_PWR_D,
|
||||
D_PWR_CHIP,
|
||||
D_PWR_C,
|
||||
D_PWR_B,
|
||||
D_PWR_A,
|
||||
D_PWR_IO
|
||||
};
|
||||
enum CLKINDEX { RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS };
|
||||
#define CLK_NAMES "run", "adc", "sync", "dbit"
|
||||
|
||||
/* Hardware Definitions */
|
||||
#define NCHAN (36)
|
||||
#define NCHAN_ANALOG (32)
|
||||
#define NCHAN_DIGITAL (64)
|
||||
#define NCHIP (1)
|
||||
#define NDAC (24)
|
||||
#define NPWR (6)
|
||||
#define NDAC_ONLY (NDAC - NPWR)
|
||||
#define DYNAMIC_RANGE (16)
|
||||
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
|
||||
#define CLK_FREQ (156.25) /* MHz */
|
||||
#define I2C_POWER_VIO_DEVICE_ID (0x40)
|
||||
#define I2C_POWER_VA_DEVICE_ID (0x41)
|
||||
#define I2C_POWER_VB_DEVICE_ID (0x42)
|
||||
#define I2C_POWER_VC_DEVICE_ID (0x43)
|
||||
#define I2C_POWER_VD_DEVICE_ID (0x44)
|
||||
#define I2C_SHUNT_RESISTER_OHMS (0.005)
|
||||
#define NCHAN (36)
|
||||
#define NCHAN_ANALOG (32)
|
||||
#define NCHAN_DIGITAL (64)
|
||||
#define NCHIP (1)
|
||||
#define NDAC (24)
|
||||
#define NPWR (6)
|
||||
#define NDAC_ONLY (NDAC - NPWR)
|
||||
#define DYNAMIC_RANGE (16)
|
||||
#define NUM_BYTES_PER_PIXEL (DYNAMIC_RANGE / 8)
|
||||
#define CLK_FREQ (156.25) /* MHz */
|
||||
#define I2C_POWER_VIO_DEVICE_ID (0x40)
|
||||
#define I2C_POWER_VA_DEVICE_ID (0x41)
|
||||
#define I2C_POWER_VB_DEVICE_ID (0x42)
|
||||
#define I2C_POWER_VC_DEVICE_ID (0x43)
|
||||
#define I2C_POWER_VD_DEVICE_ID (0x44)
|
||||
#define I2C_SHUNT_RESISTER_OHMS (0.005)
|
||||
|
||||
/** Default Parameters */
|
||||
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
|
||||
#define DEFAULT_NUM_SAMPLES (1)
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
#define DEFAULT_EXPTIME (0)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DEFAULT_PERIOD (1 * 1000 * 1000) //ns
|
||||
#define DEFAULT_DELAY (0)
|
||||
#define DEFAULT_HIGH_VOLTAGE (0)
|
||||
#define DEFAULT_VLIMIT (-100)
|
||||
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
|
||||
#define DEFAULT_TX_UDP_PORT (0x7e9a)
|
||||
#define DEFAULT_RUN_CLK (200) // 40
|
||||
#define DEFAULT_ADC_CLK (40) // 20
|
||||
#define DEFAULT_SYNC_CLK (40) // 20
|
||||
#define DEFAULT_DBIT_CLK (200)
|
||||
#define DEFAULT_DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
|
||||
#define DEFAULT_NUM_SAMPLES (1)
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
#define DEFAULT_EXPTIME (0)
|
||||
#define DEFAULT_NUM_CYCLES (1)
|
||||
#define DEFAULT_PERIOD (1 * 1000 * 1000) // ns
|
||||
#define DEFAULT_DELAY (0)
|
||||
#define DEFAULT_HIGH_VOLTAGE (0)
|
||||
#define DEFAULT_VLIMIT (-100)
|
||||
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
|
||||
#define DEFAULT_TX_UDP_PORT (0x7e9a)
|
||||
#define DEFAULT_RUN_CLK (200) // 40
|
||||
#define DEFAULT_ADC_CLK (40) // 20
|
||||
#define DEFAULT_SYNC_CLK (40) // 20
|
||||
#define DEFAULT_DBIT_CLK (200)
|
||||
|
||||
#define HIGHVOLTAGE_MIN (60)
|
||||
#define HIGHVOLTAGE_MAX (200) // min dac val
|
||||
#define DAC_MIN_MV (0)
|
||||
#define DAC_MAX_MV (2500)
|
||||
#define VCHIP_MIN_MV (1673)
|
||||
#define VCHIP_MAX_MV (2668) // min dac val
|
||||
#define POWER_RGLTR_MIN (636)
|
||||
#define POWER_RGLTR_MAX (2638) // min dac val (not vchip-max) because of dac conversions
|
||||
#define VCHIP_POWER_INCRMNT (200)
|
||||
#define VIO_MIN_MV (1200) // for fpga to function
|
||||
#define HIGHVOLTAGE_MIN (60)
|
||||
#define HIGHVOLTAGE_MAX (200) // min dac val
|
||||
#define DAC_MIN_MV (0)
|
||||
#define DAC_MAX_MV (2500)
|
||||
#define VCHIP_MIN_MV (1673)
|
||||
#define VCHIP_MAX_MV (2668) // min dac val
|
||||
#define POWER_RGLTR_MIN (636)
|
||||
#define POWER_RGLTR_MAX \
|
||||
(2638) // min dac val (not vchip-max) because of dac conversions
|
||||
#define VCHIP_POWER_INCRMNT (200)
|
||||
#define VIO_MIN_MV (1200) // for fpga to function
|
||||
|
||||
/* Defines in the Firmware */
|
||||
#define MAX_PATTERN_LENGTH (0x2000)
|
||||
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
|
||||
#define MAX_PHASE_SHIFTS_STEPS (8)
|
||||
#define MAX_PATTERN_LENGTH (0x2000)
|
||||
#define DIGITAL_IO_DELAY_MAXIMUM_PS \
|
||||
((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * \
|
||||
OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
|
||||
#define MAX_PHASE_SHIFTS_STEPS (8)
|
||||
|
||||
#define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
|
||||
#define WAIT_TIME_US_PLL (10 * 1000)
|
||||
#define WAIT_TIME_US_STP_ACQ (100)
|
||||
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
|
||||
#define WAIT_TIME_PATTERN_READ (10)
|
||||
#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
|
||||
#define WAIT_TME_US_FR_ACQDONE_REG \
|
||||
(100) // wait time in us after acquisition done to ensure there is no data
|
||||
// in fifo
|
||||
#define WAIT_TIME_US_PLL (10 * 1000)
|
||||
#define WAIT_TIME_US_STP_ACQ (100)
|
||||
#define WAIT_TIME_CONFIGURE_MAC (2 * 1000 * 1000)
|
||||
#define WAIT_TIME_PATTERN_READ (10)
|
||||
#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
|
||||
|
||||
/* MSB & LSB DEFINES */
|
||||
#define MSB_OF_64_BIT_REG_OFST (32)
|
||||
#define LSB_OF_64_BIT_REG_OFST (0)
|
||||
#define BIT32_MSK (0xFFFFFFFF)
|
||||
#define BIT16_MASK (0xFFFF)
|
||||
|
||||
#define MAXIMUM_ADC_CLK (65)
|
||||
#define PLL_VCO_FREQ_MHZ (800)
|
||||
#define MSB_OF_64_BIT_REG_OFST (32)
|
||||
#define LSB_OF_64_BIT_REG_OFST (0)
|
||||
#define BIT32_MSK (0xFFFFFFFF)
|
||||
#define BIT16_MASK (0xFFFF)
|
||||
|
||||
#define MAXIMUM_ADC_CLK (65)
|
||||
#define PLL_VCO_FREQ_MHZ (800)
|
||||
|
||||
Reference in New Issue
Block a user