Moench rw3 (#745)

* moench, removed chip version, filter resistor, filter cells, currentsoures, gain mode, setttings(modes), dbitphase, maxdbitphase, autocompdisable, comparatordisabletime, made acq start and stop a pulse, removed unused registers

* added parallel command

* remove gain plot for moench

* moench: updated adc invert val

* moench: update adcoffset to 0xf and adcphase to 140 degrees

* removed sync clock in moench

* updated min fw version

* removing config file in moench server
This commit is contained in:
2023-05-25 11:00:23 +02:00
committed by GitHub
parent 0a7fd0a51a
commit 65b8c9c5c1
30 changed files with 286 additions and 1216 deletions

View File

@@ -127,7 +127,7 @@ uint32_t ALTERA_PLL_Cntrl_Reg = 0x0;
uint32_t ALTERA_PLL_Param_Reg = 0x0;
uint32_t ALTERA_PLL_Cntrl_RcnfgPrmtrRstMask = 0x0;
uint32_t ALTERA_PLL_Cntrl_WrPrmtrMask = 0x0;
#if defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(JUNGFRAUD)
uint32_t ALTERA_PLL_Cntrl_DBIT_PLL_WrPrmtrMask = 0x0;
int ALTERA_PLL_Cntrl_DBIT_ClkIndex = 0;
@@ -136,7 +136,7 @@ uint32_t ALTERA_PLL_Cntrl_PLLRstMask = 0x0;
uint32_t ALTERA_PLL_Cntrl_AddrMask = 0x0;
int ALTERA_PLL_Cntrl_AddrOfst = 0;
#if defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(JUNGFRAUD)
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
int aofst, uint32_t wd2msk, int clk2Index) {
@@ -201,7 +201,7 @@ void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,
reg, val, useSecondWRMask));
uint32_t wrmask = ALTERA_PLL_Cntrl_WrPrmtrMask;
#if defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(JUNGFRAUD)
if (useSecondWRMask) {
wrmask = ALTERA_PLL_Cntrl_DBIT_PLL_WrPrmtrMask;
}
@@ -252,7 +252,7 @@ void ALTERA_PLL_SetPhaseShift(int32_t phase, int clkIndex, int pos) {
LOG(logDEBUG1, ("C%d phase word:0x%08x\n", clkIndex, value));
int useSecondWR = 0;
#if defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(JUNGFRAUD)
if (clkIndex == ALTERA_PLL_Cntrl_DBIT_ClkIndex) {
useSecondWR = 1;
}