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Moench rw3 (#745)

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* moench, removed chip version, filter resistor, filter cells, currentsoures, gain mode, setttings(modes), dbitphase, maxdbitphase, autocompdisable, comparatordisabletime, made acq start and stop a pulse, removed unused registers

* added parallel command

* remove gain plot for moench

* moench: updated adc invert val

* moench: update adcoffset to 0xf and adcphase to 140 degrees

* removed sync clock in moench

* updated min fw version

* removing config file in moench server
This commit is contained in:
maliakal_d
2023-05-25 11:00:23 +02:00
committed by GitHub
parent 0a7fd0a51a
commit 65b8c9c5c1
30 changed files with 286 additions and 1216 deletions
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9
slsDetectorServers/slsDetectorServer/include/ALTERA_PLL.h
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@ -4,7 +4,7 @@
#include <inttypes.h>
#if defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(JUNGFRAUD)
/**
* Set Defines
* @param creg control register
@ -14,9 +14,8 @@
* @param prmsk pll reset mask
* @param amsk address mask
* @param aofst address offset
* @param wd2msk write parameter mask for pll for dbit clock (Jungfrau/moench
* only)
* @param clk2Index clkIndex of second pll (Jungfrau/moench only)
* @param wd2msk write parameter mask for pll for dbit clock (Jungfrau only)
* @param clk2Index clkIndex of second pll (Jungfrau only)
*/
void ALTERA_PLL_SetDefines(uint32_t creg, uint32_t preg, uint32_t rprmsk,
uint32_t wpmsk, uint32_t prmsk, uint32_t amsk,
@ -51,7 +50,7 @@ void ALTERA_PLL_ResetPLLAndReconfiguration();
* Set PLL Reconfig register
* @param reg register
* @param val value
* @param useDefaultWRMask only jungfrau/moench for dbit clk (clkindex1, use
* @param useDefaultWRMask only jungfrau for dbit clk (clkindex1, use
* second WR mask)
*/
void ALTERA_PLL_SetPllReconfigReg(uint32_t reg, uint32_t val,