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gotthard2: change default clock divider of readout clocks 1 and 2 from 8 to 6
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@ -46,8 +46,8 @@
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#define DEFAULT_CURRENT_SOURCE (0)
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#define DEFAULT_TIMING_SOURCE (TIMING_INTERNAL)
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#define DEFAULT_READOUT_C0 (8) //(108333336) // rdo_clk, 108 MHz
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#define DEFAULT_READOUT_C1 (8) //(108333336) // rdo_x2_clk, 108 MHz
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#define DEFAULT_READOUT_C0 (6) //(144444448) // rdo_clk, 144 MHz
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#define DEFAULT_READOUT_C1 (6) //(144444448) // rdo_x2_clk, 144 MHz
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#define DEFAULT_SYSTEM_C0 (5) //(144444448) // run_clk, 144 MHz
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#define DEFAULT_SYSTEM_C1 (10) //(72222224) // chip_clk, 72 MHz
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#define DEFAULT_SYSTEM_C2 (5) //(144444448) // sync_clk, 144 MHz
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