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ctb moench server update: (fw update): det id changed, status reg looks at anyfifofull instead of somefifofull, datapresent looks at corresponding analog/digital fifo empty, usleep after read strobe to sync different clock

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This commit is contained in:
maliakal_d 2019-03-07 17:36:35 +01:00
parent 999a2f4d15
commit 658438df3b
11 changed files with 141 additions and 132 deletions
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13
slsDetectorServers/ctbDetectorServer/RegisterDefs.h
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@ -10,7 +10,7 @@
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST) #define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24) #define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST) #define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_CTB_VAL ((0x3 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK) #define FPGA_VERSION_DTCTR_TYP_CTB_VAL ((0x4 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
/* Fix pattern RO register */ /* Fix pattern RO register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT) #define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
@ -24,8 +24,8 @@
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST) #define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1) #define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST) #define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
//#define STATUS_FF_TST_BSY_OFST (2) #define STATUS_ANY_FF_FLL_OFST (2)
//#define STATUS_FF_TST_BSY_MSK (0x00000001 << STATUS_FF_TST_BSY_OFST) #define STATUS_ANY_FF_FLL_MSK (0x00000001 << STATUS_ANY_FF_FLL_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3) #define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST) #define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4) #define STATUS_DLY_BFR_OFST (4)
@ -58,7 +58,7 @@
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST) #define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24) #define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST) #define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x6FFFF) #define STATUS_IDLE_MSK (0x677FF)
/* Look at me RO register TODO */ /* Look at me RO register TODO */
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT) #define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
@ -93,6 +93,7 @@
/* FIFO Empty RO register TODO */ /* FIFO Empty RO register TODO */
#define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT) #define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT)
#define FIFO_EMPTY_ALL_EMPTY_MSK (0xFFFFFFFF)
/* FIFO Full RO register TODO */ /* FIFO Full RO register TODO */
#define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT) #define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT)
@ -175,6 +176,10 @@
/* FIFO Digital In Status RO register */ /* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT) #define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
/* FIFO Digital In 64 bit RO register */ /* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT) #define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)

8
slsDetectorServers/ctbDetectorServer/gitInfo.txt
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@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/ctbDetectorServer Path: slsDetectorPackage/slsDetectorServers/ctbDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: ceb515d517baf2a6e3590013fd7550186d2906b8 Repsitory UUID: 999a2f4d154ef8e61458c8f0de91d1fd3dfab981
Revision: 33 Revision: 36
Branch: refactor Branch: refactor
Last Changed Author: GitHub_GitHub Last Changed Author: GitHub_GitHub
Last Changed Rev: 4377 Last Changed Rev: 4385
Last Changed Date: 2019-03-06 09:17:39.000000002 +0100 ./RegisterDefs.h Last Changed Date: 2019-03-07 17:06:52.000000002 +0100 ./RegisterDefs.h

6
slsDetectorServers/ctbDetectorServer/gitInfoCtb.h
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@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git" #define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "ceb515d517baf2a6e3590013fd7550186d2906b8" #define GITREPUUID "999a2f4d154ef8e61458c8f0de91d1fd3dfab981"
#define GITAUTH "GitHub_GitHub" #define GITAUTH "GitHub_GitHub"
#define GITREV 0x4377 #define GITREV 0x4385
#define GITDATE 0x20190306 #define GITDATE 0x20190307
#define GITBRANCH "refactor" #define GITBRANCH "refactor"

60
slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
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@ -2174,8 +2174,9 @@ enum runStatus getRunStatus(){
FILE_LOG(logINFO, ("Status Register: %08x\n",retval)); FILE_LOG(logINFO, ("Status Register: %08x\n",retval));
// error // error
if (retval & STATUS_SM_FF_FLL_MSK) { //if (retval & STATUS_SM_FF_FLL_MSK) { This bit is high when a analog fifo is full Or when external stop
FILE_LOG(logINFORED, ("Status: Error (Some fifo full)\n")); if (retval & STATUS_ANY_FF_FLL_MSK) { // if adc or digital fifo is full
FILE_LOG(logINFORED, ("Status: Error (Any fifo full)\n"));
return ERROR; return ERROR;
} }
@ -2204,14 +2205,6 @@ enum runStatus getRunStatus(){
} }
/* until Carlos updates firmware
if (digitalEnable && !analogEnable) {
if (retval & STATUS_ALL_FF_EMPTY_MSK) {
FILE_LOG(logINFOBLUE, ("Status: Transmitting (All fifo empty)\n"));
return TRANSMITTING;
}
}*/
if (! (retval & STATUS_IDLE_MSK)) { if (! (retval & STATUS_IDLE_MSK)) {
FILE_LOG(logINFOBLUE, ("Status: Idle\n")); FILE_LOG(logINFOBLUE, ("Status: Idle\n"));
return IDLE; return IDLE;
@ -2303,6 +2296,8 @@ void readSample(int ns) {
// read strobe to all analog fifos // read strobe to all analog fifos
bus_w(addr, bus_r(addr) | DUMMY_ANLG_FIFO_RD_STRBE_MSK); bus_w(addr, bus_r(addr) | DUMMY_ANLG_FIFO_RD_STRBE_MSK);
bus_w(addr, bus_r(addr) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK)); bus_w(addr, bus_r(addr) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK));
// wait as it is connected directly to fifo running on a different clock
usleep(WAIT_TIME_FIFO_RD_STROBE);
// loop through all channels // loop through all channels
int ich = 0; int ich = 0;
@ -2337,6 +2332,8 @@ void readSample(int ns) {
// read strobe to digital fifo // read strobe to digital fifo
bus_w(addr, bus_r(addr) | DUMMY_DGTL_FIFO_RD_STRBE_MSK); bus_w(addr, bus_r(addr) | DUMMY_DGTL_FIFO_RD_STRBE_MSK);
bus_w(addr, bus_r(addr) & (~DUMMY_DGTL_FIFO_RD_STRBE_MSK)); bus_w(addr, bus_r(addr) & (~DUMMY_DGTL_FIFO_RD_STRBE_MSK));
// wait as it is connected directly to fifo running on a different clock
usleep(WAIT_TIME_FIFO_RD_STROBE);
// read fifo and write it to current position of data pointer // read fifo and write it to current position of data pointer
*((uint64_t*)now_ptr) = get64BitReg(FIFO_DIN_LSB_REG, FIFO_DIN_MSB_REG); *((uint64_t*)now_ptr) = get64BitReg(FIFO_DIN_LSB_REG, FIFO_DIN_MSB_REG);
@ -2344,21 +2341,36 @@ void readSample(int ns) {
} }
} }
uint32_t checkDataInFifo() {
uint32_t dataPresent = 0;
if (analogEnable) {
uint32_t analogFifoEmpty = bus_r(FIFO_EMPTY_REG);
FILE_LOG(logDEBUG2, ("Analog Fifo Empty (32 channels): 0x%x\n", analogFifoEmpty));
dataPresent = (~analogFifoEmpty);
}
if (!dataPresent && digitalEnable) {
int digitalFifoEmpty = ((bus_r(FIFO_DIN_STATUS_REG) & FIFO_DIN_STATUS_FIFO_EMPTY_MSK) >> FIFO_DIN_STATUS_FIFO_EMPTY_OFST);
FILE_LOG(logDEBUG2, ("Digital Fifo Empty: %d\n",digitalFifoEmpty));
dataPresent = (digitalFifoEmpty ? 0 : 1);
}
FILE_LOG(logDEBUG2, ("Data in Fifo :0x%x\n", dataPresent));
return dataPresent;
}
// only called for first sample // only called for first sample
int checkDataPresent() { int checkFifoForEndOfAcquisition() {
uint32_t dataPresent = bus_r(LOOK_AT_ME_REG); uint32_t dataPresent = checkDataInFifo();
FILE_LOG(logDEBUG2, ("LookatMe:0x%x, status:0x%x\t, fifodinstatus:0x%x\n", FILE_LOG(logDEBUG2, ("status:0x%x\n", bus_r(STATUS_REG)));
dataPresent,
bus_r(STATUS_REG), // as long as no data
bus_r(FIFO_DIN_STATUS_REG)));
// as long as fifo empty (keep checking)
while (!dataPresent) { while (!dataPresent) {
// acquisition done // acquisition done
if (!runBusy()) { if (!runBusy()) {
usleep(WAIT_TME_US_FR_LK_AT_ME_REG); // wait to be sure there is no data in fifo
dataPresent = bus_r(LOOK_AT_ME_REG); usleep(WAIT_TME_US_FR_ACQDONE_REG);
// still no data // still no data
if (!dataPresent) { if (!checkDataInFifo()) {
FILE_LOG(logINFO, ("Acquisition Finished (State: 0x%08x), " FILE_LOG(logINFO, ("Acquisition Finished (State: 0x%08x), "
"no frame found .\n", bus_r(STATUS_REG))); "no frame found .\n", bus_r(STATUS_REG)));
return FAIL; return FAIL;
@ -2368,10 +2380,10 @@ int checkDataPresent() {
break; break;
} }
} }
// check if fifo empty again // check if data in fifo again
dataPresent = bus_r(LOOK_AT_ME_REG); dataPresent = checkDataInFifo();
} }
FILE_LOG(logDEBUG2, ("Got data, Lookatme:0x%x\n", dataPresent)); FILE_LOG(logDEBUG2, ("Got data :0x%x\n", dataPresent));
return OK; return OK;
} }
@ -2381,7 +2393,7 @@ int readFrameFromFifo() {
now_ptr = ramValues; now_ptr = ramValues;
// no data for this frame // no data for this frame
if (checkDataPresent() == FAIL) { if (checkFifoForEndOfAcquisition() == FAIL) {
return FAIL; return FAIL;
} }

3
slsDetectorServers/ctbDetectorServer/slsDetectorServer_defs.h
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@ -82,11 +82,12 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS) #define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define WAIT_TME_US_FR_LK_AT_ME_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo #define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TIME_US_PLL (10 * 1000) #define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100) #define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (500 * 1000) #define WAIT_TIME_CONFIGURE_MAC (500 * 1000)
#define WAIT_TIME_PATTERN_READ (10) #define WAIT_TIME_PATTERN_READ (10)
#define WAIT_TIME_FIFO_RD_STROBE (10)
/* MSB & LSB DEFINES */ /* MSB & LSB DEFINES */
#define MSB_OF_64_BIT_REG_OFST (32) #define MSB_OF_64_BIT_REG_OFST (32)

13
slsDetectorServers/moenchDetectorServer/RegisterDefs.h
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@ -11,7 +11,7 @@
#define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST) #define FPGA_VERSION_BRD_RVSN_MSK (0x00FFFFFF << FPGA_VERSION_BRD_RVSN_OFST)
#define FPGA_VERSION_DTCTR_TYP_OFST (24) #define FPGA_VERSION_DTCTR_TYP_OFST (24)
#define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST) #define FPGA_VERSION_DTCTR_TYP_MSK (0x000000FF << FPGA_VERSION_DTCTR_TYP_OFST)
#define FPGA_VERSION_DTCTR_TYP_MOENCH_VAL ((0x2 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK) #define FPGA_VERSION_DTCTR_TYP_MOENCH_VAL ((0x5 << FPGA_VERSION_DTCTR_TYP_OFST) & FPGA_VERSION_DTCTR_TYP_MSK)
/* Fix pattern RO register */ /* Fix pattern RO register */
#define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT) #define FIX_PATT_REG (0x01 << MEM_MAP_SHIFT)
@ -25,8 +25,8 @@
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST) #define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1) #define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST) #define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
//#define STATUS_FF_TST_BSY_OFST (2) #define STATUS_ANY_FF_FLL_OFST (2)
//#define STATUS_FF_TST_BSY_MSK (0x00000001 << STATUS_FF_TST_BSY_OFST) #define STATUS_ANY_FF_FLL_MSK (0x00000001 << STATUS_ANY_FF_FLL_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3) #define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST) #define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4) #define STATUS_DLY_BFR_OFST (4)
@ -59,7 +59,7 @@
#define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST) #define STATUS_PLL_PHS_DN_MSK (0x00000001 << STATUS_PLL_PHS_DN_OFST)
#define STATUS_PT_CNTRL_STTS_OFF_OFST (24) #define STATUS_PT_CNTRL_STTS_OFF_OFST (24)
#define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST) #define STATUS_PT_CNTRL_STTS_OFF_MSK (0x000000FF << STATUS_PT_CNTRL_STTS_OFF_OFST)
#define STATUS_IDLE_MSK (0x6FFFF) #define STATUS_IDLE_MSK (0x677FF)
/* Look at me RO register TODO */ /* Look at me RO register TODO */
#define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT) #define LOOK_AT_ME_REG (0x03 << MEM_MAP_SHIFT)
@ -94,6 +94,7 @@
/* FIFO Empty RO register TODO */ /* FIFO Empty RO register TODO */
#define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT) #define FIFO_EMPTY_REG (0x08 << MEM_MAP_SHIFT)
#define FIFO_EMPTY_ALL_EMPTY_MSK (0xFFFFFFFF)
/* FIFO Full RO register TODO */ /* FIFO Full RO register TODO */
#define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT) #define FIFO_FULL_REG (0x09 << MEM_MAP_SHIFT)
@ -176,6 +177,10 @@
/* FIFO Digital In Status RO register */ /* FIFO Digital In Status RO register */
#define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT) #define FIFO_DIN_STATUS_REG (0x3B << MEM_MAP_SHIFT)
#define FIFO_DIN_STATUS_FIFO_FULL_OFST (30)
#define FIFO_DIN_STATUS_FIFO_FULL_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_FULL_OFST)
#define FIFO_DIN_STATUS_FIFO_EMPTY_OFST (31)
#define FIFO_DIN_STATUS_FIFO_EMPTY_MSK (0x00000001 << FIFO_DIN_STATUS_FIFO_EMPTY_OFST)
/* FIFO Digital In 64 bit RO register */ /* FIFO Digital In 64 bit RO register */
#define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT) #define FIFO_DIN_LSB_REG (0x3C << MEM_MAP_SHIFT)

10
slsDetectorServers/moenchDetectorServer/gitInfo.txt
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@ -1,9 +1,9 @@
Path: slsDetectorPackage/slsDetectorServers/moenchDetectorServer Path: slsDetectorPackage/slsDetectorServers/moenchDetectorServer
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
Repsitory UUID: 0765b330f116fd47b84c065d89789f4996573f23 Repsitory UUID: 999a2f4d154ef8e61458c8f0de91d1fd3dfab981
Revision: 13 Revision: 14
Branch: refactor Branch: refactor
Last Changed Author: Dhanya_Thattil Last Changed Author: GitHub_GitHub
Last Changed Rev: 4381 Last Changed Rev: 4385
Last Changed Date: 2019-03-06 13:42:29.000000002 +0100 ./RegisterDefs.h Last Changed Date: 2019-03-07 17:06:49.000000002 +0100 ./RegisterDefs.h

8
slsDetectorServers/moenchDetectorServer/gitInfoMoench.h
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@ -1,6 +1,6 @@
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git" #define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
#define GITREPUUID "0765b330f116fd47b84c065d89789f4996573f23" #define GITREPUUID "999a2f4d154ef8e61458c8f0de91d1fd3dfab981"
#define GITAUTH "Dhanya_Thattil" #define GITAUTH "GitHub_GitHub"
#define GITREV 0x4381 #define GITREV 0x4385
#define GITDATE 0x20190306 #define GITDATE 0x20190307
#define GITBRANCH "refactor" #define GITBRANCH "refactor"

84
slsDetectorServers/moenchDetectorServer/slsDetectorFunctionList.c
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@ -51,8 +51,6 @@ int highvoltage = 0;
ROI rois[MAX_ROIS]; ROI rois[MAX_ROIS];
int nROI = 0; int nROI = 0;
uint32_t adcDisableMask = 0; uint32_t adcDisableMask = 0;
int analogEnable = 1;
int digitalEnable = 0;
int nSamples = 1; int nSamples = 1;
char volatile *now_ptr = 0; char volatile *now_ptr = 0;
@ -476,8 +474,6 @@ void setupDetector() {
highvoltage = 0; highvoltage = 0;
nROI = 0; nROI = 0;
adcDisableMask = 0; adcDisableMask = 0;
analogEnable = 1;
digitalEnable = 0;
nSamples = 1; nSamples = 1;
now_ptr = 0; now_ptr = 0;
@ -589,17 +585,14 @@ void updateDataBytes() {
int getChannels() { int getChannels() {
int nchans = 0; int nchans = 0;
if (analogEnable) { nchans += NCHAN;
nchans += NCHAN_ANALOG;
// remove the channels disabled // remove the channels disabled
int ichan = 0; int ichan = 0;
for (ichan = 0; ichan < NCHAN_ANALOG; ++ichan) { for (ichan = 0; ichan < NCHAN; ++ichan) {
if (adcDisableMask & (1 << ichan)) if (adcDisableMask & (1 << ichan))
--nchans; --nchans;
} }
}
if (digitalEnable)
nchans += NCHAN_DIGITAL;
FILE_LOG(logINFO, ("\tNumber of Channels calculated: %d\n", nchans)) FILE_LOG(logINFO, ("\tNumber of Channels calculated: %d\n", nchans))
return nchans; return nchans;
} }
@ -670,7 +663,7 @@ ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret) {
// for the roi specified // for the roi specified
for (ich = arg[iroi].xmin; ich <= arg[iroi].xmax; ++ich) { for (ich = arg[iroi].xmin; ich <= arg[iroi].xmax; ++ich) {
// valid channel (disable) // valid channel (disable)
if (ich >= 0 && ich < NCHAN_ANALOG) if (ich >= 0 && ich < NCHAN)
adcDisableMask &= ~(1 << ich); adcDisableMask &= ~(1 << ich);
FILE_LOG(logDEBUG1, ("%d: ich:%d adcDisableMask:0x%08x\n", FILE_LOG(logDEBUG1, ("%d: ich:%d adcDisableMask:0x%08x\n",
@ -690,7 +683,7 @@ ROI* setROI(int n, ROI arg[], int *retvalsize, int *ret) {
if (adcDisableMask) { if (adcDisableMask) {
int ich = 0; int ich = 0;
// loop through channels // loop through channels
for (ich = 0; ich < NCHAN_ANALOG; ++ich) { for (ich = 0; ich < NCHAN; ++ich) {
// channel disabled // channel disabled
if ((~adcDisableMask) & (1 << ich)) { if ((~adcDisableMask) & (1 << ich)) {
// first channel // first channel
@ -1815,8 +1808,9 @@ enum runStatus getRunStatus(){
FILE_LOG(logINFO, ("Status Register: %08x\n",retval)); FILE_LOG(logINFO, ("Status Register: %08x\n",retval));
// error // error
if (retval & STATUS_SM_FF_FLL_MSK) { //if (retval & STATUS_SM_FF_FLL_MSK) { This bit is high when a analog fifo is full Or when external stop
FILE_LOG(logINFORED, ("Status: Error (Some fifo full)\n")); if (retval & STATUS_ANY_FF_FLL_MSK) { // if adc fifo is full
FILE_LOG(logINFORED, ("Status: Error (Any fifo full)\n"));
return ERROR; return ERROR;
} }
@ -1844,13 +1838,6 @@ enum runStatus getRunStatus(){
return TRANSMITTING; return TRANSMITTING;
} }
/* until Carlos updates firmware
if (digitalEnable && !analogEnable) {
if (retval & STATUS_ALL_FF_EMPTY_MSK) {
FILE_LOG(logINFOBLUE, ("Status: Transmitting (All fifo empty)\n"));
return TRANSMITTING;
}
}*/
if (! (retval & STATUS_IDLE_MSK)) { if (! (retval & STATUS_IDLE_MSK)) {
FILE_LOG(logINFOBLUE, ("Status: Idle\n")); FILE_LOG(logINFOBLUE, ("Status: Idle\n"));
@ -1926,7 +1913,7 @@ void readFrame(int *ret, char *mess) {
} }
void unsetFifoReadStrobes() { void unsetFifoReadStrobes() {
bus_w(DUMMY_REG, bus_r(DUMMY_REG) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK) & (~DUMMY_DGTL_FIFO_RD_STRBE_MSK)); bus_w(DUMMY_REG, bus_r(DUMMY_REG) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK));
} }
void readSample(int ns) { void readSample(int ns) {
@ -1939,15 +1926,16 @@ void readSample(int ns) {
uint32_t fifoAddr = FIFO_DATA_REG; uint32_t fifoAddr = FIFO_DATA_REG;
// read adcs // read adcs
if (analogEnable) {
// read strobe to all analog fifos // read strobe to all analog fifos
bus_w(addr, bus_r(addr) | DUMMY_ANLG_FIFO_RD_STRBE_MSK); bus_w(addr, bus_r(addr) | DUMMY_ANLG_FIFO_RD_STRBE_MSK);
bus_w(addr, bus_r(addr) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK)); bus_w(addr, bus_r(addr) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK));
// wait as it is connected directly to fifo running on a different clock
usleep(WAIT_TIME_FIFO_RD_STROBE);
// loop through all channels // loop through all channels
int ich = 0; int ich = 0;
for (ich = 0; ich < NCHAN_ANALOG; ++ich) { for (ich = 0; ich < NCHAN; ++ich) {
// if channel is in ROI // if channel is in ROI
if ((1 << ich) & ~(adcDisableMask)) { if ((1 << ich) & ~(adcDisableMask)) {
@ -1971,36 +1959,32 @@ void readSample(int ns) {
now_ptr += 2; now_ptr += 2;
} }
} }
} }
// read digital output uint32_t checkDataInFifo() {
if (digitalEnable) { uint32_t dataPresent = 0;
uint32_t analogFifoEmpty = bus_r(FIFO_EMPTY_REG);
// read strobe to digital fifo FILE_LOG(logDEBUG2, ("Analog Fifo Empty (32 channels): 0x%x\n",analogFifoEmpty));
bus_w(addr, bus_r(addr) | DUMMY_DGTL_FIFO_RD_STRBE_MSK); dataPresent = (~analogFifoEmpty);
bus_w(addr, bus_r(addr) & (~DUMMY_DGTL_FIFO_RD_STRBE_MSK)); FILE_LOG(logDEBUG2, ("Data in Fifo :0x%x\n", dataPresent));
return dataPresent;
// read fifo and write it to current position of data pointer
*((uint64_t*)now_ptr) = get64BitReg(FIFO_DIN_LSB_REG, FIFO_DIN_MSB_REG);
now_ptr += 8;
}
} }
// only called for first sample // only called for first sample
int checkDataPresent() { int checkFifoForEndOfAcquisition() {
uint32_t dataPresent = bus_r(LOOK_AT_ME_REG); uint32_t dataPresent = checkDataInFifo();
FILE_LOG(logDEBUG2, ("LookatMe:0x%x, status:0x%x\t, fifodinstatus:0x%x\n", FILE_LOG(logDEBUG2, ("status:0x%x\n", bus_r(STATUS_REG)));
dataPresent,
bus_r(STATUS_REG), // as long as no data
bus_r(FIFO_DIN_STATUS_REG)));
// as long as fifo empty (keep checking)
while (!dataPresent) { while (!dataPresent) {
// acquisition done // acquisition done
if (!runBusy()) { if (!runBusy()) {
usleep(WAIT_TME_US_FR_LK_AT_ME_REG); // wait to be sure there is no data in fifo
dataPresent = bus_r(LOOK_AT_ME_REG); usleep(WAIT_TME_US_FR_ACQDONE_REG);
// still no data // still no data
if (!dataPresent) { if (!checkDataInFifo()) {
FILE_LOG(logINFO, ("Acquisition Finished (State: 0x%08x), " FILE_LOG(logINFO, ("Acquisition Finished (State: 0x%08x), "
"no frame found .\n", bus_r(STATUS_REG))); "no frame found .\n", bus_r(STATUS_REG)));
return FAIL; return FAIL;
@ -2010,20 +1994,21 @@ int checkDataPresent() {
break; break;
} }
} }
// check if fifo empty again // check if data in fifo again
dataPresent = bus_r(LOOK_AT_ME_REG); dataPresent = checkDataInFifo();
} }
FILE_LOG(logDEBUG2, ("Got data, Lookatme:0x%x\n", dataPresent)); FILE_LOG(logDEBUG2, ("Got data :0x%x\n", dataPresent));
return OK; return OK;
} }
int readFrameFromFifo() { int readFrameFromFifo() {
int ns = 0; int ns = 0;
// point the data pointer to the starting position of data // point the data pointer to the starting position of data
now_ptr = ramValues; now_ptr = ramValues;
// no data for this frame // no data for this frame
if (checkDataPresent() == FAIL) { if (checkFifoForEndOfAcquisition() == FAIL) {
return FAIL; return FAIL;
} }
@ -2038,6 +2023,7 @@ int readFrameFromFifo() {
return OK; return OK;
} }
uint32_t runBusy() { uint32_t runBusy() {
#ifdef VIRTUAL #ifdef VIRTUAL
return virtual_status; return virtual_status;

7
slsDetectorServers/moenchDetectorServer/slsDetectorServer_defs.h
View File

@ -29,9 +29,7 @@ enum CLKINDEX {RUN_CLK, ADC_CLK, SYNC_CLK, DBIT_CLK, NUM_CLOCKS};
enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7}; enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7};
/* Hardware Definitions */ /* Hardware Definitions */
#define NCHAN (36) #define NCHAN (32)
#define NCHAN_ANALOG (32)
#define NCHAN_DIGITAL (4)
#define NCHIP (1) #define NCHIP (1)
#define NDAC (8) #define NDAC (8)
#define DYNAMIC_RANGE (16) #define DYNAMIC_RANGE (16)
@ -65,11 +63,12 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7};
#define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS) #define DIGITAL_IO_DELAY_MAXIMUM_PS ((OUTPUT_DELAY_0_OTPT_STTNG_MSK >> OUTPUT_DELAY_0_OTPT_STTNG_OFST) * OUTPUT_DELAY_0_OTPT_STTNG_STEPS)
#define WAIT_TME_US_FR_LK_AT_ME_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo #define WAIT_TME_US_FR_ACQDONE_REG (100) // wait time in us after acquisition done to ensure there is no data in fifo
#define WAIT_TIME_US_PLL (10 * 1000) #define WAIT_TIME_US_PLL (10 * 1000)
#define WAIT_TIME_US_STP_ACQ (100) #define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (500 * 1000) #define WAIT_TIME_CONFIGURE_MAC (500 * 1000)
#define WAIT_TIME_PATTERN_READ (10) #define WAIT_TIME_PATTERN_READ (10)
#define WAIT_TIME_FIFO_RD_STROBE (10)
/* MSB & LSB DEFINES */ /* MSB & LSB DEFINES */
#define MSB_OF_64_BIT_REG_OFST (32) #define MSB_OF_64_BIT_REG_OFST (32)

3
slsDetectorServers/slsDetectorServer/slsDetectorFunctionList.h
View File

@ -329,7 +329,8 @@ void readFrame(int *ret, char *mess);
void readandSendUDPFrames(int *ret, char *mess); void readandSendUDPFrames(int *ret, char *mess);
void unsetFifoReadStrobes(); void unsetFifoReadStrobes();
void readSample(int ns); void readSample(int ns);
int checkDataPresent(); uint32_t checkDataInFifo();
int checkFifoForEndOfAcquisition();
int readFrameFromFifo(); int readFrameFromFifo();
#endif #endif