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Added some commands for moench and modified the moenchServer

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git-svn-id: file:///afs/psi.ch/project/sls_det_software/svn/slsDetectorSoftware@673 951219d9-93cf-4727-9268-0efd64621fa3
This commit is contained in:
bergamaschi
2013-09-18 10:56:03 +00:00
parent 7b637e9cc6
commit 65748059cc
10 changed files with 303 additions and 26 deletions
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193
slsDetectorSoftware/moenchDetectorServer/firmware_funcs.c
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@ -39,7 +39,7 @@ int ram_size=0;
int64_t totalTime=1;
u_int32_t progressMask=0;
int phase_shift=DEFAULT_PHASE_SHIFT;
int phase_shift=0;//DEFAULT_PHASE_SHIFT;
int ipPacketSize=DEFAULT_IP_PACKETSIZE;
int udpPacketSize=DEFAULT_UDP_PACKETSIZE;
@ -253,6 +253,30 @@ int setPhaseShiftOnce(){
return OK;
}
int phaseStep(int st){
u_int32_t addr;
int i;
addr=MULTI_PURPOSE_REG;
if (st>0) {
bus_w(PLL_CNTRL_REG, 1);//reset PLL
bus_w(PLL_CNTRL_REG, 0);
phase_shift=0;
for (i=0;i<st;i++) {
bus_w(addr,(INT_RSTN_BIT|ENET_RESETN_BIT|SW1_BIT|PHASE_STEP_BIT));//0x2821
bus_w(addr,(INT_RSTN_BIT|ENET_RESETN_BIT|(SW1_BIT&~PHASE_STEP_BIT)));//0x2820
phase_shift++;
}
}
#ifdef VERBOSE
printf("Multipupose reg now:%x\n",bus_r(addr));
#endif
return phase_shift;
}
@ -356,11 +380,164 @@ u_int32_t readin(int modnum) {
}
u_int32_t setClockDivider(int d) {
int nc;
if (d>1) nc=d;// nc=161/d;
else return -1;
if (nc>255)
return -1;
int addr, addr1, addr0;
u_int32_t pat,pat1,pat0;
addr= PLL_PARAM_REG;
addr0= PLL_PARAM_OUT_REG;
addr1=PLL_CNTRL_REG;
pat1=0x10;
//write high count c0
/* pat=(1<<12)|(7<<9)|nc; */
/* bus_w(addr, pat); */
/* bus_w(addr1, pat1); */
/* bus_w(addr1, 0); */
/* usleep (1000); */
/* pat=bus_r(addr0); */
/* bus_w(addr1, 0x4); */
/* bus_w(addr1, 0); */
/* pat=bus_r(addr0); */
/* printf("M nominal count read %x (%d)\n",pat,(pat&0x1ff)); */
//write low count c0
pat=(nc-1)|(4<<12)|(1<<9);
bus_w(addr, pat);
bus_w(addr1, pat1);
bus_w(addr1, 0);
pat0=bus_r(PLL_PARAM_OUT_REG);
usleep (1000);
printf("C0 low count status %x\n",pat0);
//write high count c0
pat=(nc)|(4<<12)|(0<<9);
bus_w(addr, pat);
bus_w(addr1, pat1);
bus_w(addr1, 0);
pat0=bus_r(PLL_PARAM_OUT_REG);
printf("C0 high count status %x\n",pat0);
usleep (1000);
//write low count c1
pat=(nc-1)|(5<<12)|(1<<9);
bus_w(addr, pat);
bus_w(addr1, pat1);
bus_w(addr1, 0);
pat0=bus_r(PLL_PARAM_OUT_REG);
printf("C1 high count status %x\n",pat0);
usleep (1000);
//write high count c1
pat=(nc)|(5<<12)|(0<<9);
bus_w(addr, pat);
bus_w(addr1, pat1);
bus_w(addr1, 0);
pat0=bus_r(PLL_PARAM_OUT_REG);
printf("C1 low count status %x\n",pat0);
usleep (1000);
//reconfigure pll
pat1=0x8;
bus_w(addr1, pat1);
bus_w(addr1, 0);
pat0=bus_r(PLL_PARAM_OUT_REG);
printf("configure status %d\n",pat0);
sleep (1);
printf("finish status %x\n",pat0);
bus_w(PLL_CNTRL_REG, 1); //reset PLL
bus_w(PLL_CNTRL_REG, 0);
return 0;
}
u_int32_t getClockDivider() {
return 0;
int addr, addr1, addr0;
u_int32_t pat,pat1;
addr0= PLL_PARAM_REG;
addr= PLL_PARAM_OUT_REG;
addr1=PLL_CNTRL_REG;
pat1=0x4;
//write low count c0
pat=(4<<12)|(1<<9);
bus_w(addr0, pat);
bus_w(addr1, pat1);
bus_w(addr1, 0);
usleep (1000);
pat=bus_r(addr);
printf("C0 low count read %x (%d)\n",pat,(pat&0xff));
//write high count c0
pat=(4<<12)|(0<<9);
bus_w(addr0, pat);
bus_w(addr1, pat1);
bus_w(addr1, 0);
usleep (1000);
pat=bus_r(addr);
printf("C0 high count read %x (%d)\n",pat,(pat&0xff));
//write low count c1
pat=(5<<12)|(1<<9);
bus_w(addr0, pat);
bus_w(addr1, pat1);
bus_w(addr1, 0);
usleep (1000);
pat=bus_r(addr);
printf("C1 low count read %x (%d)\n",pat,(pat&0xff));
//write high count c1
pat=(5<<12)|(0<<9);
bus_w(addr0, pat);
bus_w(addr1, pat1);
bus_w(addr1, 0);
usleep (1000);
pat=bus_r(addr);
printf("C1 high count read %x (%d)\n",pat,(pat&0xff));
return (pat&0xff);
/* //write low count c0 */
/* pat=(0<<12)|(7<<9); */
/* bus_w(addr0, pat); */
/* bus_w(addr1, pat1); */
/* bus_w(addr1, 0); */
/* usleep (1000); */
/* pat=bus_r(addr); */
/* printf("N nominal count read %x (%d)\n",pat,pat&0x1ff); */
/* //write high count c0 */
/* pat=(1<<12)|(7<<9); */
/* bus_w(addr0, pat); */
/* bus_w(addr1, pat1); */
/* bus_w(addr1, 0); */
/* usleep (1000); */
/* pat=bus_r(addr); */
/* printf("M nominal count read %x (%d)\n",pat,(pat&0x1ff)); */
/* if ((pat&0x1ff)!=0) */
/* return 161/(pat&0x1ff); */
/* else */
/* return -1; */
}
u_int32_t setSetLength(int d) {
@ -371,6 +548,14 @@ u_int32_t getSetLength() {
return 0;
}
u_int32_t setOversampling(int d) {
if (d>=0 && d<=255)
bus_w(OVERSAMPLING_REG, d);
return bus_r(OVERSAMPLING_REG);
}
u_int32_t setWaitStates(int d1) {
return 0;
@ -1445,6 +1630,8 @@ int configureMAC(int ipad,long long int macad,long long int detectormacad, int d
// if(val!=0x2820) return -1;
return adcConfigured;
}
@ -1636,6 +1823,7 @@ u_int32_t* fifo_read_event()
*/
while((t&0x1)==0) {
printf("before readout %08x %08x\n", runState(), bus_r(LOOK_AT_ME_REG));
#ifdef VERYVERBOSE
printf("look at me reg:%08x\n",bus_r(LOOK_AT_ME_REG));
#endif
@ -1916,7 +2104,6 @@ int prepareADC(){
valw=valw&(~(0x1<<cdx));usleep(0);
valw=0xff; bus_w(ADC_WRITE_REG,(valw)); // stop point =start point */
return;
}

2
slsDetectorSoftware/moenchDetectorServer/firmware_funcs.h
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@ -29,6 +29,7 @@ u_int32_t bus_w(u_int32_t offset, u_int32_t data);
u_int32_t bus_r(u_int32_t offset);
int setPhaseShiftOnce();
int phaseStep(int st);
int cleanFifo();
int setDAQRegister();
@ -44,6 +45,7 @@ u_int32_t setTotClockDivider(int d);
u_int32_t getTotClockDivider();
u_int32_t setTotDutyCycle(int d);
u_int32_t getTotDutyCycle();
u_int32_t setOversampling(int d);
u_int32_t setExtSignal(int d, enum externalSignalFlag mode);
int getExtSignal(int d);

BIN
slsDetectorSoftware/moenchDetectorServer/moenchDetectorServer
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Binary file not shown.

11
slsDetectorSoftware/moenchDetectorServer/registers_m.h
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@ -103,6 +103,17 @@
#define PLL_PARAM_REG 0x37<<11
#define PLL_PARAM_OUT_REG 0x38<<11
#define PLL_CNTRL_REG 0x34<<11
#define ROI_REG 0x35<<11
#define OVERSAMPLING_REG 0x36<<11
#define MOENCH_CNTR_REG 0x31<<11
#define MOENCH_CNTR_OUT_REG 0x33<<11
#define MOENCH_CNTR_CONF_REG 0x32<<11
//image
#define DARK_IMAGE_REG 0x81<<11

4
slsDetectorSoftware/moenchDetectorServer/server_defs.h
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@ -47,7 +47,7 @@
#define TOKEN_TIMING_REV1 0x1f16
#define TOKEN_TIMING_REV2 0x1f0f
#define DEFAULT_PHASE_SHIFT 120
#define DEFAULT_PHASE_SHIFT 0 // 120
#define DEFAULT_IP_PACKETSIZE 0x0522
#define DEFAULT_UDP_PACKETSIZE 0x050E
#define ADC1_IP_PACKETSIZE 256*2+14+20
@ -57,7 +57,7 @@
#define DEBUGOUT
#endif
#define CLK_FREQ 32.1E+6
#define CLK_FREQ 65.6E+6
#endif

92
slsDetectorSoftware/moenchDetectorServer/server_funcs.c
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@ -79,7 +79,6 @@ int init_detector(int b, int checkType) {
}
if (b) {
int reg;
#ifdef MCB_FUNCS
printf("\nBoard Revision:0x%x\n",(bus_r(PCB_REV_REG)&BOARD_REVISION_MASK));
initDetector();
@ -89,23 +88,26 @@ int init_detector(int b, int checkType) {
testRAM();
printf("ADC_SYNC_REG:%x\n",bus_r(ADC_SYNC_REG));
//moench specific
setPhaseShiftOnce();
prepareADC();
setADC(-1); //already does setdaqreg and clean fifo
setSettings(GET_SETTINGS,-1);
// setPhaseShiftOnce(); //firmware.h
prepareADC(); // server_funcs
setADC(-1); //already does setdaqreg and clean fifo
setSettings(GET_SETTINGS,-1);
//Initialization
setFrames(1);
setTrains(1);
setExposureTime(1e6);
setPeriod(1e9);
setExposureTime(1e3);
setPeriod(1E6);
setDelay(0);
setGates(0);
setTiming(GET_EXTERNAL_COMMUNICATION_MODE);
setMaster(GET_MASTER);
setSynchronization(GET_SYNCHRONIZATION_MODE);
startReceiver(0);
startReceiver(0); //firmware
}
strcpy(mess,"dummy message");
strcpy(lastClientIP,"none");
@ -2337,18 +2339,78 @@ int get_roi(int file_des) {
int set_speed(int file_des) {
enum speedVariable arg;
int val;
int ret=FAIL;
int val,n;
int ret=OK;
int retval;
receiveDataOnly(file_des,&arg,sizeof(arg));
receiveDataOnly(file_des,&val,sizeof(val));
n=receiveDataOnly(file_des,&arg,sizeof(arg));
if (n < 0) {
sprintf(mess,"Error reading from socket\n");
ret=FAIL;
}
n=receiveDataOnly(file_des,&val,sizeof(val));
if (n < 0) {
sprintf(mess,"Error reading from socket\n");
ret=FAIL;
}
sprintf(mess,"can't set speed variable for moench\n");
if (ret==OK) {
if (val>=0) {
if (differentClients==1 && lockStatus==1 && val>=0) {
ret=FAIL;
sprintf(mess,"Detector locked by %s\n",lastClientIP);
} else {
switch (arg) {
case CLOCK_DIVIDER:
retval=setClockDivider(val);
break;
case PHASE_SHIFT:
retval=phaseStep(val);
break;
case OVERSAMPLING:
retval=setOversampling(val);
break;
default:
ret=FAIL;
sprintf(mess,"Unknown speed parameter %d",arg);
}
}
}
sendDataOnly(file_des,&ret,sizeof(ret));
sendDataOnly(file_des,mess,sizeof(mess));
switch (arg) {
case CLOCK_DIVIDER:
retval=getClockDivider();
break;
case PHASE_SHIFT:
retval=phaseStep(-1);
break;
case OVERSAMPLING:
retval=setOversampling(-1);
break;
default:
ret=FAIL;
sprintf(mess,"Unknown speed parameter %d",arg);
}
}
n = sendDataOnly(file_des,&ret,sizeof(ret));
if (ret==FAIL) {
n = sendDataOnly(file_des,mess,sizeof(mess));
} else {
n = sendDataOnly(file_des,&retval,sizeof(retval));
}
return ret;
}