diff --git a/slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h b/slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h index 3563a8b82..7b5be04b8 100644 --- a/slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h +++ b/slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h @@ -2,10 +2,11 @@ // Copyright (C) 2021 Contributors to the SLS Detector Package #pragma once + #define CTRL_REG (0x0) -#define POWER_VIO_OFST (0) -#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST) +#define POWER_VIO_OFST (0) +#define POWER_VIO_MSK (0x00000001 << POWER_VIO_OFST) #define POWER_VCC_A_OFST (1) #define POWER_VCC_A_MSK (0x00000001 << POWER_VCC_A_OFST) #define POWER_VCC_B_OFST (2) @@ -28,10 +29,10 @@ #define FPGACOMPDATE_OFST (0) #define FPGACOMPDATE_MSK (0x00ffffff << FPGACOMPDATE_OFST) -#define FPGADETTYPE_OFST (24) -#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST) +#define FPGADETTYPE_OFST (24) +#define FPGADETTYPE_MSK (0x000000ff << FPGADETTYPE_OFST) -#define EMPTY14REG (0x14) +#define FPGA_GIT_HEAD (0x14) #define FIXEDPATTERNREG (0x18) #define FIXEDPATTERNVAL (0xACDC2016) @@ -42,15 +43,15 @@ #define APICOMPDATE_OFST (0) #define APICOMPDATE_MSK (0x00ffffff << APICOMPDATE_OFST) -#define APIDETTYPE_OFST (24) -#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST) +#define APIDETTYPE_OFST (24) +#define APIDETTYPE_MSK (0x000000ff << APIDETTYPE_OFST) #define EMPTY24REG (0x24) #define PKTPACKETLENGTHREG (0x28) -#define PACKETLENGTH1G_OFST (0) -#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST) +#define PACKETLENGTH1G_OFST (0) +#define PACKETLENGTH1G_MSK (0x0000ffff << PACKETLENGTH1G_OFST) #define PACKETLENGTH10G_OFST (16) #define PACKETLENGTH10G_MSK (0x0000ffff << PACKETLENGTH10G_OFST) @@ -58,8 +59,8 @@ #define PKTNOPACKETSREG (0x30) -#define NOPACKETS1G_OFST (0) -#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST) +#define NOPACKETS1G_OFST (0) +#define NOPACKETS1G_MSK (0x0000003f << NOPACKETS1G_OFST) #define NOPACKETS10G_OFST (16) #define NOPACKETS10G_MSK (0x0000003f << NOPACKETS10G_OFST) @@ -67,12 +68,12 @@ #define PKTCTRLREG (0x38) -#define NOSERVERS_OFST (0) -#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST) +#define NOSERVERS_OFST (0) +#define NOSERVERS_MSK (0x0000003f << NOSERVERS_OFST) #define SERVERSTART_OFST (8) #define SERVERSTART_MSK (0x0000001f << SERVERSTART_OFST) -#define ETHINTERF_OFST (16) -#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST) +#define ETHINTERF_OFST (16) +#define ETHINTERF_MSK (0x00000001 << ETHINTERF_OFST) #define EMPTY3CREG (0x3C) @@ -134,25 +135,25 @@ #define FLOW_STATUS_REG (0x100) -#define RSM_BUSY_OFST (0) -#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST) +#define RSM_BUSY_OFST (0) +#define RSM_BUSY_MSK (0x00000001 << RSM_BUSY_OFST) #define RSM_TRG_WAIT_OFST (3) #define RSM_TRG_WAIT_MSK (0x00000001 << RSM_TRG_WAIT_OFST) -#define CSM_BUSY_OFST (17) -#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST) +#define CSM_BUSY_OFST (17) +#define CSM_BUSY_MSK (0x00000001 << CSM_BUSY_OFST) #define EMPTY104REG (0x104) #define FLOW_CONTROL_REG (0x108) -#define START_F_OFST (0) -#define START_F_MSK (0x00000001 << START_F_OFST) -#define STOP_F_OFST (1) -#define STOP_F_MSK (0x00000001 << STOP_F_OFST) -#define RST_F_OFST (2) -#define RST_F_MSK (0x00000001 << RST_F_OFST) -#define SW_TRIGGER_F_OFST (3) -#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST) +#define START_F_OFST (0) +#define START_F_MSK (0x00000001 << START_F_OFST) +#define STOP_F_OFST (1) +#define STOP_F_MSK (0x00000001 << STOP_F_OFST) +#define RST_F_OFST (2) +#define RST_F_MSK (0x00000001 << RST_F_OFST) +#define SW_TRIGGER_F_OFST (3) +#define SW_TRIGGER_F_MSK (0x00000001 << SW_TRIGGER_F_OFST) #define TRIGGER_ENABLE_OFST (4) #define TRIGGER_ENABLE_MSK (0x00000001 << TRIGGER_ENABLE_OFST) @@ -248,10 +249,10 @@ #define PATTERN_CNTRL_REG (0x220) -#define PATTERN_CNTRL_WR_OFST (0) -#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST) -#define PATTERN_CNTRL_RD_OFST (1) -#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST) +#define PATTERN_CNTRL_WR_OFST (0) +#define PATTERN_CNTRL_WR_MSK (0x00000001 << PATTERN_CNTRL_WR_OFST) +#define PATTERN_CNTRL_RD_OFST (1) +#define PATTERN_CNTRL_RD_MSK (0x00000001 << PATTERN_CNTRL_RD_OFST) #define PATTERN_CNTRL_ADDR_OFST (16) #define PATTERN_CNTRL_ADDR_MSK (0x00001fff << PATTERN_CNTRL_ADDR_OFST) @@ -261,16 +262,15 @@ #define PATTERN_LIMIT_STRT_OFST (0) #define PATTERN_LIMIT_STRT_MSK (0x00001fff << PATTERN_LIMIT_STRT_OFST) -#define PATTERN_LIMIT_STP_OFST (16) -#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST) +#define PATTERN_LIMIT_STP_OFST (16) +#define PATTERN_LIMIT_STP_MSK (0x00001fff << PATTERN_LIMIT_STP_OFST) #define EMPTY22CREG (0x22C) #define PATTERN_LOOP_0_ADDR_REG (0x230) #define PATTERN_LOOP_0_ADDR_STRT_OFST (0) -#define PATTERN_LOOP_0_ADDR_STRT_MSK \ - (0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST) +#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STRT_OFST) #define PATTERN_LOOP_0_ADDR_STP_OFST (16) #define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_0_ADDR_STP_OFST) @@ -294,8 +294,7 @@ #define PATTERN_LOOP_1_ADDR_REG (0x250) #define PATTERN_LOOP_1_ADDR_STRT_OFST (0) -#define PATTERN_LOOP_1_ADDR_STRT_MSK \ - (0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST) +#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STRT_OFST) #define PATTERN_LOOP_1_ADDR_STP_OFST (16) #define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_1_ADDR_STP_OFST) @@ -319,8 +318,7 @@ #define PATTERN_LOOP_2_ADDR_REG (0x270) #define PATTERN_LOOP_2_ADDR_STRT_OFST (0) -#define PATTERN_LOOP_2_ADDR_STRT_MSK \ - (0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST) +#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STRT_OFST) #define PATTERN_LOOP_2_ADDR_STP_OFST (16) #define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_2_ADDR_STP_OFST) @@ -344,8 +342,7 @@ #define PATTERN_LOOP_3_ADDR_REG (0x290) #define PATTERN_LOOP_3_ADDR_STRT_OFST (0) -#define PATTERN_LOOP_3_ADDR_STRT_MSK \ - (0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST) +#define PATTERN_LOOP_3_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STRT_OFST) #define PATTERN_LOOP_3_ADDR_STP_OFST (16) #define PATTERN_LOOP_3_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_3_ADDR_STP_OFST) @@ -369,8 +366,7 @@ #define PATTERN_LOOP_4_ADDR_REG (0x310) #define PATTERN_LOOP_4_ADDR_STRT_OFST (0) -#define PATTERN_LOOP_4_ADDR_STRT_MSK \ - (0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST) +#define PATTERN_LOOP_4_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STRT_OFST) #define PATTERN_LOOP_4_ADDR_STP_OFST (16) #define PATTERN_LOOP_4_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_4_ADDR_STP_OFST) @@ -394,8 +390,7 @@ #define PATTERN_LOOP_5_ADDR_REG (0x330) #define PATTERN_LOOP_5_ADDR_STRT_OFST (0) -#define PATTERN_LOOP_5_ADDR_STRT_MSK \ - (0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST) +#define PATTERN_LOOP_5_ADDR_STRT_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STRT_OFST) #define PATTERN_LOOP_5_ADDR_STP_OFST (16) #define PATTERN_LOOP_5_ADDR_STP_MSK (0x00001fff << PATTERN_LOOP_5_ADDR_STP_OFST) @@ -634,21 +629,20 @@ #define FIFO_TO_GB_CONTROL_REG (0x500) -#define ENABLED_CHANNELS_ADC_OFST (0) -#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST) -#define ENABLED_CHANNELS_D_OFST (8) -#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST) -#define ENABLED_CHANNELS_X_OFST (9) -#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST) -#define RO_MODE_ADC_OFST (13) -#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST) -#define RO_MODE_D_OFST (14) -#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST) -#define RO_MODE_X_OFST (15) -#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST) +#define ENABLED_CHANNELS_ADC_OFST (0) +#define ENABLED_CHANNELS_ADC_MSK (0x000000ff << ENABLED_CHANNELS_ADC_OFST) +#define ENABLED_CHANNELS_D_OFST (8) +#define ENABLED_CHANNELS_D_MSK (0x00000001 << ENABLED_CHANNELS_D_OFST) +#define ENABLED_CHANNELS_X_OFST (9) +#define ENABLED_CHANNELS_X_MSK (0x0000000f << ENABLED_CHANNELS_X_OFST) +#define RO_MODE_ADC_OFST (13) +#define RO_MODE_ADC_MSK (0x00000001 << RO_MODE_ADC_OFST) +#define RO_MODE_D_OFST (14) +#define RO_MODE_D_MSK (0x00000001 << RO_MODE_D_OFST) +#define RO_MODE_X_OFST (15) +#define RO_MODE_X_MSK (0x00000001 << RO_MODE_X_OFST) #define COUNT_FRAMES_FROM_UPDATE_OFST (16) -#define COUNT_FRAMES_FROM_UPDATE_MSK \ - (0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST) +#define COUNT_FRAMES_FROM_UPDATE_MSK (0x00000001 << COUNT_FRAMES_FROM_UPDATE_OFST) #define START_STREAMING_P_OFST (17) #define START_STREAMING_P_MSK (0x00000001 << START_STREAMING_P_OFST) @@ -817,14 +811,14 @@ #define MATTERHORNSPICTRL (0x608) -#define CONFIGSTART_P_OFST (0) -#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST) -#define PERIPHERYRST_P_OFST (1) -#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST) -#define STARTREAD_P_OFST (2) -#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST) -#define BUSY_OFST (3) -#define BUSY_MSK (0x00000001 << BUSY_OFST) +#define CONFIGSTART_P_OFST (0) +#define CONFIGSTART_P_MSK (0x00000001 << CONFIGSTART_P_OFST) +#define PERIPHERYRST_P_OFST (1) +#define PERIPHERYRST_P_MSK (0x00000001 << PERIPHERYRST_P_OFST) +#define STARTREAD_P_OFST (2) +#define STARTREAD_P_MSK (0x00000001 << STARTREAD_P_OFST) +#define BUSY_OFST (3) +#define BUSY_MSK (0x00000001 << BUSY_OFST) #define READOUTFROMASIC_OFST (4) #define READOUTFROMASIC_MSK (0x00000001 << READOUTFROMASIC_OFST) @@ -866,69 +860,100 @@ #define LINKDOWNLATCHEDOUT_OFST (0) #define LINKDOWNLATCHEDOUT_MSK (0x00000001 << LINKDOWNLATCHEDOUT_OFST) -#define TXUSERCLKACTIVE_OFST (1) -#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST) -#define RXUSERCLKACTIVE_OFST (2) -#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST) -#define RXCOMMADET_OFST (3) -#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST) -#define RXBYTEREALIGN_OFST (7) -#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST) -#define RXBYTEISALIGNED_OFST (11) -#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST) -#define GTWIZRXCDRSTABLE_OFST (15) -#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST) -#define RESETTXDONE_OFST (16) -#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST) -#define RESETRXDONE_OFST (17) -#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST) -#define RXPMARESETDONE_OFST (18) -#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST) -#define TXPMARESETDONE_OFST (22) -#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST) -#define GTTPOWERGOOD_OFST (26) -#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST) +#define TXUSERCLKACTIVE_OFST (1) +#define TXUSERCLKACTIVE_MSK (0x00000001 << TXUSERCLKACTIVE_OFST) +#define RXUSERCLKACTIVE_OFST (2) +#define RXUSERCLKACTIVE_MSK (0x00000001 << RXUSERCLKACTIVE_OFST) +#define RXCOMMADET_OFST (3) +#define RXCOMMADET_MSK (0x0000000f << RXCOMMADET_OFST) +#define RXBYTEREALIGN_OFST (7) +#define RXBYTEREALIGN_MSK (0x0000000f << RXBYTEREALIGN_OFST) +#define RXBYTEISALIGNED_OFST (11) +#define RXBYTEISALIGNED_MSK (0x0000000f << RXBYTEISALIGNED_OFST) +#define GTWIZRXCDRSTABLE_OFST (15) +#define GTWIZRXCDRSTABLE_MSK (0x00000001 << GTWIZRXCDRSTABLE_OFST) +#define RESETTXDONE_OFST (16) +#define RESETTXDONE_MSK (0x00000001 << RESETTXDONE_OFST) +#define RESETRXDONE_OFST (17) +#define RESETRXDONE_MSK (0x00000001 << RESETRXDONE_OFST) +#define RXPMARESETDONE_OFST (18) +#define RXPMARESETDONE_MSK (0x0000000f << RXPMARESETDONE_OFST) +#define TXPMARESETDONE_OFST (22) +#define TXPMARESETDONE_MSK (0x0000000f << TXPMARESETDONE_OFST) +#define GTTPOWERGOOD_OFST (26) +#define GTTPOWERGOOD_MSK (0x0000000f << GTTPOWERGOOD_OFST) -#define EMPTY654REG (0x654) +#define TRANSCEIVERSTATUS2 (0x654) + +#define RXLOCKED_OFST (0) +#define RXLOCKED_MSK (0x0000000f << RXLOCKED_OFST) #define TRANSCEIVERCONTROL (0x658) -#define GTWIZRESETALL_OFST (0) -#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST) +#define GTWIZRESETALL_OFST (0) +#define GTWIZRESETALL_MSK (0x00000001 << GTWIZRESETALL_OFST) #define RESETTXPLLANDDATAPATH_OFST (1) #define RESETTXPLLANDDATAPATH_MSK (0x00000001 << RESETTXPLLANDDATAPATH_OFST) -#define RESETTXDATAPATHIN_OFST (2) -#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST) +#define RESETTXDATAPATHIN_OFST (2) +#define RESETTXDATAPATHIN_MSK (0x00000001 << RESETTXDATAPATHIN_OFST) #define RESETRXPLLANDDATAPATH_OFST (3) #define RESETRXPLLANDDATAPATH_MSK (0x00000001 << RESETRXPLLANDDATAPATH_OFST) -#define RESETRXDATAPATHIN_OFST (4) -#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST) -#define RXPOLARITY_OFST (5) -#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST) +#define RESETRXDATAPATHIN_OFST (4) +#define RESETRXDATAPATHIN_MSK (0x00000001 << RESETRXDATAPATHIN_OFST) +#define RXPOLARITY_OFST (5) +#define RXPOLARITY_MSK (0x0000000f << RXPOLARITY_OFST) +#define RXERRORCNTRESET_OFST (9) +#define RXERRORCNTRESET_MSK (0x0000000f << RXERRORCNTRESET_OFST) +#define RXMSBLSBINVERT_OFST (13) +#define RXMSBLSBINVERT_MSK (0x0000000f << RXMSBLSBINVERT_OFST) -#define EMPTY65CREG (0x65C) +#define TRANSCEIVERERRCNT_REG0 (0x65C) -#define EMPTY660REG (0x660) +#define TRANSCEIVERERRCNT_REG1 (0x660) -#define EMPTY664REG (0x664) +#define TRANSCEIVERERRCNT_REG2 (0x664) -#define EMPTY668REG (0x668) +#define TRANSCEIVERERRCNT_REG3 (0x668) -#define EMPTY66CREG (0x66C) +#define TRANSCEIVERALIGNCNT_REG0 (0x66C) -#define EMPTY670REG (0x670) +#define RXALIGNCNTCH0_OFST (0) +#define RXALIGNCNTCH0_MSK (0x0000ffff << RXALIGNCNTCH0_OFST) -#define EMPTY674REG (0x674) +#define TRANSCEIVERALIGNCNT_REG1 (0x670) -#define EMPTY678REG (0x678) +#define RXALIGNCNTCH1_OFST (0) +#define RXALIGNCNTCH1_MSK (0x0000ffff << RXALIGNCNTCH1_OFST) -#define EMPTY67CREG (0x67C) +#define TRANSCEIVERALIGNCNT_REG2 (0x674) -#define EMPTY680REG (0x680) +#define RXALIGNCNTCH2_OFST (0) +#define RXALIGNCNTCH2_MSK (0x0000ffff << RXALIGNCNTCH2_OFST) -#define EMPTY684REG (0x684) +#define TRANSCEIVERALIGNCNT_REG3 (0x678) -#define EMPTY688REG (0x688) +#define RXALIGNCNTCH3_OFST (0) +#define RXALIGNCNTCH3_MSK (0x0000ffff << RXALIGNCNTCH3_OFST) + +#define TRANSCEIVERLASTWORD_REG0 (0x67C) + +#define RXDATACH0_OFST (0) +#define RXDATACH0_MSK (0x0000ffff << RXDATACH0_OFST) + +#define TRANSCEIVERLASTWORD_REG1 (0x680) + +#define RXDATACH1_OFST (0) +#define RXDATACH1_MSK (0x0000ffff << RXDATACH1_OFST) + +#define TRANSCEIVERLASTWORD_REG2 (0x684) + +#define RXDATACH2_OFST (0) +#define RXDATACH2_MSK (0x0000ffff << RXDATACH2_OFST) + +#define TRANSCEIVERLASTWORD_REG3 (0x688) + +#define RXDATACH3_OFST (0) +#define RXDATACH3_MSK (0x0000ffff << RXDATACH3_OFST) #define EMPTY68CREG (0x68C) @@ -990,18 +1015,18 @@ #define DBITFIFOCTRLREG (0x700) -#define DBITRD_OFST (0) -#define DBITRD_MSK (0x00000001 << DBITRD_OFST) -#define DBITRST_OFST (1) -#define DBITRST_MSK (0x00000001 << DBITRST_OFST) -#define DBITFULL_OFST (2) -#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST) -#define DBITEMPTY_OFST (3) -#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST) +#define DBITRD_OFST (0) +#define DBITRD_MSK (0x00000001 << DBITRD_OFST) +#define DBITRST_OFST (1) +#define DBITRST_MSK (0x00000001 << DBITRST_OFST) +#define DBITFULL_OFST (2) +#define DBITFULL_MSK (0x00000001 << DBITFULL_OFST) +#define DBITEMPTY_OFST (3) +#define DBITEMPTY_MSK (0x00000001 << DBITEMPTY_OFST) #define DBITUNDERFLOW_OFST (4) #define DBITUNDERFLOW_MSK (0x00000001 << DBITUNDERFLOW_OFST) -#define DBITOVERFLOW_OFST (5) -#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST) +#define DBITOVERFLOW_OFST (5) +#define DBITOVERFLOW_MSK (0x00000001 << DBITOVERFLOW_OFST) #define EMPTYREG (0x704)