* dac WIP

* dacs WIP

* DACs are working with names

* namechanges of vrfsh->vshaper, vrfshnpol->vshaperneg

* pattern for MY3, configure MAC for MY3
This commit is contained in:
Marie Andrä
2019-10-07 12:13:25 +02:00
committed by Dhanya Thattil
parent 16f7b42533
commit 5f94b5c246
14 changed files with 665 additions and 151 deletions

View File

@ -428,7 +428,6 @@ format
TEMPERATURE_FPGA2, /**< temperature sensor (fpga2 (eiger:febl) */
TEMPERATURE_FPGA3, /**< temperature sensor (fpga3 (eiger:febr) */
M_vIpre, /**< mythen 3 >*/
M_vIbias, /**< mythen 3 >*/
M_vIinSh, /**< mythen 3 >*/
M_VdcSh, /**< mythen 3 >*/
M_Vth2, /**< mythen 3 >*/
@ -436,7 +435,6 @@ format
M_Vth3, /**< mythen 3 >*/
M_casSh, /**< mythen 3 >*/
M_cas, /**< mythen 3 >*/
M_vIbiasSh, /**< mythen 3 >*/
M_vIcin, /**< mythen 3 >*/
M_vIpreOut, /**< mythen 3 >*/
V_POWER_A = 100, /**new chiptest board */