mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 10:07:59 +02:00
Dac (#67)
* dac WIP * dacs WIP * DACs are working with names * namechanges of vrfsh->vshaper, vrfshnpol->vshaperneg * pattern for MY3, configure MAC for MY3
This commit is contained in:
Marie Andrä
committed by
Dhanya Thattil
Dhanya Thattil
parent
16f7b42533
commit
5f94b5c246
@ -7,6 +7,7 @@ add_executable(mythen3DetectorServer_virtual
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../slsDetectorServer/src/communication_funcs_UDP.c
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../slsDetectorServer/src/DAC6571.c
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../slsDetectorServer/src/common.c
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../slsDetectorServer/src/LTC2620_Driver.c
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)
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include_directories(
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@ -5,14 +5,14 @@ support_lib = ../../slsSupportLib/include/
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CROSS = nios2-buildroot-linux-gnu-
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CC = $(CROSS)gcc
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CFLAGS += -Wall -DMYTHEN3D -DSTOP_SERVER -I$(main_inc) -I$(support_lib) -I$(current_dir)#-DVERBOSEI #-DVERBOSE
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CFLAGS += -Wall -DMYTHEN3D -DSTOP_SERVER -I$(main_inc) -I$(support_lib) -I$(current_dir) -DDEBUG1 #-DVERBOSEI #-DVERBOSE
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LDLIBS += -lm
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PROGS = mythen3DetectorServer
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DESTDIR ?= bin
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INSTMODE = 0777
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SRCS = slsDetectorFunctionList.c
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SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)nios.c $(main_src)DAC6571.c $(main_src)common.c
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SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)nios.c $(main_src)DAC6571.c $(main_src)common.c $(main_src)LTC2620_Driver.c
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OBJS = $(SRCS:.c=.o)
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@ -2,14 +2,19 @@
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#pragma once
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/* Definitions for FPGA*/
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#define REG_OFFSET (4)
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#define BASE_CONTROL (0x0)
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#define BASE_PATTERN_CONTROL (0x200 )
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#define BASE_PATTERN_RAM (0x10000 )
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#define BASE_PATTERN_CONTROL (0x200)
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#define BASE_PATTERN_RAM (0x10000)
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#define BASE_UDP_RAM (0x1000) // fix it
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/* Basic detector FPGA registers --------------------------------------------------*/
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/* Module Control Board Serial Number Register */
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#define MCB_SERIAL_NO_REG (0x000 * REG_OFFSET + BASE_CONTROL)
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/* FPGA Version register */
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#define FPGA_VERSION_REG (0x04 + BASE_CONTROL)
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#define FPGA_VERSION_REG (0x001 * REG_OFFSET + BASE_CONTROL)
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#define FPGA_COMPILATION_DATE_OFST (0)
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#define FPGA_COMPILATION_DATE_MSK (0x00FFFFFF << FPGA_COMPILATION_DATE_OFST)
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@ -17,64 +22,67 @@
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#define DETECTOR_TYPE_MSK (0x000000FF << DETECTOR_TYPE_OFST)
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/* Module Control Board Serial Number Register */
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#define MCB_SERIAL_NO_REG (0x00 + BASE_CONTROL)
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/* API Version Register */
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#define API_VERSION_REG (0x08 + BASE_CONTROL)
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#define API_VERSION_REG (0x002 * REG_OFFSET + BASE_CONTROL)
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#define API_VERSION_OFST (0)
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#define API_VERSION_MSK (0x00FFFFFF << API_VERSION_OFST)
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#define API_VERSION_DETECTOR_TYPE_OFST (24) //Not used in software
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#define API_VERSION_DETECTOR_TYPE_MSK (0x000000FF << API_VERSION_DETECTOR_TYPE_OFST) //Not used in software
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/* Fix pattern register */
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#define FIX_PATT_REG (0x0C + BASE_CONTROL)
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#define FIX_PATT_REG (0x003 * REG_OFFSET + BASE_CONTROL)
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#define FIX_PATT_VAL (0xACDC2019)
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/* Status register */
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#define STATUS_REG (0x10 + BASE_CONTROL)
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#define STATUS_REG (0x004 * REG_OFFSET + BASE_CONTROL)
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#ifdef VIRTUAL // until firmware is ready ----------------------------------
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#define RUN_BUSY_OFST (0)
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#define RUN_BUSY_MSK (0x00000001 << RUN_BUSY_OFST)
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#endif
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/* Look at me register */
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#define LOOK_AT_ME_REG (0x14 + BASE_CONTROL) //Not used in firmware or software, good to play with
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/* Look at me register, read only */
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#define LOOK_AT_ME_REG (0x005 * REG_OFFSET + BASE_CONTROL) //Not used in firmware or software, good to play with
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#define DTA_OFFSET_REG (0x104 * REG_OFFSET + BASE_CONTROL)
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/* Pattern Control FPGA registers --------------------------------------------------*/
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/* Pattern status Register*/
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#define PAT_STATUS_REG (0x00 + BASE_PATTERN_CONTROL)
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#define PAT_STATUS_REG (0x000 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Delay left 64bit Register */
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#define GET_DELAY_LSB_REG (0x08 + BASE_PATTERN_CONTROL)
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#define GET_DELAY_MSB_REG (0x0C + BASE_PATTERN_CONTROL)
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#define GET_DELAY_LSB_REG (0x0002 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define GET_DELAY_MSB_REG (0x0003 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Cycles left 64bit Register */
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#define GET_CYCLES_LSB_REG (0x10 + BASE_PATTERN_CONTROL)
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#define GET_CYCLES_MSB_REG (0x14 + BASE_PATTERN_CONTROL)
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#define GET_CYCLES_LSB_REG (0x0004 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define GET_CYCLES_MSB_REG (0x0005 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Frames left 64bit Register */
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#define GET_FRAMES_LSB_REG (0x18 + BASE_PATTERN_CONTROL)
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#define GET_FRAMES_MSB_REG (0x1C + BASE_PATTERN_CONTROL)
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#define GET_FRAMES_LSB_REG (0x0006 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define GET_FRAMES_MSB_REG (0x0007 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Period left 64bit Register */
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#define GET_PERIOD_LSB_REG (0x20 + BASE_PATTERN_CONTROL)
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#define GET_PERIOD_MSB_REG (0x24 + BASE_PATTERN_CONTROL)
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#define GET_PERIOD_LSB_REG (0x0008 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define GET_PERIOD_MSB_REG (0x0009 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Delay 64bit Write-register */
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#define SET_DELAY_LSB_REG (0x88 + BASE_PATTERN_CONTROL)
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#define SET_DELAY_MSB_REG (0x8C + BASE_PATTERN_CONTROL)
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#define SET_DELAY_LSB_REG (0x0102 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define SET_DELAY_MSB_REG (0x0103 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Cylces 64bit Write-register */
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#define SET_CYCLES_LSB_REG (0x90 + BASE_PATTERN_CONTROL)
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#define SET_CYCLES_MSB_REG (0x94 + BASE_PATTERN_CONTROL)
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#define SET_CYCLES_LSB_REG (0x0104 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define SET_CYCLES_MSB_REG (0x0105 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Frames 64bit Write-register */
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#define SET_FRAMES_LSB_REG (0x98 + BASE_PATTERN_CONTROL)
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#define SET_FRAMES_MSB_REG (0x9C + BASE_PATTERN_CONTROL)
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#define SET_FRAMES_LSB_REG (0x0106 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define SET_FRAMES_MSB_REG (0x0107 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Period 64bit Write-register */
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#define SET_PERIOD_LSB_REG (0xA0 + BASE_PATTERN_CONTROL)
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#define SET_PERIOD_MSB_REG (0xA4 + BASE_PATTERN_CONTROL)
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#define SET_PERIOD_LSB_REG (0x0108 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define SET_PERIOD_MSB_REG (0x0109 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Pattern Control FPGA registers --------------------------------------------------*/
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@ -85,76 +93,78 @@
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// #define PATTERN_IO_CNTRL_MSB_REG (0x8C + BASE_CONTROL)
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/* Pattern Limit RW Register */
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#define PATTERN_LIMIT_REG (0x100 + BASE_PATTERN_CONTROL)
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#define PATTERN_LIMIT_REG (0x1000 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_LIMIT_STRT_OFST (0)
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#define PATTERN_LIMIT_STRT_MSK (0x00001FFF << PATTERN_LIMIT_STRT_OFST)
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#define PATTERN_LIMIT_STP_OFST (16)
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#define PATTERN_LIMIT_STP_MSK (0x00001FFF << PATTERN_LIMIT_STP_OFST)
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/* Pattern Wait Timer 0 64bit RW Register */
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#define PATTERN_WAIT_TIMER_0_LSB_REG (0x1100 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_TIMER_0_MSB_REG (0x1101 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Pattern Wait 0 RW Register*/
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#define PATTERN_WAIT_0_ADDR_REG (0x188 + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_0_ADDR_REG (0x1102 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_0_ADDR_OFST (0)
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#define PATTERN_WAIT_0_ADDR_MSK (0x00001FFF << PATTERN_WAIT_0_ADDR_OFST)
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/* Pattern Wait 1 RW Register*/
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#define PATTERN_WAIT_1_ADDR_REG (0x19C + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_1_ADDR_OFST (0)
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#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
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/* Pattern Wait 2 RW Register*/
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#define PATTERN_WAIT_2_ADDR_REG (0x1B0 + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_2_ADDR_OFST (0)
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#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
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/* Pattern Wait Timer 0 64bit RW Register */
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#define PATTERN_WAIT_TIMER_0_LSB_REG (0x180 + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_TIMER_0_MSB_REG (0x184 + BASE_PATTERN_CONTROL)
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/* Pattern Wait Timer 1 64bit RW Register */
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#define PATTERN_WAIT_TIMER_1_LSB_REG (0x194 + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_TIMER_1_MSB_REG (0x198 + BASE_PATTERN_CONTROL)
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/* Pattern Wait Timer 2 64bit RW Register */
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#define PATTERN_WAIT_TIMER_2_LSB_REG (0x1A8 + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_TIMER_2_MSB_REG (0x1AC + BASE_PATTERN_CONTROL)
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/* Pattern Loop 0 Iteration RW Register */
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#define PATTERN_LOOP_0_ITERATION_REG (0x1103 * REG_OFFSET + BASE_PATTERN_CONTROL) // patnloop
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/* Pattern Loop 0 Address RW Register */
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#define PATTERN_LOOP_0_ADDR_REG (0x190 + BASE_PATTERN_CONTROL)
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#define PATTERN_LOOP_0_ADDR_REG (0x1104 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_LOOP_0_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_0_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STRT_OFST)
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#define PATTERN_LOOP_0_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_0_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_0_ADDR_STP_OFST)
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/* Pattern Wait Timer 1 64bit RW Register */
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#define PATTERN_WAIT_TIMER_1_LSB_REG (0x1105 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_TIMER_1_MSB_REG (0x1106 * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Pattern Wait 1 RW Register*/
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#define PATTERN_WAIT_1_ADDR_REG (0x1107 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_1_ADDR_OFST (0)
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#define PATTERN_WAIT_1_ADDR_MSK (0x00001FFF << PATTERN_WAIT_1_ADDR_OFST)
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/* Pattern Loop 1 Iteration RW Register */
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#define PATTERN_LOOP_1_ITERATION_REG (0x1108 * REG_OFFSET + BASE_PATTERN_CONTROL) // patnloop
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/* Pattern Loop 1 Address RW Register */
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#define PATTERN_LOOP_1_ADDR_REG (0x1A4 + BASE_PATTERN_CONTROL)
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#define PATTERN_LOOP_1_ADDR_REG (0x1109 * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_LOOP_1_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_1_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STRT_OFST)
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#define PATTERN_LOOP_1_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_1_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_1_ADDR_STP_OFST)
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/* Pattern Wait Timer 2 64bit RW Register */
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#define PATTERN_WAIT_TIMER_2_LSB_REG (0x110A * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_TIMER_2_MSB_REG (0x110B * REG_OFFSET + BASE_PATTERN_CONTROL)
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/* Pattern Wait 2 RW Register*/
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#define PATTERN_WAIT_2_ADDR_REG (0x110C * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_WAIT_2_ADDR_OFST (0)
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#define PATTERN_WAIT_2_ADDR_MSK (0x00001FFF << PATTERN_WAIT_2_ADDR_OFST)
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/* Pattern Loop 2 Iteration RW Register */
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#define PATTERN_LOOP_2_ITERATION_REG (0x110D * REG_OFFSET + BASE_PATTERN_CONTROL) // patnloop
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/* Pattern Loop 0 Address RW Register */
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#define PATTERN_LOOP_2_ADDR_REG (0x1B8 + BASE_PATTERN_CONTROL)
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#define PATTERN_LOOP_2_ADDR_REG (0x110E * REG_OFFSET + BASE_PATTERN_CONTROL)
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#define PATTERN_LOOP_2_ADDR_STRT_OFST (0)
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#define PATTERN_LOOP_2_ADDR_STRT_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STRT_OFST)
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#define PATTERN_LOOP_2_ADDR_STP_OFST (16)
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#define PATTERN_LOOP_2_ADDR_STP_MSK (0x00001FFF << PATTERN_LOOP_2_ADDR_STP_OFST)
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/* Pattern Loop 0 Iteration RW Register */
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#define PATTERN_LOOP_0_ITERATION_REG (0x18C + BASE_PATTERN_CONTROL) // patnloop
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/* Pattern Loop 1 Iteration RW Register */
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#define PATTERN_LOOP_1_ITERATION_REG (0x1A0 + BASE_PATTERN_CONTROL) // patnloop
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/* Pattern Loop 2 Iteration RW Register */
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#define PATTERN_LOOP_2_ITERATION_REG (0x1B4 + BASE_PATTERN_CONTROL) // patnloop
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/* Register of first word */
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#define PATTERN_STEP0_LSB_REG (0x0 + BASE_PATTERN_RAM)
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#define PATTERN_STEP0_MSB_REG (0x4 + BASE_PATTERN_RAM)
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#define PATTERN_STEP0_LSB_REG (0x0 * REG_OFFSET + BASE_PATTERN_RAM)
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#define PATTERN_STEP0_MSB_REG (0x1 * REG_OFFSET + BASE_PATTERN_RAM)
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Binary file not shown.
@ -3,6 +3,7 @@
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#include "clogger.h"
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#include "nios.h"
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#include "DAC6571.h"
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#include "LTC2620_Driver.h"
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#include "common.h"
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#include "RegisterDefs.h"
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@ -36,6 +37,7 @@ int32_t clkPhase[NUM_CLOCKS] = {0, 0, 0};
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uint32_t clkDivider[NUM_CLOCKS] = {125, 20, 80};
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int highvoltage = 0;
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int dacValues[NDAC] = {0};
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int detPos[2] = {0, 0};
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int isFirmwareCheckDone() {
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@ -74,7 +76,7 @@ void basictests() {
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return;
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}
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// does check only if flag is 0 (by default), set by command line
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if ((!debugflag) && ((testFpga() == FAIL))) {
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if ((!debugflag) && ((testFpga() == FAIL)|| (testBus() == FAIL))) {
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strcpy(firmware_message,
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"Could not pass basic tests of FPGA and bus. Dangerous to continue.\n");
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FILE_LOG(logERROR, ("%s\n\n", firmware_message));
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@ -82,19 +84,98 @@ void basictests() {
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firmware_check_done = 1;
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return;
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}
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uint16_t hversion = getHardwareVersionNumber();
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uint32_t ipadd = getDetectorIP();
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uint64_t macadd = getDetectorMAC();
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int64_t fwversion = getDetectorId(DETECTOR_FIRMWARE_VERSION);
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int64_t swversion = getDetectorId(DETECTOR_SOFTWARE_VERSION);
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int64_t sw_fw_apiversion = 0;
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int64_t client_sw_apiversion = getDetectorId(CLIENT_SOFTWARE_API_VERSION);
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uint32_t requiredFirmwareVersion = REQRD_FRMWRE_VRSN;
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if (fwversion >= MIN_REQRD_VRSN_T_RD_API)
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sw_fw_apiversion = getDetectorId(SOFTWARE_FIRMWARE_API_VERSION);
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FILE_LOG(logINFOBLUE, ("************ Mythen3 Server *********************\n"
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"Hardware Version:\t\t 0x%x\n"
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"Detector IP Addr:\t\t 0x%x\n"
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"Detector MAC Addr:\t\t 0x%llx\n\n"
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"Firmware Version:\t\t 0x%llx\n"
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"Software Version:\t\t 0x%llx\n"
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"F/w-S/w API Version:\t\t 0x%llx\n"
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"Required Firmware Version:\t 0x%x\n"
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"Client-Software API Version:\t 0x%llx\n"
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"********************************************************\n",
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hversion,
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ipadd,
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(long long unsigned int)macadd,
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(long long int)fwversion,
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(long long int)swversion,
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(long long int)sw_fw_apiversion,
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requiredFirmwareVersion,
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(long long int)client_sw_apiversion
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));
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// return if flag is not zero, debug mode
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if (debugflag) {
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firmware_check_done = 1;
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return;
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}
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//cant read versions
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FILE_LOG(logINFO, ("Testing Firmware-software compatibility:\n"));
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if(!fwversion || !sw_fw_apiversion){
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strcpy(firmware_message,
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"Cant read versions from FPGA. Please update firmware.\n");
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FILE_LOG(logERROR, (firmware_message));
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firmware_compatibility = FAIL;
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firmware_check_done = 1;
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return;
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}
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//check for API compatibility - old server
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if(sw_fw_apiversion > requiredFirmwareVersion){
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sprintf(firmware_message,
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"This detector software software version (0x%llx) is incompatible.\n"
|
||||
"Please update detector software (min. 0x%llx) to be compatible with this firmware.\n",
|
||||
(long long int)sw_fw_apiversion,
|
||||
(long long int)requiredFirmwareVersion);
|
||||
FILE_LOG(logERROR, (firmware_message));
|
||||
firmware_compatibility = FAIL;
|
||||
firmware_check_done = 1;
|
||||
return;
|
||||
}
|
||||
|
||||
//check for firmware compatibility - old firmware
|
||||
if( requiredFirmwareVersion > fwversion) {
|
||||
sprintf(firmware_message,
|
||||
"This firmware version (0x%llx) is incompatible.\n"
|
||||
"Please update firmware (min. 0x%llx) to be compatible with this server.\n",
|
||||
(long long int)fwversion,
|
||||
(long long int)requiredFirmwareVersion);
|
||||
FILE_LOG(logERROR, (firmware_message));
|
||||
firmware_compatibility = FAIL;
|
||||
firmware_check_done = 1;
|
||||
return;
|
||||
}
|
||||
FILE_LOG(logINFO, ("Compatibility - success\n"));
|
||||
firmware_check_done = 1;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
int checkType() {
|
||||
#ifdef VIRTUAL
|
||||
return OK;
|
||||
#endif
|
||||
volatile u_int32_t type = ((bus_r(FPGA_VERSION_REG) & DETECTOR_TYPE_MSK) >> DETECTOR_TYPE_OFST);
|
||||
if (type != MYTHEN3){
|
||||
FILE_LOG(logERROR, ("This is not a Mythen3 Server (read %d, expected %d)\n", type, MYTHEN3));
|
||||
return FAIL;
|
||||
}
|
||||
FILE_LOG(logERROR, ("This is not a Mythen3 Server (read %d, expected %d)\n", type, MYTHEN3));
|
||||
return FAIL;
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
@ -117,6 +198,34 @@ int testFpga() {
|
||||
return ret;
|
||||
}
|
||||
|
||||
int testBus() {
|
||||
#ifdef VIRTUAL
|
||||
return OK;
|
||||
#endif
|
||||
FILE_LOG(logINFO, ("Testing Bus:\n"));
|
||||
|
||||
int ret = OK;
|
||||
u_int32_t addr = DTA_OFFSET_REG;
|
||||
int times = 1000 * 1000;
|
||||
int i = 0;
|
||||
|
||||
for (i = 0; i < times; ++i) {
|
||||
bus_w(addr, i * 100);
|
||||
if (i * 100 != bus_r(addr)) {
|
||||
FILE_LOG(logERROR, ("Mismatch! Wrote 0x%x, read 0x%x\n",
|
||||
i * 100, bus_r(addr)));
|
||||
ret = FAIL;
|
||||
}
|
||||
}
|
||||
|
||||
bus_w(addr, 0);
|
||||
|
||||
if (ret == OK) {
|
||||
FILE_LOG(logINFO, ("Successfully tested bus %d times\n", times));
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* Ids */
|
||||
|
||||
int64_t getDetectorId(enum idMode arg){
|
||||
@ -141,21 +250,28 @@ u_int64_t getFirmwareVersion() {
|
||||
#ifdef VIRTUAL
|
||||
return 0;
|
||||
#endif
|
||||
return 0;
|
||||
return ((bus_r(FPGA_VERSION_REG) & FPGA_COMPILATION_DATE_MSK) >> FPGA_COMPILATION_DATE_OFST);
|
||||
}
|
||||
|
||||
u_int64_t getFirmwareAPIVersion() {
|
||||
#ifdef VIRTUAL
|
||||
return 0;
|
||||
#endif
|
||||
return ((bus_r(API_VERSION_REG) & API_VERSION_MSK) >> API_VERSION_OFST);
|
||||
}
|
||||
|
||||
u_int16_t getHardwareVersionNumber() {
|
||||
#ifdef VIRTUAL
|
||||
return 0;
|
||||
#endif
|
||||
return bus_r(MCB_SERIAL_NO_REG);
|
||||
}
|
||||
|
||||
u_int32_t getDetectorNumber(){
|
||||
#ifdef VIRTUAL
|
||||
return 0;
|
||||
#endif
|
||||
return 0;
|
||||
return bus_r(MCB_SERIAL_NO_REG);
|
||||
}
|
||||
|
||||
|
||||
@ -236,8 +352,11 @@ void setupDetector() {
|
||||
#ifndef VIRTUAL
|
||||
// hv
|
||||
DAC6571_SetDefines(HV_HARD_MAX_VOLTAGE, HV_DRIVER_FILE_NAME);
|
||||
//dac
|
||||
LTC2620_D_SetDefines(DAC_MAX_MV, DAC_DRIVER_FILE_NAME, NDAC);
|
||||
#endif
|
||||
setHighVoltage(DEFAULT_HIGH_VOLTAGE);
|
||||
setDefaultDacs();
|
||||
|
||||
// Initialization of acquistion parameters
|
||||
setTimer(FRAME_NUMBER, DEFAULT_NUM_FRAMES);
|
||||
@ -246,9 +365,23 @@ void setupDetector() {
|
||||
setTimer(ACQUISITION_TIME, DEFAULT_EXPTIME);
|
||||
setTimer(FRAME_PERIOD, DEFAULT_PERIOD);
|
||||
setTimer(DELAY_AFTER_TRIGGER, DEFAULT_DELAY_AFTER_TRIGGER);
|
||||
|
||||
}
|
||||
|
||||
int setDefaultDacs() {
|
||||
int ret = OK;
|
||||
FILE_LOG(logINFOBLUE, ("Setting Default Dac values\n"));
|
||||
{
|
||||
int i = 0;
|
||||
const int defaultvals[NDAC] = DEFAULT_DAC_VALS;
|
||||
for(i = 0; i < NDAC; ++i) {
|
||||
// if not already default, set it to default
|
||||
if (dacValues[i] != defaultvals[i]) {
|
||||
setDAC((enum DACINDEX)i,defaultvals[i],0);
|
||||
}
|
||||
}
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
/* set parameters - dr, roi */
|
||||
|
||||
@ -351,7 +484,8 @@ int validateTimer(enum timerIndex ind, int64_t val, int64_t retval) {
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return OK;
|
||||
return OK;
|
||||
|
||||
}
|
||||
|
||||
|
||||
@ -379,6 +513,44 @@ int64_t getTimeLeft(enum timerIndex ind){
|
||||
return retval;
|
||||
}
|
||||
|
||||
|
||||
/* parameters - dac, hv */
|
||||
void setDAC(enum DACINDEX ind, int val, int mV) {
|
||||
if (val < 0)
|
||||
return;
|
||||
|
||||
FILE_LOG(logDEBUG1, ("Setting dac[%d]: %d %s \n", (int)ind, val, (mV ? "mV" : "dac units")));
|
||||
int dacval = val;
|
||||
#ifdef VIRTUAL
|
||||
if (!mV) {
|
||||
dacValues[ind] = val;
|
||||
}
|
||||
// convert to dac units
|
||||
else if (LTC2620_D_VoltageToDac(val, &dacval) == OK) {
|
||||
dacValues[ind] = dacval;
|
||||
}
|
||||
#else
|
||||
if (LTC2620_D_SetDACValue((int)ind, val, mV, &dacval) == OK) {
|
||||
dacValues[ind] = dacval;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
int getDAC(enum DACINDEX ind, int mV) {
|
||||
if (!mV) {
|
||||
FILE_LOG(logDEBUG1, ("Getting DAC %d : %d dac\n",ind, dacValues[ind]));
|
||||
return dacValues[ind];
|
||||
}
|
||||
int voltage = -1;
|
||||
LTC2620_D_DacToVoltage(dacValues[ind], &voltage);
|
||||
FILE_LOG(logDEBUG1, ("Getting DAC %d : %d dac (%d mV)\n",ind, dacValues[ind], voltage));
|
||||
return voltage;
|
||||
}
|
||||
|
||||
int getMaxDacSteps() {
|
||||
return LTC2620_D_GetMaxNumSteps();
|
||||
}
|
||||
|
||||
int setHighVoltage(int val){
|
||||
// limit values
|
||||
if (val > HV_SOFT_MAX_VOLTAGE ) {
|
||||
@ -401,10 +573,15 @@ int setHighVoltage(int val){
|
||||
|
||||
|
||||
int configureMAC() {
|
||||
#ifdef VIRTUAL
|
||||
uint32_t dstip = udpDetails.dstip;
|
||||
int dstport = udpDetails.dstport;
|
||||
|
||||
uint32_t srcip = udpDetails.srcip;
|
||||
uint32_t dstip = udpDetails.dstip;
|
||||
uint64_t srcmac = udpDetails.srcmac;
|
||||
uint64_t dstmac = udpDetails.dstmac;
|
||||
int srcport = udpDetails.srcport;
|
||||
int dstport = udpDetails.dstport;
|
||||
|
||||
#ifdef VIRTUAL
|
||||
char cDestIp[MAX_STR_LENGTH];
|
||||
memset(cDestIp, 0, MAX_STR_LENGTH);
|
||||
sprintf(cDestIp, "%d.%d.%d.%d", (dstip>>24)&0xff,(dstip>>16)&0xff,(dstip>>8)&0xff,(dstip)&0xff);
|
||||
@ -414,9 +591,108 @@ int configureMAC() {
|
||||
return FAIL;
|
||||
}
|
||||
#endif
|
||||
FILE_LOG(logINFOBLUE, ("Configuring MAC\n"));
|
||||
|
||||
FILE_LOG(logINFO, ("\tSource IP : %d.%d.%d.%d \t\t(0x%08x)\n",
|
||||
(srcip>>24)&0xff,(srcip>>16)&0xff,(srcip>>8)&0xff,(srcip)&0xff, srcip));
|
||||
FILE_LOG(logINFO, ("\tSource MAC : %02x:%02x:%02x:%02x:%02x:%02x \t(0x%010llx)\n",
|
||||
(unsigned int)((srcmac>>40)&0xFF),
|
||||
(unsigned int)((srcmac>>32)&0xFF),
|
||||
(unsigned int)((srcmac>>24)&0xFF),
|
||||
(unsigned int)((srcmac>>16)&0xFF),
|
||||
(unsigned int)((srcmac>>8)&0xFF),
|
||||
(unsigned int)((srcmac>>0)&0xFF),
|
||||
(long long unsigned int)srcmac));
|
||||
FILE_LOG(logINFO, ("\tSource Port : %d \t\t\t(0x%08x)\n", srcport, srcport));
|
||||
|
||||
FILE_LOG(logINFO, ("\tDest. IP : %d.%d.%d.%d \t\t(0x%08x)\n",
|
||||
(dstip>>24)&0xff,(dstip>>16)&0xff,(dstip>>8)&0xff,(dstip)&0xff, dstip));
|
||||
FILE_LOG(logINFO, ("\tDest. MAC : %02x:%02x:%02x:%02x:%02x:%02x \t(0x%010llx)\n",
|
||||
(unsigned int)((dstmac>>40)&0xFF),
|
||||
(unsigned int)((dstmac>>32)&0xFF),
|
||||
(unsigned int)((dstmac>>24)&0xFF),
|
||||
(unsigned int)((dstmac>>16)&0xFF),
|
||||
(unsigned int)((dstmac>>8)&0xFF),
|
||||
(unsigned int)((dstmac>>0)&0xFF),
|
||||
(long long unsigned int)dstmac));
|
||||
FILE_LOG(logINFO, ("\tDest. Port : %d \t\t\t(0x%08x)\n\n",dstport, dstport));
|
||||
|
||||
// start addr
|
||||
uint32_t addr = BASE_UDP_RAM;
|
||||
// calculate rxr endpoint offset
|
||||
//addr += (iRxEntry * RXR_ENDPOINT_OFST);//TODO: is there round robin already implemented?
|
||||
// get struct memory
|
||||
udp_header *udp = (udp_header*) (Nios_getBaseAddress() + addr/(sizeof(u_int32_t)));
|
||||
memset(udp, 0, sizeof(udp_header));
|
||||
|
||||
// mac addresses
|
||||
// msb (32) + lsb (16)
|
||||
udp->udp_destmac_msb = ((dstmac >> 16) & BIT32_MASK);
|
||||
udp->udp_destmac_lsb = ((dstmac >> 0) & BIT16_MASK);
|
||||
// msb (16) + lsb (32)
|
||||
udp->udp_srcmac_msb = ((srcmac >> 32) & BIT16_MASK);
|
||||
udp->udp_srcmac_lsb = ((srcmac >> 0) & BIT32_MASK);
|
||||
|
||||
// ip addresses
|
||||
udp->ip_srcip_msb = ((srcip >> 16) & BIT16_MASK);
|
||||
udp->ip_srcip_lsb = ((srcip >> 0) & BIT16_MASK);
|
||||
udp->ip_destip_msb = ((dstip >> 16) & BIT16_MASK);
|
||||
udp->ip_destip_lsb = ((dstip >> 0) & BIT16_MASK);
|
||||
|
||||
// source port
|
||||
udp->udp_srcport = srcport;
|
||||
udp->udp_destport = dstport;
|
||||
|
||||
// other defines
|
||||
udp->udp_ethertype = 0x800;
|
||||
udp->ip_ver = 0x4;
|
||||
udp->ip_ihl = 0x5;
|
||||
udp->ip_flags = 0x2; //FIXME
|
||||
udp->ip_ttl = 0x40;
|
||||
udp->ip_protocol = 0x11;
|
||||
// total length is redefined in firmware
|
||||
|
||||
// calcChecksum(udp);
|
||||
|
||||
//TODO?
|
||||
//cleanFifos();
|
||||
//resetCore();
|
||||
//alignDeserializer();
|
||||
return OK;
|
||||
}
|
||||
|
||||
void calcChecksum(udp_header* udp) {
|
||||
int count = IP_HEADER_SIZE;
|
||||
long int sum = 0;
|
||||
|
||||
// start at ip_tos as the memory is not continous for ip header
|
||||
uint16_t *addr = (uint16_t*) (&(udp->ip_tos));
|
||||
|
||||
sum += *addr++;
|
||||
count -= 2;
|
||||
|
||||
// ignore ethertype (from udp header)
|
||||
addr++;
|
||||
|
||||
// from identification to srcip_lsb
|
||||
while( count > 2 ) {
|
||||
sum += *addr++;
|
||||
count -= 2;
|
||||
}
|
||||
|
||||
// ignore src udp port (from udp header)
|
||||
addr++;
|
||||
|
||||
if (count > 0)
|
||||
sum += *addr; // Add left-over byte, if any
|
||||
while (sum >> 16)
|
||||
sum = (sum & 0xffff) + (sum >> 16);// Fold 32-bit sum to 16 bits
|
||||
long int checksum = sum & 0xffff;
|
||||
checksum += UDP_IP_HEADER_LENGTH_BYTES;
|
||||
FILE_LOG(logINFO, ("\tIP checksum is 0x%lx\n",checksum));
|
||||
udp->ip_checksum = checksum;
|
||||
}
|
||||
|
||||
/* pattern */
|
||||
|
||||
uint64_t readPatternWord(int addr) {
|
||||
@ -427,9 +703,9 @@ uint64_t readPatternWord(int addr) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
FILE_LOG(logINFORED, (" Reading (Executing) Pattern Word (addr:0x%x)\n", addr));
|
||||
uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr; // the first word in RAM as base plus the offset of the word to write (addr)
|
||||
uint32_t reg_msb = PATTERN_STEP0_MSB_REG + addr;
|
||||
FILE_LOG(logINFORED, (" Reading Pattern Word (addr:0x%x)\n", addr));
|
||||
uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr * REG_OFFSET * 2; // the first word in RAM as base plus the offset of the word to write (addr)
|
||||
uint32_t reg_msb = PATTERN_STEP0_MSB_REG + addr * REG_OFFSET * 2;
|
||||
|
||||
// read value
|
||||
uint64_t retval = get64BitReg(reg_lsb, reg_msb);
|
||||
@ -451,8 +727,8 @@ uint64_t writePatternWord(int addr, uint64_t word) {
|
||||
}
|
||||
|
||||
FILE_LOG(logINFO, ("Setting Pattern Word (addr:0x%x, word:0x%llx)\n", addr, (long long int) word));
|
||||
uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr; // the first word in RAM as base plus the offset of the word to write (addr)
|
||||
uint32_t reg_msb = PATTERN_STEP0_MSB_REG + addr;
|
||||
uint32_t reg_lsb = PATTERN_STEP0_LSB_REG + addr * REG_OFFSET * 2; // the first word in RAM as base plus the offset of the word to write (addr)
|
||||
uint32_t reg_msb = PATTERN_STEP0_MSB_REG + addr * REG_OFFSET * 2;
|
||||
|
||||
// write word
|
||||
set64BitReg(word, reg_lsb, reg_msb);
|
||||
@ -503,7 +779,7 @@ int setPatternWaitAddress(int level, int addr) {
|
||||
}
|
||||
|
||||
// get
|
||||
uint32_t regval = bus_r((reg & mask) >> offset);
|
||||
uint32_t regval = ((bus_r(reg) & mask) >> offset);
|
||||
FILE_LOG(logDEBUG1, (" Wait Address retval (level:%d, addr:0x%x)\n", level, regval));
|
||||
return regval;
|
||||
}
|
||||
|
||||
@ -1,6 +1,8 @@
|
||||
#pragma once
|
||||
#include "sls_detector_defs.h"
|
||||
|
||||
#define REQRD_FRMWRE_VRSN 0x190000
|
||||
#define MIN_REQRD_VRSN_T_RD_API 0x190000
|
||||
|
||||
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
|
||||
|
||||
@ -11,6 +13,8 @@
|
||||
#define HV_SOFT_MAX_VOLTAGE (200)
|
||||
#define HV_HARD_MAX_VOLTAGE (530)
|
||||
#define HV_DRIVER_FILE_NAME ("/etc/devlinks/hvdac")
|
||||
#define DAC_DRIVER_FILE_NAME ("/etc/devlinks/dac")
|
||||
#define DAC_MAX_MV (2048)
|
||||
|
||||
/** Default Parameters */
|
||||
#define DEFAULT_NUM_FRAMES (1)
|
||||
@ -23,29 +27,58 @@
|
||||
#define DEFAULT_TICK_CLK (20) // will be fixed later. Not configurable
|
||||
#define DEFAULT_SAMPLING_CLK (80)
|
||||
|
||||
/* Firmware Definitions */
|
||||
#define IP_HEADER_SIZE (20)
|
||||
|
||||
/** Other Definitions */
|
||||
#define BIT16_MASK (0xFFFF)
|
||||
|
||||
/* Enums */
|
||||
enum CLKINDEX {RUN_CLK, TICK_CLK, SAMPLING_CLK, NUM_CLOCKS};
|
||||
enum DACINDEX {VIBIASSH, VTRIM, VIPRE, VRFSHNPOL, VTH1, VIPREOUT, VRF, VTH2, CAS, CASSH, VPL, VDCSH, VICIN, VICINSH, VICBIAS, VPH, VTH3, VRFSH};
|
||||
#define DEFAULT_DAC_VALS {1200, /* vIbiasSh */ \
|
||||
2300, /* vTrim */ \
|
||||
2150, /* vIpre */ \
|
||||
2300, /* VrfShNpol */ \
|
||||
900, /* Vth1 */ \
|
||||
1000, /* vIpreOut */ \
|
||||
900, /* Vrf */ \
|
||||
900, /* Vth2 */ \
|
||||
1474, /* cas */ \
|
||||
983, /* casSh */ \
|
||||
900, /* VPL */ \
|
||||
655, /* VdcSh */ \
|
||||
1400, /* vIcin */ \
|
||||
1400, /* vIcinSh */ \
|
||||
1200, /* vIcbias */ \
|
||||
960, /* VPH */ \
|
||||
900, /* Vth3 */ \
|
||||
1100 /* VrfSh */ \
|
||||
enum DACINDEX {CASSH, VTH2, VRFSH, VRFSHNPOL, VIPREOUT, VTH3, VTH1, VICIN, CAS, VRF, VPH, VIPRE, VIINSH, VPL, VTRIM, VDCSH};
|
||||
#define DEFAULT_DAC_VALS {1200, /* casSh */ \
|
||||
2800, /* Vth2 */ \
|
||||
1280, /* VrfSh */ \
|
||||
2800, /* VrfShNpol */ \
|
||||
1220, /* vIpreOut */ \
|
||||
2800, /* Vth3 */ \
|
||||
2800, /* Vth1 */ \
|
||||
1708, /* vIcin */ \
|
||||
1800, /* cas */ \
|
||||
1100, /* Vrf */ \
|
||||
1712, /* VPH */ \
|
||||
2624, /* vIpre */ \
|
||||
1708, /* vIinSh */ \
|
||||
1100, /* VPL */ \
|
||||
2800, /* vTrim */ \
|
||||
800 /* VdcSh */ \
|
||||
};
|
||||
|
||||
|
||||
/* Defines in the Firmware */
|
||||
#define MAX_PATTERN_LENGTH (0x8192) // maximum number of words (64bit)
|
||||
#define MAX_PATTERN_LENGTH (0x2000) // maximum number of words (64bit)
|
||||
|
||||
/* Struct Definitions */
|
||||
typedef struct udp_header_struct {
|
||||
uint32_t udp_destmac_msb;
|
||||
uint16_t udp_srcmac_msb;
|
||||
uint16_t udp_destmac_lsb;
|
||||
uint32_t udp_srcmac_lsb;
|
||||
uint8_t ip_tos;
|
||||
uint8_t ip_ihl: 4, ip_ver: 4;
|
||||
uint16_t udp_ethertype;
|
||||
uint16_t ip_identification;
|
||||
uint16_t ip_totallength;
|
||||
uint8_t ip_protocol;
|
||||
uint8_t ip_ttl;
|
||||
uint16_t ip_fragmentoffset: 13, ip_flags: 3;
|
||||
uint16_t ip_srcip_msb;
|
||||
uint16_t ip_checksum;
|
||||
uint16_t ip_destip_msb;
|
||||
uint16_t ip_srcip_lsb;
|
||||
uint16_t udp_srcport;
|
||||
uint16_t ip_destip_lsb;
|
||||
uint16_t udp_checksum;
|
||||
uint16_t udp_destport;
|
||||
} udp_header;
|
||||
#define UDP_IP_HEADER_LENGTH_BYTES (28)
|
||||
Reference in New Issue
Block a user