mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 18:17:59 +02:00
moench speeds (#776)
* added other speeds and updated readoutspeedlist, test, gui
This commit is contained in:
@ -167,6 +167,11 @@
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#define CONFIG_OPRTN_MDE_2_X_10GbE_MSK (0x00000001 << CONFIG_OPRTN_MDE_2_X_10GbE_OFST)
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#define CONFIG_INNR_PRIMRY_INTRFCE_OFST (17)
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#define CONFIG_INNR_PRIMRY_INTRFCE_MSK (0x00000001 << CONFIG_INNR_PRIMRY_INTRFCE_OFST)
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#define CONFIG_READOUT_SPEED_OFST (20)
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#define CONFIG_READOUT_SPEED_MSK (0x00000003 << CONFIG_READOUT_SPEED_OFST)
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#define CONFIG_QUARTER_SPEED_10MHZ_VAL ((0x0 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
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#define CONFIG_HALF_SPEED_20MHZ_VAL ((0x1 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
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#define CONFIG_FULL_SPEED_40MHZ_VAL ((0x2 << CONFIG_READOUT_SPEED_OFST) & CONFIG_READOUT_SPEED_MSK)
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#define CONFIG_TDMA_ENABLE_OFST (24)
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#define CONFIG_TDMA_ENABLE_MSK (0x00000001 << CONFIG_TDMA_ENABLE_OFST)
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#define CONFIG_TDMA_TIMESLOT_OFST (25) // 1ms
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Binary file not shown.
@ -1411,23 +1411,37 @@ int setReadoutSpeed(int val) {
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// stop state machine if running
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if (runBusy()) {
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stopStateMachine();
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return FAIL;
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}
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if (isHardwareVersion_1_0()) {
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LOG(logERROR, ("Cannot set full speed. Not implemented for this pcb version (1.0)\n"));
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return FAIL;
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}
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uint32_t adcOfst = 0;
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uint32_t sampleAdcSpeed = 0;
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uint32_t adcPhase = 0;
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uint32_t config = 0;
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uint32_t sampleAdcDecimationFactor = 0;
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switch (val) {
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case FULL_SPEED:
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if (isHardwareVersion_1_0()) {
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LOG(logERROR, ("Cannot set full speed. Should not be here\n"));
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return FAIL;
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}
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LOG(logINFO, ("Setting Full Speed (40 MHz):\n"));
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sampleAdcSpeed = SAMPLE_ADC_FULL_SPEED;
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adcPhase = ADC_PHASE_DEG_FULL_SPEED;
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adcOfst = ADC_OFST_FULL_SPEED_VAL;
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config = CONFIG_FULL_SPEED_40MHZ_VAL;
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sampleAdcDecimationFactor = ADC_DECMT_FULL_SPEED
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<< SAMPLE_ADC_DECMT_FACTOR_OFST;
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break;
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case HALF_SPEED:
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LOG(logINFO, ("Setting Speed Speed (20 MHz):\n"));
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config = CONFIG_HALF_SPEED_20MHZ_VAL;
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sampleAdcDecimationFactor = ADC_DECMT_HALF_SPEED
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<< SAMPLE_ADC_DECMT_FACTOR_OFST;
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break;
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case QUARTER_SPEED:
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LOG(logINFO, ("Setting Quarter Speed (10 MHz):\n"));
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config = CONFIG_QUARTER_SPEED_10MHZ_VAL;
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sampleAdcDecimationFactor = ADC_DECMT_QUARTER_SPEED
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<< SAMPLE_ADC_DECMT_FACTOR_OFST;
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break;
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default:
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@ -1435,23 +1449,35 @@ int setReadoutSpeed(int val) {
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return FAIL;
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}
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bus_w(ADC_OFST_REG, (bus_r(ADC_OFST_REG) & ~ADC_OFFSET_MSK));
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bus_w(ADC_OFST_REG, (bus_r(ADC_OFST_REG) |
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((adcOfst << ADC_OFFSET_OFST) & ADC_OFFSET_MSK)));
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LOG(logINFO, ("\tSet ADC Ofst Reg to 0x%x\n",
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((bus_r(ADC_OFST_REG) & ADC_OFFSET_MSK) >> ADC_OFFSET_OFST)));
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bus_w(CONFIG_REG, bus_r(CONFIG_REG) & ~CONFIG_READOUT_SPEED_MSK);
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bus_w(CONFIG_REG, bus_r(CONFIG_REG) | config);
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LOG(logINFO, ("\tSet Config Reg to 0x%x\n", bus_r(CONFIG_REG)));
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bus_w(SAMPLE_REG, sampleAdcSpeed);
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bus_w(SAMPLE_REG, bus_r(SAMPLE_REG) & ~SAMPLE_ADC_DECMT_FACTOR_MSK);
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bus_w(SAMPLE_REG, bus_r(SAMPLE_REG) | sampleAdcDecimationFactor);
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LOG(logINFO, ("\tSet Sample Reg to 0x%x\n", bus_r(SAMPLE_REG)));
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setPhase(ADC_CLK, adcPhase, 1);
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LOG(logINFO, ("\tSet ADC Phase Reg to %d deg\n", adcPhase));
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// TODO: adcofst, adcphase?
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return OK;
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}
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int getReadoutSpeed(int *retval) {
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*retval = FULL_SPEED;
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u_int32_t speed = bus_r(CONFIG_REG) & CONFIG_READOUT_SPEED_MSK;
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switch (speed) {
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case CONFIG_FULL_SPEED_40MHZ_VAL:
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*retval = FULL_SPEED;
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break;
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case CONFIG_HALF_SPEED_20MHZ_VAL:
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*retval = HALF_SPEED;
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break;
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case CONFIG_QUARTER_SPEED_10MHZ_VAL:
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*retval = QUARTER_SPEED;
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break;
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default:
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LOG(logERROR, ("Unknown speed val: %d\n", speed));
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*retval = -1;
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return FAIL;
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}
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return OK;
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}
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@ -65,6 +65,10 @@
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#define MAX_PHASE_SHIFTS (240)
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#define BIT16_MASK (0xFFFF)
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#define ADC_DECMT_QUARTER_SPEED (0x3)
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#define ADC_DECMT_HALF_SPEED (0x1)
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#define ADC_DECMT_FULL_SPEED (0x0)
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// pipeline
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#define ADC_PORT_INVERT_VAL (0x55555555)
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@ -9438,10 +9438,8 @@ int set_readout_speed(int file_des) {
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switch (arg) {
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#if defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)
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case FULL_SPEED:
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#ifndef MOENCHD
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case HALF_SPEED:
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case QUARTER_SPEED:
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#endif
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#elif GOTTHARD2D
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case G2_108MHZ:
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case G2_144MHZ:
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