eiger server bug fix: read and write reg only wrote to the right fpga, fixed

This commit is contained in:
2018-12-03 10:55:32 +01:00
parent 2c08c1e7ce
commit 550ed4b1c2
4 changed files with 48 additions and 20 deletions

View File

@ -1,5 +1,5 @@
/** API versions */
#define APIRECEIVER 0x180823
#define APIEIGER 0x180820
#define APIEIGER 0x181130
#define APIJUNGFRAU 0x180823
#define APIGOTTHARD 0x181203