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10.0.0.rc (#1260)
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* alignedData now uses std::align_alloc

* imagedata is now allocated on the heap

* m3 server fix for trimbits and badchannels that are shifted by 1

* formatting

* binary in

* added check for proper memory allocation

* commenting out the example in receiver data call back changing size as it affects users using debugging mode to print out headers

* fixed warnings

* commenting out the example in receiver data call back changing size as it affects users using debugging mode to print out headers

* got rid of cast to uint64

* got rid of Reorder function

* added sanity check to only enable for chipttestboard and xilinx

* removed Gotthard stuff

* update the comment about how to modify data on a data call back from the receiver

* autogenerated commands and make format

* changed font size in GUI

* clang-format with clang-format version 17

* updated update_image_size in xilinx

* version number automated for python build

* mistakenly set version back to 0.0.0

* updated github workflow scripts to support automatic version numbering with environment variable

* managed to load VERSION file in yaml file - simplifies things

* saving changes in git workflow failed

* got typo in github workflow

* updatet regex pattern to support postfix

* normalized version to PEP 440 specification in update_version.py

* bug did not support version 0.0.0

* upgrading to c++17 from c++11 and patch command has to be found before applying patch on libzmq (#1195)

* Dev/allow localhost for virtual tests (#1190)

* remove the check for localhost being used in rx_hostname for python test for simulators, run rx_arping test only if hostname is not 'localhost'

* fix tests for fpath: cannot set back to empty anymore (empty is default)

* default rx_hostname arg = localhost, and default settings path =../../settingsdir

* changed virtual tests script for better printout on exceptions

* fix for catching generaltests exceptions and exiting instead of continuing

* fix minor

* fixed shared memeory tests to include current env and fixed prints for errors

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>

* added regex pattern matching to version in toml file

* Dev/gitea docker (#1194)

* gitea workflows for RH8 and RH9
* using our docker images

* version now supports . before postfix

* rough draft of test acquire of all detectors for frames caught and file size. ctb not included yet

* moved dbitoffset, dbitreorder and dbitlist to GeneralData

* added error message on receiver side, throw error

* removed log as error already printed

* added tests to check file size and frames caught with an acquire (virtual) for every detector

* minor printout removed

* typo fixed

* removed minor printout

* incorrect counter mask tested

* fix 10g adc enable mask, switched with 1g

* fixed hardcoded values of nchip nchan etc from detPArameters

* fixed ctb tests, need to fix in develoepr (if digital modfe not enabled, should not take into accoutn dbitlist or dbitoffset or dbitreorder

* only reorder bits if some sort of digital readout mode enabled

* trying to fix acquire for xilinx

* fix for xilinx ctb virtual

* alloweing all tests

* typo

* fix for slsreceiver killed but complaining for virtual tests with script

* fixed bug found by @AliceMazzoleni99 that for ctb server is still shown in pgrep -f if xilinx server running, so now the pid is killed and looking for any DetectorServer_virtual instead. also reset color coding after Log

* check if process running for kill -9 slsReceiver fail

* removed -9 to kill with cleanup

* frame synchonrizer fixes: typo of iterator for loop and zmg_msg_t list cleaned up before sending multi part zmq; test written for the frame synchronizer, test_simulator.py rewritten for more robustness and refactoring commonality between both scripts

* better error messageS

* minor

* typo

* moving the erasure of the fnum to after sending the zmg packets and also deleteing all old frames when end of acquisition

* fix bug in blackfin read access to firmware registers

* updates api version based on version file & converted shell script files to python

* updated all makefiles

* refactoring code and compiling binary

* formatting

* rewrote end() for StaticVector

* rearranged receiver topics, differentiated btween receiver variants and added info about slsFrameSynchronizer

* typo

* minor aesthetics

* minor

* added extra fs link and fixed execute_program warning

* and now with link

* updating pmods

* adresses review comments

* dummy commit for versionAPI

* formatted and updated versionAPI.h

* added expat to host section

* updated documentation for pip installation as well

* Dev/add numpy  (#1227)

* added numpy dependency
* added build specifications for python version and platform

* updates files/variants for pmods for 9.2.0 (#1233)

* tests for bool in ToString/StringTo (#1230)

- Added tests for ToString/StringTo<bool>
- Added overload for ToString of bool (previously went through int)

* added docs for SLSDETNAME (#1228)

* added docs for SLSDETNAME

* clarification on hostname

* added examples on module index

* fixes

* fixed typo

* Dev/update test framesynchronizer (#1221)

* raise an exception if the pull socket python script had errors at startup (for eg if pyzmq was not installed)

* minor changes that got lost in the merge of automate_version_part 2 PR

---------

Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>

* added workflow for python wheels

* wip

* formatting

* wip

* wip to parse vector of rois at command line

* wip

* first level test

* can get individual rois, but not connected to command yet

* rois shoudl work. left to implement tests for individual rois, create multiple datasets (1 for each roi) in the virutal data file. currently virutal dataset with roi is not implemented and a warning is given instead. wonder why since the inviduviaual roi files are clipped

* all tests pased

* minor

* fixed rx_roi for multi modules jungfrau , tests for eiger, multi modules jungfrau in x and 2 interfaces

* works for eiger as well

* switched to vector instead of std::array<ROI, 2>>, which prints extra [-1, -1] when theres only 1 udp interface

* wip

* fix for empty roi vectors (which shouldnt be) as you cant know if its all or not in roi

* wip: to map roi to virutal

* fix for eiger, added python test for testig roi in different module and detector type configurations

* wip, fails with master and virtual

* works for complete roi

* wip, works for a single roi

* works for all rois

* wip to fix tests

* 1d fixes

* rois test work on 1d as well

* check master file creation as well in rx_roi tests

* get rx_roi from metadata from rxr, cant reconstruct. fixed clear roi should give 1 roi min

* gui shows roi now

* format

* updated python bindings

* updated master file versions

* cmd generation and formatting

* minor fixes in command line and help

* minor

* doesnt happen anymore

* comment

* minor

* redundant getRxROI in Detector class for multi level and module level

* refactor cmd parsing (detid can be parsed directly)

* refactor cmd line

* refactor command line parsing of roi

* modified comments about ctb and xilinx not using roi

* refactoring

* refactorign

* refactoring wip

* wip refactoring

* formattin

* to avoid confusion, moved default initialized, single sized declared vector of roi to be created at setDetectorType

* pybind only 1 function for getRxROI

* command line help

* specified number of receiver error message

* minor comment

* refactored to take out repetitive code, need to adjust for slsMulti and slsFrameSync

* wip

* works, need to add tests

* made Commadnlineoptions into a class

* wip test

* fixed tests

* cleaning up properly , semaphore leaks, child process/thread throwing handled

* getuid issue on github workflow

* constexpr and checking if options object type is same

* unnecessary capture

* remove testing code, minor

* fixed help, -t for multi should not be supported as it never had it

* Formatting

* hdf5 definitions in test when not compiled with hdf5

* typo

* moved optstring and long options to the constructor

* raising a SIGINT when the child thread has an exception so that the parent thread can exit all the threads and clean up gracefully

* minor test typo

* check status of child exiting and use that to send sigint to all the child processes from the parent

* fixed validation in network_utils, added a tests to throw for port 65535 in test mode (option on for sls_use_tests), multi:parent process checks child process exit status to send sigint to others

* moving set signal handler to network utils

* readoutspeed in rx master file and  other master file inconsistencies (#1245)

readout speed added to json and h5 master files.
Also fixed master file inconsistencies

Sserver binaries
- update server binaries because readoutspeed needs to be sent to receiver with rx_hostname command

API
- added const to Detector class set/getburstmode

Python
- updated python bindings (burstmode const and roi arguments)

Cmd generation
- added pragma once in Caller.in.h as Caller is included in test files

m3: num channels due to #counters < 3
* workaround for m3 for messed up num channels (client always assumes all counters enabled and adds them to num channels), fix for hdf5

g2: exptime master file inconsistency
- exptime didnt match because of round of when setting burst mode (sets to a different clk divider)
- so updating actual time for all timers (exptime, period, subexptime etc, )  in Module class, get timer values from detector when setting it and then send to receiver to write in master file

ctb image size incorrect:
-  write actual size into master file and not the reserved size (digital reduces depending on dbit list and dbit offset)
- added a calculate ctb image size free function in generalData.h that is used there as well as for the tests.


master file inconsistencies
- refactored master attributes writing using templates
-    names changed to keep it consistent between json and hdf5 master file (Version, Pixels, Exposure Times, GateDelays, Acquisition Period, etc.)
-  datatypes changed to keep it simple where possible: imageSize, dynamicRange, tengiga, quad, readnrows, analog, analogsamples, digital, digitalsamples, dbitreorder, dbitoffset, transceivermask, transeiver, transceiversamples, countermask, gates =>int
- replacing "toString" with arrays, objects etc for eg for scan, rois, etc.
- json header always written (empty dataset or empty brackets)
- hdf5 needs const char* so have to convert strings to it, but taking care that strings exist prior to push_back
- master attributes (redundant string literals->error prone

tests for master file
- suppressed deprecated functions in rapidjson warnings just for the tests
- added slsREceiverSoftware/src to allow access to receiver_defs.h to test binary/hdf5 version
- refactored acquire tests by moving all the acquire tests from individual detector type files to a single one=test-Caller-acquire.cpp
- set some default settings (loadBasicSettings) for a basic acquire at load config part for the test_simulator python scripts. so minimum number of settings for detector to be set for any acquire tests.
- added tests to test master files for json and hdf5= test-Caller-master-attributes.cpp
- added option to add '-m' markers for tests using test_simulator python script

* doc: added inst on how to set persistentn NIC changes after reboot for each ethernet interface such as rx 4096, rx-usecs, adaptive-rx and gro etc.

* added permanent ethtool settings also for fedora or modern rhel

* troubleshooting doc: permanent changes for 10g pc tuning (#1247)

* doc: added inst on how to set persistentn NIC changes after reboot for each ethernet interface such as rx 4096, rx-usecs, adaptive-rx and gro etc.

* added permanent ethtool settings also for fedora or modern rhel

* ifcfg scripts still work on rhel8, just not preferred

* added dataformat for jungfrau

* eiger basic mod

* eiger doc done

* added moench

* done

* free shm exposed in python as free function and detector function

* minimum change

* added quad and updated about 1gbe/10gbe

* more info

* remove arguments info

* replacing commands with links

* minor

* detail explanation of eiger

* fixed imagesize ctb issue (out values not transferred, setting any dbit values was not recalculatign image size in generaldata)

* fixed ctb dbit clock changing period in tests as it was setting run clock instead

* python accessing freed shared memory object (#1253)

* added a 'isValid' member in shared memory (also updated shm version) with default true, any access to shared memory() checks also for validity. any free will set this to false and then unmap shm. Any access to shm will then check validity in python.

* fixed tests for shm

* added tests in python as well

---------

Co-authored-by: Alice <alice.mazzoleni@psi.ch>

* updated error message

* made markers argument in ParseArguments a boolean instead of an int

* removed relative path compared to where executable run in test script for settingsdir

* fix roi test

* updating versions (#1258)

* updating package version, client version, server versions. Renaming server versions, using hardlinks in serverBin. Removing ctb servers in serverBin. (#1259)

* fixed no interpolation mode for moench (#1262)

Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>

* fixed multi receiver and frames sync help throw of bad variant access (#1265)

* 1000/doc c standard (#1267)

* updated c++11 to c++17

* more about c++11 and updating readme

* updated documentation for receiver arguments and also making receiver constructor explicit

* minor fix for rxr err message

* fixed doc about gcc version

* 1000/release notes (#1269)

* updated firmware and server version in release notes

* release notes wip

* updated notes(prs done)

* updated release notes. wip

* Release notes

* minor

* minor fix

* 1000/doc architecture commands (#1271)

* sw architecture and setup commands

* 1000/shm free obsolete (#1273)

* freeing obsolete shm withoua a 'isValid' should access raw pointers. Need to move this all into the shm class

* fixed obsolete shm free issue

* minor

* ensuring the test works platform independent for size of int

* removed verify, update, fixed getUser to be a free function, generated commands, python bindings yet to do

* python bindings

* fixed tests

* minor

* minor

* format

* userdetails refinedg

* fixed caller test

* updated client api version (#1277)

* one doesnt need to open shared memory to call removesharedmemory, and calling hasMemoryvalid without opening will cause segfault (not used now, but could in the future)

* fix test on shm

* minor

* added image source files from draw.io to create the images (#1280)

* 1000/fix_actual_tests (#1282)

- fix acquire fail in tests (adcreg test)
- roi tests fail after overlapping invalid test and acquire after
- print udp dest mac in server properly
- fixed udp dst list get (server was not sending entry proper size to match proper struct size in client)
- updated server binaries and updated hard links in serverBin
- added documentation regarding gui:  zmqport and zmqip in terms of gui, rx_zmqstream
- removed print - probably ended there for debuggung

---------

Co-authored-by: Alice <alice.mazzoleni@psi.ch>

* 1000/fix_m3_tests (#1286)

* testing clkdiv one must ensure the exptime delay etc all are reset to the exact values for tests

* change dac max values for vth values for m3 in client side (set module

* 1000/doc_cmake (#1289)

* more detail documentation in installation

* more detail documentation in installation

* added links to api examples

* reverted back that vthreshold dacs in m3 have min and max as 200 and 2400 (#1294)

* update release notes and date (#1298)

---------

Co-authored-by: Mazzoleni Alice Francesca <mazzol_a@pc17378.psi.ch>
Co-authored-by: Erik Fröjdh <erik.frojdh@gmail.com>
Co-authored-by: AliceMazzoleni99 <alice.mazzoleni@psi.ch>
Co-authored-by: Martin Mueller <martin.mueller@psi.ch>
Co-authored-by: froejdh_e <erik.frojdh@psi.ch>
Co-authored-by: Anna Bergamaschi <anna.bergamaschi@psi.ch>
This commit is contained in:
maliakal_d
2025-09-10 11:13:36 +02:00
committed by GitHub
parent c10bc5e530
commit 54e4c46f02
253 changed files with 35062 additions and 32286 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
slsDetectorServers/CMakeLists.txt
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@@ -13,7 +13,6 @@ install(TARGETS slsProjectCSettings
add_subdirectory(ctbDetectorServer)
add_subdirectory(xilinx_ctbDetectorServer)
add_subdirectory(eigerDetectorServer)
add_subdirectory(gotthardDetectorServer)
add_subdirectory(jungfrauDetectorServer)
add_subdirectory(mythen3DetectorServer)
add_subdirectory(gotthard2DetectorServer)

1
slsDetectorServers/compileAllServers.sh
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@@ -2,7 +2,6 @@
# Copyright (C) 2021 Contributors to the SLS Detector Package
det_list=("ctbDetectorServer
gotthardDetectorServer
gotthard2DetectorServer
jungfrauDetectorServer
mythen3DetectorServer

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slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServer_developer Executable file
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slsDetectorServers/ctbDetectorServer/bin/ctbDetectorServerv9.1.0
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slsDetectorServers/ctbDetectorServer/slsDetectorFunctionList.c
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@@ -15,6 +15,8 @@
#include "loadPattern.h"
#include <netinet/in.h>
#include <stdio.h>
#include <stdlib.h>
#include <string.h>
#include <unistd.h> // usleep
#ifdef VIRTUAL
@@ -92,6 +94,10 @@ void basictests() {
LOG(logINFOBLUE, ("********* Chip Test Board Virtual Server *********\n"));
#else
LOG(logINFOBLUE, ("************* Chip Test Board Server *************\n"));
initError = enableBlackfinAMCExternalAccessExtension(initErrorMessage);
if (initError == FAIL) {
return;
}
initError = defineGPIOpins(initErrorMessage);
if (initError == FAIL) {
return;
@@ -437,6 +443,32 @@ uint32_t getDetectorIP() {
return res;
}
int enableBlackfinAMCExternalAccessExtension(char *mess) {
unsigned int value;
const char *file_path = BFIN_AMC_ACCESS_EXTENSION_FNAME;
FILE *file = fopen(file_path, "r");
if (!file) {
strcpy(mess, "Failed to enable blackfin AMC access extension. Could "
"not read EBIU_AMBCTL1\n");
LOG(logERROR, (mess));
return FAIL;
}
fscanf(file, "%x", &value);
fclose(file);
value |= BFIN_AMC_ACCESS_EXTENSION_ENA_VAL;
file = fopen(file_path, "w");
if (!file) {
strcpy(mess, "Failed to enable blackfin AMC access extension. Could "
"not write EBIU_AMBCTL1\n");
LOG(logERROR, (mess));
return FAIL;
}
fprintf(file, "0x%x", value);
fclose(file);
return OK;
}
/* initialization */
void initControlServer() {
@@ -1095,26 +1127,17 @@ int setNumTransceiverSamples(int val) {
int getNumTransceiverSamples() { return ntSamples; }
int setExpTime(int64_t val) {
if (val < 0) {
LOG(logERROR, ("Invalid exptime: %lld ns\n", (long long int)val));
return FAIL;
}
LOG(logINFO, ("Setting exptime %lld ns\n", (long long int)val));
val *= (1E-3 * clkFrequency[RUN_CLK]);
setPatternWaitTime(0, val);
setPatternWaitInterval(0, val);
// validate for tolerance
int64_t retval = getExpTime();
val /= (1E-3 * clkFrequency[RUN_CLK]);
if (val != retval) {
return FAIL;
}
return OK;
}
int64_t getExpTime() {
return getPatternWaitTime(0) / (1E-3 * clkFrequency[RUN_CLK]);
}
int64_t getExpTime() { return getPatternWaitInterval(0); }
int setPeriod(int64_t val) {
if (val < 0) {
@@ -2267,11 +2290,23 @@ void *start_timer(void *arg) {
int packetsPerFrame = ceil((double)imageSize / (double)dataSize);
// Generate Data
char imageData[imageSize];
char *imageData = (char *)malloc(imageSize);
memset(imageData, 0, imageSize);
if (imageData == NULL) {
LOG(logERROR, ("Can not allocate image Data RAM."
"Probable cause: Memory Leak.\n"));
return NULL;
}
/*
for (int i = 0; i < imageSize; i += sizeof(uint16_t)) {
*((uint16_t *)(imageData + i)) = i;
}
*/
for (int i = 0; i < imageSize; i += 2 * sizeof(uint64_t)) {
*((uint64_t *)(imageData + i)) = 0xffffffffffffffff;
}
// Send data
uint64_t frameNr = 0;
@@ -2328,6 +2363,8 @@ void *start_timer(void *arg) {
setNextFrameNumber(frameNr + numFrames);
}
free(imageData);
closeUDPSocket(0);
sharedMemory_setStatus(IDLE);

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slsDetectorServers/eigerDetectorServer/bin/eigerDetectorServerv10.0.0 Executable file
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slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServerv10.0.0 Executable file
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slsDetectorServers/gotthard2DetectorServer/bin/gotthard2DetectorServerv9.0.0
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slsDetectorServers/gotthardDetectorServer/.target-makefrag
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@@ -1 +0,0 @@
AXIS_BUILDTYPE ?= cris-axis-linux-gnu

45
slsDetectorServers/gotthardDetectorServer/CMakeLists.txt
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@@ -1,45 +0,0 @@
# SPDX-License-Identifier: LGPL-3.0-or-other
# Copyright (C) 2021 Contributors to the SLS Detector Package
add_executable(gotthardDetectorServer_virtual
slsDetectorFunctionList.c
../slsDetectorServer/src/slsDetectorServer.c
../slsDetectorServer/src/slsDetectorServer_funcs.c
../slsDetectorServer/src/communication_funcs.c
../slsDetectorServer/src/blackfin.c
../slsDetectorServer/src/AD9252.c
../slsDetectorServer/src/AD9257.c
../slsDetectorServer/src/LTC2620.c
../slsDetectorServer/src/common.c
../slsDetectorServer/src/commonServerFunctions.c
../slsDetectorServer/src/programViaBlackfin.c
../slsDetectorServer/src/communication_funcs_UDP.c
../slsDetectorServer/src/sharedMemory.c
../../slsSupportLib/src/md5.c
)
include_directories(
../slsDetectorServer/include
../../slsSupportLib/include
)
target_include_directories(gotthardDetectorServer_virtual
PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}
)
target_compile_definitions(gotthardDetectorServer_virtual
PUBLIC GOTTHARDD VIRTUAL STOP_SERVER
)
target_link_libraries(gotthardDetectorServer_virtual
PUBLIC pthread rt slsProjectCSettings
)
set_target_properties(gotthardDetectorServer_virtual PROPERTIES
RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin
)
install(TARGETS gotthardDetectorServer_virtual
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}
)
configure_file(config_gotthard.txt ${CMAKE_BINARY_DIR}/bin/config_gotthard.txt COPYONLY)

48
slsDetectorServers/gotthardDetectorServer/Makefile
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@@ -1,48 +0,0 @@
# SPDX-License-Identifier: LGPL-3.0-or-other
# Copyright (C) 2021 Contributors to the SLS Detector Package
current_dir = $(shell pwd)
main_inc = ../slsDetectorServer/include/
main_src = ../slsDetectorServer/src/
support_lib = ../../slsSupportLib/include/
md5_dir = ../../slsSupportLib/src/
CROSS = bfin-uclinux-
CC = $(CROSS)gcc
CFLAGS += -Wall -std=gnu99 -DGOTTHARDD -DSTOP_SERVER -I$(main_inc) -I$(support_lib) -I$(current_dir) #-DVERBOSEI #-DVERBOSE
LDLIBS += -lm -lrt -pthread
PROGS = gotthardDetectorServer
DESTDIR ?= bin
INSTMODE = 0777
SRCS = slsDetectorFunctionList.c
SRCS += $(main_src)slsDetectorServer.c $(main_src)slsDetectorServer_funcs.c $(main_src)communication_funcs.c $(main_src)blackfin.c $(main_src)AD9252.c $(main_src)AD9257.c $(main_src)LTC2620.c $(main_src)programViaBlackfin.c $(main_src)common.c $(main_src)commonServerFunctions.c $(main_src)/sharedMemory.c $(md5_dir)md5.c
OBJS = $(SRCS:.c=.o)
all: clean $(PROGS)
version: clean versioning $(PROGS)
boot: $(OBJS)
version_branch=$(API_BRANCH)
version_name=APIGOTTHARD
version_path=slsDetectorServers/gotthardDetectorServer
versioning:
cd ../../ && echo $(PWD) && echo `tput setaf 6; python updateAPIVersion.py $(version_name) $(version_path); tput sgr0;`
$(PROGS): $(OBJS)
# echo $(OBJS)
mkdir -p $(DESTDIR)
$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
mv $(PROGS) $(DESTDIR)
cp config_gotthard.txt $(DESTDIR)
rm *.gdb
rm $(main_src)*.o $(md5_dir)*.o
clean:
rm -rf $(DESTDIR)/$(PROGS) *.o *.gdb $(main_src)*.o $(md5_dir)*.o

394
slsDetectorServers/gotthardDetectorServer/RegisterDefs.h
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@@ -1,394 +0,0 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#pragma once
/* Definitions for FPGA*/
#define MEM_MAP_SHIFT (11)
/** Gain register */
#define GAIN_REG (0x10 << MEM_MAP_SHIFT)
#define GAIN_CONFGAIN_OFST (0)
#define GAIN_CONFGAIN_MSK (0x000000FF << GAIN_CONFGAIN_OFST)
#define GAIN_CONFGAIN_HGH_GAIN_VAL \
((0x0 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_DYNMC_GAIN_VAL \
((0x8 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_LW_GAIN_VAL \
((0x6 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_MDM_GAIN_VAL \
((0x2 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
#define GAIN_CONFGAIN_VRY_HGH_GAIN_VAL \
((0x1 << GAIN_CONFGAIN_OFST) & GAIN_CONFGAIN_MSK)
/** Flow Control register */
// #define FLOW_CONTROL_REG (0x11 << MEM_MAP_SHIFT)
/** Flow Status register */
// #define FLOW_STATUS_REG (0x12 << MEM_MAP_SHIFT)
/** Frame register */
// #define FRAME_REG (0x13 << MEM_MAP_SHIFT)
/** Multi Purpose register */
#define MULTI_PURPOSE_REG (0x14 << MEM_MAP_SHIFT)
#define PHS_STP_OFST (0)
#define PHS_STP_MSK (0x00000001 << PHS_STP_OFST)
#define RST_CNTR_OFST (2)
#define RST_CNTR_MSK (0x00000001 << RST_CNTR_OFST)
#define SW1_OFST (5)
#define SW1_MSK (0x00000001 << SW1_OFST)
#define WRT_BCK_OFST (6)
#define WRT_BCK_MSK (0x00000001 << WRT_BCK_OFST)
#define RST_OFST (7)
#define RST_MSK (0x00000001 << RST_OFST)
#define PLL_CLK_SL_OFST (8)
#define PLL_CLK_SL_MSK (0x00000007 << PLL_CLK_SL_OFST)
#define PLL_CLK_SL_MSTR_VAL ((0x1 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_MSTR_ADC_VAL ((0x2 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_SLV_VAL ((0x3 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define PLL_CLK_SL_SLV_ADC_VAL ((0x4 << PLL_CLK_SL_OFST) & PLL_CLK_SL_MSK)
#define ENT_RSTN_OFST (11)
#define ENT_RSTN_MSK (0x00000001 << ENT_RSTN_OFST)
#define INT_RSTN_OFST (12)
#define INT_RSTN_MSK (0x00000001 << INT_RSTN_OFST)
#define DGTL_TST_OFST (14)
#define DGTL_TST_MSK (0x00000001 << DGTL_TST_OFST)
#define CHNG_AT_PWR_ON_OFST (15) // Not used in SW
#define CHNG_AT_PWR_ON_MSK (0x00000001 << CHNG_AT_PWR_ON_OFST) // Not used in SW
#define RST_TO_SW1_DLY_OFST (16)
#define RST_TO_SW1_DLY_MSK (0x0000000F << RST_TO_SW1_DLY_OFST)
#define STRT_ACQ_DLY_OFST (20)
#define STRT_ACQ_DLY_MSK (0x0000000F << STRT_ACQ_DLY_OFST)
/** DAQ register */
#define DAQ_REG (0x15 << MEM_MAP_SHIFT)
#define DAQ_TKN_TMNG_OFST (0)
#define DAQ_TKN_TMNG_MSK (0x0000FFFF << DAQ_TKN_TMNG_OFST)
#define DAQ_TKN_TMNG_BRD_RVSN_1_VAL \
((0x1f16 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_TKN_TMNG_BRD_RVSN_2_VAL \
((0x1f10 << DAQ_TKN_TMNG_OFST) & DAQ_TKN_TMNG_MSK)
#define DAQ_PCKT_LNGTH_OFST (16)
#define DAQ_PCKT_LNGTH_MSK (0x0000FFFF << DAQ_PCKT_LNGTH_OFST)
#define DAQ_PCKT_LNGTH_NO_ROI_VAL \
((0x0013f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
#define DAQ_PCKT_LNGTH_ROI_VAL \
((0x0007f << DAQ_PCKT_LNGTH_OFST) & DAQ_PCKT_LNGTH_MSK)
/** Time From Start register */
// #define TIME_FROM_START_REG (0x16 << MEM_MAP_SHIFT)
/** DAC Control register */
#define SPI_REG (0x17 << MEM_MAP_SHIFT)
#define SPI_DAC_SRL_CS_OTPT_OFST (0)
#define SPI_DAC_SRL_CS_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CS_OTPT_OFST)
#define SPI_DAC_SRL_CLK_OTPT_OFST (1)
#define SPI_DAC_SRL_CLK_OTPT_MSK (0x00000001 << SPI_DAC_SRL_CLK_OTPT_OFST)
#define SPI_DAC_SRL_DGTL_OTPT_OFST (2)
#define SPI_DAC_SRL_DGTL_OTPT_MSK (0x00000001 << SPI_DAC_SRL_DGTL_OTPT_OFST)
/** ADC SPI register */
#define ADC_SPI_REG (0x18 << MEM_MAP_SHIFT)
#define ADC_SPI_SRL_CLK_OTPT_OFST (0)
#define ADC_SPI_SRL_CLK_OTPT_MSK (0x00000001 << ADC_SPI_SRL_CLK_OTPT_OFST)
#define ADC_SPI_SRL_DT_OTPT_OFST (1)
#define ADC_SPI_SRL_DT_OTPT_MSK (0x00000001 << ADC_SPI_SRL_DT_OTPT_OFST)
#define ADC_SPI_SRL_CS_OTPT_OFST (2)
#define ADC_SPI_SRL_CS_OTPT_MSK (0x0000001F << ADC_SPI_SRL_CS_OTPT_OFST)
/** ADC Sync register */
#define ADC_SYNC_REG (0x19 << MEM_MAP_SHIFT)
#define ADC_SYNC_ENET_STRT_DLY_OFST (0)
#define ADC_SYNC_ENET_STRT_DLY_MSK (0x0000000F << ADC_SYNC_ENET_STRT_DLY_OFST)
#define ADC_SYNC_ENET_STRT_DLY_VAL \
((0x4 << ADC_SYNC_ENET_STRT_DLY_OFST) & ADC_SYNC_ENET_STRT_DLY_MSK)
#define ADC_SYNC_TKN1_HGH_DLY_OFST (4)
#define ADC_SYNC_TKN1_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_HGH_DLY_OFST)
#define ADC_SYNC_TKN1_HGH_DLY_VAL \
((0x1 << ADC_SYNC_TKN1_HGH_DLY_OFST) & ADC_SYNC_TKN1_HGH_DLY_MSK)
#define ADC_SYNC_TKN2_HGH_DLY_OFST (8)
#define ADC_SYNC_TKN2_HGH_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_HGH_DLY_OFST)
#define ADC_SYNC_TKN2_HGH_DLY_VAL \
((0x2 << ADC_SYNC_TKN2_HGH_DLY_OFST) & ADC_SYNC_TKN2_HGH_DLY_MSK)
#define ADC_SYNC_TKN1_LOW_DLY_OFST (12)
#define ADC_SYNC_TKN1_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN1_LOW_DLY_OFST)
#define ADC_SYNC_TKN1_LOW_DLY_VAL \
((0x2 << ADC_SYNC_TKN1_LOW_DLY_OFST) & ADC_SYNC_TKN1_LOW_DLY_MSK)
#define ADC_SYNC_TKN2_LOW_DLY_OFST (16)
#define ADC_SYNC_TKN2_LOW_DLY_MSK (0x0000000F << ADC_SYNC_TKN2_LOW_DLY_OFST)
#define ADC_SYNC_TKN2_LOW_DLY_VAL \
((0x3 << ADC_SYNC_TKN2_LOW_DLY_OFST) & ADC_SYNC_TKN2_LOW_DLY_MSK)
// 0x32214
#define ADC_SYNC_TKN_VAL \
(ADC_SYNC_ENET_STRT_DLY_VAL | ADC_SYNC_TKN1_HGH_DLY_VAL | \
ADC_SYNC_TKN2_HGH_DLY_VAL | ADC_SYNC_TKN1_LOW_DLY_VAL | \
ADC_SYNC_TKN2_LOW_DLY_VAL)
#define ADC_SYNC_CLEAN_FIFOS_OFST (20)
#define ADC_SYNC_CLEAN_FIFOS_MSK (0x00000001 << ADC_SYNC_CLEAN_FIFOS_OFST)
#define ADC_SYNC_ENET_DELAY_OFST (24)
#define ADC_SYNC_ENET_DELAY_MSK (0x000000FF << ADC_SYNC_ENET_DELAY_OFST)
#define ADC_SYNC_ENET_DELAY_NO_ROI_VAL \
((0x88 << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
#define ADC_SYNC_ENET_DELAY_ROI_VAL \
((0x1b << ADC_SYNC_ENET_DELAY_OFST) & ADC_SYNC_ENET_DELAY_MSK)
/** Time From Start register */
// #define MU_TIME_REG (0x1a << MEM_MAP_SHIFT)
/** Temperatre SPI In register */
#define TEMP_SPI_IN_REG (0x1b << MEM_MAP_SHIFT)
#define TEMP_SPI_IN_T1_CLK_OFST (0)
#define TEMP_SPI_IN_T1_CLK_MSK (0x00000001 << TEMP_SPI_IN_T1_CLK_OFST)
#define TEMP_SPI_IN_T1_CS_OFST (1)
#define TEMP_SPI_IN_T1_CS_MSK (0x00000001 << TEMP_SPI_IN_T1_CS_OFST)
#define TEMP_SPI_IN_T2_CLK_OFST (2)
#define TEMP_SPI_IN_T2_CLK_MSK (0x00000001 << TEMP_SPI_IN_T2_CLK_OFST)
#define TEMP_SPI_IN_T2_CS_OFST (3)
#define TEMP_SPI_IN_T2_CS_MSK (0x00000001 << TEMP_SPI_IN_T2_CS_OFST)
#define TEMP_SPI_IN_IDLE_MSK \
(TEMP_SPI_IN_T1_CS_MSK | TEMP_SPI_IN_T2_CS_MSK | TEMP_SPI_IN_T1_CLK_MSK | \
TEMP_SPI_IN_T2_CLK_MSK)
/** Temperatre SPI Out register */
#define TEMP_SPI_OUT_REG (0x1c << MEM_MAP_SHIFT)
#define TEMP_SPI_OUT_T1_DT_OFST (0)
#define TEMP_SPI_OUT_T1_DT_MSK (0x00000001 << TEMP_SPI_OUT_T1_DT_OFST)
#define TEMP_SPI_OUT_T2_DT_OFST (1)
#define TEMP_SPI_OUT_T2_DT_MSK (0x00000001 << TEMP_SPI_OUT_T2_DT_OFST)
/** TSE Configure register */
#define TSE_CONF_REG (0x1d << MEM_MAP_SHIFT)
/** SPI Configure register */
#define ENET_CONF_REG (0x1e << MEM_MAP_SHIFT)
/** Write TSE Shadow register */
// #define WRITE_TSE_SHADOW_REG (0x1f << MEM_MAP_SHIFT)
/** High Voltage register */
#define HV_REG (0x20 << MEM_MAP_SHIFT)
#define HV_ENBL_OFST (0)
#define HV_ENBL_MSK (0x00000001 << HV_ENBL_OFST)
#define HV_SEL_OFST (1)
#define HV_SEL_MSK (0x00000007 << HV_SEL_OFST)
#define HV_SEL_90_VAL ((0x0 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_110_VAL ((0x1 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_120_VAL ((0x2 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_150_VAL ((0x3 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_180_VAL ((0x4 << HV_SEL_OFST) & HV_SEL_MSK)
#define HV_SEL_200_VAL ((0x5 << HV_SEL_OFST) & HV_SEL_MSK)
/** Dummy register */
#define DUMMY_REG (0x21 << MEM_MAP_SHIFT)
/** Firmware Version register */
#define FPGA_VERSION_REG (0x22 << MEM_MAP_SHIFT)
#define FPGA_VERSION_OFST (0)
#define FPGA_VERSION_MSK \
(0x00FFFFFF << FPGA_VERSION_OFST) // to get in format yymmdd
/* Fix Pattern register */
#define FIX_PATT_REG (0x23 << MEM_MAP_SHIFT)
#define FIX_PATT_VAL (0xACDC1980)
/** 16 bit Control register */
#define CONTROL_REG (0x24 << MEM_MAP_SHIFT)
#define CONTROL_STRT_ACQ_OFST (0)
#define CONTROL_STRT_ACQ_MSK (0x00000001 << CONTROL_STRT_ACQ_OFST)
#define CONTROL_STP_ACQ_OFST (1)
#define CONTROL_STP_ACQ_MSK (0x00000001 << CONTROL_STP_ACQ_OFST)
#define CONTROL_STRT_FF_TST_OFST (2) // Not used in FW & SW
#define CONTROL_STRT_FF_TST_MSK (0x00000001 << CONTROL_STRT_FF_TST_OFST)
#define CONTROL_STP_FF_TST_OFST (3) // Not used in FW & SW
#define CONTROL_STP_FF_TST_MSK (0x00000001 << CONTROL_STP_FF_TST_OFST)
#define CONTROL_STRT_RDT_OFST (4)
#define CONTROL_STRT_RDT_MSK (0x00000001 << CONTROL_STRT_RDT_OFST)
#define CONTROL_STP_RDT_OFST (5)
#define CONTROL_STP_RDT_MSK (0x00000001 << CONTROL_STP_RDT_OFST)
#define CONTROL_STRT_EXPSR_OFST (6)
#define CONTROL_STRT_EXPSR_MSK (0x00000001 << CONTROL_STRT_EXPSR_OFST)
#define CONTROL_STP_EXPSR_OFST (7)
#define CONTROL_STP_EXPSR_MSK (0x00000001 << CONTROL_STP_EXPSR_OFST)
#define CONTROL_STRT_TRN_OFST (8)
#define CONTROL_STRT_TRN_MSK (0x00000001 << CONTROL_STRT_TRN_OFST)
#define CONTROL_STP_TRN_OFST (9)
#define CONTROL_STP_TRN_MSK (0x00000001 << CONTROL_STP_TRN_OFST)
#define CONTROL_SYNC_RST_OFST (10)
#define CONTROL_SYNC_RST_MSK (0x00000001 << CONTROL_SYNC_RST_OFST)
/** Status register */
#define STATUS_REG (0x25 << MEM_MAP_SHIFT)
#define STATUS_RN_BSY_OFST (0)
#define STATUS_RN_BSY_MSK (0x00000001 << STATUS_RN_BSY_OFST)
#define STATUS_RDT_BSY_OFST (1)
#define STATUS_RDT_BSY_MSK (0x00000001 << STATUS_RDT_BSY_OFST)
#define STATUS_WTNG_FR_TRGGR_OFST (3)
#define STATUS_WTNG_FR_TRGGR_MSK (0x00000001 << STATUS_WTNG_FR_TRGGR_OFST)
#define STATUS_DLY_BFR_OFST (4)
#define STATUS_DLY_BFR_MSK (0x00000001 << STATUS_DLY_BFR_OFST)
#define STATUS_DLY_AFTR_OFST (5)
#define STATUS_DLY_AFTR_MSK (0x00000001 << STATUS_DLY_AFTR_OFST)
#define STATUS_EXPSNG_OFST (6)
#define STATUS_EXPSNG_MSK (0x00000001 << STATUS_EXPSNG_OFST)
#define STATUS_CNT_ENBL_OFST (7)
#define STATUS_CNT_ENBL_MSK (0x00000001 << STATUS_CNT_ENBL_OFST)
#define STATUS_RD_STT_OFST (8)
#define STATUS_RD_STT_MSK (0x00000007 << STATUS_RD_STT_OFST)
#define STATUS_RN_STT_OFST (12)
#define STATUS_RN_STT_MSK (0x00000007 << STATUS_RN_STT_OFST)
#define STATUS_SM_FF_FLL_OFST (15)
#define STATUS_SM_FF_FLL_MSK (0x00000001 << STATUS_SM_FF_FLL_OFST)
#define STATUS_ALL_FF_EMPTY_OFST (11)
#define STATUS_ALL_FF_EMPTY_MSK (0x00000001 << STATUS_ALL_FF_EMPTY_OFST)
#define STATUS_RN_MSHN_BSY_OFST (17)
#define STATUS_RN_MSHN_BSY_MSK (0x00000001 << STATUS_RN_MSHN_BSY_OFST)
#define STATUS_RD_MSHN_BSY_OFST (18)
#define STATUS_RD_MSHN_BSY_MSK (0x00000001 << STATUS_RD_MSHN_BSY_OFST)
#define STATUS_RN_FNSHD_OFST (20)
#define STATUS_RN_FNSHD_MSK (0x00000001 << STATUS_RN_FNSHD_OFST)
#define STATUS_IDLE_MSK (0x0000FFFF << 0)
/** Config register */
#define CONFIG_REG (0x26 << MEM_MAP_SHIFT)
#define CONFIG_SLAVE_OFST (0) // Not used in FW & SW
#define CONFIG_SLAVE_MSK (0x00000001 << CONFIG_SLAVE_OFST)
#define CONFIG_MASTER_OFST (1) // Not used in FW & SW
#define CONFIG_MASTER_MSK (0x00000001 << CONFIG_MASTER_OFST)
#define CONFIG_TM_GT_ENBL_OFST (2) // Not used in FW & SW
#define CONFIG_TM_GT_ENBL_MSK (0x00000001 << CONFIG_TM_GT_ENBL_OFST)
#define CONFIG_CPU_RDT_OFST (12)
#define CONFIG_CPU_RDT_MSK (0x00000001 << CONFIG_CPU_RDT_OFST)
#define CONFIG_CNTNS_RDT_OFST (23) // Not used in FW & SW
#define CONFIG_CNTNS_RDT_MSK (0x00000001 << CONFIG_CNTNS_RDT_OFST)
#define CONFIG_ACCMLT_CNTS_OFST (24) // Not used in FW & SW
#define CONFIG_ACCMLT_CNTS_MSK (0x00000001 << CONFIG_ACCMLT_CNTS_OFST)
/** External Signal register */
#define EXT_SIGNAL_REG (0x27 << MEM_MAP_SHIFT)
#define EXT_SIGNAL_OFST (0)
#define EXT_SIGNAL_MSK (0x00000007 << EXT_SIGNAL_OFST)
#define EXT_SIGNAL_OFF_VAL ((0x0 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_RSNG_VAL ((0x3 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
#define EXT_SIGNAL_TRGGR_IN_FLLNG_VAL \
((0x4 << EXT_SIGNAL_OFST) & EXT_SIGNAL_MSK)
/** Look at me register */
// #define LOOK_AT_ME_REG (0x28 << MEM_MAP_SHIFT)
/** FPGA SVN register */
// #define FPGA_SVN_REG (0x29 << MEM_MAP_SHIFT)
/** Chip of Interest register */
#define CHIP_OF_INTRST_REG (0x2a << MEM_MAP_SHIFT)
#define CHIP_OF_INTRST_ADC_SEL_OFST (0)
#define CHIP_OF_INTRST_ADC_SEL_MSK (0x0000001F << CHIP_OF_INTRST_ADC_SEL_OFST)
#define CHIP_OF_INTRST_NUM_CHNNLS_OFST (16)
#define CHIP_OF_INTRST_NUM_CHNNLS_MSK \
(0x0000FFFF << CHIP_OF_INTRST_NUM_CHNNLS_OFST)
/** Out MUX register */
// #define OUT_MUX_REG (0x2b << MEM_MAP_SHIFT)
/** Board Version register */
#define BOARD_REVISION_REG (0x2c << MEM_MAP_SHIFT)
#define BOARD_REVISION_OFST (0)
#define BOARD_REVISION_MSK (0x0000FFFF << BOARD_REVISION_OFST)
#define DETECTOR_TYPE_OFST (16)
#define DETECTOR_TYPE_MSK (0x0000000F << DETECTOR_TYPE_OFST)
// #define DETECTOR_TYPE_GOTTHARD_VAL (??)
#define DETECTOR_TYPE_MOENCH_VAL (2)
/** Memory Test register */
// #define MEMORY_TEST_REG (0x2d << MEM_MAP_SHIFT)
/** Hit Threshold register */
// #define HIT_THRESHOLD_REG (0x2e << MEM_MAP_SHIFT)
/** Hit Count register */
// #define HIT_COUNT_REG (0x2f << MEM_MAP_SHIFT)
/* 16 bit Fifo Data register */
#define FIFO_DATA_REG (0x50 << MEM_MAP_SHIFT) // Not used in FW and SW (16bit)
/** Dacs Set 1 register */
// #define DACS_SET_1_REG (0x65 << MEM_MAP_SHIFT)
/** Dacs Set 2 register */
// #define DACS_SET_2_REG (0x66 << MEM_MAP_SHIFT)
/** Dacs Set 3 register */
// #define DACS_SET_3_REG (0x67 << MEM_MAP_SHIFT)
/* Set Delay 64 bit register */
#define SET_DELAY_LSB_REG (0x68 << MEM_MAP_SHIFT)
#define SET_DELAY_MSB_REG (0x69 << MEM_MAP_SHIFT)
/* Get Delay 64 bit register */
#define GET_DELAY_LSB_REG (0x6a << MEM_MAP_SHIFT)
#define GET_DELAY_MSB_REG (0x6b << MEM_MAP_SHIFT)
/* Set Triggers 64 bit register */
#define SET_TRAINS_LSB_REG (0x6c << MEM_MAP_SHIFT)
#define SET_TRAINS_MSB_REG (0x6d << MEM_MAP_SHIFT)
/* Get Triggers 64 bit register */
#define GET_TRAINS_LSB_REG (0x6e << MEM_MAP_SHIFT)
#define GET_TRAINS_MSB_REG (0x6f << MEM_MAP_SHIFT)
/* Set Frames 64 bit register */
#define SET_FRAMES_LSB_REG (0x70 << MEM_MAP_SHIFT)
#define SET_FRAMES_MSB_REG (0x71 << MEM_MAP_SHIFT)
/* Get Frames 64 bit register */
#define GET_FRAMES_LSB_REG (0x72 << MEM_MAP_SHIFT)
#define GET_FRAMES_MSB_REG (0x73 << MEM_MAP_SHIFT)
/* Set Period 64 bit register */
#define SET_PERIOD_LSB_REG (0x74 << MEM_MAP_SHIFT)
#define SET_PERIOD_MSB_REG (0x75 << MEM_MAP_SHIFT)
/* Get Period 64 bit register */
#define GET_PERIOD_LSB_REG (0x76 << MEM_MAP_SHIFT)
#define GET_PERIOD_MSB_REG (0x77 << MEM_MAP_SHIFT)
/* Set Exptime 64 bit register */
#define SET_EXPTIME_LSB_REG (0x78 << MEM_MAP_SHIFT)
#define SET_EXPTIME_MSB_REG (0x79 << MEM_MAP_SHIFT)
/* Get Exptime 64 bit register */
#define GET_EXPTIME_LSB_REG (0x7a << MEM_MAP_SHIFT)
#define GET_EXPTIME_MSB_REG (0x7b << MEM_MAP_SHIFT)
/* Set Gates 64 bit register */
// #define SET_GATES_LSB_REG (0x7c << MEM_MAP_SHIFT)
// #define SET_GATES_MSB_REG (0x7d << MEM_MAP_SHIFT)
/* Set Gates 64 bit register */
// #define GET_GATES_LSB_REG (0x7e << MEM_MAP_SHIFT)
// #define GET_GATES_MSB_REG (0x7f << MEM_MAP_SHIFT)
/* Dark Image starting address */
#define DARK_IMAGE_REG (0x81 << MEM_MAP_SHIFT)
/* Gain Image starting address */
#define GAIN_IMAGE_REG (0x82 << MEM_MAP_SHIFT)
/* Counter Block Memory starting address */
#define COUNTER_MEMORY_REG (0x85 << MEM_MAP_SHIFT)

23
slsDetectorServers/gotthardDetectorServer/bin/config_gotthard.txt
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@@ -1,23 +0,0 @@
#masterflags (no_master, is_master, is_slave)
masterflags no_master
#master default delay
masterdefaultdelay 70
#patternphase
patternphase 0
#adcphase
adcphase 0
#slave pattern phase
slavepatternphase 0
#slave adc phase
slaveadcphase 0
#rst to sw1 delay
rsttosw1delay 2
#start acquisition delay
startacqdelay 1

BIN
slsDetectorServers/gotthardDetectorServer/bin/gotthardDetectorServerv9.0.0
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23
slsDetectorServers/gotthardDetectorServer/config_gotthard.txt
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@@ -1,23 +0,0 @@
#masterflags (no_master, is_master, is_slave)
masterflags no_master
#master default delay
masterdefaultdelay 70
#patternphase
patternphase 0
#adcphase
adcphase 0
#slave pattern phase
slavepatternphase 0
#slave adc phase
slaveadcphase 0
#rst to sw1 delay
rsttosw1delay 2
#start acquisition delay
startacqdelay 1

1927
slsDetectorServers/gotthardDetectorServer/slsDetectorFunctionList.c
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159
slsDetectorServers/gotthardDetectorServer/slsDetectorServer_defs.h
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@@ -1,159 +0,0 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#pragma once
#include "sls/sls_detector_defs.h"
#include <stdlib.h>
#define NUM_HARDWARE_VERSIONS (2)
#define HARDWARE_VERSION_NUMBERS \
{ 0x1, 0x2 }
#define HARDWARE_VERSION_NAMES \
{ "1.0", "2.0" }
#define LINKED_SERVER_NAME "gotthardDetectorServer"
#ifdef VIRTUAL
#define CTRL_SRVR_INIT_TIME_US (2 * 1000 * 1000)
#else
#define CTRL_SRVR_INIT_TIME_US (300 * 1000)
#endif
/* Enums */
enum ADCINDEX { TEMP_FPGA, TEMP_ADC };
enum DACINDEX {
G_VREF_DS,
G_VCASCN_PB,
G_VCASCP_PB,
G_VOUT_CM,
G_VCASC_OUT,
G_VIN_CM,
G_VREF_COMP,
G_IB_TESTC
};
enum CLKINDEX { ADC_CLK, NUM_CLOCKS };
#define CLK_NAMES "adc"
#define DAC_NAMES \
"vref_ds", "vcascn_pb", "vcascp_pb", "vout_cm", "vcasc_out", "vin_cm", \
"vref_comp", "ib_testc"
#define DEFAULT_DAC_VALS \
{ \
660, /* G_VREF_DS */ \
650, /* G_VCASCN_PB */ \
1480, /* G_VCASCP_PB */ \
1520, /* G_VOUT_CM */ \
1320, /* G_VCASC_OUT */ \
1350, /* G_VIN_CM */ \
350, /* G_VREF_COMP */ \
2001 /* G_IB_TESTC */ \
};
/* for 25 um */
#define CONFIG_FILE "config_gotthard.txt"
/* Hardware Definitions */
#define NCHAN (128)
#define NCHIP (10)
#define NDAC (8)
#define NCHIPS_PER_ADC (2)
#define NCHAN_PER_ADC (256)
#define DYNAMIC_RANGE (16)
#define NUM_BITS_PER_PIXEL (DYNAMIC_RANGE / 8)
#define DATA_BYTES (NCHIP * NCHAN * NUM_BITS_PER_PIXEL)
#define CLK_FREQ (32007729) // Hz
#define MAX_EXT_SIGNALS (1)
/** Firmware Definitions */
#define IP_PACKET_SIZE_NO_ROI \
(NCHIP * (NCHAN / 2) * 2 + 14 + 20) // 2 packets, so divide by 2
#define IP_PACKET_SIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 14 + 20)
#define UDP_PACKETSIZE_NO_ROI \
(NCHIP * (NCHAN / 2) * 2 + 4 + 8 + 2) // 2 packets, so divide by 2
#define UDP_PACKETSIZE_ROI (NCHIPS_PER_ADC * NCHAN * 2 + 4 + 8 + 2)
/** Default Parameters */
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)
#define DEFAULT_EXPTIME (1 * 1000 * 1000) // 1 ms
#define DEFAULT_PERIOD (1 * 1000 * 1000 * 1000) // 1 s
#define DEFAULT_DELAY (0)
#define DEFAULT_SETTINGS (DYNAMICGAIN)
#define DEFAULT_TIMING_MODE (AUTO_TIMING)
#define DEFAULT_TRIGGER_MODE (TRIGGER_IN_RISING_EDGE)
#define DEFAULT_HIGH_VOLTAGE (0)
#define DEFAULT_PHASE_SHIFT (120)
#define DEFAULT_TX_UDP_PORT (0xE185)
#define DAC_MIN_MV (0)
#define DAC_MAX_MV (2500)
/** ENEt conf structs */
typedef struct mac_header_struct {
u_int8_t mac_dest_mac2;
u_int8_t mac_dest_mac1;
u_int8_t mac_dummy1;
u_int8_t mac_dummy2;
u_int8_t mac_dest_mac6;
u_int8_t mac_dest_mac5;
u_int8_t mac_dest_mac4;
u_int8_t mac_dest_mac3;
u_int8_t mac_src_mac4;
u_int8_t mac_src_mac3;
u_int8_t mac_src_mac2;
u_int8_t mac_src_mac1;
u_int16_t mac_ether_type;
u_int8_t mac_src_mac6;
u_int8_t mac_src_mac5;
} mac_header;
typedef struct ip_header_struct {
u_int16_t ip_len;
u_int8_t ip_tos;
u_int8_t ip_ihl : 4, ip_ver : 4;
u_int16_t ip_offset : 13, ip_flag : 3;
u_int16_t ip_ident;
u_int16_t ip_chksum;
u_int8_t ip_protocol;
u_int8_t ip_ttl;
u_int32_t ip_sourceip;
u_int32_t ip_destip;
} ip_header;
typedef struct udp_header_struct {
u_int16_t udp_destport;
u_int16_t udp_srcport;
u_int16_t udp_chksum;
u_int16_t udp_len;
} udp_header;
typedef struct mac_conf_struct {
mac_header mac;
ip_header ip;
udp_header udp;
u_int32_t npack;
u_int32_t lpack;
u_int32_t npad;
u_int32_t cdone;
} mac_conf;
typedef struct tse_conf_struct {
u_int32_t rev; // 0x0
u_int32_t scratch;
u_int32_t command_config;
u_int32_t mac_0; // 0x3
u_int32_t mac_1;
u_int32_t frm_length;
u_int32_t pause_quant;
u_int32_t rx_section_empty; // 0x7
u_int32_t rx_section_full;
u_int32_t tx_section_empty;
u_int32_t tx_section_full;
u_int32_t rx_almost_empty; // 0xB
u_int32_t rx_almost_full;
u_int32_t tx_almost_empty;
u_int32_t tx_almost_full;
u_int32_t mdio_addr0; // 0xF
u_int32_t mdio_addr1;
} tse_conf;

4
slsDetectorServers/jungfrauDetectorServer/CMakeLists.txt
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@@ -36,6 +36,10 @@ set_target_properties(jungfrauDetectorServer_virtual PROPERTIES
RUNTIME_OUTPUT_DIRECTORY ${CMAKE_BINARY_DIR}/bin
)
# to compile fore 32 bit on a 64 bit machine
#target_compile_options(jungfrauDetectorServer_virtual PRIVATE -m32)
#target_link_options(jungfrauDetectorServer_virtual PRIVATE -m32)
install(TARGETS jungfrauDetectorServer_virtual
EXPORT "${TARGETS_EXPORT_NAME}"
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}

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slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServerv10.0.0 Executable file
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slsDetectorServers/jungfrauDetectorServer/bin/jungfrauDetectorServerv9.1.0
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slsDetectorServers/moenchDetectorServer/bin/moenchDetectorServerv10.0.0 Executable file
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slsDetectorServers/moenchDetectorServer/bin/moenchDetectorServerv9.0.0
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slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServerv10.0.0 Executable file
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slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServerv9.1.1
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slsDetectorServers/slsDetectorServer/include/AD9252.h
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@@ -1,32 +0,0 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#pragma once
#include <inttypes.h>
/**
* Set Defines
* @param reg spi register
* @param cmsk chip select mask
* @param clkmsk clock output mask
* @param dmsk digital output mask
* @param dofst digital output offset
*/
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst);
/**
* Disable SPI
*/
void AD9252_Disable();
/**
* Set SPI reg value
* @param codata value to be set
*/
void AD9252_Set(int addr, int val);
/**
* Configure
*/
void AD9252_Configure();

17
slsDetectorServers/slsDetectorServer/include/blackfin.h
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@@ -5,6 +5,23 @@
#include <inttypes.h>
#include <sys/types.h>
/** enable support for ARDY signal on interface to FPGA
* needed to properly translate avalon_mm_waitrequest in the CTB firmware
* https://www.analog.com/media/en/dsp-documentation/processor-manuals/bf537_hwr_Rev3.2.pdf
* page 274
* */
#define BFIN_EBIU_AMBCTL1_B2_ARDY_ENA_OFST (0)
#define BFIN_EBIU_AMBCTL1_B2_ARDY_ENA_MSK \
(1 << BFIN_EBIU_AMBCTL1_B2_ARDY_ENA_OFST)
#define BFIN_EBIU_AMBCTL1_B2_ARDY_POL_OFST (1)
#define BFIN_EBIU_AMBCTL1_B2_ARDY_POL_MSK \
(1 << BFIN_EBIU_AMBCTL1_B2_ARDY_POL_OFST)
#define BFIN_AMC_ACCESS_EXTENSION_ENA_VAL \
(BFIN_EBIU_AMBCTL1_B2_ARDY_ENA_MSK | BFIN_EBIU_AMBCTL1_B2_ARDY_POL_MSK)
#define BFIN_AMC_ACCESS_EXTENSION_FNAME \
"/sys/kernel/debug/blackfin/ebiu_amc/EBIU_AMBCTL1"
/** I2C defines */
#define I2C_CLOCK_MHZ (131.25)

13
slsDetectorServers/slsDetectorServer/include/loadPattern.h
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@@ -27,10 +27,15 @@ int getPatternWaitAddress(int level);
int validate_setPatternWaitAddresses(char *message, int level, int addr);
void setPatternWaitAddress(int level, int addr);
int validate_getPatternWaitTime(char *message, int level, uint64_t *waittime);
uint64_t getPatternWaitTime(int level);
int validate_setPatternWaitTime(char *message, int level, uint64_t waittime);
void setPatternWaitTime(int level, uint64_t t);
int validate_getPatternWaitClocksAndInterval(char *message, int level,
uint64_t *waittime, int clocks);
uint64_t getPatternWaitClocks(int level);
uint64_t getPatternWaitInterval(int level);
int validate_setPatternWaitClocksAndInterval(char *message, int level,
uint64_t waittime, int clocks);
void setPatternWaitClocks(int level, uint64_t t);
void setPatternWaitInterval(int level, uint64_t t);
int validate_getPatternLoopCycles(char *message, int level, int *numLoops);
int getPatternLoopCycles(int level);

88
slsDetectorServers/slsDetectorServer/include/slsDetectorFunctionList.h
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@@ -2,27 +2,17 @@
// Copyright (C) 2021 Contributors to the SLS Detector Package
#include "sls/sls_detector_defs.h"
#include "slsDetectorServer_defs.h" // DAC_INDEX, ADC_INDEX, also include RegisterDefs.h
#ifdef GOTTHARDD
#include "AD9252.h" // old board compatibility
#include "clogger.h" // runState(enum TLogLevel)
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(CHIPTESTBOARDD)
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD)
#include "AD9257.h" // commonServerFunctions.h, blackfin.h, ansi.h
#endif
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
#include "programViaNios.h"
#elif defined(CHIPTESTBOARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(GOTTHARDD)
#include "programViaBlackfin.h"
#endif
#if defined(MYTHEN3D) || defined(GOTTHARD2D)
#include "nios.h"
#elif defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(CHIPTESTBOARDD)
#include "programViaNios.h"
#elif defined(CHIPTESTBOARDD) || defined(JUNGFRAUD) || defined(MOENCHD)
#include "blackfin.h"
#include "programViaBlackfin.h"
#endif
#ifdef ARMPROCESSOR
@@ -76,8 +66,7 @@ int testBus();
#endif
#endif
#if defined(GOTTHARDD) || \
((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
#if ((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
defined(VIRTUAL))
void setTestImageMode(int ival);
int getTestImageMode();
@@ -102,7 +91,7 @@ u_int16_t getHardwareVersionNumber();
u_int16_t getHardwareSerialNumber();
#endif
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(GOTTHARD2D) || \
defined(MYTHEN3D) || defined(GOTTHARDD)
defined(MYTHEN3D)
int isHardwareVersion_1_0();
#endif
#if defined(JUNGFRAUD)
@@ -124,6 +113,10 @@ void setModuleId(int modid);
u_int64_t getDetectorMAC();
u_int32_t getDetectorIP();
#if defined(CHIPTESTBOARDD)
int enableBlackfinAMCExternalAccessExtension(char *mess);
#endif
// initialization
void initControlServer();
void initStopServer();
@@ -162,8 +155,7 @@ void setADIFDefaults();
#if defined(GOTTHARD2D) || defined(EIGERD) || defined(JUNGFRAUD)
int readConfigFile();
#endif
#if defined(GOTTHARDD) || defined(GOTTHARD2D) || defined(EIGERD) || \
defined(MYTHEN3D)
#if defined(GOTTHARD2D) || defined(EIGERD) || defined(MYTHEN3D)
int checkCommandLineConfiguration();
#endif
#ifdef EIGERD
@@ -177,9 +169,6 @@ int readRegister(uint32_t offset, uint32_t *retval);
int setBit(const uint32_t addr, const int nBit, int validate);
int clearBit(const uint32_t addr, const int nBit, int validate);
int getBit(const uint32_t addr, const int nBit, int *retval);
#elif GOTTHARDD
void writeRegister16And32(uint32_t offset, uint32_t data);
uint32_t readRegister16And32(uint32_t offset);
#endif
// firmware functions (resets)
@@ -197,32 +186,19 @@ int isChipConfigured();
int powerChip(int on, char *mess);
int getPowerChip();
int configureChip(char *mess);
int readConfigFile(char *mess, char *fileName, char *fileType);
int resetChip(char *mess);
#endif
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D)
void cleanFifos();
void resetCore();
void resetPeripheral();
#elif GOTTHARDD
void setPhaseShiftOnce();
void setPhaseShift(int numphaseshift);
void cleanFifos();
void setADCSyncRegister();
void setDAQRegister();
void setChipOfInterestRegister(int adc);
void setROIADC(int adc);
void setGbitReadout();
int readConfigFile();
void setMasterSlaveConfiguration();
#endif
// parameters - dr, roi
int setDynamicRange(int dr);
int getDynamicRange(int *retval);
#ifdef GOTTHARDD
int setROI(ROI arg);
ROI getROI();
#endif
#if defined(JUNGFRAUD) || defined(MOENCHD)
void setADCInvertRegister(uint32_t val);
uint32_t getADCInvertRegister();
@@ -334,9 +310,8 @@ void updatePacketizing();
int64_t getNumFramesLeft();
int64_t getNumTriggersLeft();
#endif
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(GOTTHARDD) || \
defined(CHIPTESTBOARDD) || defined(MYTHEN3D) || defined(GOTTHARD2D) || \
defined(XILINX_CHIPTESTBOARDD)
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)
int setDelayAfterTrigger(int64_t val);
int64_t getDelayAfterTrigger();
int64_t getDelayAfterTriggerLeft();
@@ -345,9 +320,6 @@ int64_t getPeriodLeft();
#ifdef GOTTHARD2D
int64_t getNumBurstsLeft();
#endif
#ifdef GOTTHARDD
int64_t getExpTimeLeft();
#endif
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)
int64_t getFramesFromStart();
@@ -460,8 +432,8 @@ int setMaster(enum MASTERINDEX m);
int setTop(enum TOPINDEX t);
int isTop(int *retval);
#endif
#if defined(MYTHEN3D) || defined(EIGERD) || defined(GOTTHARDD) || \
defined(GOTTHARD2D) || defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(MYTHEN3D) || defined(EIGERD) || defined(GOTTHARD2D) || \
defined(JUNGFRAUD) || defined(MOENCHD)
int isMaster(int *retval);
#endif
@@ -487,15 +459,12 @@ int setAnalogPulsing(int enable);
int setNegativePolarity(int enable);
int setDACS(int *dacs);
#endif
#if defined(GOTTHARDD) || defined(MYTHEN3D)
#if defined(MYTHEN3D)
void setExtSignal(int signalIndex, enum externalSignalFlag mode);
int getExtSignal(int signalIndex);
#endif
// configure mac
#ifdef GOTTHARDD
void calcChecksum(mac_conf *mac, int sourceip, int destip);
#endif
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(GOTTHARD2D)
void setNumberofUDPInterfaces(int val);
#endif
@@ -523,9 +492,6 @@ void setupHeader(int iRxEntry, enum interfaceType type, uint32_t destip,
defined(XILINX_CHIPTESTBOARDD)
void calcChecksum(udp_header *udp);
#endif
#ifdef GOTTHARDD
int getAdcConfigured();
#endif
int configureMAC();
int setDetectorPosition(int pos[]);
@@ -639,10 +605,6 @@ int getActivate(int *retval);
int getDataStream(enum portPosition port, int *retval);
int setDataStream(enum portPosition port, int enable);
// gotthard specific - adc phase
#elif GOTTHARDD
int setPhase(enum CLKINDEX ind, int val, int degrees);
#elif MYTHEN3D
int checkDetectorType(char *mess);
int powerChip(int on);
@@ -742,8 +704,7 @@ int softwareTrigger();
#if defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)
int softwareTrigger(int block);
#endif
#if defined(EIGERD) || defined(MYTHEN3D) || defined(CHIPTESTBOARDD) || \
defined(XILINX_CHIPTESTBOARDD)
#if defined(EIGERD) || defined(MYTHEN3D) || defined(CHIPTESTBOARDD)
int startReadOut();
#endif
enum runStatus getRunStatus();
@@ -762,16 +723,11 @@ int checkFifoForEndOfAcquisition();
int readFrameFromFifo();
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(CHIPTESTBOARDD) || defined(MYTHEN3D) || defined(GOTTHARD2D) || \
defined(XILINX_CHIPTESTBOARDD)
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
defined(MYTHEN3D) || defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)
u_int32_t runBusy();
#endif
#ifdef GOTTHARDD
u_int32_t runState(enum TLogLevel lev);
#endif
// common
int calculateDataBytes();
int getTotalNumberOfChannels();

4
slsDetectorServers/slsDetectorServer/include/slsDetectorServer_funcs.h
View File

@@ -104,7 +104,7 @@ int set_pattern_word(int);
int set_pattern_loop_addresses(int);
int set_pattern_loop_cycles(int);
int set_pattern_wait_addr(int);
int set_pattern_wait_time(int);
int set_pattern_wait_clocks(int);
int set_pattern_mask(int);
int get_pattern_mask(int);
int set_pattern_bit_mask(int);
@@ -336,3 +336,5 @@ int get_timing_info_decoder(int);
int set_timing_info_decoder(int);
int get_collection_mode(int);
int set_collection_mode(int);
int get_pattern_wait_interval(int);
int set_pattern_wait_interval(int);

212
slsDetectorServers/slsDetectorServer/src/AD9252.c
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@@ -1,212 +0,0 @@
// SPDX-License-Identifier: LGPL-3.0-or-other
// Copyright (C) 2021 Contributors to the SLS Detector Package
#include "AD9252.h"
#include "blackfin.h"
#include "clogger.h"
#include "commonServerFunctions.h" // blackfin.h, ansi.h
/* AD9252 ADC DEFINES */
#define AD9252_ADC_NUMBITS (24)
// default value is 0xF
#define AD9252_DEV_IND_2_REG (0x04)
#define AD9252_CHAN_H_OFST (0)
#define AD9252_CHAN_H_MSK (0x00000001 << AD9252_CHAN_H_OFST)
#define AD9252_CHAN_G_OFST (1)
#define AD9252_CHAN_G_MSK (0x00000001 << AD9252_CHAN_G_OFST)
#define AD9252_CHAN_F_OFST (2)
#define AD9252_CHAN_F_MSK (0x00000001 << AD9252_CHAN_F_OFST)
#define AD9252_CHAN_E_OFST (3)
#define AD9252_CHAN_E_MSK (0x00000001 << AD9252_CHAN_E_OFST)
// default value is 0x0F
#define AD9252_DEV_IND_1_REG (0x05)
#define AD9252_CHAN_D_OFST (0)
#define AD9252_CHAN_D_MSK (0x00000001 << AD9252_CHAN_D_OFST)
#define AD9252_CHAN_C_OFST (1)
#define AD9252_CHAN_C_MSK (0x00000001 << AD9252_CHAN_C_OFST)
#define AD9252_CHAN_B_OFST (2)
#define AD9252_CHAN_B_MSK (0x00000001 << AD9252_CHAN_B_OFST)
#define AD9252_CHAN_A_OFST (3)
#define AD9252_CHAN_A_MSK (0x00000001 << AD9252_CHAN_A_OFST)
#define AD9252_CLK_CH_DCO_OFST (4)
#define AD9252_CLK_CH_DCO_MSK (0x00000001 << AD9252_CLK_CH_DCO_OFST)
#define AD9252_CLK_CH_IFCO_OFST (5)
#define AD9252_CLK_CH_IFCO_MSK (0x00000001 << AD9252_CLK_CH_IFCO_OFST)
// default value is 0x00
#define AD9252_POWER_MODE_REG (0x08)
#define AD9252_POWER_INTERNAL_OFST (0)
#define AD9252_POWER_INTERNAL_MSK (0x00000007 << AD9252_POWER_INTERNAL_OFST)
#define AD9252_INT_CHIP_RUN_VAL \
((0x0 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_FULL_PWR_DWN_VAL \
((0x1 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_STANDBY_VAL \
((0x2 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
#define AD9252_INT_RESET_VAL \
((0x3 << AD9252_POWER_INTERNAL_OFST) & AD9252_POWER_INTERNAL_MSK)
// default value is 0x0
#define AD9252_TEST_MODE_REG (0x0D)
#define AD9252_OUT_TEST_OFST (0)
#define AD9252_OUT_TEST_MSK (0x0000000F << AD9252_OUT_TEST_OFST)
#define AD9252_TST_OFF_VAL ((0x0 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_MDSCL_SHRT_VAL \
((0x1 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PSTV_FS_VAL \
((0x2 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_NGTV_FS_VAL \
((0x3 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_ALTRNTNG_CHKRBRD_VAL \
((0x4 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PN_23_SQNC_VAL \
((0x5 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_PN_9_SQNC__VAL \
((0x6 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_0_WRD_TGGL_VAL \
((0x7 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_USR_INPT_VAL \
((0x8 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_0_BT_TGGL_VAL \
((0x9 << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_x_SYNC_VAL \
((0xa << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_1_BIT_HGH_VAL \
((0xb << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_MXD_BT_FRQ_VAL \
((0xc << AD9252_OUT_TEST_OFST) & AD9252_OUT_TEST_MSK)
#define AD9252_TST_RST_SHRT_GN_OFST (4)
#define AD9252_TST_RST_SHRT_GN_MSK (0x00000001 << AD9252_TST_RST_SHRT_GN_OFST)
#define AD9252_TST_RST_LNG_GN_OFST (5)
#define AD9252_TST_RST_LNG_GN_MSK (0x00000001 << AD9252_TST_RST_LNG_GN_OFST)
#define AD9252_USER_IN_MODE_OFST (6)
#define AD9252_USER_IN_MODE_MSK (0x00000003 << AD9252_USER_IN_MODE_OFST)
#define AD9252_USR_IN_SNGL_VAL \
((0x0 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_ALTRNT_VAL \
((0x1 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_SNGL_ONC_VAL \
((0x2 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
#define AD9252_USR_IN_ALTRNT_ONC_VAL \
((0x3 << AD9252_USER_IN_MODE_OFST) & AD9252_USER_IN_MODE_MSK)
// default value is 0x00
#define AD9252_OUT_MODE_REG (0x14)
#define AD9252_OUT_FORMAT_OFST (0)
#define AD9252_OUT_FORMAT_MSK (0x00000003 << AD9252_OUT_FORMAT_OFST)
#define AD9252_OUT_BINARY_OFST_VAL \
((0x0 << AD9252_OUT_FORMAT_OFST) & AD9252_OUT_FORMAT_MSK)
#define AD9252_OUT_TWOS_COMPL_VAL \
((0x1 << AD9252_OUT_FORMAT_OFST) & AD9252_OUT_FORMAT_MSK)
#define AD9252_OUT_OTPT_INVRT_OFST (2)
#define AD9252_OUT_OTPT_INVRT_MSK (0x00000001 << AD9252_OUT_OTPT_INVRT_OFST)
#define AD9252_OUT_LVDS_OPT_OFST (6)
#define AD9252_OUT_LVDS_OPT_MSK (0x00000001 << AD9252_OUT_LVDS_OPT_OFST)
#define AD9252_OUT_LVDS_ANSI_VAL \
((0x0 << AD9252_OUT_LVDS_OPT_OFST) & AD9252_OUT_LVDS_OPT_MSK)
#define AD9252_OUT_LVDS_IEEE_VAL \
((0x1 << AD9252_OUT_LVDS_OPT_OFST) & AD9252_OUT_LVDS_OPT_MSK)
// default value is 0x3
#define AD9252_OUT_PHASE_REG (0x16)
#define AD9252_OUT_CLK_OFST (0)
#define AD9252_OUT_CLK_MSK (0x0000000F << AD9252_OUT_CLK_OFST)
#define AD9252_OUT_CLK_0_VAL ((0x0 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_60_VAL \
((0x1 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_120_VAL \
((0x2 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_180_VAL \
((0x3 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_300_VAL \
((0x5 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_360_VAL \
((0x6 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_480_VAL \
((0x8 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_540_VAL \
((0x9 << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_600_VAL \
((0xa << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK)
#define AD9252_OUT_CLK_660_VAL \
((0xb << AD9252_OUT_CLK_OFST) & AD9252_OUT_CLK_MSK) // 0xb - 0xf is 660
// defines from the fpga
uint32_t AD9252_Reg = 0x0;
uint32_t AD9252_CsMask = 0x0;
uint32_t AD9252_ClkMask = 0x0;
uint32_t AD9252_DigMask = 0x0;
int AD9252_DigOffset = 0x0;
void AD9252_SetDefines(uint32_t reg, uint32_t cmsk, uint32_t clkmsk,
uint32_t dmsk, int dofst) {
AD9252_Reg = reg;
AD9252_CsMask = cmsk;
AD9252_ClkMask = clkmsk;
AD9252_DigMask = dmsk;
AD9252_DigOffset = dofst;
}
void AD9252_Disable() {
bus_w(AD9252_Reg, (bus_r(AD9252_Reg) | AD9252_CsMask | AD9252_ClkMask) &
~(AD9252_DigMask));
}
void AD9252_Set(int addr, int val) {
u_int32_t codata;
codata = val + (addr << 8);
LOG(logINFO,
("\tSetting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr));
serializeToSPI(AD9252_Reg, codata, AD9252_CsMask, AD9252_ADC_NUMBITS,
AD9252_ClkMask, AD9252_DigMask, AD9252_DigOffset, 0);
}
void AD9252_Configure() {
LOG(logINFOBLUE, ("Configuring ADC9252:\n"));
// power mode reset
LOG(logINFO, ("\tPower mode reset\n"));
AD9252_Set(AD9252_POWER_MODE_REG, AD9252_INT_RESET_VAL);
// power mode chip run
LOG(logINFO, ("\tPower mode chip run\n"));
AD9252_Set(AD9252_POWER_MODE_REG, AD9252_INT_CHIP_RUN_VAL);
// binary offset
LOG(logINFO, ("\tBinary offset\n"));
AD9252_Set(AD9252_OUT_MODE_REG, AD9252_OUT_BINARY_OFST_VAL);
// output clock phase
#ifdef GOTTHARDD
LOG(logINFO, ("\tOutput clock phase is at default: 180\n"));
#else
LOG(logINFO, ("\tOutput clock phase: 60\n"));
AD9257_Set(AD9257_OUT_PHASE_REG, AD9257_OUT_CLK_60_VAL);
#endif
// lvds-iee reduced , binary offset
LOG(logINFO, ("\tLvds-iee reduced, binary offset\n"));
AD9252_Set(AD9252_OUT_MODE_REG, AD9252_OUT_LVDS_IEEE_VAL);
// all devices on chip to receive next command
LOG(logINFO, ("\tAll devices on chip to receive next command\n"));
AD9252_Set(AD9252_DEV_IND_2_REG, AD9252_CHAN_H_MSK | AD9252_CHAN_G_MSK |
AD9252_CHAN_F_MSK | AD9252_CHAN_E_MSK);
AD9252_Set(AD9252_DEV_IND_1_REG, AD9252_CHAN_D_MSK | AD9252_CHAN_C_MSK |
AD9252_CHAN_B_MSK | AD9252_CHAN_A_MSK |
AD9252_CLK_CH_DCO_MSK |
AD9252_CLK_CH_IFCO_MSK);
// no test mode
LOG(logINFO, ("\tNo test mode\n"));
AD9252_Set(AD9252_TEST_MODE_REG, AD9252_TST_OFF_VAL);
#ifdef TESTADC
LOG(logINFOBLUE, ("Putting ADC in Test Mode!\n");
// mixed bit frequency test mode
LOG(logINFO, ("\tMixed bit frequency test mode\n"));
AD9252_Set(AD9252_TEST_MODE_REG, AD9252_TST_MXD_BT_FRQ_VAL);
#endif
}

2
slsDetectorServers/slsDetectorServer/src/AD9257.c
View File

@@ -318,7 +318,7 @@ void AD9257_Configure() {
AD9257_CLK_CH_IFCO_MSK);
// vref
#if defined(GOTTHARDD) || defined(MOENCHD)
#if defined(MOENCHD)
LOG(logINFO, ("\tVref default at 2.0\n"));
AD9257_SetVrefVoltage(AD9257_VREF_DEFAULT_VAL, 0);
#else

3
slsDetectorServers/slsDetectorServer/src/common.c
View File

@@ -504,8 +504,7 @@ int setupDetectorServer(char *mess, char *sname) {
// blackfin boards (respawn) (only kept for backwards compatibility)
#ifndef VIRTUAL
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
defined(GOTTHARDD)
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD)
// delete every line with DetectorServer in /etc/inittab
strcpy(cmd, "sed -i '/DetectorServer/d' /etc/inittab");
if (executeCommand(cmd, retvals, logDEBUG1) == FAIL) {

95
slsDetectorServers/slsDetectorServer/src/loadPattern.c
View File

@@ -11,6 +11,10 @@
#ifdef MYTHEN3D
extern enum TLogLevel trimmingPrint;
extern uint32_t clkDivider[];
#endif
#ifdef CHIPTESTBOARDD
extern uint32_t clkFrequency[];
#endif
#if defined(CHIPTESTBOARDD) || defined(XILINX_CHIPTESTBOARDD)
@@ -317,7 +321,8 @@ void setPatternWaitAddress(int level, int addr) {
}
}
int validate_getPatternWaitTime(char *message, int level, uint64_t *waittime) {
int validate_getPatternWaitClocksAndInterval(char *message, int level,
uint64_t *waittime, int clocks) {
// validate input
if (level < 0 || level >= MAX_LEVELS) {
sprintf(message,
@@ -326,11 +331,15 @@ int validate_getPatternWaitTime(char *message, int level, uint64_t *waittime) {
LOG(logERROR, (message));
return FAIL;
}
*waittime = getPatternWaitTime(level);
if (clocks) {
*waittime = getPatternWaitClocks(level);
} else {
*waittime = getPatternWaitInterval(level);
}
return OK;
}
uint64_t getPatternWaitTime(int level) {
uint64_t getPatternWaitClocks(int level) {
switch (level) {
case 0:
return getU64BitReg(PATTERN_WAIT_TIMER_0_LSB_REG,
@@ -357,7 +366,25 @@ uint64_t getPatternWaitTime(int level) {
}
}
int validate_setPatternWaitTime(char *message, int level, uint64_t waittime) {
uint64_t getPatternWaitInterval(int level) {
uint64_t numClocks = getPatternWaitClocks(level);
int runclk = 0;
#ifdef CHIPTESTBOARDD
runclk = clkFrequency[RUN_CLK];
#elif XILINX_CHIPTESTBOARDD
runclk = RUN_CLK;
#elif MYTHEN3D
runclk = clkDivider[SYSTEM_C0];
#endif
if (runclk == 0) {
LOG(logERROR, ("runclk is 0. Cannot divide by 0. Returning -1.\n"));
return -1;
}
return numClocks / (1E-3 * runclk);
}
int validate_setPatternWaitClocksAndInterval(char *message, int level,
uint64_t waittime, int clocks) {
// validate input
if (level < 0 || level >= MAX_LEVELS) {
sprintf(message,
@@ -367,12 +394,21 @@ int validate_setPatternWaitTime(char *message, int level, uint64_t waittime) {
return FAIL;
}
setPatternWaitTime(level, waittime);
uint64_t retval = 0;
if (clocks) {
setPatternWaitClocks(level, waittime);
// validate result
retval = getPatternWaitClocks(level);
LOG(logDEBUG1, ("Pattern wait time in clocks (level:%d) retval: %d\n",
level, (long long int)retval));
} else {
setPatternWaitInterval(level, waittime);
// validate result
retval = getPatternWaitInterval(level);
LOG(logDEBUG1, ("Pattern wait time (level:%d) retval: %d\n", level,
(long long int)retval));
}
// validate result
uint64_t retval = getPatternWaitTime(level);
LOG(logDEBUG1, ("Pattern wait time (level:%d) retval: %d\n", level,
(long long int)retval));
int ret = OK;
char mode[128];
memset(mode, 0, sizeof(mode));
@@ -381,13 +417,13 @@ int validate_setPatternWaitTime(char *message, int level, uint64_t waittime) {
return ret;
}
void setPatternWaitTime(int level, uint64_t t) {
void setPatternWaitClocks(int level, uint64_t t) {
#ifdef MYTHEN3D
LOG(trimmingPrint,
#else
LOG(logINFO,
#endif
("Setting Pattern Wait Time (level:%d) :%lld\n", level,
("Setting Pattern Wait Time in clocks (level:%d) :%lld\n", level,
(long long int)t));
switch (level) {
case 0:
@@ -421,6 +457,26 @@ void setPatternWaitTime(int level, uint64_t t) {
}
}
void setPatternWaitInterval(int level, uint64_t t) {
#ifdef MYTHEN3D
LOG(trimmingPrint,
#else
LOG(logINFO,
#endif
("Setting Pattern Wait Time (level:%d) :%lld ns\n", level,
(long long int)t));
int runclk = 0;
#ifdef CHIPTESTBOARDD
runclk = clkFrequency[RUN_CLK];
#elif XILINX_CHIPTESTBOARDD
runclk = RUN_CLK;
#elif MYTHEN3D
runclk = clkDivider[SYSTEM_C0];
#endif
uint64_t numClocks = t * (1E-3 * runclk);
setPatternWaitClocks(level, numClocks);
}
int validate_getPatternLoopCycles(char *message, int level, int *numLoops) {
// validate input
if (level < 0 || level >= MAX_LEVELS) {
@@ -797,7 +853,7 @@ int loadPattern(char *message, enum TLogLevel printLevel,
}
}
// iocontrol
#if !defined(MYTHEN3D) && !defined(XILINX_CHIPTESTBOARDD) // TODO
#if !defined(MYTHEN3D)
if (ret == OK) {
ret = validate_writePatternIOControl(message, pat->ioctrl);
}
@@ -830,7 +886,8 @@ int loadPattern(char *message, enum TLogLevel printLevel,
}
// wait time
ret = validate_setPatternWaitTime(message, i, pat->waittime[i]);
ret = validate_setPatternWaitClocksAndInterval(message, i,
pat->waittime[i], 1);
if (ret == FAIL) {
break;
}
@@ -857,7 +914,7 @@ int getPattern(char *message, patternParameters *pat) {
pat->word[i] = retval64;
}
// iocontrol
#if !defined(MYTHEN3D) && !defined(XILINX_CHIPTESTBOARDD) // TODO
#if !defined(MYTHEN3D)
if (ret == OK) {
validate_readPatternIOControl();
}
@@ -894,7 +951,8 @@ int getPattern(char *message, patternParameters *pat) {
pat->wait[i] = retval1;
// wait time
ret = validate_getPatternWaitTime(message, i, &retval64);
ret = validate_getPatternWaitClocksAndInterval(message, i,
&retval64, 1);
if (ret == FAIL) {
break;
}
@@ -993,12 +1051,12 @@ int loadPatternFile(char *patFname, char *errMessage) {
}
// patioctrl
#if !defined(MYTHEN3D) && !defined(XILINX_CHIPTESTBOARDD) // TODO
#if !defined(MYTHEN3D) // TODO
if (!strncmp(line, "patioctrl", strlen("patioctrl"))) {
uint64_t arg = 0;
// cannot scan values
#ifdef VIRTUAL
#if defined(VIRTUAL) || defined(XILINX_CHIPTESTBOARDD)
if (sscanf(line, "%s 0x%lx", command, &arg) != 2) {
#else
if (sscanf(line, "%s 0x%llx", command, &arg) != 2) {
@@ -1095,7 +1153,8 @@ int loadPatternFile(char *patFname, char *errMessage) {
break;
}
if (validate_setPatternWaitTime(temp, level, waittime) == FAIL) {
if (validate_setPatternWaitClocksAndInterval(temp, level, waittime,
1) == FAIL) {
break;
}
}

66
slsDetectorServers/slsDetectorServer/src/slsDetectorServer.c
View File

@@ -30,11 +30,7 @@ extern int checkModuleFlag;
extern int ignoreConfigFileFlag;
// Global variables from slsDetectorFunctionList
#ifdef GOTTHARDD
extern int phaseShift;
#endif
#if defined(GOTTHARDD) || defined(GOTTHARD2D) || defined(EIGERD) || \
defined(MYTHEN3D)
#if defined(GOTTHARD2D) || defined(EIGERD) || defined(MYTHEN3D)
extern int masterCommandLine;
#endif
#ifdef EIGERD
@@ -59,8 +55,7 @@ int main(int argc, char *argv[]) {
char version[MAX_STR_LENGTH] = {0};
memset(version, 0, MAX_STR_LENGTH);
ignoreConfigFileFlag = 0;
#if defined(GOTTHARDD) || defined(GOTTHARD2D) || defined(EIGERD) || \
defined(MYTHEN3D)
#if defined(GOTTHARD2D) || defined(EIGERD) || defined(MYTHEN3D)
masterCommandLine = -1;
#endif
#ifdef EIGERD
@@ -82,17 +77,16 @@ int main(int argc, char *argv[]) {
"\t-g, --nomodule : [Mythen3][Gotthard2][Xilinx Ctb] \n"
"\t Generic or No Module mode. Skips "
"detector type checks. \n"
"\t-f, --phaseshift <value> : [Gotthard] only. Sets phase shift. \n"
"\t-d, --devel : Developer mode. Skips firmware "
"checks. \n"
"\t-u, --update : Update mode. Skips firmware checks "
"and "
"initial detector setup. \n"
"\t-i, --ignore-config : "
"[Eiger][Jungfrau][Gotthard][Gotthard2] \n"
"[Eiger][Jungfrau][Gotthard2] \n"
"\t Ignore config file. \n"
"\t-m, --master <master> : "
"[Eiger][Mythen3][Gotthard][Gotthard2] \n"
"[Eiger][Mythen3][Gotthard2] \n"
"\t Set Master to 0 or 1. Precedence "
"over "
"config file. Only for virtual servers except Eiger. \n"
@@ -117,7 +111,6 @@ int main(int argc, char *argv[]) {
{"help", no_argument, NULL, 'h'},
{"version", no_argument, NULL, 'v'},
{"port", required_argument, NULL, 'p'},
{"phaseshift", required_argument, NULL, 'f'},
{"nomodule", no_argument, NULL, 'g'}, // generic
{"devel", no_argument, NULL, 'd'},
{"update", no_argument, NULL, 'u'},
@@ -133,7 +126,7 @@ int main(int argc, char *argv[]) {
int c = 0;
while (c != -1) {
c = getopt_long(argc, argv, "hvp:f:gduim:t:s", long_options,
c = getopt_long(argc, argv, "hvp:gduim:t:s", long_options,
&option_index);
// Detect the end of the options
@@ -143,9 +136,7 @@ int main(int argc, char *argv[]) {
switch (c) {
case 'v':
#ifdef GOTTHARDD
strcpy(version, APIGOTTHARD);
#elif EIGERD
#ifdef EIGERD
strcpy(version, APIEIGER);
#elif JUNGFRAUD
strcpy(version, APIJUNGFRAU);
@@ -157,33 +148,20 @@ int main(int argc, char *argv[]) {
strcpy(version, APIMYTHEN3);
#elif GOTTHARD2D
strcpy(version, APIGOTTHARD2);
#elif XILINX_CHIPTESTBOARDD
strcpy(version, APIXILINXCTB);
#endif
LOG(logINFO, ("SLS Detector Server Version: %s\n", version));
exit(EXIT_SUCCESS);
return EXIT_SUCCESS;
case 'p':
if (sscanf(optarg, "%d", &portno) != 1) {
LOG(logERROR, ("Cannot scan port argument\n%s", helpMessage));
exit(EXIT_FAILURE);
return EXIT_FAILURE;
}
LOG(logINFO, ("Detected port: %d\n", portno));
break;
case 'f':
#ifndef GOTTHARDD
LOG(logERROR,
("Phase shift argument not implemented for this detector\n"));
exit(EXIT_FAILURE);
#else
if (sscanf(optarg, "%d", &phaseShift) != 1) {
LOG(logERROR,
("Cannot scan phase shift argument\n%s", helpMessage));
exit(EXIT_FAILURE);
}
LOG(logINFO, ("Detected phase shift: %d\n", phaseShift));
#endif
break;
case 'g':
LOG(logINFO, ("Detected generic mode (no module)\n"));
checkModuleFlag = 0;
@@ -205,13 +183,12 @@ int main(int argc, char *argv[]) {
break;
case 'i':
#if defined(EIGERD) || defined(GOTTHARDD) || defined(GOTTHARD2D) || \
defined(JUNGFRAUD)
#if defined(EIGERD) || defined(GOTTHARD2D) || defined(JUNGFRAUD)
LOG(logINFO, ("Ignoring config file\n"));
ignoreConfigFileFlag = 1;
#else
LOG(logERROR, ("No server config files for this detector\n"));
exit(EXIT_FAILURE);
return EXIT_FAILURE;
#endif
break;
@@ -219,12 +196,11 @@ int main(int argc, char *argv[]) {
#if !defined(VIRTUAL) && !defined(EIGERD)
LOG(logERROR, ("Cannot set master via the detector server for this "
"detector\n"));
exit(EXIT_FAILURE);
#elif defined(GOTTHARDD) || defined(GOTTHARD2D) || defined(EIGERD) || \
defined(MYTHEN3D)
return EXIT_FAILURE;
#elif defined(GOTTHARD2D) || defined(EIGERD) || defined(MYTHEN3D)
if (sscanf(optarg, "%d", &masterCommandLine) != 1) {
LOG(logERROR, ("Cannot scan master argument\n%s", helpMessage));
exit(EXIT_FAILURE);
return EXIT_FAILURE;
}
if (masterCommandLine == 1) {
LOG(logINFO, ("Detector Master mode\n"));
@@ -233,7 +209,7 @@ int main(int argc, char *argv[]) {
}
#else
LOG(logERROR, ("No master implemented for this detector server\n"));
exit(EXIT_FAILURE);
return EXIT_FAILURE;
#endif
break;
@@ -241,7 +217,7 @@ int main(int argc, char *argv[]) {
#ifdef EIGERD
if (sscanf(optarg, "%d", &topCommandLine) != 1) {
LOG(logERROR, ("Cannot scan top argument\n%s", helpMessage));
exit(EXIT_FAILURE);
return EXIT_FAILURE;
}
if (topCommandLine == 1) {
LOG(logINFO, ("Detector Top mode\n"));
@@ -250,16 +226,16 @@ int main(int argc, char *argv[]) {
}
#else
LOG(logERROR, ("No top implemented for this detector server\n"));
exit(EXIT_FAILURE);
return EXIT_FAILURE;
#endif
break;
case 'h':
printf("%s", helpMessage);
exit(EXIT_SUCCESS);
return EXIT_SUCCESS;
default:
printf("\n%s", helpMessage);
exit(EXIT_FAILURE);
return EXIT_FAILURE;
}
}
@@ -400,5 +376,5 @@ int main(int argc, char *argv[]) {
#endif
}
LOG(logINFO, ("Goodbye!\n"));
return 0;
return EXIT_SUCCESS;
}

385
slsDetectorServers/slsDetectorServer/src/slsDetectorServer_funcs.c
View File

@@ -20,9 +20,7 @@
#include <unistd.h>
// defined in the detector specific Makefile
#ifdef GOTTHARDD
const enum detectorType myDetectorType = GOTTHARD;
#elif EIGERD
#ifdef EIGERD
const enum detectorType myDetectorType = EIGER;
#elif JUNGFRAUD
const enum detectorType myDetectorType = JUNGFRAU;
@@ -281,7 +279,6 @@ void function_table() {
flist[F_SET_STORAGE_CELL_DELAY] = &set_storage_cell_delay;
flist[F_GET_FRAMES_LEFT] = &get_frames_left;
flist[F_GET_TRIGGERS_LEFT] = &get_triggers_left;
flist[F_GET_EXPTIME_LEFT] = &get_exptime_left;
flist[F_GET_PERIOD_LEFT] = &get_period_left;
flist[F_GET_DELAY_AFTER_TRIGGER_LEFT] = &get_delay_after_trigger_left;
flist[F_GET_MEASURED_PERIOD] = &get_measured_period;
@@ -290,8 +287,6 @@ void function_table() {
flist[F_GET_ACTUAL_TIME] = &get_actual_time;
flist[F_GET_MEASUREMENT_TIME] = &get_measurement_time;
flist[F_SET_DYNAMIC_RANGE] = &set_dynamic_range;
flist[F_SET_ROI] = &set_roi;
flist[F_GET_ROI] = &get_roi;
flist[F_LOCK_SERVER] = &lock_server;
flist[F_GET_LAST_CLIENT_IP] = &get_last_client_ip;
flist[F_ENABLE_TEN_GIGA] = &enable_ten_giga;
@@ -302,7 +297,7 @@ void function_table() {
flist[F_SET_PATTERN_LOOP_ADDRESSES] = &set_pattern_loop_addresses;
flist[F_SET_PATTERN_LOOP_CYCLES] = &set_pattern_loop_cycles;
flist[F_SET_PATTERN_WAIT_ADDR] = &set_pattern_wait_addr;
flist[F_SET_PATTERN_WAIT_TIME] = &set_pattern_wait_time;
flist[F_SET_PATTERN_WAIT_CLOCKS] = &set_pattern_wait_clocks;
flist[F_SET_PATTERN_MASK] = &set_pattern_mask;
flist[F_GET_PATTERN_MASK] = &get_pattern_mask;
flist[F_SET_PATTERN_BIT_MASK] = &set_pattern_bit_mask;
@@ -518,7 +513,8 @@ void function_table() {
flist[F_SET_TIMING_INFO_DECODER] = &set_timing_info_decoder;
flist[F_GET_COLLECTION_MODE] = &get_collection_mode;
flist[F_SET_COLLECTION_MODE] = &set_collection_mode;
flist[F_GET_PATTERN_WAIT_INTERVAL] = &get_pattern_wait_interval;
flist[F_SET_PATTERN_WAIT_INTERVAL] = &set_pattern_wait_interval;
// check
if (NUM_DET_FUNCTIONS >= RECEIVER_ENUM_START) {
LOG(logERROR, ("The last detector function enum has reached its "
@@ -642,7 +638,7 @@ int get_external_signal_flag(int file_des) {
LOG(logDEBUG1, ("Getting external signal flag (%d)\n", arg));
#if !defined(GOTTHARDD) && !defined(MYTHEN3D)
#if !defined(MYTHEN3D)
functionNotImplemented();
#else
// get
@@ -673,7 +669,7 @@ int set_external_signal_flag(int file_des) {
LOG(logDEBUG1,
("Setting external signal flag [%d] to %d\n", signalIndex, flag));
#if !defined(GOTTHARDD) && !defined(MYTHEN3D)
#if !defined(MYTHEN3D)
functionNotImplemented();
#else
if (Server_VerifyLock() == OK) {
@@ -831,8 +827,8 @@ int set_firmware_test(int file_des) {
memset(mess, 0, sizeof(mess));
LOG(logDEBUG1, ("Executing firmware test\n"));
#if !defined(GOTTHARDD) && !defined(JUNGFRAUD) && !defined(MOENCHD) && \
!defined(CHIPTESTBOARDD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(GOTTHARD2D) && !defined(MYTHEN3D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@@ -850,8 +846,8 @@ int set_bus_test(int file_des) {
memset(mess, 0, sizeof(mess));
LOG(logDEBUG1, ("Executing bus test\n"));
#if !defined(GOTTHARDD) && !defined(JUNGFRAUD) && !defined(MOENCHD) && \
!defined(CHIPTESTBOARDD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D)
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(GOTTHARD2D) && !defined(MYTHEN3D)
functionNotImplemented();
#else
ret = testBus();
@@ -872,8 +868,7 @@ int set_image_test_mode(int file_des) {
return printSocketReadError();
LOG(logDEBUG1, ("Setting image test mode to \n", arg));
#if defined(GOTTHARDD) || \
((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
#if ((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
defined(VIRTUAL))
setTestImageMode(arg);
#else
@@ -888,8 +883,7 @@ int get_image_test_mode(int file_des) {
int retval = -1;
LOG(logDEBUG1, ("Getting image test mode\n"));
#if defined(GOTTHARDD) || \
((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
#if ((defined(EIGERD) || defined(JUNGFRAUD) || defined(MOENCHD)) && \
defined(VIRTUAL))
retval = getTestImageMode();
LOG(logDEBUG1, ("image test mode retval: %d\n", retval));
@@ -903,32 +897,7 @@ enum DACINDEX getDACIndex(enum dacIndex ind) {
enum DACINDEX serverDacIndex = -1;
// check if dac exists for this detector
switch (ind) {
#ifdef GOTTHARDD
case VREF_DS:
serverDacIndex = G_VREF_DS;
break;
case VCASCN_PB:
serverDacIndex = G_VCASCN_PB;
break;
case VCASCP_PB:
serverDacIndex = G_VCASCP_PB;
break;
case VOUT_CM:
serverDacIndex = G_VOUT_CM;
break;
case VCASC_OUT:
serverDacIndex = G_VCASC_OUT;
break;
case VIN_CM:
serverDacIndex = G_VIN_CM;
break;
case VREF_COMP:
serverDacIndex = G_VREF_COMP;
break;
case IB_TESTC:
serverDacIndex = G_IB_TESTC;
break;
#elif EIGERD
#ifdef EIGERD
case VTHRESHOLD:
serverDacIndex = E_VTHRESHOLD;
break;
@@ -1273,15 +1242,7 @@ int validateAndSetDac(enum dacIndex ind, int val, int mV) {
#endif
#endif
#ifdef GOTTHARDD
if (retval == -1) {
ret = FAIL;
strcpy(mess, "Invalid Voltage. Valid values are 0, 90, "
"110, 120, 150, 180, 200\n");
LOG(logERROR, (mess));
} else
validate(&ret, mess, val, retval, "set high voltage", DEC);
#elif EIGERD
#ifdef EIGERD
if ((retval != SLAVE_HIGH_VOLTAGE_READ_VAL) && (retval < 0)) {
ret = FAIL;
if (retval == -1)
@@ -1524,7 +1485,7 @@ int get_adc(int file_des) {
serverAdcIndex = TEMP_FPGA;
break;
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MOENCHD)
#if defined(JUNGFRAUD) || defined(MOENCHD)
case TEMPERATURE_FPGA:
serverAdcIndex = TEMP_FPGA;
break;
@@ -1693,14 +1654,9 @@ int write_register(int file_des) {
sprintf(mess, "Could not write to register 0x%x.\n", addr);
LOG(logERROR, (mess));
}
#else
#ifdef GOTTHARDD
writeRegister16And32(addr, val);
uint32_t retval = readRegister16And32(addr);
#else
writeRegister(addr, val);
uint32_t retval = readRegister(addr);
#endif
LOG(logDEBUG1, ("Write register retval (0x%x): 0x%x\n", addr, retval));
// validate
if (validate && ret == OK && retval != val) {
@@ -1737,8 +1693,6 @@ int read_register(int file_des) {
addr);
LOG(logERROR, (mess));
}
#elif GOTTHARDD
retval = readRegister16And32(addr);
#else
retval = readRegister(addr);
#endif
@@ -1872,12 +1826,6 @@ void validate_settings(enum detectorSettings sett) {
#elif JUNGFRAUD
case GAIN0:
case HIGHGAIN0:
#elif GOTTHARDD
case DYNAMICGAIN:
case HIGHGAIN:
case LOWGAIN:
case MEDIUMGAIN:
case VERYHIGHGAIN:
#elif GOTTHARD2D
case DYNAMICGAIN:
case FIXGAIN1:
@@ -1938,16 +1886,6 @@ int set_settings(int file_des) {
if ((int)isett != GET_FLAG) {
validate(&ret, mess, (int)isett, (int)retval, "set settings", DEC);
#ifdef GOTTHARDD
if (ret == OK) {
ret = resetToDefaultDacs(0);
if (ret == FAIL) {
strcpy(mess, "Could change settings, but could not set to "
"default dacs\n");
LOG(logERROR, (mess));
}
}
#endif
#ifdef MYTHEN3D
// changed for setsettings (direct),
// custom trimbit file (setmodule with myMod.reg as -1),
@@ -2706,8 +2644,8 @@ int get_delay_after_trigger(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(GOTTHARDD) && \
!defined(CHIPTESTBOARDD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@@ -2729,8 +2667,8 @@ int set_delay_after_trigger(int file_des) {
LOG(logDEBUG1,
("Setting delay after trigger %lld ns\n", (long long int)arg));
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(GOTTHARDD) && \
!defined(CHIPTESTBOARDD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@@ -2940,8 +2878,8 @@ int get_frames_left(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(GOTTHARDD) && \
!defined(CHIPTESTBOARDD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@@ -2958,8 +2896,8 @@ int get_triggers_left(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(GOTTHARDD) && \
!defined(CHIPTESTBOARDD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@@ -2970,28 +2908,13 @@ int get_triggers_left(int file_des) {
return Server_SendResult(file_des, INT64, &retval, sizeof(retval));
}
int get_exptime_left(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#ifndef GOTTHARDD
functionNotImplemented();
#else
// get only
retval = getExpTimeLeft();
LOG(logDEBUG1, ("retval exptime left %lld ns\n", (long long int)retval));
#endif
return Server_SendResult(file_des, INT64, &retval, sizeof(retval));
}
int get_period_left(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(GOTTHARDD) && \
!defined(CHIPTESTBOARDD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@@ -3007,8 +2930,8 @@ int get_delay_after_trigger_left(int file_des) {
memset(mess, 0, sizeof(mess));
int64_t retval = -1;
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(GOTTHARDD) && \
!defined(CHIPTESTBOARDD) && !defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(MYTHEN3D) && !defined(GOTTHARD2D) && \
!defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
@@ -3132,9 +3055,8 @@ int set_dynamic_range(int file_des) {
case 16:
case 32:
#endif
#if defined(GOTTHARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(CHIPTESTBOARDD) || defined(GOTTHARD2D) || \
defined(XILINX_CHIPTESTBOARDD)
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD) || \
defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)
case 16:
#endif
if (dr >= 0) {
@@ -3165,67 +3087,6 @@ int set_dynamic_range(int file_des) {
return Server_SendResult(file_des, INT32, &retval, sizeof(retval));
}
int set_roi(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
ROI arg;
// receive ROI
if (receiveData(file_des, &arg.xmin, sizeof(int), INT32) < 0)
return printSocketReadError();
if (receiveData(file_des, &arg.xmax, sizeof(int), INT32) < 0)
return printSocketReadError();
if (receiveData(file_des, &arg.ymin, sizeof(int), INT32) < 0)
return printSocketReadError();
if (receiveData(file_des, &arg.ymax, sizeof(int), INT32) < 0)
return printSocketReadError();
LOG(logDEBUG1, ("Set ROI: [%d, %d, %d, %d]\n", arg.xmin, arg.xmax, arg.ymin,
arg.ymax));
#ifndef GOTTHARDD
functionNotImplemented();
#else
// only set
if (Server_VerifyLock() == OK) {
ret = setROI(arg);
if (ret == FAIL) {
sprintf(mess, "Could not set ROI. Invalid xmin or xmax\n");
LOG(logERROR, (mess));
}
// old firmware requires a redo configure mac
else {
configure_mac();
}
}
#endif
return Server_SendResult(file_des, INT32, NULL, 0);
}
int get_roi(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
ROI retval;
#ifndef GOTTHARDD
functionNotImplemented();
#else
// only get
retval = getROI();
LOG(logDEBUG1, ("nRois: (%d, %d, %d, %d)\n", retval.xmin, retval.xmax,
retval.ymin, retval.ymax));
#endif
Server_SendResult(file_des, INT32, NULL, 0);
if (ret != FAIL) {
sendData(file_des, &retval.xmin, sizeof(int), INT32);
sendData(file_des, &retval.xmax, sizeof(int), INT32);
sendData(file_des, &retval.ymin, sizeof(int), INT32);
sendData(file_des, &retval.ymax, sizeof(int), INT32);
}
return ret;
}
int lock_server(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
@@ -3275,8 +3136,8 @@ int enable_ten_giga(int file_des) {
return printSocketReadError();
LOG(logDEBUG, ("Setting 10GbE: %d\n", arg));
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(GOTTHARDD) || \
defined(GOTTHARD2D) || defined(XILINX_CHIPTESTBOARDD)
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(GOTTHARD2D) || \
defined(XILINX_CHIPTESTBOARDD)
functionNotImplemented();
#else
// set & get
@@ -3535,13 +3396,13 @@ int set_pattern_wait_addr(int file_des) {
return Server_SendResult(file_des, INT32, &retval, sizeof(retval));
}
int set_pattern_wait_time(int file_des) {
int set_pattern_wait_clocks(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
uint64_t args[2] = {-1, -1};
uint64_t retval = -1;
if (receiveData(file_des, args, sizeof(args), INT32) < 0)
if (receiveData(file_des, args, sizeof(args), INT64) < 0)
return printSocketReadError();
#if !defined(CHIPTESTBOARDD) && !defined(XILINX_CHIPTESTBOARDD) && \
!defined(MYTHEN3D)
@@ -3549,16 +3410,23 @@ int set_pattern_wait_time(int file_des) {
#else
int loopLevel = (int)args[0];
uint64_t timeval = args[1];
LOG(logDEBUG1, ("Setting Pattern wait time (loopLevel:%d timeval:0x%llx)\n",
loopLevel, (long long int)timeval));
LOG(logDEBUG1,
("Setting Pattern wait clocks (loopLevel:%d clocks:0x%lld)\n",
loopLevel, (long long int)timeval));
if (((int64_t)timeval == GET_FLAG) || (Server_VerifyLock() == OK)) {
// set
if ((int64_t)timeval != GET_FLAG) {
ret = validate_setPatternWaitTime(mess, loopLevel, timeval);
ret = validate_setPatternWaitClocksAndInterval(mess, loopLevel,
timeval, 1);
}
// get
if (ret == OK) {
ret = validate_getPatternWaitTime(mess, loopLevel, &retval);
ret = validate_getPatternWaitClocksAndInterval(mess, loopLevel,
&retval, 1);
if ((int64_t)timeval != GET_FLAG) {
validate64(&ret, mess, (int64_t)timeval, retval,
"set pattern wait clocks", DEC);
}
}
}
#endif
@@ -3688,12 +3556,6 @@ int write_adc_register(int file_des) {
if (Server_VerifyLock() == OK) {
#if defined(JUNGFRAUD) || defined(MOENCHD) || defined(CHIPTESTBOARDD)
AD9257_Set(addr, val);
#elif GOTTHARDD
if (isHardwareVersion_1_0()) {
AD9252_Set(addr, val);
} else {
AD9257_Set(addr, val);
}
#endif
}
#endif
@@ -4060,7 +3922,7 @@ int program_fpga(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
#if defined(EIGERD) || defined(GOTTHARDD)
#if defined(EIGERD)
functionNotImplemented();
return Server_SendResult(file_des, INT32, NULL, 0);
#else
@@ -4074,8 +3936,7 @@ int reset_fpga(int file_des) {
memset(mess, 0, sizeof(mess));
LOG(logDEBUG1, ("Reset FPGA\n"));
#if defined(EIGERD) || defined(GOTTHARDD) || defined(GOTTHARD2D) || \
defined(MYTHEN3D)
#if defined(EIGERD) || defined(GOTTHARD2D) || defined(MYTHEN3D)
functionNotImplemented();
#else
// only set
@@ -5481,7 +5342,8 @@ int set_dest_udp_mac(int file_des) {
if (receiveData(file_des, &arg, sizeof(arg), INT64) < 0)
return printSocketReadError();
LOG(logINFO, ("Setting udp destination mac: 0x%lx\n", arg));
LOG(logINFO,
("Setting udp destination mac: 0x%llx\n", (long long unsigned)arg));
// only set
if (Server_VerifyLock() == OK) {
@@ -5502,7 +5364,8 @@ int get_dest_udp_mac(int file_des) {
LOG(logDEBUG1, ("Getting udp destination mac\n"));
// get only
retval = udpDetails[0].dstmac;
LOG(logDEBUG1, ("udp destination mac retval: 0x%lx\n", retval));
LOG(logDEBUG1,
("udp destination mac retval: 0x%llx\n", (long long unsigned)retval));
return Server_SendResult(file_des, INT64, &retval, sizeof(retval));
}
@@ -6052,7 +5915,7 @@ int set_clock_phase(int file_des) {
(args[2] == 0 ? "" : "degrees")));
#if !defined(CHIPTESTBOARDD) && !defined(JUNGFRAUD) && !defined(MOENCHD) && \
!defined(GOTTHARDD) && !defined(GOTTHARD2D) && !defined(MYTHEN3D)
!defined(GOTTHARD2D) && !defined(MYTHEN3D)
functionNotImplemented();
#else
// only set
@@ -6062,8 +5925,7 @@ int set_clock_phase(int file_des) {
int inDegrees = args[2] == 0 ? 0 : 1;
enum CLKINDEX c = 0;
switch (ind) {
#if defined(CHIPTESTBOARDD) || defined(JUNGFRAUD) || defined(MOENCHD) || \
defined(GOTTHARDD)
#if defined(CHIPTESTBOARDD) || defined(JUNGFRAUD) || defined(MOENCHD)
case ADC_CLOCK:
c = ADC_CLK;
break;
@@ -6093,15 +5955,6 @@ int set_clock_phase(int file_des) {
sprintf(modeName, "%s clock (%d) phase %s", clock_names[c], (int)c,
(inDegrees == 0 ? "" : "(degrees)"));
// gotthard1d doesnt take degrees and cannot get phase
#ifdef GOTTHARDD
if (inDegrees != 0) {
ret = FAIL;
strcpy(mess,
"Cannot set phase in degrees for this detector.\n");
LOG(logERROR, (mess));
}
#else
if (getPhase(c, inDegrees) == val) {
LOG(logINFO, ("Same %s: %d\n", modeName, val));
} else if (inDegrees && (val < 0 || val > 359)) {
@@ -6118,18 +5971,12 @@ int set_clock_phase(int file_des) {
"phase shifts)\n",
modeName, val, getMaxPhase(c) - 1);
LOG(logERROR, (mess));
}
#endif
else {
} else {
int ret = setPhase(c, val, inDegrees);
if (ret == FAIL) {
sprintf(mess, "Could not set %s to %d.\n", modeName, val);
LOG(logERROR, (mess));
}
// gotthard1d doesnt take degrees and cannot get phase
#ifndef GOTTHARDD
else {
} else {
int retval = getPhase(c, inDegrees);
LOG(logDEBUG1, ("retval %s : %d\n", modeName, retval));
if (!inDegrees) {
@@ -6145,7 +5992,6 @@ int set_clock_phase(int file_des) {
}
}
}
#endif
}
}
}
@@ -7411,7 +7257,8 @@ int get_receiver_parameters(int file_des) {
// dynamic range
ret = getDynamicRange(&i32);
if (ret == FAIL) {
i32 = 0;
sprintf(mess, "Could not get dynamic range.\n");
return sendError(file_des);
}
n += sendData(file_des, &i32, sizeof(i32), INT32);
if (n < 0)
@@ -7463,32 +7310,7 @@ int get_receiver_parameters(int file_des) {
if (n < 0)
return printSocketReadError();
// roi
{
ROI roi;
#ifdef GOTTHARDD
roi = getROI();
#else
roi.xmin = -1;
roi.xmax = -1;
roi.ymin = -1;
roi.ymax = -1;
#endif
n += sendData(file_des, &roi.xmin, sizeof(int), INT32);
if (n < 0)
return printSocketReadError();
n += sendData(file_des, &roi.xmax, sizeof(int), INT32);
if (n < 0)
return printSocketReadError();
n += sendData(file_des, &roi.ymin, sizeof(int), INT32);
if (n < 0)
return printSocketReadError();
n += sendData(file_des, &roi.ymax, sizeof(int), INT32);
if (n < 0)
return printSocketReadError();
}
// counter mask
// counter mask
#ifdef MYTHEN3D
u32 = getCounterMask();
#else
@@ -7615,6 +7437,20 @@ int get_receiver_parameters(int file_des) {
u32 = 0;
#endif
n += sendData(file_des, &u32, sizeof(u32), INT32);
if (n < 0)
return printSocketReadError();
// readout speed
#if !defined(CHIPTESTBOARDD) && !defined(XILINX_CHIPTESTBOARDD)
ret = getReadoutSpeed(&i32);
if (ret == FAIL) {
sprintf(mess, "Could not get readout speed.\n");
return sendError(file_des);
}
#else
i32 = 0;
#endif
n += sendData(file_des, &i32, sizeof(i32), INT32);
if (n < 0)
return printSocketReadError();
@@ -8459,8 +8295,7 @@ int get_bursts_left(int file_des) {
int start_readout(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
#if !defined(MYTHEN3D) && !defined(CHIPTESTBOARDD) && \
!defined(XILINX_CHIPTESTBOARDD)
#if !defined(MYTHEN3D) && !defined(CHIPTESTBOARDD)
functionNotImplemented();
#else
if (Server_VerifyLock() == OK) {
@@ -8594,8 +8429,8 @@ int get_master(int file_des) {
LOG(logDEBUG1, ("Getting master\n"));
#if !defined(MYTHEN3D) && !defined(EIGERD) && !defined(GOTTHARDD) && \
!defined(GOTTHARD2D) && !defined(JUNGFRAUD) && !defined(MOENCHD)
#if !defined(MYTHEN3D) && !defined(EIGERD) && !defined(GOTTHARD2D) && \
!defined(JUNGFRAUD) && !defined(MOENCHD)
functionNotImplemented();
#else
ret = isMaster(&retval);
@@ -9357,7 +9192,7 @@ int get_dest_udp_list(int file_des) {
memset(mess, 0, sizeof(mess));
uint32_t arg = 0;
uint16_t retvals16[2] = {};
uint32_t retvals32[3] = {};
uint32_t retvals32[2] = {};
uint64_t retvals64[2] = {};
if (receiveData(file_des, &arg, sizeof(arg), INT32) < 0)
@@ -9890,8 +9725,7 @@ void receive_program_via_blackfin(int file_des, enum PROGRAM_INDEX index,
char *checksum, char *serverName,
int forceDeleteNormalFile) {
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD) && \
!defined(GOTTHARDD)
#if !defined(JUNGFRAUD) && !defined(MOENCHD) && !defined(CHIPTESTBOARDD)
ret = FAIL;
sprintf(mess,
"Could not %s. program via blackfin not implmented for this "
@@ -10598,15 +10432,9 @@ int set_bit(int file_des) {
ret = setBit(addr, nBit, validate);
#else
uint32_t bitmask = (1 << nBit);
#ifdef GOTTHARDD
uint32_t val = readRegister16And32(addr) | bitmask;
writeRegister16And32(addr, val);
uint32_t retval = readRegister16And32(addr) | bitmask;
#else
uint32_t val = readRegister(addr) | bitmask;
writeRegister(addr, val);
uint32_t retval = readRegister(addr) | bitmask;
#endif
if (validate && (!(retval & bitmask))) {
ret = FAIL;
}
@@ -10647,15 +10475,9 @@ int clear_bit(int file_des) {
ret = clearBit(addr, nBit, validate);
#else
uint32_t bitmask = (1 << nBit);
#ifdef GOTTHARDD
uint32_t val = readRegister16And32(addr) & ~bitmask;
writeRegister16And32(addr, val);
uint32_t retval = readRegister16And32(addr) & ~bitmask;
#else
uint32_t val = readRegister(addr) & ~bitmask;
writeRegister(addr, val);
uint32_t retval = readRegister(addr) & ~bitmask;
#endif
if (validate && (retval & bitmask)) {
ret = FAIL;
}
@@ -10695,12 +10517,8 @@ int get_bit(int file_des) {
sprintf(mess, "Could not get bit %d.\n", nBit);
LOG(logERROR, (mess));
}
#else
#ifdef GOTTHARDD
uint32_t regval = readRegister16And32(addr);
#else
uint32_t regval = readRegister(addr);
#endif
retval = (regval & (1 << nBit)) >> nBit;
LOG(logDEBUG1, ("regval: 0x%x bit value:0%d\n", regval, retval));
#endif
@@ -11209,3 +11027,54 @@ int set_collection_mode(int file_des) {
#endif
return Server_SendResult(file_des, INT32, NULL, 0);
}
int get_pattern_wait_interval(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
int loopLevel = -1;
uint64_t retval = -1;
if (receiveData(file_des, &loopLevel, sizeof(loopLevel), INT32) < 0)
return printSocketReadError();
#if !defined(CHIPTESTBOARDD) && !defined(XILINX_CHIPTESTBOARDD) && \
!defined(MYTHEN3D)
functionNotImplemented();
#else
LOG(logDEBUG1,
("Getting Pattern wait interva (loopLevel:%d)\n", loopLevel));
ret = validate_getPatternWaitClocksAndInterval(mess, loopLevel, &retval, 0);
#endif
return Server_SendResult(file_des, INT64, &retval, sizeof(retval));
}
int set_pattern_wait_interval(int file_des) {
ret = OK;
memset(mess, 0, sizeof(mess));
uint64_t args[2] = {-1, -1};
if (receiveData(file_des, args, sizeof(args), INT64) < 0)
return printSocketReadError();
#if !defined(CHIPTESTBOARDD) && !defined(XILINX_CHIPTESTBOARDD) && \
!defined(MYTHEN3D)
functionNotImplemented();
#else
int loopLevel = (int)args[0];
uint64_t timeval = args[1];
LOG(logDEBUG1,
("Setting Pattern wait interval (loopLevel:%d timeval:0x%llx ns)\n",
loopLevel, (long long int)timeval));
if (Server_VerifyLock() == OK) {
ret = validate_setPatternWaitClocksAndInterval(mess, loopLevel, timeval,
0);
if (ret == OK) {
uint64_t retval = 0;
ret = validate_getPatternWaitClocksAndInterval(mess, loopLevel,
&retval, 0);
validate64(&ret, mess, (int64_t)timeval, retval,
"set pattern wait interval", DEC);
}
}
#endif
return Server_SendResult(file_des, INT64, NULL, 0);
}

6
slsDetectorServers/xilinx_ctbDetectorServer/CMakeLists.txt
View File

@@ -40,3 +40,9 @@ set_target_properties(xilinx_ctbDetectorServer_virtual PROPERTIES
install(TARGETS xilinx_ctbDetectorServer_virtual
RUNTIME DESTINATION ${CMAKE_INSTALL_BINDIR}
)
configure_file(chip_config_xilinx.txt ${CMAKE_BINARY_DIR}/bin/chip_config_xilinx.txt COPYONLY)
configure_file(reset_chip_xilinx.txt ${CMAKE_BINARY_DIR}/bin/reset_chip_xilinx.txt COPYONLY)
configure_file(enable_clock_pattern.pyat ${CMAKE_BINARY_DIR}/bin/enable_clock_pattern.pyat COPYONLY)
configure_file(readout_pattern.pyat ${CMAKE_BINARY_DIR}/bin/readout_pattern.pyat COPYONLY)

4
slsDetectorServers/xilinx_ctbDetectorServer/Makefile
View File

@@ -47,6 +47,10 @@ $(PROGS): $(OBJS)
mkdir -p $(DESTDIR)
$(CC) -o $@ $^ $(CFLAGS) $(LDLIBS)
mv $(PROGS) $(DESTDIR)
cp chip_config_xilinx.txt $(DESTDIR)
cp reset_chip_xilinx.txt $(DESTDIR)
cp enable_clock_pattern.pyat $(DESTDIR)
cp readout_pattern.pyat $(DESTDIR)
rm $(main_src)*.o $(md5_dir)*.o
clean:
rm -rf $(DESTDIR)/$(PROGS) *.o *.gdb $(main_src)*.o $(md5_dir)*.o

1107
slsDetectorServers/xilinx_ctbDetectorServer/RegisterDefs.h
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File diff suppressed because it is too large Load Diff

BIN
slsDetectorServers/xilinx_ctbDetectorServer/bin/xilinx_ctbDetectorServer_developer Executable file
View File

Binary file not shown.

BIN
slsDetectorServers/xilinx_ctbDetectorServer/bin/xilinx_ctbDetectorServerv9.1.0
View File

Binary file not shown.

24
slsDetectorServers/xilinx_ctbDetectorServer/chip_config_xilinx.txt Normal file
View File

@@ -0,0 +1,24 @@
# Prepare MH02 configuration
reg 0xB1B0 0x00000041
reg 0xB1B4 0x01200004
# configure Matterhorn SPI
setbit 0xB1B8 0
# wait till config is done
pollbit 0xB1B8 3 0
# reset transceiver
reg 0xB820 0x0
reg 0xB820 0x1
reg 0xB820 0x0
# set MSB LSB inversions and polarity for transceiver
reg 0xB820 0x61e0
# Enable MH02 PLL clock
pattern enable_clock_pattern.pyat
# start the flow
setbit 0xB004 0
clearbit 0xB004 0
sleep 1

8
slsDetectorServers/xilinx_ctbDetectorServer/enable_clock_pattern.pyat Normal file
View File

@@ -0,0 +1,8 @@
patword 0x0000 0x0000000000000000
patword 0x0001 0x0000000000008000
patword 0x0002 0x0000000000008000
patword 0x0003 0x0000000000008000
patword 0x0004 0x0000000000008000
patword 0x0005 0x0000000000008000
patioctrl 0x01b3ffff
patlimits 0x0000 0x0005

22
slsDetectorServers/xilinx_ctbDetectorServer/readout_pattern.pyat Normal file
View File

@@ -0,0 +1,22 @@
patword 0x0000 0x0000000000008000
patword 0x0001 0x0000000000008000
patword 0x0002 0x0000000000008000
patword 0x0003 0x0000000000008000
patword 0x0004 0x0000000000008000
patword 0x0005 0x0000000000008000
patword 0x0006 0x0000000000008000
patword 0x0007 0x0000000000008000
patword 0x0008 0x0000000000008000
patword 0x0009 0x0000000000008000
patword 0x000a 0x0000000000008000
patword 0x000b 0x0000000000108000
patword 0x000c 0x0000000000108000
patword 0x000d 0x0000000000108000
patword 0x000e 0x0000000000108000
patword 0x000f 0x0000000000008000
patword 0x0010 0x0000000000008000
patword 0x0011 0x0000000000008000
patword 0x0012 0x0000000000008000
patword 0x0013 0x0000000000008000
patioctrl 0x01b3ffff
patlimits 0x0000 0x0013

40
slsDetectorServers/xilinx_ctbDetectorServer/reset_chip_xilinx.txt Normal file
View File

@@ -0,0 +1,40 @@
# turn off clock
setbit 0xB1B0 16
setbit 0xB1B8 0
sleep 1
# reset Matterhorn periphery
setbit 0xB1B8 1
sleep 1
# turn on clock
clearbit 0xB1B0 16
setbit 0xB1B8 0
sleep 1
# reset rx transceiver datapath
setbit 0xB820 4
sleep 1
# reset 8b10b counters
setbit 0xB820 9
setbit 0xB820 10
setbit 0xB820 11
setbit 0xB820 12
sleep 1
clearbit 0xB820 9
clearbit 0xB820 10
# reset buffer fifos
reg 0x9024 0xFFFFFFFF
reg 0x9028 0xFFFFFFFF
reg 0x902C 0xFFFFFFFF
reg 0x9024 0x0
reg 0x9028 0x0
reg 0x902C 0x0
setbit 0xA000 18
# load default pattern
pattern readout_pattern.pyat

374
slsDetectorServers/xilinx_ctbDetectorServer/slsDetectorFunctionList.c
View File

@@ -492,7 +492,19 @@ void setTransceiverAlignment(int align) {
#endif
int isTransceiverAligned() {
return (bus_r(TRANSCEIVERSTATUS) & RXBYTEISALIGNED_MSK);
#ifdef VIRTUAL
return 1;
#endif
int times = 0;
int retval = bus_r(TRANSCEIVERSTATUS2) & RXLOCKED_MSK;
while (retval) {
retval = bus_r(TRANSCEIVERSTATUS2) & RXLOCKED_MSK;
times++;
usleep(10);
if (times == 5)
return 1;
}
return retval;
}
int waitTransceiverAligned(char *mess) {
@@ -511,7 +523,9 @@ int waitTransceiverAligned(char *mess) {
int times = 0;
while (transceiverWordAligned == 0) {
if (times++ > WAIT_TIME_OUT_0US_TIMES) {
sprintf(mess, "Transceiver alignment timed out\n");
sprintf(mess, "Transceiver alignment timed out. Check connection, "
"p-n inversions, LSB-MSB inversions, link error "
"counters and channel enable settings\n");
LOG(logERROR, (mess));
return FAIL;
}
@@ -587,34 +601,197 @@ int getPowerChip() {
int configureChip(char *mess) {
LOG(logINFOBLUE, ("\tConfiguring chip\n"));
// enable correct endianness (Only for MH_PR_2)
// uint32_t addr = MATTERHORNSPIREG1;
// bus_w(addr, bus_r(addr) &~MATTERHORNSPI1_MSK);
// bus_w(addr, bus_r(addr) | ((0x40000 << MATTERHORNSPI1_OFST) &
// MATTERHORNSPI1_MSK));
// start configuration
uint32_t addr = MATTERHORNSPICTRL;
bus_w(addr, bus_r(addr) | CONFIGSTART_P_MSK);
bus_w(addr, bus_r(addr) & ~CONFIGSTART_P_MSK);
// wait until configuration is done
#ifndef VIRTUAL
int configDone = (bus_r(MATTERHORNSPICTRL) & BUSY_MSK);
int times = 0;
while (configDone == 0) {
if (times++ > WAIT_TIME_OUT_0US_TIMES) {
sprintf(mess, "Configuration of chip timed out\n");
LOG(logERROR, (mess));
return FAIL;
}
usleep(0);
configDone = (bus_r(MATTERHORNSPICTRL) & BUSY_MSK);
chipConfigured = 0;
if (readConfigFile(mess, CONFIG_CHIP_FILE, "chip config") == FAIL) {
return FAIL;
}
#endif
if (readConfigFile(mess, RESET_CHIP_FILE, "reset chip") == FAIL) {
return FAIL;
}
LOG(logINFOBLUE, ("Chip configured.\n"));
chipConfigured = 1;
LOG(logINFOBLUE, ("\tChip configured\n"));
return OK;
}
int readConfigFile(char *mess, char *fileName, char *fileType) {
const int fileNameSize = 128;
char fname[fileNameSize];
if (getAbsPath(fname, fileNameSize, fileName) == FAIL) {
sprintf(mess, "Could not get full path for %s file [%s].\n", fileType,
fname);
LOG(logERROR, (mess));
return FAIL;
}
if (access(fname, F_OK) != 0) {
sprintf(mess, "Could not find %s file [%s].\n", fileType, fname);
LOG(logERROR, (mess));
return FAIL;
}
FILE *fd = fopen(fname, "r");
if (fd == NULL) {
sprintf(mess, "Could not open on-board detector server %s file [%s].\n",
fileType, fname);
LOG(logERROR, (mess));
return FAIL;
}
LOG(logINFOBLUE, ("Reading %s file %s\n", fileType, fname));
const size_t LZ = 256;
char line[LZ];
memset(line, 0, LZ);
char command[LZ];
// keep reading a line
while (fgets(line, LZ, fd)) {
// ignore comments
if (line[0] == '#') {
LOG(logDEBUG1, ("Ignoring Comment\n"));
continue;
}
// ignore empty lines
if (strlen(line) <= 1) {
LOG(logDEBUG1, ("Ignoring Empty line\n"));
continue;
}
// removing leading spaces
if (line[0] == ' ' || line[0] == '\t') {
int len = strlen(line);
// find first valid character
int i = 0;
for (i = 0; i < len; ++i) {
if (line[i] != ' ' && line[i] != '\t') {
break;
}
}
// ignore the line full of spaces (last char \n)
if (i >= len - 1) {
LOG(logDEBUG1, ("Ignoring line full of spaces\n"));
continue;
}
// copying only valid char
char temp[LZ];
memset(temp, 0, LZ);
memcpy(temp, line + i, strlen(line) - i);
memset(line, 0, LZ);
memcpy(line, temp, strlen(temp));
LOG(logDEBUG1, ("Removing leading spaces.\n"));
}
LOG(logDEBUG1, ("Command to process: (size:%d) %.*s\n", strlen(line),
strlen(line) - 1, line));
memset(command, 0, LZ);
// reg command
if (!strncmp(line, "reg", strlen("reg"))) {
uint32_t addr = 0;
uint32_t val = 0;
if (sscanf(line, "%s %x %x", command, &addr, &val) != 3) {
sprintf(mess, "Could not scan reg command. Line:[%s].\n", line);
LOG(logERROR, (mess));
return FAIL;
}
bus_w(addr, val);
LOG(logINFOBLUE, ("Wrote 0x%x to 0x%x\n", val, addr));
}
// setbit command
else if (!strncmp(line, "setbit", strlen("setbit"))) {
uint32_t addr = 0;
uint32_t bit = 0;
if (sscanf(line, "%s %x %d", command, &addr, &bit) != 3) {
sprintf(mess, "Could not scan setbit command. Line:[%s].\n",
line);
LOG(logERROR, (mess));
return FAIL;
}
bus_w(addr, bus_r(addr) | (1 << bit));
LOG(logINFOBLUE, ("Set bit %d in 0x%x\n", bit, addr));
}
// clearbit command
else if (!strncmp(line, "clearbit", strlen("clearbit"))) {
uint32_t addr = 0;
uint32_t bit = 0;
if (sscanf(line, "%s %x %d", command, &addr, &bit) != 3) {
sprintf(mess, "Could not scan clearbit command. Line:[%s].\n",
line);
LOG(logERROR, (mess));
return FAIL;
}
bus_w(addr, bus_r(addr) & ~(1 << bit));
LOG(logINFOBLUE, ("Cleared bit %d in 0x%x\n", bit, addr));
}
// pollbit command
else if (!strncmp(line, "pollbit", strlen("pollbit"))) {
uint32_t addr = 0;
uint32_t bit = 0;
uint32_t val = 0;
if (sscanf(line, "%s %x %d %d", command, &addr, &bit, &val) != 4) {
sprintf(mess, "Could not scan pollbit command. Line:[%s].\n",
line);
LOG(logERROR, (mess));
return FAIL;
}
#ifndef VIRTUAL
int times = 0;
while (((bus_r(addr) >> bit) & 0x1) != val) {
if (times++ > WAIT_TIME_OUT_0US_TIMES) {
sprintf(mess, "Polling bit %d in 0x%x timed out\n", bit,
addr);
LOG(logERROR, (mess));
return FAIL;
}
usleep(0);
}
#endif
LOG(logINFOBLUE, ("Polled bit %d in 0x%x\n", bit, addr));
}
// pattern command
else if (!strncmp(line, "pattern", strlen("pattern"))) {
// take a file name and call loadPatterFile
char patternFileName[LZ];
if (sscanf(line, "%s %s", command, patternFileName) != 2) {
sprintf(mess, "Could not scan pattern command. Line:[%s].\n",
line);
LOG(logERROR, (mess));
return FAIL;
}
if (loadPatternFile(patternFileName, mess) == FAIL) {
return FAIL;
}
LOG(logINFOBLUE, ("loaded pattern [%s].\n", patternFileName));
}
// sleep command
else if (!strncmp(line, "sleep", strlen("sleep"))) {
int time = 0;
if (sscanf(line, "%s %d", command, &time) != 2) {
sprintf(mess, "Could not scan sleep command. Line:[%s].\n",
line);
LOG(logERROR, (mess));
return FAIL;
}
usleep(time * 1000 * 1000);
LOG(logINFOBLUE, ("Slept for %d s\n", time));
}
// other commands
else {
sprintf(mess,
"Could not scan command from on-board server "
"%s file. Line:[%s].\n",
fileType, line);
break;
}
memset(line, 0, LZ);
}
fclose(fd);
LOG(logINFOBLUE, ("Successfully read %s file.\n", fileType));
return OK;
}
@@ -863,24 +1040,17 @@ int getNumTransceiverSamples() {
}
int setExpTime(int64_t val) {
if (val < 0) {
LOG(logERROR, ("Invalid exptime: %lld ns\n", (long long int)val));
return FAIL;
}
LOG(logINFO, ("Setting exptime %lld ns\n", (long long int)val));
val *= (1E-3 * RUN_CLK);
setPatternWaitTime(0, val);
setPatternWaitInterval(0, val);
// validate for tolerance
int64_t retval = getExpTime();
val /= (1E-3 * RUN_CLK);
if (val != retval) {
return FAIL;
}
return OK;
}
int64_t getExpTime() { return getPatternWaitTime(0) / (1E-3 * RUN_CLK); }
int64_t getExpTime() { return getPatternWaitInterval(0); }
int setPeriod(int64_t val) {
if (val < 0) {
@@ -1335,31 +1505,13 @@ int startStateMachine() {
return OK;
#endif
LOG(logINFOBLUE, ("Starting State Machine\n"));
// cleanFifos(); removing this for now as its done before readout pattern
LOG(logINFOBLUE, ("Starting readout\n"));
// start state machine
bus_w(FLOW_CONTROL_REG, bus_r(FLOW_CONTROL_REG) | START_F_MSK);
LOG(logINFORED, ("Waiting for exposing to be done\n"));
int exposingDone = (bus_r(FLOW_STATUS_REG) & RSM_BUSY_MSK);
while (exposingDone != 0) {
usleep(0);
exposingDone = (bus_r(FLOW_STATUS_REG) & RSM_BUSY_MSK);
}
LOG(logINFORED, ("Starting readout of chip to fifo\n"));
// MM:readout via pattern does not work right now due to firmware bug,
// readout via MatterhornCTRL for the moment
// bus_w(FLOW_CONTROL_REG, bus_r(FLOW_CONTROL_REG) | START_F_MSK);
bus_w(MATTERHORNSPICTRL, bus_r(MATTERHORNSPICTRL) | STARTREAD_P_MSK);
LOG(logINFORED, ("Waiting until k-words or end of acquisition\n"));
usleep(0);
int commaDet = (bus_r(TRANSCEIVERSTATUS) & RXCOMMADET_MSK);
while (commaDet == 0) {
usleep(0);
commaDet = (bus_r(TRANSCEIVERSTATUS) & RXCOMMADET_MSK);
}
LOG(logINFORED, ("Kwords or end of acquisition detected\n"));
return OK;
}
@@ -1385,8 +1537,12 @@ void *start_timer(void *arg) {
packetSize, packetsPerFrame));
// Generate Data
char imageData[imageSize];
char *imageData = (char *)malloc(imageSize);
memset(imageData, 0, imageSize);
if (imageData == NULL) {
LOG(logERROR, ("Can not allocate image.\n"));
return NULL;
}
for (int i = 0; i < imageSize; i += sizeof(uint16_t)) {
*((uint16_t *)(imageData + i)) = i;
}
@@ -1409,6 +1565,7 @@ void *start_timer(void *arg) {
usleep(expUs);
int srcOffset = 0;
int dataSent = 0;
// loop packet
for (int i = 0; i != packetsPerFrame; ++i) {
@@ -1425,10 +1582,12 @@ void *start_timer(void *arg) {
header->column = detPos[X];
// fill data
int remaining = imageSize - dataSent;
int dataSize = remaining < maxDataSize ? remaining : maxDataSize;
memcpy(packetData + sizeof(sls_detector_header),
imageData + srcOffset,
(imageSize < maxDataSize ? imageSize : maxDataSize));
srcOffset += maxDataSize;
imageData + srcOffset, dataSize);
srcOffset += dataSize;
dataSent += dataSize;
sendUDPPacket(0, 0, packetData, packetSize);
}
@@ -1474,56 +1633,6 @@ int stopStateMachine() {
return OK;
}
int startReadOut() {
LOG(logINFOBLUE, ("Starting Readout\n"));
#ifdef VIRTUAL
// cannot set #frames and exptiem temporarily to 1 and 0,
// because have to set it back after readout (but this is non blocking)
return startStateMachine();
#endif
// check if data in fifo
int ret = FAIL;
if (transceiverEnable) {
if ((bus_r(X_FIFO_EMPTY_STATUS_REG) & X_FIFO_EMPTY_STATUS_MSK) !=
X_FIFO_EMPTY_STATUS_MSK) {
LOG(logINFO, ("Data in transceiver fifo\n"));
ret = OK;
}
}
if (analogEnable) {
if (bus_r(A_FIFO_EMPTY_STATUS_REG) != BIT32_MSK) {
LOG(logINFO, ("Data in analog fifo\n"));
ret = OK;
}
}
if (digitalEnable) {
if ((bus_r(D_FIFO_EMPTY_STATUS_REG) & D_FIFO_EMPTY_STATUS_MSK) !=
D_FIFO_EMPTY_STATUS_MSK) {
LOG(logINFO, ("Data in digital fifo\n"));
ret = OK;
}
}
// if no module, dont check fifo empty
if (checkModuleFlag && ret == FAIL) {
LOG(logERROR, ("No data in fifo\n"));
return FAIL;
}
LOG(logINFOBLUE, ("Streaming data from fifo\n"));
bus_w(FIFO_TO_GB_CONTROL_REG,
bus_r(FIFO_TO_GB_CONTROL_REG) | START_STREAMING_P_MSK);
// wait until streaming is done (not same as fifo empty)
int streamingBusy = (bus_r(STATUSREG1) & TRANSMISSIONBUSY_MSK);
while (streamingBusy != 0) {
usleep(0);
streamingBusy = (bus_r(STATUSREG1) & TRANSMISSIONBUSY_MSK);
}
LOG(logINFORED, ("Streaming done\n"));
return OK;
}
int softwareTrigger() {
#ifndef VIRTUAL
// ready for trigger
@@ -1559,36 +1668,33 @@ enum runStatus getRunStatus() {
LOG(logINFOBLUE, ("Status: IDLE\n"));
return IDLE;
#endif
uint32_t retval = bus_r(FLOW_STATUS_REG);
LOG(logINFO, ("Flow Status Register: %08x\n", retval));
uint32_t retval = bus_r(STATUS_REG);
LOG(logINFO, ("Status Register: %08x\n", retval));
if (retval & RSM_TRG_WAIT_MSK) {
LOG(logINFOBLUE, ("Status: WAITING\n"));
return WAITING;
} else if (retval & RSM_BUSY_MSK) {
LOG(logINFOBLUE, ("Status: RUNNING (exposing)\n"));
return RUNNING;
} else if (bus_r(MATTERHORNSPICTRL) & READOUTFROMASIC_MSK) {
LOG(logINFOBLUE, ("Status: RUNNING (data from chip to fifo)\n"));
return RUNNING;
} else if (bus_r(STATUSREG1) & TRANSMISSIONBUSY_MSK) {
LOG(logINFOBLUE, ("Status: TRANSMITTING\n"));
return TRANSMITTING;
if (retval == 0x0) {
return IDLE;
}
LOG(logINFOBLUE, ("Status: IDLE\n"));
return IDLE;
// TODO: STOPPED, ERROR?
if (retval & RX_NOT_GOOD_MSK) {
LOG(logINFOBLUE, ("Status: ERROR\n"));
return ERROR;
}
if (retval & WAIT_FOR_TRIGGER_MSK) {
LOG(logINFOBLUE, ("Status: WAITING\n"));
return WAITING;
}
LOG(logINFOBLUE, ("Status: RUNNING\n"));
return RUNNING;
// TODO: STOPPED?
}
u_int32_t runBusy() {
#ifdef VIRTUAL
return ((sharedMemory_getStatus() == RUNNING) ? 1 : 0);
#endif
uint32_t exposingBusy = bus_r(FLOW_STATUS_REG) & RSM_BUSY_MSK;
uint32_t fillingFifoBusy = bus_r(MATTERHORNSPICTRL) & READOUTFROMASIC_MSK;
uint32_t streamingBusy = bus_r(STATUSREG1) & TRANSMISSIONBUSY_MSK;
return (exposingBusy || fillingFifoBusy || streamingBusy);
return (bus_r(STATUS_REG));
}
void waitForAcquisitionEnd() {

5
slsDetectorServers/xilinx_ctbDetectorServer/slsDetectorServer_defs.h
View File

@@ -4,7 +4,7 @@
#include "RegisterDefs.h"
#include "sls/sls_detector_defs.h"
#define REQRD_FRMWRE_VRSN (0x230710)
#define REQRD_FRMWRE_VRSN (0x250203)
#define KERNEL_DATE_VRSN "Wed Nov 29 17:32:14 CET 2023"
#define LINKED_SERVER_NAME "xilinx_ctbDetectorServer"
@@ -40,6 +40,9 @@
#define SLOWADC_DRIVER_FILE_NAME CURRENT_BOARD_LINKS_FOLDER "/ai%d"
#define TEMP_DRIVER_FILE_NAME DEVICE_TREE_DST "0/in_temp7_input"
#define CONFIG_CHIP_FILE "chip_config_xilinx.txt"
#define RESET_CHIP_FILE "reset_chip_xilinx.txt"
/** Default Parameters */
#define DEFAULT_NUM_FRAMES (1)
#define DEFAULT_NUM_CYCLES (1)