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ctb server: introducing 1 us delay between rd strobe and fifo read due to different clocks
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@ -10,6 +10,7 @@
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#include "MAX1932.h" // hv
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#include "INA226.h" // i2c
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#include "ALTERA_PLL.h" // pll
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#include <time.h>
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#ifndef VIRTUAL
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#include "programfpga.h"
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#else
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@ -2351,8 +2352,14 @@ void readSample(int ns) {
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// read strobe to all analog fifos
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bus_w(addr, bus_r(addr) | DUMMY_ANLG_FIFO_RD_STRBE_MSK);
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bus_w(addr, bus_r(addr) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK));
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// wait as it is connected directly to fifo running on a different clock
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//usleep(WAIT_TIME_FIFO_RD_STROBE);
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// wait for 1 us to latch different clocks of read and read strobe
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{
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int i = 0;
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for (i = 0; i < WAIT_TIME_1US_FOR_LOOP_CNT; ++i)
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;
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}
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if (!(ns%1000)) {
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FILE_LOG(logDEBUG1, ("Reading sample ns:%d of %d AEmtpy:0x%x AFull:0x%x Status:0x%x\n",
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ns, nSamples, bus_r(FIFO_EMPTY_REG), bus_r(FIFO_FULL_REG), bus_r(STATUS_REG)));
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@ -2391,6 +2398,14 @@ void readSample(int ns) {
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// read strobe to digital fifo
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bus_w(addr, bus_r(addr) | DUMMY_DGTL_FIFO_RD_STRBE_MSK);
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bus_w(addr, bus_r(addr) & (~DUMMY_DGTL_FIFO_RD_STRBE_MSK));
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// wait for 1 us to latch different clocks of read and read strobe
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{
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int i = 0;
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for (i = 0; i < WAIT_TIME_1US_FOR_LOOP_CNT; ++i)
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;
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}
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// wait as it is connected directly to fifo running on a different clock
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if (!(ns%1000)) {
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FILE_LOG(logDEBUG1, ("Reading sample ns:%d of %d DEmtpy:%d DFull:%d Status:0x%x\n",
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@ -85,7 +85,7 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
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#define WAIT_TIME_US_STP_ACQ (100)
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#define WAIT_TIME_CONFIGURE_MAC (500 * 1000)
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#define WAIT_TIME_PATTERN_READ (10)
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#define WAIT_TIME_FIFO_RD_STROBE (10)
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#define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
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/* MSB & LSB DEFINES */
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#define MSB_OF_64_BIT_REG_OFST (32)
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@ -7,4 +7,4 @@
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#define APIRECEIVER 0x190405
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#define APIGUI 0x190405
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#define APIEIGER 0x190418
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#define APICTB 0x190418
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#define APICTB 0x190423
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