ctb server: introducing 1 us delay between rd strobe and fifo read due to different clocks

This commit is contained in:
maliakal_d 2019-04-23 14:35:07 +02:00
parent 21cab38921
commit 4e3baf41cb
5 changed files with 21 additions and 6 deletions

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@ -1,7 +1,7 @@
CROSS = bfin-uclinux- CROSS = bfin-uclinux-
CC = $(CROSS)gcc CC = $(CROSS)gcc
CFLAGS += -Wall -DCHIPTESTBOARDD -DSTOP_SERVER -DDEBUG1 #-DJCTB -DVERBOSEI #-DVERBOSE CFLAGS += -Wall -DCHIPTESTBOARDD -DSTOP_SERVER -DDEBUG1 #-DJCTB -DVERBOSEI #-DVERBOSE
LDLIBS += -lm -lstdc++ LDLIBS += -lm -lstdc++
PROGS = ctbDetectorServer PROGS = ctbDetectorServer
DESTDIR ?= bin DESTDIR ?= bin

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@ -10,6 +10,7 @@
#include "MAX1932.h" // hv #include "MAX1932.h" // hv
#include "INA226.h" // i2c #include "INA226.h" // i2c
#include "ALTERA_PLL.h" // pll #include "ALTERA_PLL.h" // pll
#include <time.h>
#ifndef VIRTUAL #ifndef VIRTUAL
#include "programfpga.h" #include "programfpga.h"
#else #else
@ -2351,8 +2352,14 @@ void readSample(int ns) {
// read strobe to all analog fifos // read strobe to all analog fifos
bus_w(addr, bus_r(addr) | DUMMY_ANLG_FIFO_RD_STRBE_MSK); bus_w(addr, bus_r(addr) | DUMMY_ANLG_FIFO_RD_STRBE_MSK);
bus_w(addr, bus_r(addr) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK)); bus_w(addr, bus_r(addr) & (~DUMMY_ANLG_FIFO_RD_STRBE_MSK));
// wait as it is connected directly to fifo running on a different clock
//usleep(WAIT_TIME_FIFO_RD_STROBE); // wait for 1 us to latch different clocks of read and read strobe
{
int i = 0;
for (i = 0; i < WAIT_TIME_1US_FOR_LOOP_CNT; ++i)
;
}
if (!(ns%1000)) { if (!(ns%1000)) {
FILE_LOG(logDEBUG1, ("Reading sample ns:%d of %d AEmtpy:0x%x AFull:0x%x Status:0x%x\n", FILE_LOG(logDEBUG1, ("Reading sample ns:%d of %d AEmtpy:0x%x AFull:0x%x Status:0x%x\n",
ns, nSamples, bus_r(FIFO_EMPTY_REG), bus_r(FIFO_FULL_REG), bus_r(STATUS_REG))); ns, nSamples, bus_r(FIFO_EMPTY_REG), bus_r(FIFO_FULL_REG), bus_r(STATUS_REG)));
@ -2391,6 +2398,14 @@ void readSample(int ns) {
// read strobe to digital fifo // read strobe to digital fifo
bus_w(addr, bus_r(addr) | DUMMY_DGTL_FIFO_RD_STRBE_MSK); bus_w(addr, bus_r(addr) | DUMMY_DGTL_FIFO_RD_STRBE_MSK);
bus_w(addr, bus_r(addr) & (~DUMMY_DGTL_FIFO_RD_STRBE_MSK)); bus_w(addr, bus_r(addr) & (~DUMMY_DGTL_FIFO_RD_STRBE_MSK));
// wait for 1 us to latch different clocks of read and read strobe
{
int i = 0;
for (i = 0; i < WAIT_TIME_1US_FOR_LOOP_CNT; ++i)
;
}
// wait as it is connected directly to fifo running on a different clock // wait as it is connected directly to fifo running on a different clock
if (!(ns%1000)) { if (!(ns%1000)) {
FILE_LOG(logDEBUG1, ("Reading sample ns:%d of %d DEmtpy:%d DFull:%d Status:0x%x\n", FILE_LOG(logDEBUG1, ("Reading sample ns:%d of %d DEmtpy:%d DFull:%d Status:0x%x\n",
@ -2399,7 +2414,7 @@ void readSample(int ns) {
((bus_r(FIFO_DIN_STATUS_REG) & FIFO_DIN_STATUS_FIFO_FULL_MSK) >> FIFO_DIN_STATUS_FIFO_FULL_OFST), ((bus_r(FIFO_DIN_STATUS_REG) & FIFO_DIN_STATUS_FIFO_FULL_MSK) >> FIFO_DIN_STATUS_FIFO_FULL_OFST),
bus_r(STATUS_REG))); bus_r(STATUS_REG)));
} }
// read fifo and write it to current position of data pointer // read fifo and write it to current position of data pointer
*((uint64_t*)now_ptr) = get64BitReg(FIFO_DIN_LSB_REG, FIFO_DIN_MSB_REG); *((uint64_t*)now_ptr) = get64BitReg(FIFO_DIN_LSB_REG, FIFO_DIN_MSB_REG);
now_ptr += 8; now_ptr += 8;

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@ -85,7 +85,7 @@ enum DACINDEX {D0, D1, D2, D3, D4, D5, D6, D7, D8, D9,
#define WAIT_TIME_US_STP_ACQ (100) #define WAIT_TIME_US_STP_ACQ (100)
#define WAIT_TIME_CONFIGURE_MAC (500 * 1000) #define WAIT_TIME_CONFIGURE_MAC (500 * 1000)
#define WAIT_TIME_PATTERN_READ (10) #define WAIT_TIME_PATTERN_READ (10)
#define WAIT_TIME_FIFO_RD_STROBE (10) #define WAIT_TIME_1US_FOR_LOOP_CNT (50) // around 30 is 1 us in blackfin
/* MSB & LSB DEFINES */ /* MSB & LSB DEFINES */
#define MSB_OF_64_BIT_REG_OFST (32) #define MSB_OF_64_BIT_REG_OFST (32)

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@ -7,4 +7,4 @@
#define APIRECEIVER 0x190405 #define APIRECEIVER 0x190405
#define APIGUI 0x190405 #define APIGUI 0x190405
#define APIEIGER 0x190418 #define APIEIGER 0x190418
#define APICTB 0x190418 #define APICTB 0x190423