* gain plot: dont allow zoom, only zoom on main plot

* fixed gain plot zooming

* fixing panning for gainplots
This commit is contained in:
Dhanya Thattil
2022-10-18 15:27:44 +02:00
committed by GitHub
parent d2c4827b31
commit 4a7cd051c1
11 changed files with 157 additions and 13 deletions

View File

@ -3217,8 +3217,22 @@ void *start_timer(void *arg) {
// Generate data
char imageData[imagesize];
memset(imageData, 0, imagesize);
for (int i = 0; i < imagesize; i += sizeof(uint16_t)) {
*((uint16_t *)(imageData + i)) = i;
const int nchannels = NCHIP * NCHAN;
int gainVal = 0;
int channelVal = 0;
for (int i = 0; i < nchannels; ++i) {
if ((i % nchannels) < 400) {
gainVal = 1;
} else if ((i % nchannels) < 800) {
gainVal = 2;
} else {
gainVal = 3;
}
channelVal = (i & ~GAIN_VAL_MSK) | (gainVal << GAIN_VAL_OFST);
*((uint16_t *)(imageData + i * sizeof(uint16_t))) =
(uint16_t)channelVal;
// LOG(logINFORED, ("[%d]:0x%08x\n", i, channelVal));
}
char vetoData[vetodatasize];
memset(vetoData, 0, sizeof(vetodatasize));

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@ -94,6 +94,9 @@
#define DEFAULT_ASIC_DOUT_RDY_SRC (0x5)
#define DEFAULT_ASIC_DOUT_RDY_DLY (0x3)
#define GAIN_VAL_OFST (12)
#define GAIN_VAL_MSK (0x3 << GAIN_VAL_OFST)
#define VETO_DATA_SIZE (160)
typedef struct {
uint64_t frameNumber;

View File

@ -2580,13 +2580,21 @@ void *start_timer(void *arg) {
{
const int npixels = (NCHAN * NCHIP);
const int pixelsPerPacket = dataSize / NUM_BYTES_PER_PIXEL;
int dataVal = 0;
int gainVal = 0;
int pixelVal = 0;
for (int i = 0; i < npixels; ++i) {
// avoiding gain also being divided when gappixels enabled in call
// back
if (i > 0 && i % pixelsPerPacket == 0) {
++pixelVal;
if (i % pixelsPerPacket == 0) {
++dataVal;
}
if ((i % 1024) < 300) {
gainVal = 1;
} else if ((i % 1024) < 600) {
gainVal = 2;
} else {
gainVal = 3;
}
pixelVal = (dataVal & ~GAIN_VAL_MSK) | (gainVal << GAIN_VAL_OFST);
// to debug multi module geometry (row, column) in virtual servers (all pixels
// in a module set to particular value)
#ifdef TEST_MOD_GEOMETRY

View File

@ -138,6 +138,9 @@ enum CLKINDEX { RUN_CLK, ADC_CLK, DBIT_CLK, NUM_CLOCKS };
#define MAX_PHASE_SHIFTS (240)
#define BIT16_MASK (0xFFFF)
#define GAIN_VAL_OFST (14)
#define GAIN_VAL_MSK (0x3 << GAIN_VAL_OFST)
// pipeline
#define ADC_PORT_INVERT_VAL (0x5A5A5A5A)
#define ADC_PORT_INVERT_BOARD2_VAL (0x453b2a9c)