mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-18 07:47:12 +02:00
some changes in the moench executables
This commit is contained in:
@ -8,6 +8,16 @@
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#include "mcb_funcs.h"
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#include "slow_adc.h"
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#include "registers_m.h"
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#define ADC_SPI_REG ADC_WRITE_REG
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#define ADC_SERIAL_CLK_OUT_OFST (0)
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#define ADC_SERIAL_CLK_OUT_MSK (0x00000001 << ADC_SERIAL_CLK_OUT_OFST)
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#define ADC_SERIAL_DATA_OUT_OFST (1)
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#define ADC_SERIAL_DATA_OUT_MSK (0x00000001 << ADC_SERIAL_DATA_OUT_OFST)
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#define ADC_SERIAL_CS_OUT_OFST (2)
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#define ADC_SERIAL_CS_OUT_MSK (0x0000000F << ADC_SERIAL_CS_OUT_OFST)
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#include "AD9257.h"
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//#define VERBOSE
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//#define VERYVERBOSE
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@ -1718,60 +1728,60 @@ int initConfGain(int isettings,int val,int imod){
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int setADC(int adc){
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/* int reg,nchips,mask,nchans; */
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/* int setADC(int adc){ */
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/* /\* int reg,nchips,mask,nchans; *\/ */
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/* if(adc==-1) ROI_flag=0; */
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/* else ROI_flag=1; */
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/* /\* if(adc==-1) ROI_flag=0; *\/ */
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/* /\* else ROI_flag=1; *\/ */
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/* // setDAQRegister();//token timing */
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/* cleanFifo();//adc sync */
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/* /\* // setDAQRegister();//token timing *\/ */
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/* /\* cleanFifo();//adc sync *\/ */
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/* //with gotthard module */
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/* if(withGotthard){ */
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/* //set packet size */
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/* ipPacketSize= DEFAULT_IP_PACKETSIZE; */
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/* udpPacketSize=DEFAULT_UDP_PACKETSIZE; */
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/* //set channel mask */
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/* nchips = GOTTHARDNCHIP; */
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/* nchans = GOTTHARDNCHAN; */
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/* mask = ACTIVE_ADC_MASK; */
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/* } */
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/* /\* //with gotthard module *\/ */
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/* /\* if(withGotthard){ *\/ */
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/* /\* //set packet size *\/ */
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/* /\* ipPacketSize= DEFAULT_IP_PACKETSIZE; *\/ */
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/* /\* udpPacketSize=DEFAULT_UDP_PACKETSIZE; *\/ */
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/* /\* //set channel mask *\/ */
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/* /\* nchips = GOTTHARDNCHIP; *\/ */
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/* /\* nchans = GOTTHARDNCHAN; *\/ */
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/* /\* mask = ACTIVE_ADC_MASK; *\/ */
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/* /\* } *\/ */
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/* //with moench module all adc */
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/* else{/\* if(adc==-1){*\/ */
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/* //set packet size */
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/* ipPacketSize= DEFAULT_IP_PACKETSIZE; */
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/* udpPacketSize=DEFAULT_UDP_PACKETSIZE; */
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/* //set channel mask */
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/* nchips = N_CHIP; */
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/* nchans = N_CHANS; */
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/* mask = ACTIVE_ADC_MASK; */
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/* }/\* */
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/* //with moench module 1 adc -- NOT IMPLEMENTED */
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/* else{ */
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/* ipPacketSize= ADC1_IP_PACKETSIZE; */
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/* udpPacketSize=ADC1_UDP_PACKETSIZE; */
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/* //set channel mask */
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/* nchips = NCHIPS_PER_ADC; */
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/* nchans = GOTTHARDNCHAN; */
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/* mask = 1<<adc; */
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/* }*\/ */
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/* /\* //with moench module all adc *\/ */
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/* /\* else{/\\* if(adc==-1){*\\/ *\/ */
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/* /\* //set packet size *\/ */
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/* /\* ipPacketSize= DEFAULT_IP_PACKETSIZE; *\/ */
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/* /\* udpPacketSize=DEFAULT_UDP_PACKETSIZE; *\/ */
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/* /\* //set channel mask *\/ */
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/* /\* nchips = N_CHIP; *\/ */
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/* /\* nchans = N_CHANS; *\/ */
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/* /\* mask = ACTIVE_ADC_MASK; *\/ */
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/* /\* }/\\* *\/ */
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/* /\* //with moench module 1 adc -- NOT IMPLEMENTED *\/ */
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/* /\* else{ *\/ */
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/* /\* ipPacketSize= ADC1_IP_PACKETSIZE; *\/ */
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/* /\* udpPacketSize=ADC1_UDP_PACKETSIZE; *\/ */
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/* /\* //set channel mask *\/ */
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/* /\* nchips = NCHIPS_PER_ADC; *\/ */
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/* /\* nchans = GOTTHARDNCHAN; *\/ */
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/* /\* mask = 1<<adc; *\/ */
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/* /\* }*\\/ *\/ */
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/* //set channel mask */
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/* reg = (nchans*nchips)<<CHANNEL_OFFSET; */
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/* reg&=CHANNEL_MASK; */
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/* reg|=(ACTIVE_ADC_MASK & mask); */
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/* bus_w(CHIP_OF_INTRST_REG,reg); */
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/* /\* //set channel mask *\/ */
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/* /\* reg = (nchans*nchips)<<CHANNEL_OFFSET; *\/ */
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/* /\* reg&=CHANNEL_MASK; *\/ */
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/* /\* reg|=(ACTIVE_ADC_MASK & mask); *\/ */
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/* /\* bus_w(CHIP_OF_INTRST_REG,reg); *\/ */
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/* //#ifdef DDEBUG */
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/* printf("Chip of Interest Reg:%x\n",bus_r(CHIP_OF_INTRST_REG)); */
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/* //#endif */
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/* /\* //#ifdef DDEBUG *\/ */
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/* /\* printf("Chip of Interest Reg:%x\n",bus_r(CHIP_OF_INTRST_REG)); *\/ */
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/* /\* //#endif *\/ */
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/* adcConfigured = adc; */
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/* /\* adcConfigured = adc; *\/ */
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return adcConfigured;
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}
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/* return adcConfigured; */
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/* } */
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@ -2450,103 +2460,101 @@ int allocateRAM() {
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int writeADC(int addr, int val) {
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u_int32_t valw,codata,csmask;
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int i,cdx,ddx;
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cdx=0; ddx=1;
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csmask=0xfc; // 1111100
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codata=val + (addr<< 8);
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printf("***** ADC SPI WRITE TO REGISTER %04X value %04X\n",addr,val);
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// start point
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valw=0xff;
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bus_w16(ADC_WRITE_REG,(valw));
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//chip sel bar down
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valw=((0xffffffff&(~csmask)));
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bus_w16(ADC_WRITE_REG,valw);
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for (i=0;i<24;i++) {
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//cldwn
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valw=valw&(~(0x1<<cdx));
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bus_w16(ADC_WRITE_REG,valw);
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// usleep(0);
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//write data (i)
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valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx);
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bus_w16(ADC_WRITE_REG,valw);
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// usleep(0);
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//clkup
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valw=valw+(0x1<<cdx);
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bus_w16(ADC_WRITE_REG,valw);
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// usleep(0);
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}
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// stop point =start point
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valw=valw&(~(0x1<<cdx));
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// usleep(0);
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valw=0xff;
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bus_w16(ADC_WRITE_REG,(valw));
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//usleep in between
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// usleep(50000);
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setAdc(addr,val);
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return OK;
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/* u_int32_t valw,codata,csmask; */
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/* int i,cdx,ddx; */
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/* cdx=0; ddx=1; */
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/* csmask=0xfc; // 1111100 */
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/* codata=val + (addr<< 8); */
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/* printf("***** ADC SPI WRITE TO REGISTER %04X value %04X\n",addr,val); */
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/* // start point */
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/* valw=0xff; */
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/* bus_w16(ADC_WRITE_REG,(valw)); */
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/* //chip sel bar down */
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/* valw=((0xffffffff&(~csmask))); */
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/* bus_w16(ADC_WRITE_REG,valw); */
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/* for (i=0;i<24;i++) { */
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/* //cldwn */
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/* valw=valw&(~(0x1<<cdx)); */
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/* bus_w16(ADC_WRITE_REG,valw); */
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/* // usleep(0); */
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/* //write data (i) */
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/* valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx); */
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/* bus_w16(ADC_WRITE_REG,valw); */
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/* // usleep(0); */
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/* //clkup */
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/* valw=valw+(0x1<<cdx); */
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/* bus_w16(ADC_WRITE_REG,valw); */
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/* // usleep(0); */
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/* } */
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/* // stop point =start point */
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/* valw=valw&(~(0x1<<cdx)); */
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/* // usleep(0); */
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/* valw=0xff; */
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/* bus_w16(ADC_WRITE_REG,(valw)); */
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/* //usleep in between */
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/* // usleep(50000); */
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/* return OK; */
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}
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int prepareADC(){
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printf("Preparing ADC\n");
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u_int32_t codata,csmask;
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int cdx,ddx;
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cdx=0; ddx=1;
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csmask=0x7c; // 1111100
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/* int prepareADC(){ */
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/* printf("Preparing ADC\n"); */
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/* u_int32_t codata,csmask; */
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/* int cdx,ddx; */
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/* cdx=0; ddx=1; */
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/* csmask=0x7c; // 1111100 */
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/* #define ADCREG1 0x08 */
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/* #define ADCREG2 0x14//20 */
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/* #define ADCREG3 0x4 */
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/* #define ADCREG4 0x5 */
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codata=0;
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writeADC(0x08,0x3);//reset
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writeADC(0x08,0x0);//run!
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writeADC(0x04,0xf);//all chans
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writeADC(0x04,0x3f);//all chans
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/* /\* #define ADCREG1 0x08 *\/ */
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/* /\* #define ADCREG2 0x14//20 *\/ */
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/* /\* #define ADCREG3 0x4 *\/ */
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/* /\* #define ADCREG4 0x5 *\/ */
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/* codata=0; */
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/* writeADC(0x08,0x3);//reset */
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/* writeADC(0x08,0x0);//run! */
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/* writeADC(0x04,0xf);//all chans */
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/* writeADC(0x04,0x3f);//all chans */
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// writeADC(0x16,0x4);//output clock phase
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// writeADC(0x18,0x4);// vref 1V
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// writeADC(0x14,0x0);
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writeADC(0x14,0x40);//lvds reduced range -- offset binary
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/* // writeADC(0x16,0x4);//output clock phase */
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/* // writeADC(0x18,0x4);// vref 1V */
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/* // writeADC(0x14,0x0); */
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/* writeADC(0x14,0x40);//lvds reduced range -- offset binary */
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writeADC(0xD,0x0);//no test mode
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/* writeADC(0xD,0x0);//no test mode */
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#ifdef TESTADC
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/* #ifdef TESTADC */
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////////////TEST ADC!!!!!!!!!!
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/* ////////////TEST ADC!!!!!!!!!! */
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printf("***************************************** *******\n");
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printf("******* PUTTING ADC IN TEST MODE!!!!!!!!! *******\n");
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printf("***************************************** *******\n");
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/* printf("***************************************** *******\n"); */
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/* printf("******* PUTTING ADC IN TEST MODE!!!!!!!!! *******\n"); */
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/* printf("***************************************** *******\n"); */
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// writeADC(0xD,0x4);//ALTERNATING CHECKERBOARD
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/* // writeADC(0xD,0x4);//ALTERNATING CHECKERBOARD */
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// writeADC(0xD,0x7);//ONE/ZERO WORD TOGGLE
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/* // writeADC(0xD,0x7);//ONE/ZERO WORD TOGGLE */
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/* writeADC(0x19,0xf0);//user input */
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/* writeADC(0x1A,0xf0);//user input */
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/* writeADC(0x1B,0x0f);//user input */
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/* writeADC(0x1C,0x0f);//user input */
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/* writeADC(0xD,0x48);//user input, alternate */
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/* /\* writeADC(0x19,0xf0);//user input *\/ */
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/* /\* writeADC(0x1A,0xf0);//user input *\/ */
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/* /\* writeADC(0x1B,0x0f);//user input *\/ */
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/* /\* writeADC(0x1C,0x0f);//user input *\/ */
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/* /\* writeADC(0xD,0x48);//user input, alternate *\/ */
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/* //writeADC(0xD,0xA);//1xsync */
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// writeADC(0xD,0xB);//1xbit high
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writeADC(0xD,0xC);//1xmixed frequqncy
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/* /\* //writeADC(0xD,0xA);//1xsync *\/ */
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/* // writeADC(0xD,0xB);//1xbit high */
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/* writeADC(0xD,0xC);//1xmixed frequqncy */
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#endif
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/* #endif */
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@ -2554,15 +2562,15 @@ int prepareADC(){
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bus_w(ADC_LATCH_DISABLE_REG,0x0); // enable all ADCs
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// bus_w(DAQ_REG,0x12); //adc pipeline=18
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/* bus_w(ADC_LATCH_DISABLE_REG,0x0); // enable all ADCs */
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/* // bus_w(DAQ_REG,0x12); //adc pipeline=18 */
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//bus_w(DAQ_REG,0xbbbbbbbb);
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// bus_w(ADC_INVERSION_REG,0x1f6170c6);
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/* //bus_w(DAQ_REG,0xbbbbbbbb); */
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/* // bus_w(ADC_INVERSION_REG,0x1f6170c6); */
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return OK;
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/* return OK; */
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}
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/* } */
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int clearRAM() {
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