mirror of
https://github.com/slsdetectorgroup/slsDetectorPackage.git
synced 2025-06-23 01:58:00 +02:00
some changes in the moench executables
This commit is contained in:
141
slsDetectorSoftware/jctbDetectorServer/AD9257.h
Executable file
141
slsDetectorSoftware/jctbDetectorServer/AD9257.h
Executable file
@ -0,0 +1,141 @@
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#ifndef AD9257_H
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#define AD9257_H
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#include "ansi.h"
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#include "commonServerFunctions.h"
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#include <stdio.h>
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/* AD9257 ADC DEFINES */
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#define AD9257_ADC_NUMBITS (24)
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#define AD9257_DEV_IND_2_REG (0x04)
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#define AD9257_CHAN_H_OFST (0)
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#define AD9257_CHAN_H_MSK (0x00000001 << AD9257_CHAN_H_OFST)
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#define AD9257_CHAN_G_OFST (1)
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#define AD9257_CHAN_G_MSK (0x00000001 << AD9257_CHAN_G_OFST)
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#define AD9257_CHAN_F_OFST (2)
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#define AD9257_CHAN_F_MSK (0x00000001 << AD9257_CHAN_F_OFST)
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#define AD9257_CHAN_E_OFST (3)
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#define AD9257_CHAN_E_MSK (0x00000001 << AD9257_CHAN_E_OFST)
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#define AD9257_DEV_IND_1_REG (0x05)
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#define AD9257_CHAN_D_OFST (0)
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#define AD9257_CHAN_D_MSK (0x00000001 << AD9257_CHAN_D_OFST)
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#define AD9257_CHAN_C_OFST (1)
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#define AD9257_CHAN_C_MSK (0x00000001 << AD9257_CHAN_C_OFST)
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#define AD9257_CHAN_B_OFST (2)
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#define AD9257_CHAN_B_MSK (0x00000001 << AD9257_CHAN_B_OFST)
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#define AD9257_CHAN_A_OFST (3)
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#define AD9257_CHAN_A_MSK (0x00000001 << AD9257_CHAN_A_OFST)
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#define AD9257_CLK_CH_DCO_OFST (4)
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#define AD9257_CLK_CH_DCO_MSK (0x00000001 << AD9257_CLK_CH_DCO_OFST)
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#define AD9257_CLK_CH_IFCO_OFST (5)
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#define AD9257_CLK_CH_IFCO_MSK (0x00000001 << AD9257_CLK_CH_IFCO_OFST)
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#define AD9257_POWER_MODE_REG (0x08)
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#define AD9257_POWER_INTERNAL_OFST (0)
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#define AD9257_POWER_INTERNAL_MSK (0x00000003 << AD9257_POWER_INTERNAL_OFST)
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#define AD9257_INT_RESET_VAL (0x3)
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#define AD9257_INT_CHIP_RUN_VAL (0x0)
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#define AD9257_POWER_EXTERNAL_OFST (5)
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#define AD9257_POWER_EXTERNAL_MSK (0x00000001 << AD9257_POWER_EXTERNAL_OFST)
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#define AD9257_EXT_FULL_POWER_VAL (0x0)
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#define AD9257_EXT_STANDBY_VAL (0x1)
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#define AD9257_OUT_MODE_REG (0x14)
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#define AD9257_OUT_FORMAT_OFST (0)
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#define AD9257_OUT_FORMAT_MSK (0x00000001 << AD9257_OUT_FORMAT_OFST)
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#define AD9257_OUT_BINARY_OFST_VAL (0)
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#define AD9257_OUT_TWOS_COMPL_VAL (1)
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#define AD9257_OUT_LVDS_OPT_OFST (6)
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#define AD9257_OUT_LVDS_OPT_MSK (0x00000001 << AD9257_OUT_LVDS_OPT_OFST)
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#define AD9257_OUT_LVDS_ANSI_VAL (0)
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#define AD9257_OUT_LVDS_IEEE_VAL (1)
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#define AD9257_OUT_PHASE_REG (0x16)
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#define AD9257_OUT_CLK_OFST (0)
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#define AD9257_OUT_CLK_MSK (0x0000000F << AD9257_OUT_CLK_OFST)
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#define AD9257_OUT_CLK_60_VAL (0x1)
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#define AD9257_IN_CLK_OFST (4)
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#define AD9257_IN_CLK_MSK (0x00000007 << AD9257_IN_CLK_OFST)
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#define AD9257_IN_CLK_0_VAL (0x0)
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#define AD9257_VREF_REG (0x18)
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#define AD9257_VREF_OFST (0)
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#define AD9257_VREF_MSK (0x00000003 << AD9257_VREF_OFST)
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#define AD9257_VREF_1_33_VAL (0x2)
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#define AD9257_TEST_MODE_REG (0x0D)
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#define AD9257_OUT_TEST_OFST (0)
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#define AD9257_OUT_TEST_MSK (0x0000000F << AD9257_OUT_TEST_OFST)
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#define AD9257_NONE_VAL (0x0)
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#define AD9257_MIXED_BIT_FREQ_VAL (0xC)
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#define AD9257_TEST_RESET_SHORT_GEN (4)
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#define AD9257_TEST_RESET_LONG_GEN (5)
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#define AD9257_USER_IN_MODE_OFST (6)
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#define AD9257_USER_IN_MODE_MSK (0x00000003 << AD9257_USER_IN_MODE_OFST)
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void setAdc(int addr, int val) {
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u_int32_t codata;
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codata = val + (addr << 8);
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printf(" Setting ADC SPI Register. Wrote 0x%04x at 0x%04x\n", val, addr);
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serializeToSPI(ADC_SPI_REG, codata, ADC_SERIAL_CS_OUT_MSK, AD9257_ADC_NUMBITS,
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ADC_SERIAL_CLK_OUT_MSK, ADC_SERIAL_DATA_OUT_MSK, ADC_SERIAL_DATA_OUT_OFST);
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}
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void prepareADC(){
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printf("\n\nPreparing ADC ... \n");
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//power mode reset
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printf("power mode reset:\n");
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setAdc(AD9257_POWER_MODE_REG,
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(AD9257_INT_RESET_VAL << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK);
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//power mode chip run
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printf("power mode chip run:\n");
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setAdc(AD9257_POWER_MODE_REG,
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(AD9257_INT_CHIP_RUN_VAL << AD9257_POWER_INTERNAL_OFST) & AD9257_POWER_INTERNAL_MSK);
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//output clock phase
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printf("output clock phase:\n");
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setAdc(AD9257_OUT_PHASE_REG,
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(AD9257_OUT_CLK_60_VAL << AD9257_OUT_CLK_OFST) & AD9257_OUT_CLK_MSK);
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// lvds-iee reduced , binary offset
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printf("lvds-iee reduced, binary offset:\n");
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setAdc(AD9257_OUT_MODE_REG,
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(AD9257_OUT_LVDS_IEEE_VAL << AD9257_OUT_LVDS_OPT_OFST) & AD9257_OUT_LVDS_OPT_MSK);
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// all devices on chip to receive next command
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printf("all devices on chip to receive next command:\n");
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setAdc(AD9257_DEV_IND_2_REG,
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AD9257_CHAN_H_MSK | AD9257_CHAN_G_MSK | AD9257_CHAN_F_MSK | AD9257_CHAN_E_MSK);
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setAdc(AD9257_DEV_IND_1_REG,
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AD9257_CHAN_D_MSK | AD9257_CHAN_C_MSK | AD9257_CHAN_B_MSK | AD9257_CHAN_A_MSK |
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AD9257_CLK_CH_DCO_MSK | AD9257_CLK_CH_IFCO_MSK);
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// vref 1.33
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printf("vref 1.33:\n");
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setAdc(AD9257_VREF_REG,
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(AD9257_VREF_1_33_VAL << AD9257_VREF_OFST) & AD9257_VREF_MSK);
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// no test mode
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printf("no test mode:\n");
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setAdc(AD9257_TEST_MODE_REG,
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(AD9257_NONE_VAL << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK);
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#ifdef TESTADC
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printf("***************************************** *******\n");
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printf("******* PUTTING ADC IN TEST MODE!!!!!!!!! *******\n");
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printf("***************************************** *******\n");
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// mixed bit frequency test mode
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printf("mixed bit frequency test mode:\n");
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setAdc(AD9257_TEST_MODE_REG,
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(AD9257_MIXED_BIT_FREQ_VAL << AD9257_OUT_TEST_OFST) & AD9257_OUT_TEST_MSK);
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#endif
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}
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#endif //AD9257_H
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@ -6,10 +6,10 @@
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CROSS = bfin-uclinux-
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CC = $(CROSS)gcc
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CFLAGS += -Wall -DMOENCHD -DMCB_FUNCS -DDACS_INT -DDEBUG -DV1 -DCTB #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL #-DDACS_INT_CSERVER
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CFLAGS += -Wall -DMOENCHD -DMCB_FUNCS -DDACS_INT -DDEBUG -DV1 -DCTB -DOLDVERSION #-DVERBOSE #-DVERYVERBOSE #-DVIRTUAL #-DDACS_INT_CSERVER
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PROGS= jctbDetectorServer
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PROGS= jctbDetectorServer
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INSTDIR= /tftpboot
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INSTMODE= 0777
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@ -31,10 +31,14 @@ boot: $(OBJS)
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versioning:
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@echo `tput setaf 6; ./updateGitVersion.sh; tput sgr0;`
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jctbDetectorServer: $(OBJS)
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jctbDetectorServerNew: $(OBJS)
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echo $(OBJS)
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$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@)
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jctbDetectorServer: $(OBJS)
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echo $(OBJS)
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$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@) -DOLDVERSION
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jungfrauADCTEst: $(OBJS)
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echo $(OBJS)
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$(CC) $(CFLAGS) -o $@ $^ $(LDLIBS_$@) $(LDFLAGS_$@) -DTESTADC
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@ -2,9 +2,13 @@
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#define BLACKFIN_H
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#define CSP0 0x20200000
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#define MEM_SIZE 0x100000
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#define MEM_SIZE 0x100000
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#ifndef OLDVERSION
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#define MEM_MAP_SHIFT 1
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#endif
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#ifdef OLDVERSION
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#define MEM_MAP_SHIFT 11
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#endif
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#include <sys/types.h>
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int mapCSP0(void);
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73
slsDetectorSoftware/jctbDetectorServer/commonServerFunctions.h
Executable file
73
slsDetectorSoftware/jctbDetectorServer/commonServerFunctions.h
Executable file
@ -0,0 +1,73 @@
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#ifndef COMMON_SERVER_FUNCTIONS_H
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#define COMMON_SERVER_FUNCTIONS_H
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#ifndef GOTTHARDD //gotthard already had bus_w etc defined in its firmware_funcs.c (not yet made with common files)
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#include "blackfin.h"
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#endif
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/* global variables */
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void SPIChipSelect (u_int32_t* valw, u_int32_t addr, u_int32_t csmask) {
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// start point
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(*valw) = 0xffffffff; // old board compatibility (not using specific bits)
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bus_w (addr, (*valw));
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// chip sel bar down
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(*valw) &= ~csmask; /* todo with test: done a bit different, not with previous value */
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bus_w (addr, (*valw));
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}
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void SPIChipDeselect (u_int32_t* valw, u_int32_t addr, u_int32_t csmask, u_int32_t clkmask) {
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// chip sel bar up
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(*valw) |= csmask; /* todo with test: not done for spi */
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bus_w (addr, (*valw));
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//clk down
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(*valw) &= ~clkmask;
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bus_w (addr, (*valw));
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// stop point = start point of course
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(*valw) = 0xffffffff; // old board compatibility (not using specific bits)
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bus_w (addr, (*valw));
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}
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void sendDataToSPI (u_int32_t* valw, u_int32_t addr, u_int32_t val, int numbitstosend, u_int32_t clkmask, u_int32_t digoutmask, int digofset) {
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int i = 0;
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for (i = 0; i < numbitstosend; ++i) {
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// clk down
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(*valw) &= ~clkmask;
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bus_w (addr, (*valw));
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// write data (i)
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(*valw) = (((*valw) & ~digoutmask) + // unset bit
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(((val >> (numbitstosend - 1 - i)) & 0x1) << digofset)); // each bit from val starting from msb
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bus_w (addr, (*valw));
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// clk up
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(*valw) |= clkmask ;
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bus_w (addr, (*valw));
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}
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}
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void serializeToSPI(u_int32_t addr, u_int32_t val, u_int32_t csmask, int numbitstosend, u_int32_t clkmask, u_int32_t digoutmask, int digofset) {
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#ifdef VERBOSE
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if (numbitstosend == 16)
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printf("Writing to SPI Register: 0x%04x\n",val);
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else
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printf("Writing to SPI Register: 0x%08x\n", val);
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#endif
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u_int32_t valw;
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SPIChipSelect (&valw, addr, csmask);
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sendDataToSPI(&valw, addr, val, numbitstosend, clkmask, digoutmask, digofset);
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SPIChipDeselect(&valw, addr, csmask, clkmask);
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}
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#endif //COMMON_SERVER_FUNCTIONS_H
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@ -8,6 +8,16 @@
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#include "mcb_funcs.h"
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#include "slow_adc.h"
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#include "registers_m.h"
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#define ADC_SPI_REG ADC_WRITE_REG
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#define ADC_SERIAL_CLK_OUT_OFST (0)
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#define ADC_SERIAL_CLK_OUT_MSK (0x00000001 << ADC_SERIAL_CLK_OUT_OFST)
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#define ADC_SERIAL_DATA_OUT_OFST (1)
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#define ADC_SERIAL_DATA_OUT_MSK (0x00000001 << ADC_SERIAL_DATA_OUT_OFST)
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#define ADC_SERIAL_CS_OUT_OFST (2)
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#define ADC_SERIAL_CS_OUT_MSK (0x0000000F << ADC_SERIAL_CS_OUT_OFST)
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#include "AD9257.h"
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//#define VERBOSE
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//#define VERYVERBOSE
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@ -1718,60 +1728,60 @@ int initConfGain(int isettings,int val,int imod){
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int setADC(int adc){
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/* int reg,nchips,mask,nchans; */
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/* int setADC(int adc){ */
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/* /\* int reg,nchips,mask,nchans; *\/ */
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/* if(adc==-1) ROI_flag=0; */
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/* else ROI_flag=1; */
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/* /\* if(adc==-1) ROI_flag=0; *\/ */
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/* /\* else ROI_flag=1; *\/ */
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/* // setDAQRegister();//token timing */
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/* cleanFifo();//adc sync */
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/* /\* // setDAQRegister();//token timing *\/ */
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/* /\* cleanFifo();//adc sync *\/ */
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/* //with gotthard module */
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/* if(withGotthard){ */
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/* //set packet size */
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/* ipPacketSize= DEFAULT_IP_PACKETSIZE; */
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/* udpPacketSize=DEFAULT_UDP_PACKETSIZE; */
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/* //set channel mask */
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/* nchips = GOTTHARDNCHIP; */
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/* nchans = GOTTHARDNCHAN; */
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/* mask = ACTIVE_ADC_MASK; */
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/* } */
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/* /\* //with gotthard module *\/ */
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/* /\* if(withGotthard){ *\/ */
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/* /\* //set packet size *\/ */
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/* /\* ipPacketSize= DEFAULT_IP_PACKETSIZE; *\/ */
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/* /\* udpPacketSize=DEFAULT_UDP_PACKETSIZE; *\/ */
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/* /\* //set channel mask *\/ */
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/* /\* nchips = GOTTHARDNCHIP; *\/ */
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/* /\* nchans = GOTTHARDNCHAN; *\/ */
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/* /\* mask = ACTIVE_ADC_MASK; *\/ */
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/* /\* } *\/ */
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/* //with moench module all adc */
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/* else{/\* if(adc==-1){*\/ */
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/* //set packet size */
|
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/* ipPacketSize= DEFAULT_IP_PACKETSIZE; */
|
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/* udpPacketSize=DEFAULT_UDP_PACKETSIZE; */
|
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/* //set channel mask */
|
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/* nchips = N_CHIP; */
|
||||
/* nchans = N_CHANS; */
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/* mask = ACTIVE_ADC_MASK; */
|
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/* }/\* */
|
||||
/* //with moench module 1 adc -- NOT IMPLEMENTED */
|
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/* else{ */
|
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/* ipPacketSize= ADC1_IP_PACKETSIZE; */
|
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/* udpPacketSize=ADC1_UDP_PACKETSIZE; */
|
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/* //set channel mask */
|
||||
/* nchips = NCHIPS_PER_ADC; */
|
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/* nchans = GOTTHARDNCHAN; */
|
||||
/* mask = 1<<adc; */
|
||||
/* }*\/ */
|
||||
/* /\* //with moench module all adc *\/ */
|
||||
/* /\* else{/\\* if(adc==-1){*\\/ *\/ */
|
||||
/* /\* //set packet size *\/ */
|
||||
/* /\* ipPacketSize= DEFAULT_IP_PACKETSIZE; *\/ */
|
||||
/* /\* udpPacketSize=DEFAULT_UDP_PACKETSIZE; *\/ */
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/* /\* //set channel mask *\/ */
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||||
/* /\* nchips = N_CHIP; *\/ */
|
||||
/* /\* nchans = N_CHANS; *\/ */
|
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/* /\* mask = ACTIVE_ADC_MASK; *\/ */
|
||||
/* /\* }/\\* *\/ */
|
||||
/* /\* //with moench module 1 adc -- NOT IMPLEMENTED *\/ */
|
||||
/* /\* else{ *\/ */
|
||||
/* /\* ipPacketSize= ADC1_IP_PACKETSIZE; *\/ */
|
||||
/* /\* udpPacketSize=ADC1_UDP_PACKETSIZE; *\/ */
|
||||
/* /\* //set channel mask *\/ */
|
||||
/* /\* nchips = NCHIPS_PER_ADC; *\/ */
|
||||
/* /\* nchans = GOTTHARDNCHAN; *\/ */
|
||||
/* /\* mask = 1<<adc; *\/ */
|
||||
/* /\* }*\\/ *\/ */
|
||||
|
||||
/* //set channel mask */
|
||||
/* reg = (nchans*nchips)<<CHANNEL_OFFSET; */
|
||||
/* reg&=CHANNEL_MASK; */
|
||||
/* reg|=(ACTIVE_ADC_MASK & mask); */
|
||||
/* bus_w(CHIP_OF_INTRST_REG,reg); */
|
||||
/* /\* //set channel mask *\/ */
|
||||
/* /\* reg = (nchans*nchips)<<CHANNEL_OFFSET; *\/ */
|
||||
/* /\* reg&=CHANNEL_MASK; *\/ */
|
||||
/* /\* reg|=(ACTIVE_ADC_MASK & mask); *\/ */
|
||||
/* /\* bus_w(CHIP_OF_INTRST_REG,reg); *\/ */
|
||||
|
||||
/* //#ifdef DDEBUG */
|
||||
/* printf("Chip of Interest Reg:%x\n",bus_r(CHIP_OF_INTRST_REG)); */
|
||||
/* //#endif */
|
||||
/* /\* //#ifdef DDEBUG *\/ */
|
||||
/* /\* printf("Chip of Interest Reg:%x\n",bus_r(CHIP_OF_INTRST_REG)); *\/ */
|
||||
/* /\* //#endif *\/ */
|
||||
|
||||
/* adcConfigured = adc; */
|
||||
/* /\* adcConfigured = adc; *\/ */
|
||||
|
||||
return adcConfigured;
|
||||
}
|
||||
/* return adcConfigured; */
|
||||
/* } */
|
||||
|
||||
|
||||
|
||||
@ -2450,103 +2460,101 @@ int allocateRAM() {
|
||||
|
||||
|
||||
int writeADC(int addr, int val) {
|
||||
|
||||
|
||||
u_int32_t valw,codata,csmask;
|
||||
int i,cdx,ddx;
|
||||
cdx=0; ddx=1;
|
||||
csmask=0xfc; // 1111100
|
||||
|
||||
codata=val + (addr<< 8);
|
||||
printf("***** ADC SPI WRITE TO REGISTER %04X value %04X\n",addr,val);
|
||||
// start point
|
||||
valw=0xff;
|
||||
bus_w16(ADC_WRITE_REG,(valw));
|
||||
|
||||
//chip sel bar down
|
||||
valw=((0xffffffff&(~csmask)));
|
||||
bus_w16(ADC_WRITE_REG,valw);
|
||||
|
||||
for (i=0;i<24;i++) {
|
||||
//cldwn
|
||||
valw=valw&(~(0x1<<cdx));
|
||||
bus_w16(ADC_WRITE_REG,valw);
|
||||
// usleep(0);
|
||||
|
||||
//write data (i)
|
||||
valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx);
|
||||
bus_w16(ADC_WRITE_REG,valw);
|
||||
// usleep(0);
|
||||
|
||||
//clkup
|
||||
valw=valw+(0x1<<cdx);
|
||||
bus_w16(ADC_WRITE_REG,valw);
|
||||
// usleep(0);
|
||||
}
|
||||
|
||||
// stop point =start point
|
||||
valw=valw&(~(0x1<<cdx));
|
||||
// usleep(0);
|
||||
valw=0xff;
|
||||
bus_w16(ADC_WRITE_REG,(valw));
|
||||
|
||||
//usleep in between
|
||||
// usleep(50000);
|
||||
|
||||
setAdc(addr,val);
|
||||
return OK;
|
||||
/* u_int32_t valw,codata,csmask; */
|
||||
/* int i,cdx,ddx; */
|
||||
/* cdx=0; ddx=1; */
|
||||
/* csmask=0xfc; // 1111100 */
|
||||
|
||||
/* codata=val + (addr<< 8); */
|
||||
/* printf("***** ADC SPI WRITE TO REGISTER %04X value %04X\n",addr,val); */
|
||||
/* // start point */
|
||||
/* valw=0xff; */
|
||||
/* bus_w16(ADC_WRITE_REG,(valw)); */
|
||||
|
||||
/* //chip sel bar down */
|
||||
/* valw=((0xffffffff&(~csmask))); */
|
||||
/* bus_w16(ADC_WRITE_REG,valw); */
|
||||
|
||||
/* for (i=0;i<24;i++) { */
|
||||
/* //cldwn */
|
||||
/* valw=valw&(~(0x1<<cdx)); */
|
||||
/* bus_w16(ADC_WRITE_REG,valw); */
|
||||
/* // usleep(0); */
|
||||
|
||||
/* //write data (i) */
|
||||
/* valw=(valw&(~(0x1<<ddx)))+(((codata>>(23-i))&0x1)<<ddx); */
|
||||
/* bus_w16(ADC_WRITE_REG,valw); */
|
||||
/* // usleep(0); */
|
||||
|
||||
/* //clkup */
|
||||
/* valw=valw+(0x1<<cdx); */
|
||||
/* bus_w16(ADC_WRITE_REG,valw); */
|
||||
/* // usleep(0); */
|
||||
/* } */
|
||||
|
||||
/* // stop point =start point */
|
||||
/* valw=valw&(~(0x1<<cdx)); */
|
||||
/* // usleep(0); */
|
||||
/* valw=0xff; */
|
||||
/* bus_w16(ADC_WRITE_REG,(valw)); */
|
||||
/* //usleep in between */
|
||||
/* // usleep(50000); */
|
||||
/* return OK; */
|
||||
}
|
||||
|
||||
int prepareADC(){
|
||||
printf("Preparing ADC\n");
|
||||
u_int32_t codata,csmask;
|
||||
int cdx,ddx;
|
||||
cdx=0; ddx=1;
|
||||
csmask=0x7c; // 1111100
|
||||
/* int prepareADC(){ */
|
||||
/* printf("Preparing ADC\n"); */
|
||||
/* u_int32_t codata,csmask; */
|
||||
/* int cdx,ddx; */
|
||||
/* cdx=0; ddx=1; */
|
||||
/* csmask=0x7c; // 1111100 */
|
||||
|
||||
/* #define ADCREG1 0x08 */
|
||||
/* #define ADCREG2 0x14//20 */
|
||||
/* #define ADCREG3 0x4 */
|
||||
/* #define ADCREG4 0x5 */
|
||||
codata=0;
|
||||
writeADC(0x08,0x3);//reset
|
||||
writeADC(0x08,0x0);//run!
|
||||
writeADC(0x04,0xf);//all chans
|
||||
writeADC(0x04,0x3f);//all chans
|
||||
/* /\* #define ADCREG1 0x08 *\/ */
|
||||
/* /\* #define ADCREG2 0x14//20 *\/ */
|
||||
/* /\* #define ADCREG3 0x4 *\/ */
|
||||
/* /\* #define ADCREG4 0x5 *\/ */
|
||||
/* codata=0; */
|
||||
/* writeADC(0x08,0x3);//reset */
|
||||
/* writeADC(0x08,0x0);//run! */
|
||||
/* writeADC(0x04,0xf);//all chans */
|
||||
/* writeADC(0x04,0x3f);//all chans */
|
||||
|
||||
// writeADC(0x16,0x4);//output clock phase
|
||||
// writeADC(0x18,0x4);// vref 1V
|
||||
// writeADC(0x14,0x0);
|
||||
writeADC(0x14,0x40);//lvds reduced range -- offset binary
|
||||
/* // writeADC(0x16,0x4);//output clock phase */
|
||||
/* // writeADC(0x18,0x4);// vref 1V */
|
||||
/* // writeADC(0x14,0x0); */
|
||||
/* writeADC(0x14,0x40);//lvds reduced range -- offset binary */
|
||||
|
||||
writeADC(0xD,0x0);//no test mode
|
||||
/* writeADC(0xD,0x0);//no test mode */
|
||||
|
||||
#ifdef TESTADC
|
||||
/* #ifdef TESTADC */
|
||||
|
||||
|
||||
////////////TEST ADC!!!!!!!!!!
|
||||
/* ////////////TEST ADC!!!!!!!!!! */
|
||||
|
||||
printf("***************************************** *******\n");
|
||||
printf("******* PUTTING ADC IN TEST MODE!!!!!!!!! *******\n");
|
||||
printf("***************************************** *******\n");
|
||||
/* printf("***************************************** *******\n"); */
|
||||
/* printf("******* PUTTING ADC IN TEST MODE!!!!!!!!! *******\n"); */
|
||||
/* printf("***************************************** *******\n"); */
|
||||
|
||||
|
||||
// writeADC(0xD,0x4);//ALTERNATING CHECKERBOARD
|
||||
/* // writeADC(0xD,0x4);//ALTERNATING CHECKERBOARD */
|
||||
|
||||
// writeADC(0xD,0x7);//ONE/ZERO WORD TOGGLE
|
||||
/* // writeADC(0xD,0x7);//ONE/ZERO WORD TOGGLE */
|
||||
|
||||
/* writeADC(0x19,0xf0);//user input */
|
||||
/* writeADC(0x1A,0xf0);//user input */
|
||||
/* writeADC(0x1B,0x0f);//user input */
|
||||
/* writeADC(0x1C,0x0f);//user input */
|
||||
/* writeADC(0xD,0x48);//user input, alternate */
|
||||
/* /\* writeADC(0x19,0xf0);//user input *\/ */
|
||||
/* /\* writeADC(0x1A,0xf0);//user input *\/ */
|
||||
/* /\* writeADC(0x1B,0x0f);//user input *\/ */
|
||||
/* /\* writeADC(0x1C,0x0f);//user input *\/ */
|
||||
/* /\* writeADC(0xD,0x48);//user input, alternate *\/ */
|
||||
|
||||
/* //writeADC(0xD,0xA);//1xsync */
|
||||
// writeADC(0xD,0xB);//1xbit high
|
||||
writeADC(0xD,0xC);//1xmixed frequqncy
|
||||
/* /\* //writeADC(0xD,0xA);//1xsync *\/ */
|
||||
/* // writeADC(0xD,0xB);//1xbit high */
|
||||
/* writeADC(0xD,0xC);//1xmixed frequqncy */
|
||||
|
||||
|
||||
|
||||
#endif
|
||||
/* #endif */
|
||||
|
||||
|
||||
|
||||
@ -2554,15 +2562,15 @@ int prepareADC(){
|
||||
|
||||
|
||||
|
||||
bus_w(ADC_LATCH_DISABLE_REG,0x0); // enable all ADCs
|
||||
// bus_w(DAQ_REG,0x12); //adc pipeline=18
|
||||
/* bus_w(ADC_LATCH_DISABLE_REG,0x0); // enable all ADCs */
|
||||
/* // bus_w(DAQ_REG,0x12); //adc pipeline=18 */
|
||||
|
||||
//bus_w(DAQ_REG,0xbbbbbbbb);
|
||||
// bus_w(ADC_INVERSION_REG,0x1f6170c6);
|
||||
/* //bus_w(DAQ_REG,0xbbbbbbbb); */
|
||||
/* // bus_w(ADC_INVERSION_REG,0x1f6170c6); */
|
||||
|
||||
return OK;
|
||||
/* return OK; */
|
||||
|
||||
}
|
||||
/* } */
|
||||
|
||||
|
||||
int clearRAM() {
|
||||
|
||||
@ -81,7 +81,7 @@ int getTemperature(int tempSensor);
|
||||
int initHighVoltage(int val,int imod);
|
||||
int initConfGain(int isettings,int val,int imod);
|
||||
|
||||
int setADC(int adc);
|
||||
//int setADC(int adc);
|
||||
//int configureMAC(int ipad, long long int macad, long long int detectormacadd, int detipad, int ival, int udpport);
|
||||
int configureMAC(uint32_t destip,uint64_t destmac,uint64_t sourcemac,int detipad,int ival,uint32_t destport);
|
||||
int getAdcConfigured();
|
||||
@ -160,7 +160,7 @@ int allocateRAM();
|
||||
|
||||
|
||||
int writeADC(int addr, int val);
|
||||
int prepareADC();
|
||||
//int prepareADC();
|
||||
|
||||
|
||||
|
||||
|
||||
@ -1,9 +1,9 @@
|
||||
Path: slsDetectorsPackage/slsDetectorSoftware/jctbDetectorServer
|
||||
URL: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
|
||||
Repository Root: origin git@github.com:slsdetectorgroup/slsDetectorPackage.git
|
||||
Repsitory UUID: c35203ebfb35ba605eaff601ce46e4d29c1f5690
|
||||
Revision: 24
|
||||
Repsitory UUID: 9ae128961675230ad322ff2867f1862dbe8566a7
|
||||
Revision: 25
|
||||
Branch: developer
|
||||
Last Changed Author: Anna_Bergamaschi
|
||||
Last Changed Rev: 3761
|
||||
Last Changed Date: 2018-04-27 14:46:10.176661554 +0200 ./server_funcs.h
|
||||
Last Changed Rev: 3764
|
||||
Last Changed Date: 2018-05-07 14:30:14.000000002 +0200 ./Makefile
|
||||
|
||||
@ -1,6 +1,6 @@
|
||||
#define GITURL "git@github.com:slsdetectorgroup/slsDetectorPackage.git"
|
||||
#define GITREPUUID "c35203ebfb35ba605eaff601ce46e4d29c1f5690"
|
||||
#define GITREPUUID "9ae128961675230ad322ff2867f1862dbe8566a7"
|
||||
#define GITAUTH "Anna_Bergamaschi"
|
||||
#define GITREV 0x3761
|
||||
#define GITDATE 0x20180427
|
||||
#define GITREV 0x3764
|
||||
#define GITDATE 0x20180507
|
||||
#define GITBRANCH "developer"
|
||||
|
||||
Reference in New Issue
Block a user