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m3: changed clk 0 1 2 to 100MHz (#636)
* m3: changed clk 0 1 2 to 100MHz * m3:fix clk 2 * binaries in
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@ -57,9 +57,9 @@
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#define DEFAULT_TRIMBIT_VALUE (0)
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#define DEFAULT_COUNTER_DISABLED_VTH_VAL (2800)
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#define DEFAULT_READOUT_C0 (12) //(083333333) // rdo_clk, 83.33 MHz
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#define DEFAULT_READOUT_C1 (12) //(083333333) // rdo_smp_clk, 83.33 MHz
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#define DEFAULT_SYSTEM_C0 (20) //(050000000) // run_clk, 20 MHz
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#define DEFAULT_READOUT_C0 (10) //(100000000) // rdo_clk, 100 MHz
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#define DEFAULT_READOUT_C1 (10) //(100000000) // rdo_smp_clk, 100 MHz
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#define DEFAULT_SYSTEM_C0 (10) //(100000000) // run_clk, 100 MHz
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#define DEFAULT_SYSTEM_C1 (8) //(125000000) // str_clk, 125 MHz const
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#define DEFAULT_SYSTEM_C2 (5) //(200000000) // smp_clk, 200 MHz const
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#define DEFAULT_TRIMMING_RUN_CLKDIV (40) // (25000000) // 25 MHz
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@ -11,4 +11,4 @@
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#define APIEIGER "7.0.0.rc1 0x221212"
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#define APIGOTTHARD "7.0.0.rc2 0x221220"
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#define APIMYTHEN3 "7.0.0.rc2 0x230117"
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#define APIMYTHEN3 "7.0.0.rc2 0x230125"
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