m3: changed clk 0 1 2 to 100MHz (#636)

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* m3: changed clk 0 1 2 to 100MHz

* m3:fix clk 2

* binaries in

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This commit is contained in:

Dhanya Thattil

2023-01-25 11:54:37 +01:00

committed by GitHub

parent c7af9c9f3e

commit 3f7c9529dd

3 changed files with 4 additions and 4 deletions

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BIN

slsDetectorServers/mythen3DetectorServer/bin/mythen3DetectorServerv7.0.0.rc2

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